IEEE 1284-Compatible Parallel Interface Controller with High-Speed Asy
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CD1284
IEEE 1284-Compatible Parallel Interface Controller with High-Speed Asynchronous Serial Ports
Parallel Port (Peripheral-side)
High-speed, bidirectional, multi-protocol parallel port: Hardware implementation modes IEEE (Standard) 1284 specification (including automatic negotiation) Centronics-compatible mode Reverse Byte mode Reverse Nibble mode (extended capabilities port) mode with run-length encoding/decoding (enhanced parallel port) mode 2-Mbytes/sec. transfer rate modes 64-byte parallel FIFO with interface
Serial UARTs
Serial channel asynchronous protocol support 115.2 kbps (register-setcompatible functionally identical CD1400) Twelve-byte FIFOs each transmitter receiver with programmable threshold receive FIFO interrupt generation Improved interrupt schemes: Good Data interrupts eliminate need character status check User-programmable automatic flow control serial channels Special character recognition generation. Special character processing, particularly useful UNIX environments, optionally handled automatically serial channels. modem control signals channel (DTR, DSR, RTS, CTS,
2001, this document replaces Basis Communications Corp. document. CL-CD1284 IEEE 1284-Compatible Parallel Interface Controller
2001
Information this document provided connection with Intel® products. license, express implied, estoppel otherwise, intellectual property rights granted this document. Except provided Intel's Terms Conditions Sale such products, Intel assumes liability whatsoever, Intel disclaims express implied warranty, relating sale and/or Intel products including liability warranties relating fitness particular purpose, merchantability, infringement patent, copyright other intellectual property right. Intel products intended medical, life saving, life sustaining applications. Intel make changes specifications product descriptions time, without notice. Designers must rely absence characteristics features instructions marked "reserved" "undefined." Intel reserves these future definition shall have responsibility whatsoever conflicts incompatibilities arising from future changes them. CD1284 contain design defects errors known errata which cause product deviate from published specifications. Current characterized errata available request. Contact your local Intel sales office your distributor obtain latest specifications before placing your product order. Copies documents which have ordering number referenced this document, other Intel literature obtained calling 1-800548-4725 visiting Intel's website http://www.intel.com. Copyright Intel Corporation, 2001 *Third-party brands names property their respective owners.
IEEE 1284-Compatible Parallel Interface Controller CD1284
Contents
Overview Conventions
Abbreviations.15 Acronyms Diagram.17 List.18 Register Summary Tables.24 Register Usage.27 Device Architecture Interface.33 5.2.1 Read Cycles 5.2.2 Write Cycles 5.2.3 Service-Acknowledge Cycles 5.2.4 Cycles.34 Serial Port Service Requests 5.3.1 Interrupts 5.3.2 DMAREQ* Parallel Interrupt Source.36 5.3.3 Serial Service Request Polling 5.3.4 Daisy-Chaining Service Requests with CD1400s Parallel Port Service Requests.43 5.4.1 Hardware-Activated Context Switch, Parallel.48 5.4.2 Software-Activated Context Switch, Parallel Serial Data Reception Transmission 5.5.1 Receiver Operation 5.5.2 Receiver Timer Operations 5.5.3 Receive Exceptions.52 5.5.4 Transmitter Operation Flow Control 5.6.1 In-Band Flow Control.55 5.6.2 Receiver In-Band Flow Control 5.6.3 Out-of-Band Flow Control.58 5.6.4 Modem Signals General-Purpose Receive Special Character Processing 5.7.1 UNIX, Character Processing 5.7.2 Non-UNIX, Receive Special Character Processing.63 Transmit Special Character Processing 5.8.1 Line Terminating Characters 5.8.2 Embedded Transmit Commands.67 5.8.3 Send Special Character Command.68 Baud Rate Generation.72
Information
Register Summary
Functional Description.31
CD1284 IEEE 1284-Compatible Parallel Interface Controller
5.10 5.11
5.12
5.13
5.14 5.15 5.16 5.17
Serial Diagnostic Facilities Loopback Parallel Port FIFO Data Pipeline Overview 5.11.1 IEEE 1284 Protocols 5.11.2 Interface 5.11.3 Parallel Port FIFO 5.11.4 Receive Direction 5.11.5 Receiving Compressed Data. 5.11.6 Stale Data (Stale, OneChar, Timeout Status Bits) 5.11.7 Transmit Direction CD1284 Parallel Port Overview 5.12.1 Terminology 5.12.2 Signal Names 5.12.3 State Machine 5.12.4 Configuration. 5.12.5 Interrupts 5.12.6 Manual Mode 5.12.7 Control Signals. 5.12.8 Parallel Port Interface FIFO 5.12.9 1284 Negotiations 5.12.10 Data Transfers 5.12.11 Compatible Mode Status 1284 Parallel Protocol Support 5.13.1 Compatibility Mode. 5.13.2 Reverse-Nibble Reverse-Byte Modes 5.13.3 Request 5.13.4 Mode. 5.13.5 Mode Protocol Timing General-Purpose Port Parallel Port Interface. Hardware Configurations 5.17.1 Interfacing Intel, Microprocessor-Based System 5.17.2 Interfacing Motorola, Microprocessor-Based System. 5.17.3 Interfacing National Semiconductor, Microprocessor-Based System86 Overview Initialization 6.2.1 Device Reset. 6.2.2 Global Function Initialization 6.2.3 Serial Channel Initialization. Serial Poll Mode Examples 6.3.1 Polling Routine Examples Hardware-Activated Service Examples. 6.4.1 Serial Receive Service 6.4.2 Serial Transmit Service 6.4.3 Modem Service Parallel Channel Service Routines. 6.5.1 Software-Activated Service Examples (Poll)
Programming
IEEE 1284-Compatible Parallel Interface Controller CD1284
6.5.2 Hardware-Activated Service Examples .102 Baud Rate Derivation .102 Baud Rate Tables.103 ASCII Code Tables.106 6.8.1 Hexadecimal Character .106 6.8.2 Decimal Character .107 Global Registers.108 7.1.1 Channel Access Register .108 7.1.2 Global Firmware Revision Code Register .108 7.1.3 General-Purpose Direction Register.109 7.1.4 General-Purpose Register.109 7.1.5 Modem Interrupting Channel Register .109 7.1.6 Modem Interrupt Register.110 7.1.7 Parallel Interrupt Register.111 7.1.8 Prescaler Period Register .111 7.1.9 Receive Interrupting Channel Register .112 7.1.10 Receive Interrupt Register.112 7.1.11 Service Request Register.112 7.1.12 Transmit Interrupting Channel Register .113 7.1.13 Transmit Interrupt Register.113 Virtual Registers .113 7.2.1 Modem Interrupt Status Register .114 7.2.2 Modem Interrupt Vector Register .114 7.2.3 Parallel Interrupt Vector Register .115 7.2.4 Receive Data/Status Registers .115 7.2.5 Receive Interrupt Vector Register .116 7.2.6 Transmit Data Register .117 7.2.7 Transmit Interrupt Vector Register .117 7.2.8 Service Request Register .118 Channel Registers.118 7.3.1 Channel Command Register .118 7.3.2 Channel Control Status Register.122 Channel Registers Parallel Pipeline .123 7.4.1 Channel Option Register .123 7.4.2 Channel Option Register .124 7.4.3 Channel Option Register .125 7.4.4 Channel Option Register .126 7.4.5 Channel Option Register .128 7.4.6 Local Interrupt Vector Register.128 7.4.7 LNext Character Register.129 Modem Change Option Registers .129 7.5.1 Modem Change Option Register 1.129 7.5.2 Modem Change Option Register 2.130 7.5.3 Modem Signal Value Register 1.130 7.5.4 Modem Signal Value Register 2.131 7.5.5 Receive Baud Rate Period Register.131 7.5.6 Receive Clock Option Register .131 7.5.7 Received Data Count Register .132
Detailed Register Descriptions .108
CD1284 IEEE 1284-Compatible Parallel Interface Controller
7.5.8 Receive Timeout Period Register. Special Character Registers 7.6.1 Special Character Register 7.6.2 Special Character Register 7.6.3 Special Character Register 7.6.4 Special Character Register 7.6.5 Received Character Range Detection. 7.6.6 Special Character Range High 7.6.7 Special Character Range 7.6.8 Serial Service Request Enable Register 7.6.9 Transmit Baud Rate Period Register. 7.6.10 Transmit Clock Option Register Channel Registers Parallel Pipeline 7.7.1 Data Error Register 7.7.2 Buffer Data Register High. 7.7.3 Buffer Data Register Low. 7.7.4 Firmware Revision Code Holding Register Status Register. 7.7.5 Local Interrupt Vector Register 7.7.6 Parallel Auxiliary Control Register. 7.7.7 Parallel Channel Reset Register 7.7.8 Parallel FIFO Control Register 7.7.9 Parallel FIFO Empty Pointer Register 7.7.10 Parallel FIFO Fill Pointer Register. 7.7.11 Parallel FIFO Holding Register 7.7.12 Parallel FIFO Holding Register 7.7.13 Parallel FIFO Quantity Register 7.7.14 Parallel FIFO Status Register. 7.7.15 Parallel FIFO Threshold Register. 7.7.16 Length Count Register. 7.7.17 Stale Data Timer Count Register 7.7.18 Stale Data Timer Period Register. Channel Registers Parallel Port 7.8.1 Address Register 7.8.2 Host Timeout Value Register 7.8.3 Input Value Register. 7.8.4 Manual Data Register 7.8.5 Negotiation Enable Register 7.8.6 Negotiation Status Register 7.8.7 Ones Detect Register 7.8.8 Output Value Register 7.8.9 Parallel Channel Interrupt Enable Register 7.8.10 Parallel Channel Interrupt Status Register 7.8.11 Parallel Configuration Register. 7.8.12 Special Command Register. 7.8.13 Short Pulse Register Control Registers 7.9.1 Signal Status Register. 7.9.2 Zeros Detect Register
IEEE 1284-Compatible Parallel Interface Controller CD1284
Electrical Specifications .155
Absolute Maximum Ratings.155 Recommended Operating Conditions .155 Characteristics.157 8.3.1 Asynchronous Timing.157 8.3.2 Synchronous Timing.163
10.0 11.0 12.0 Index
Package Dimensions .169 Ordering Information .170 Appendix .171
11.1 Commonly Asked Questions .171
Appendix .172
.173
CD1284 IEEE 1284-Compatible Parallel Interface Controller
Figures
Functional Block Diagram CD1284 Sample System Block Diagram CD1284 Functional Block Diagram Internal Address Generation Control Signal Generation. CD1284 Daisy-Chain Connections Interrupt Generation Logic FIFO Timer Processing CD1284 Receive Character Processing CD1284 Transmit Character Processing FIFO Data Path Functional Diagram Receive FIFO Data Path Functional Diagram Transmit Cable Connection. External Buffer Control. Intel, 80x86 Family Interface Motorola, 68020 Interface National Semiconductor, 32000 Interface Flow Diagram CD1284 Master Initialization Sequence. Polling Flow Chart Reset Timing Clock Timing Asynchronous Read Cycle Timing Asynchronous Write Cycle Timing Asynchronous Service Acknowledge Cycle Timing Asynchronous Read Cycle Timing Asynchronous Read Cycle Timing (Two Back-to-Back Reads) Asynchronous Write Cycle Timing Asynchronous Write Cycle Timing (Two Back-to-Back Writes). Synchronous Read Cycle Timing. Synchronous Write Cycle Timing Synchronous Service Acknowledge Cycle Timing Synchronous Write Cycle Timing (Two Back-to-Back 3-Cycle Writes) Synchronous Read Cycle Timing (Two Back-to-Back 3-Cycle Reads) UART RS232 Port Interface Motherboard Example Schematic
IEEE 1284-Compatible Parallel Interface Controller CD1284
Tables
Descriptions Global Registers.24 Virtual Registers Serial Virtual Registers Serial Parallel Channel Registers Serial Channel Registers Parallel Pipeline (Selected Channel CAR) Channel Registers Parallel Port (Selected Channel CAR) Global Registers.27 Virtual Registers Virtual Registers Serial Parallel Channel Registers Serial Channel Registers Parallel Pipeline (Selected Channel CAR) Channel Registers Parallel Port (Selected Channel CAR) Request-Type Assignments CCSR[6:5] Encoding CCSR[2:1] Encoding Control Bits.58 Out-of-Band Connections.59 Modem Control Functions Signal Names System Clock Settings Baud Rate Constants .103 Baud Rate Constants 20.2752 .104 Baud Rate Constants 20.00 .104 Baud Rate Constants 18.432 .105 Baud Rate Constants .105 Asynchronous Timing Reference Parameters.157 Synchronous Timing Reference Parameters .164
CD1284 IEEE 1284-Compatible Parallel Interface Controller
Revision History
Revision Date 2001 Initial release. Description
IEEE 1284-Compatible Parallel Interface Controller CD1284
Figure Functional Block Diagram
GENERALPURPOSE PORT Compression/ Decompression DATA Mover DATA PIPELINE Bytes Control State Machine Level-2 Electrical Interface
LOCAL INTERFACE
CONTROL
FIFO
IEEE1284 PERIPHERAL PARALLEL PORT SERIAL PORT
REGISTERS FIFO MODIFIED CD1400 CORE
SERIAL PORT
CD1284 IEEE 1284-Compatible Parallel Interface Controller
Overview
Ideal printers, scanners, tape drives, set-top boxes, data acquisition applications, CD1284 multi-function interface controller that implements high-speed, multi-protocol parallel port asynchronous serial ports. device both programmed operation (parallel port only), providing flexibility local interface design high-speed data transfers between device main memory. parallel port implements modes IEEE 1284 Standard Signaling Method Bidirectional Parallel Peripheral Interface Personal Computers specification, including EPP, ECP, Reverse Byte, Reverse Nibble, Compatible. Data transfer rates Mbytes/sec.) achievable parallel port when device operates with 25-MHz clock. parallel port data control signals implement IEEE 1284-defined Level-2 interface drive type (symmetrical), current capability (±14 mA), slew rate (0.4 V/ns), hysteresis +7.0 protection implemented). serial ports implement standard asynchronous protocol. Functionally, serial ports identical register-set-compatible with CD1400. table below, shows differences between CD1283 CD1284.
Device CD1283 CD1284 Number Serial Channels Number Parallel Channels
Also included general-purpose port that provides eight bits individual direction programmable that used status control external functions.
Theory Operation
CD1284 efficient high-performance communications controller using on-chip RISC processor, which off-loads much work sending receiving data from CPU. Specifically data communications applications, RISC processor employs highperformance architecture developed Intel. This internal executes instructions clock cycle, uses windowed architecture ensure zero-overhead context switching each type internal interrupt. processor transparent user does require programming. manages serial data movement between serial channels provides flexible interrupt interface parallel channel. parallel channel, being separate having intelligence, implements very high-speed, peripheral-side parallel data interface. Each serial channels consist separate byte receive transmit FIFOs. parallel channel single 64-byte FIFO support higher speeds obtainable parallel data port. serial receive FIFOs have programmable thresholds minimize interrupt latency requirements. parallel port FIFO programmable threshold both receive transmit directions. deep FIFOs reduce both number interrupt requests made time required service them. time required service requests reduced four unique vectors that provide internal interrupt conditions. Whether receive, transmit, modem signal change, parallel port, system spends less time determining source interrupt.The serial receive interrupt service time further reduced providing types receive vectors: `good' data other `exception' data. does spend
IEEE 1284-Compatible Parallel Interface Controller CD1284
time determining status every character. When receive vector signifies good data, removes data from FIFO. Checking status necessary. Exception data (framing error, overrun, break, etc.) causes interrupt with vector that immediately identify manage. RISC processor assisted process sending receiving serial data specialized hardware called `bit engines'. These logic blocks perform actual task sending receiving individual bits character, thus removing task timing duration from on-chip processor. processor assembles bits into characters tests various parameters (for example, parity, framing, etc.) then places characters FIFO. Since managing every character, special character processing possible such looking responding flowcontrol characters (XON/XOFF) performing UNIX-style character substitutions range checking. This reduces interrupt overhead automatically performing many operations that normally does. Flow-control, example, performed without involvement. Those operations completely removed from responsibility. CD1284 daisy-chained with other CD1284 CD1400 devices implement larger more complex systems. Fair Share feature assures equal access service requests across multiple devices (Fair Share implemented parallel port interrupt request). parallel channel within CD1284 implements protocols defined peripheral side IEEE 1284. This specification defines four bidirectional protocols that allow peripheral device communicate with host system (IBM equivalent) through parallel printer channel. modes include Reverse Nibble, Reverse Byte (IBM PS/2 style), ECP, implemented Intel 80386SL processor). both operate data rates high Mbytes/sec. IEEE 1284 port implemented functional blocks: data pipeline, which includes 64-byte FIFO interface, high-speed state-machine, which controls parallel port implements slave-side IEEE 1284 protocols. internal RISC processor assists parallel channel providing interrupt generation, acknowledgment functions, data interface Parallel Port registers. defined IEEE 1284 specification, CD1284 mode, provides (run length encoded) data compression both directions. This data compression performed automatically enabled) capable compressing long strings bytes) identical data into two-byte sequence (command/count data). Since common patterns have large amounts identical data, CD1284 greatly reduces data transmission times printer applications. mode defines means sending address data over parallel channel much like processor address data interface. This found widespread SCSI interface adapters that provide these services laptop computers. following figure shows possible configuration CD1284 laser-printer application. this example, CD1284 provides parallel serial data interface host system server. also provides serial channel control communication with printer console, well general-purpose static control/status.
CD1284 IEEE 1284-Compatible Parallel Interface Controller
Figure CD1284 Sample System Block Diagram
ADDRESS CONTROL PROCESSOR DATA
I/O: INTERNAL STATUS CONTROL
IEEE 1284 PARALLEL CHANNEL
CD1284
HIGH-SPEED SERIAL CHANNEL (RS-232, INFRARED) HIGH-SPEED SERIAL CHANNEL LASER PRINTER CONSOLE
IEEE 1284-Compatible Parallel Interface Controller CD1284
Conventions
Abbreviations
Symbol Units Measure degree Celsius hertz (cycles second) kilobyte (1,024 bytes) kilohertz kilohm megabyte (1,048,576 bytes) megahertz (1,000 kilohertz) microfarad microsecond (1,000 nanoseconds) milliampere millisecond (1,000 microseconds) nanosecond picovolt
Kbyte Mbyte
`tbd' indicates values that determined', `n/a' designates `not available', `N/C' indicates that connect'.
Acronyms
Acronym Definition (Sheet BIOS CISC CMOS DRAM FIFO GPIO alternating current basic input/output system complex instruction computer complementary metal-oxide semiconductor direct current direct-memory access dynamic random-access memory extended capibilities port enhanced parallel port first in/first general-purpose
CD1284 IEEE 1284-Compatible Parallel Interface Controller
Acronym
Definition (Sheet
HCMOS HDLC MQFP SDLC SRAM VRAM
high-performance complementary metal-oxide semiconductor high-level data link control integrated circuit instruction data cache industry standard architecture least-significant microprocessing unit most-significant programmed point-to-point protocol metric quad flat pack random-access memory run-length encoded read/write synchronous data link control static random-access memory software interrupt instruction translation look-aside buffer translation table base transitor-transitor logic video random-access memory write buffer
IEEE 1284-Compatible Parallel Interface Controller CD1284
Information
Diagram
BYTESWAP
DB[10]
DB[11]
DB[12]
DB[13]
DB[8]
DB[9]
DB[14]
DB[15]
OUTEN
A[0]
A[1]
A[2]
A[3]
A[4]
A[5]
A[6]
DB[7] DB[6] DB[5] DB[4] DB[3] DB[2] DB[1] DB[0] DMAACK* DMAREQ* RI3* RI2* TXD3 RXD3 TXD2 RXD2 DTR3* RTS3* CTS3* DSR3* CD3* DTR2* RTS2* CTS2* DSR2* CD2*
CLK/2 RESET* R/W* DTACK* DPASS* DGRANT* SVCACKP* SVCREQP* SVCACKM* SVCREQM* SVCACKT* SVCREQT* SVCACKR* SVCREQR* GP[0] GP[1] GP[2] GP[3] GP[4] GP[5] GP[6] GP[7] PDBEN
CD1284
100-Pin MQFP
PerBsy
PerClk
A_1284
EBDIR
PD[6]
PD[1]
Xflag
HstBsy
PD[7]
PD[2]
PD[5]
PD[4]
NOTE: Denotes negative-true signal. `N/C' indicates connection; make connection these pins.
AkDaRq
nDatAv
HstClk
PD[3]
PD[0]
nInit
(See table next page.)
CD1284 IEEE 1284-Compatible Parallel Interface Controller
Names
Compatibility
Reverse Nibble Mode
Reverse Byte Mode
Mode
Mode
Inputs A_128 HstBsy HstClk nInit SLCTIN* AUTOFD* STROBE* INIT* A_1284 HstBsy HstClk nInit A_1284 HstBsy HstClk nInit A_1284 HstAck HstClk nRevReq nAStrb nDStrb nWrite nInit
Outputs AkDaR PerBsy PerClk nDatAv XFlag PError BUSY ACK* FAULT* SELECT AkDaRq PerBsy PerClk nDatAv XFlag AkDaRq PerBsy PerClk nDatAv XFlag nAkRev PerAck PerClk nPerReq XFlag USER1 nWait Intr USER2 USER3
List
following conventions used pin-description tables:
after name indicates that signal active-low indicates input-only indicates output-only `I/O' indicates bidirectional `OD' indicates open-drain output that user must through pull-up resistor (usually about `AR' indicates active release (pin drives releases `OD') `TS' indicates tristate indicates ascending numbers indicates descending numbers
Type Number Pins (Sheet Number Reset State
Name
1,10,
RESET*
IEEE 1284-Compatible Parallel Interface Controller CD1284
Name
Type
Number Pins (Sheet
Number
Reset State
OUTEN CLK/2 DB[15:0] A[6:0] R/W* BYTESWAP DTACK* DMAREQ* DMAACK* SVCREQR* SVCACKR* SVCREQT* SVCACKT* SVCREQP* SVCACKP* SVCREQM* SVCACKM* DGRANT* DPASS* PD[7:0] GP[7:0] A_1284 HstBsy HstClk nInit AkDaRq PerBsy PerClk nDatAv Xflag EBDIR PDBEN TXD3
92-99, 84-90 41-48 53-60 High High High High High High High
CD1284 IEEE 1284-Compatible Parallel Interface Controller
Name
Type
Number Pins (Sheet
Number
Reset State
RXD3 TXD2 RXD2 RTS2* RTS3* DTR2* DTR3* CTS2* CTS3* DSR2* DSR3* CD2* CD3* RI2* RI3*
High High High High High
Table
Symbol RESET*
Descriptions (Sheet
Type Description ACTIVE-LOW RESET: This input initializes device default condition. internal registers their reset condition transfer operations default state. OUTPUT ENABLE: This must enable output functions. When OUTEN `0', forces output pins remain tristate condition. Typically, OUTEN used only test purposes. User designs must this through pull-up resistor. SYSTEM CLOCK: This input 25-MHz maximum; recommended minimum satisfactory device performance. SYSTEM CLOCK DIVIDED OUTPUT: This signal equivalent internal operating clock device. BIDIRECTIONAL DATA BUS: Only transfers writes Buffer register true 16-bit operations. During register writes other than Buffer register, bits [7:0] written addressed register. Register reads duplicate register contents both lower byte [7:0] upper byte [15:8]. ADDRESS BUS: Together with SVCACK* inputs DS*, this input selects On-Chip register read write operation acknowledgment service request. READ/WRITE*: This input must register read operation, must register write. R/W* ignored operations. ACTIVE-LOW CHIP SELECT: When active, input combines with DS*, initiates cycle with CD1284. must during read/write operations.
OUTEN
CLK/2
DB[15:0]
92-99,
A[6:0]
84-90
R/W*
IEEE 1284-Compatible Parallel Interface Controller CD1284
Table
Symbol
Descriptions (Sheet
Type Description ACTIVE-LOW DATA STROBE: During active cycle, input strobes data into On-Chip registers write cycles enables data onto data during read cycles. ignored during operations. BYTESWAP: This input determines byte order 2-byte transfers writes Buffer register. When BYTESWAP `1', then Data bits [15:8] driven with byte transferred first parallel port bus. Data bits [7:0] driven with byte transferred second parallel port bus. When BYTESWAP `0', data order reversed, bits [7:0] driven with byte transferred first bits [15:8] driven with byte transferred second. ACTIVE-LOW DATA TRANSFER ACKNOWLEDGE: This output indicates: when device completes requested operation, and, when current cycle finish. This signal implement wait-state insertion local CPU. DTACK* does activate cycles.It active-release output, driving logic then releasing DTACK* must ties external through pull-up resistor. ACTIVE-LOW REQUEST: When internal control DMAen set, output DMAREQ* asserted internal FIFO conditions warrant transfer. DMAREQ* deasserted falling edge DMAACK* when transfers cannot continue past current transfer. ACTIVE-LOW ACKNOWLEDGE: This input never asserted unless response DMAREQ* from chip. DMAACK* only handshake signal recognized during transfer. (CS* must high whenever DMAACK* asserted). direction transfer determined internal control DMAdir. ACTIVE-LOW SERVICE REQUEST RECEIVE: This open-drain output must tied external through pull-up resistor. When active, device serialreceive FIFO either reached programmed threshold exception condition exists that requires attention. ACTIVE-LOW SERVICE ACKNOWLEDGE RECEIVE: This input driven during service acknowledge cycles begin servicing receive-service request. must driven active except response receive-service request presented device. ACTIVE-LOW SERVICE REQUEST TRANSMIT: This open-drain output must tied external through pull-up resistor. When active, device serial transmit FIFO serial transmitter empty requires attention. ACTIVE-LOW SERVICE ACKNOWLEDGE TRANSMIT INPUT: This input driven during service acknowledge cycles begin servicing transmit-service request. must driven active except response transmit-service request presented device. ACTIVE-LOW SERVICE REQUEST PARALLEL: This open-drain output must tied external through pull-up resistor. SVCREQP* activated FIFO threshold FIFO full/empty conditions. ACTIVE-LOW SERVICE ACKNOWLEDGE PARALLEL: This input cannot driven active except response parallel service request presented device. ACTIVE-LOW SERVICE REQUEST STATUS (Modem): This open-drain output that must tied external through pull-up resistor. When active, programmed modem signal change occurs requires attention. ACTIVE-LOW SERVICE ACKNOWLEDGE STATUS (Modem): This input driven during service acknowledge cycles begin servicing modem-service request. must driven active except response modem-service request presented device. ACTIVE-LOW DAISY GRANT: This input driven active during service acknowledge cycles enable daisy-chain function. This input, when qualified with valid service acknowledge (SVCACKR*, SVCACKT*, SVCACKM*, SVCACKP*), activates CD1284 service-acknowledge cycle.
BYTESWAP
DTACK*
DMAREQ*
DMAACK*
SVCREQR*
SVCACKR*
SVCREQT*
SVCACKT*
SVCREQP*
SVCACKP*
SVCREQM*
SVCACKM*
DGRANT*
CD1284 IEEE 1284-Compatible Parallel Interface Controller
Table
Symbol
Descriptions (Sheet
Type Description ACTIVE-LOW DAISY PASS: This output driven active during service acknowledge cycles enable next device daisy chain. driven active when valid service request exists type service acknowledge input active. multiple CD1284 designs, this signal normally connected DGRANT* input next device chain. PARALLEL PORT DATA LINES [7:0]: Bidirectional (depending protocol being used), these signals used transfer data through interface between master slave. GENERAL PURPOSE [7:0]: General-purpose input/output port data lines. These signals individually direction programmable inputs outputs. corresponding GPDIR register controls direction each signal. GPIO register provides control/status actual signals. 1284 ACTIVE INPUT: (SLCTIN* Compatibility mode). Active-high. INIT SIGNAL: (INIT* Compatibility mode). Active-low. HOST BUSY: (AUTOFD* Compatibility mode). Active-high. HOST CLOCK: (STROBE* Compatibility mode). Active-low.
DPASS*
PD[7:0]
41-48
GP[7:0]
53-60
A_1284 nInit HstBsy HstClk
above four parallel handshake signals driven master IEEE 1284 interface, such inputs CD1284. Their functions depend transfer protocol selected. Refer IEEE 1284 document protocol functions. PerClk PerBsy AkDaRq Xflag nDatAv PERIPHERAL CLOCK: (ACK* Compatibility mode). Active-low. PERIPHERAL BUSY: (BUSY Compatibility mode). Active-high. ACKNOWLEDGE DATA REQUEST: (PError Compatibility mode). EXTENSIBILITY FLAG: (SELECT Compatibility mode). DATA AVAILABLE: (FAULT* Compatibility mode). Active-low.
above five parallel handshake signals driven slave IEEE 1284 interface outputs from CD1284. Their functions depend transfer protocol selected. Refer IEEE 1284 document protocol functions. EXTERNAL BUFFER DIRECTION: This signal controlled internal parallelport-control state machine used control direction external buffer connected parallel-port data bus. external buffer could desirable applications that require higher drive capacity than those provided CD1284. EBDIR used conjunction with PDBEN control this buffer. EBDIR logic when parallel data output mode logic when input mode. connected directly direction control input 74245-type device. PARALLEL DATA ENABLE: This signal used control buffer parallel port data lines applications requiring more signal drive capability than that provided CD1284. signal controlled internal parallel port control state-machine. When low, parallel port data (not driving); when high, port output mode actively driving. signal toggles between states during output modes active (high) only when data pins active driving state. This signal logically connected enable control 74245 equivalent) bidirectional buffers. TRANSMIT DATA: TXD[3,2] outputs serial channel numbers three. RECEIVE DATA: RXD[3, outputs serial channel numbers three. REQUEST SEND: These active-low outputs serial channel numbers three. DATA TERMINAL READY: These active-low outputs serial channels three. CLEAR SEND: These active-low inputs serial channels three.
EBDIR
PDBEN
TXD[3,2] RXD[3,2] RTS[3,2]* DTR[3,2]* CTS[3,2]*
IEEE 1284-Compatible Parallel Interface Controller CD1284
Table
Symbol DSR[3,2]* CD[3,2] RI[3,2]
Descriptions (Sheet
Type Description DATA READY: These active-low inputs serial channels three. CARRIER DETECT: These active-low inputs serial chanels three. RING INDICATOR: These active-low inputs chanels three.
CD1284 IEEE 1284-Compatible Parallel Interface Controller
Table
Name GFRCR GPDIR GPIO MICR RICR SVRR TICR
Register Summary
Register Summary Tables
Global Registers
Poll Poll Poll Poll Poll Page Data Data ch[1] Data ch[0] ch[1] ch[1] ch[0] ch[0]
Firmware Revision Code Data MdIreq PPIreq Data Mdbusy PPort Data Mdunfair Pipeline Data Data
8-Bit Binary Value RxIreq DMAREQ TxIreq Rxbusy ExtM Txbusy Rxunfair ExtT Txunfair ExtR
Table
Name MISR MIVR PIVR RDSR
(data)
Virtual Registers Serial
DSRch CTSch RIch CDch Page
Received Character Timeout Det2 Det1 Det0 Break
RDSR
(status)
RIVR TIVR
Transmit Character
Table
Name EOSRR
Virtual Registers Serial Parallel
Page
IEEE 1284-Compatible Parallel Interface Controller CD1284
Table
Name CCR1 CCSR COR1 COR2 COR3 COR4 COR5 LIVR MCOR1 MCOR2 MSVR1 MSVR2 RBPR RCOR RDCR RTPR SCHR1 SCHR2 SCHR3 SCHR4 SCRH SCRL SRER TBPR TCOR
Channel Registers Serial
Chan RxEN Parity SCDRNG IGNCR ISTRIP RxFloff ParM1 TxIBE SCD34 ICRNL Send RxFlon ParM0 INLCR CMOE Chan Ignore SCD12 IGNBRK TxEN Stop1 RxTh3 TxFloff Stop0 RtsAO RxTh2 PEH[2] TxFlon ChL1 CtsAE RxTh1 PEH[1] ONLCR ChL0 DsrAE RxTh0 PEH[0] OCRNL Page DTRth2 DTRth1 DTRth0 ClkSel2 ClkSel1 ClkSel0 TxRdy TxEmpty NNDT ClkSel2 ClkSel1 ClkSel0
-BRKINT
LNext Character DSRzd DSRod CTSzd CTSod RIzd RIod CDzd CDod DTRth3
Binary Divisor Value
Binary Count Value Special Character Special Character Special Character Special Character Character Range high Character Range MdmChg RxData
Binary Divisor Value
NOTE: contents offsets apply channels; channel being access given time controlled CAR. Section 7.3.1.1 through Section 7.3.1.4 channel-specific settings.
CD1284 IEEE 1284-Compatible Parallel Interface Controller
Table
Name DMABUF DMABUF HRSR LIVR PACR PCRR PFCR PFEP PFFP PFHR1 PFHR2 PFQR PFSR PFTR RLCR SDTCR SDTPR
Channel Registers Parallel Pipeline (Selected Channel CAR)
DMAwrerr HR1full DMArderr HR1tag Bufwrerr HR2full Bufrderr HR2tag HR1wrerr DMAfull HR1rderr DMAmpty ClearTO RLEen setTAG HR2wrerr DMAact AsyncDMA ErrEn HR2rderr Ctnot0 Unfair PChReset DMAbufWe Page OneChar DataErr
User-Defined Bits ShrtTen FIFOres ShrtStal DMAen StaleOff DMAdir FIFOlock IntEn
6-Bit Binary FIFO Pointer Value 6-Bit Binary FIFO Pointer Value 8-Bit Character Data 8-Bit Character Data Data Space Available FIFO 0x'40
FFfull
FFempty
Timeout
HRtag
HRdata
Stale
Transfer Threshold 7-Bit Unsigned Binary Count 8-Bit Stale Data Timer Count 8-Bit Stale Data Timeout Value
Table
Name HTVR PCIER PCISR
Channel Registers Parallel Port (Selected Channel CAR) (Sheet
Page HTVR[2] nInit HTVR[1] HstBsy HTVR[0] HstClk HstClk nINIT nINIT ManOE RevRq
8-Bit Binary Value HTVR[7] HTVR[6] HTVR[5] HTVR[4] HTVR[3] A1284
8-Bit Binary Data NegOK PerBsy ManMd NegFl PerClk TimEn TimeOvr E1284 HostTO AkDaRq NegCh NegCh ETxfr ImedTerm xFlag SigCh SigCh Ig_SEL TstMux A1284 nDatAv EPPAW EPPAW
4-Bit Negotiation Result Code nInit DirCh DirCh HstBsy IDReq IDReq MMDir EPIrq
HTmrTst[1:0] ClrPs SetPs
IEEE 1284-Compatible Parallel Interface Controller CD1284
Table
Name
Channel Registers Parallel Port (Selected Channel CAR) (Sheet
Page nInit nInit HstBsy HstBsy HstClk HstClk
8-Bit Binary Value A1284 A1284
Register Usage
Table through Table present register tunctionality.
Table
Name GFRCR GPDIR GPIO MICR RICR SVRR TICR
Global Registers
Reset Parallel Init Parallel Parallel Serial Init Serial Serial GPIO Control
Table
Name MISR MIVR PIVR RDSR (data) RDSR (status) RIVR TIVR
Virtual Registers
Reset Parallel Init Parallel Parallel Serial Init Serial Serial
CD1284 IEEE 1284-Compatible Parallel Interface Controller
Table Virtual Registers Serial Parallel
Name EOSRR Reset Parallel Init Parallel Parallel Serial Init Serial Serial
Table Channel Registers Serial
Name CCSR COR1 COR2 COR3 COR4 COR5 LIVR MCOR1 MCOR2 MSVR1 MSVR2 RBPR RCOR RDCR RTPR SCHR1 SCHR2 SCHR3 SCHR4 SCRH SCRL SRER TBPR TCOR Reset Parallel Init Parallel Parallel Serial Init Serial Serial
IEEE 1284-Compatible Parallel Interface Controller CD1284
Table Channel Registers Parallel Pipeline (Selected Channel CAR)
Name DMABUF(H) DMABUF(L) HRSR HTVR LIVR PACR PCRR PFCR PFEP PFFP PFHR1 PFHR2 PFQR PFSR PFTR RLCR SDTCR SDTPR Reset Parallel Init Parallel Parallel Parallel Error Parallel Status Serial Init
Table Channel Registers Parallel Port (Selected Channel CAR) (Sheet
Name PCIER PCISR Reset Parallel Init Parallel Parallel Parallel Error Parallel Status
(EPP)1
(Manual)
(Manual)
CD1284 IEEE 1284-Compatible Parallel Interface Controller
Table Channel Registers Parallel Port (Selected Channel CAR) (Sheet
Name Reset Parallel Init Parallel Parallel Parallel Error Parallel Status
(RevRequest)
NOTE: Items parentheses denote Operational mode.
IEEE 1284-Compatible Parallel Interface Controller CD1284
Functional Description
Device Architecture
CD1284 described small computer system designed purpose sending receiving both serial parallel data. comprises RISC processor (Multi-Channel Processing Unit MPU), RAM, ROM, local interface logic, serial data channels, IEEE 1284-compliant parallel port with specialized data pipeline designed high-speed transfers. Architecturally, CD1284 devices merged into single unit. part modified, twochannel version Intel CD1400. other part specialized parallel interface port supported deep FIFO interface logic. interrupt structure CD1400 been enhanced include interrupt requirements parallel port. This section describes modified CD1400 core overall device architecture. Further sections provide details specific parallel channel. Chapter provides detailed descriptions encoding registers discussed this chapter. true RISC processor. addition having compact efficient instructions, `windowed' architecture that allows handle channel registers time. Before beginning operations given channel, loads internal Index register that forces accesses appropriate registers. Index register becomes part internal address allows direct addressing register bank hardware resources selected channel. address computation required select proper channel. This same windowed scheme carried through interface well (Figure channel-specific accesses, first loads (Channel Access register) with pointer channel accessed. Thereafter, read write operations occur with proper channel. software defines register address once this valid channels because part internal addressing.
CD1284 IEEE 1284-Compatible Parallel Interface Controller
Figure CD1284 Functional Block Diagram
PARALLEL PORT FIFO
PARALLEL PORT LOGIC
CONTROL STATE MACHINE INTERFACE LOGIC
INTERRUPT LOGIC CHANNEL LOGIC TIMING CHANNEL LOGIC TIMING
Figure Internal Address Generation
REGISTER ARRAY PARALLEL PORT REGISTERS (CHANNEL ADDRESS
ADDRESS GENERATION
CHANNEL REGISTERS
CHANNEL REGISTERS
serial data channels made `bit engines' that off-load task receiving transmitting each from MPU. When receiving data after processing complete bit, engines interrupt that perform next required task. example, takes adds character being assembled. When transmitting, sends engine next character being transmitted. concerned with basic timing; this task handled engines, leaving free perform higher-level processing, such detecting special characters.
IEEE 1284-Compatible Parallel Interface Controller CD1284
described above, Channel separate entity comprised FIFO data interface, well high-speed state machine that handles modes defined IEEE 1284 specification. Channel performs slave, peripheral, function IEEE 1284 interface programmed accept negotiations into defined modes. aids parallel port providing local access (through CAR) provides interrupt support (generation response). However, this only action where involved parallel port service-request activities.
Interface
interface comprises 8-bit bidirectional data bus, 7-bit address bus, 16-bit port control inputs identify type cycle occurring. Although strobe names basic timing match that Motorola 68000 family, CD1284 fits easily into environment. most cases, when reads writes internal CD1284 location, actually accesses location array serve bank registers. Some locations however, mapped actual hardware resources example, when hard output signal required (such servicerequest output SVRR) when necessary read actual state input (such modem input). CD1284 synchronous device. internal operations occur edges levels (phases) internal clock. internal clock generated dividing external (system) clock two. When performs cycle with CD1284, strobes; address, data sampled rising edges internal clock. illustrated Chapter 8.0, external control signals must meet setup times with respect system clock edges. Once cycle starts, sequence events locked clock CD1284. With events (address setup, write data setup, read data available) occurring predictable times. necessary design synchronous interface CD1284. asynchronous design, DTACK* (Data Transfer Acknowledge) signal indicates that CD1284 completed requested data transfer cycles except DMA. DTACK* input wait-state generation logic that pauses until operation complete. strobes (Chip Select Data Strobe) meet minimum setup time with respect system clock edge, CD1284 does detect request, cycle delays full-system clock cycles, meeting setup time. cycle commences follows predictable timing with DTACK* signaling end.
5.2.1
Read Cycles
Read cycles initiated when both inputs activated R/W* (read/ write) input high. strobes address inputs must meet setup times specified Chapter 8.0. Both signals must valid cycle start. Cycle times measured from whichever signals goes active last. CD1284 signals completion read cycle (placing data from addressed register data pins) activating DTACK*. read cycle terminates when removes DS*.
CD1284 IEEE 1284-Compatible Parallel Interface Controller
5.2.2
Write Cycles
Write cycle timing strobe activity nearly identical read cycles except that R/W* signal must held low. Write data, strobes, address inputs must meet setup hold times specified Chapter 8.0. DTACK* indicates that cycle complete CD1284 accepted data. Removing both terminates cycle.
5.2.3
Service-Acknowledge Cycles
Service-acknowledge cycles special-case read cycle. Timing basically same normal read cycle, SVCACK* inputs activated instead input slightly longer setup time required SVCACK* input than input). data that CD1284 provides during read cycle contents Interrupt Vector register associated with type request being acknowledged (RIVR receive, TIVR transmit, MIVR modem, PIVR parallel port) channel requesting service (see Section 5.3.1 more information). with read write cycles, DTACK* indicates cycle. When removes SVCACK* cycle terminates. When completed service routine writes EOSRR, subsequent cycle, started immediately, delayed approximately This time required internal processor complete activities associated with switch service-acknowledge context. These activities involve FIFO pointer updates restoration environment prior procedure. These must completed before internal registers modified CPU. situation occurs that attempts access before internal procedures complete, CD1284 holds cycle until ready. This does cause problem system designs that monitor DTACK*; cycle extended until DTACK* becomes active delay automatically met. system design does monitor DTACK*, mechanism must provided introduce required delay.
Warning:
Failure observe delay requirement cause device malfunction.
5.2.4
Cycles
CD1284 provides bidirectional 16-bit interface parallel port. This only direct data interface port; other 8-bit register accesses normal interface, described above. handshake between CD1284 circuitry uses signals: DMAREQ* (DMA Request) DMAACK* (DMA Acknowledge). address ignored during transfers. When internal conditions warrant transfer when FIFO falls below programmed threshold forward direction rises above threshold reverse direction) transfers enabled PFCR, device requests service driving DMAREQ* signal low. DMAREQ* remains active until FIFO less than empty locations remaining (forward direction) until FIFO less than bytes remaining (reverse direction). forward direction, controller logic responds placing data 16-bit data driving DMAACK* low. This cycle repeated until FIFO less than empty locations remaining there more data send. reverse direction, CD1284 responds active DMAACK* signal driving contents DMABUF register onto data bus.
IEEE 1284-Compatible Parallel Interface Controller CD1284
Odd-byte transfers reverse direction handled interrupt basis. When number bytes FIFO odd, bytes, except last, transferred number 16-bit cycles (two bytes cycle). byte remaining held PFHR1 interrupt generated when stale data timer expires. Status indicating that PFHR1 data shown PFSR. interrupt service routine must manually remove remaining byte from interface. forward direction, remaining byte directly written PFHR1 once last cycle complete. additional input signal determines endian format (whether least-significant byte data bits 15:8) 16-bit buffer. BYTESWAP selects whether lower upper byte buffer moves into FIFO data pipeline first forward direction from FIFO data pipeline buffer first reverse direction. BYTESWAP low, least-significant byte (DB[7:0]) immediately moves into data pipeline. BYTESWAP high, opposite occurs (DB[15:8] move into pipeline first). effective duration transfer block (burst) determined threshold value PFTR. Regardless where port moving data, when this threshold reached (exceeded receive; less than transmit) cycle begins remains active until FIFO less than bytes remaining (receive) less than empty locations remaining (transmit). SVRR provides determine cycle being requested. SVRR[7] true cycle currently being requested. This status indication provided general system status. Refer Chapter detailed information cycle options timing values.
Serial Port Service Requests
This section describes service-request structure serial ports CD1284. Refer Section detailed description parallel port service-request architecture. From point view, CD1284 operates three modes: normal operation, service request/acknowledge, DMA. Normal mode allows make changes obtain current operating status global per-channel basis. Service-request/acknowledge mode determines when particular channel requires service, example, when serial receive FIFO reached programmed threshold requires emptying. unique behavior CD1284 that service request only responded after device placed service-acknowledge `context'. This context switch occurs when request acknowledged, either activating appropriate SVCACK* input proper manipulation internal registers (software-activated mode). When detects condition channel that requires attention, posts service request internally externally. external request activation SVCREQ* output pins, depending whether type service needed receive, transmit, modem signal change. Included with internal request channel pointer channel requiring service. When service acknowledge begins, this pointer loaded into CAR, thus request automatically services proper channel. This purpose context switch, prepares CD1284 servicing proper channel.
CD1284 IEEE 1284-Compatible Parallel Interface Controller
completion acknowledge procedure, CD1284 must taken acknowledge context informing that procedure complete. This restores original internal state before context change. This operation occurs after performs `dummy' write EOSRR. Several registers within serial channel portion CD1284 only accessed when context switch been made. These Virtual registers. example, cannot place data directly serial transmit FIFO arbitrary time. must wait transmit service request indicating that FIFO empty, then acknowledge Once acknowledge procedure begins, transmit FIFO available loading. CD1284 makes requests service when enabled need exists. basic ways that made aware these service requests through hardware (interrupt) software (polling internal CD1284 registers). Which method dependent hardware/software design system; CD1284 functions well either environment. following section discusses trade-offs either basic method combine maximum performance.
5.3.1
Interrupts
term interrupt generalized description method where CD1284 gains attention CPU. Interrupt used interchangeably with `service request' same function. Interrupt often describes unconditional response part CPU. Whether this case, source still same service request from CD1284. Hardware signals generated CD1284 (SVCREQR*, SVCREQT*, SVCREQM*) connected interrupt input start interrupt service routine. service routine then begin servicing request from CD1284 starting acknowledge sequence. SVCREQ* outputs connected interrupt circuitry individually using three unique interrupt-level inputs they logically OR'ed together (not wire-OR'ed) into single interrupt applied interrupt-level input. latter case, examine SVRR determine which service requests active. method (single multiple interrupts) chosen designer dependent system requirements hardware and/or board-space limitations. CD1284 restrictions. likely that interrupt latency slightly shorter with first method since individual interrupt levels cause software vector directly correct service routine without first checking source interrupt. matter which interrupt method used, result same. Once recognized that service request active, service-acknowledge routine must executed process request. There ways start acknowledge force context switch: four hardware input pins making specific reads/writes internal registers.
5.3.2
DMAREQ* Parallel Interrupt Source
Interrupts generated FIFO threshold conditions; therefore, system design requires data move through interrupts, connect DMAREQ* directly interrupt input logically into same interrupt input SVCREQP*. DMAREQ* used generate interrupts, following required:
16-bit data interface must implemented support 16-bit reads DMABUF register. threshold value PFTR must initialized. DMAREQ* remains active until FIFO nearly empty (Rx) nearly full (Tx), followed
toggling DMAen data moved to/from FIFO through (refer Section 5.2.4).
IEEE 1284-Compatible Parallel Interface Controller CD1284
However, software easily change this clearing DMAen (PFCR[6]) start interrupt service routine resetting end.
SVCREQP* DMAREQ* logically OR'ed together, service routine must start
checking SVRR determine which signal active.
SVCACKP* must activated response DMAREQ* likewise, DMAACK* must
activated response SVCREQ*.
DMAdir (PFCR[5]) determine whether write read to/from DMABUF
register.
PFQR determine many reads 16-bit DMABUF register necessary
empty pipeline. Note however, four must added PFQR value, that number must then divided truncated nearest integer account extra four bytes holding registers 16-bit DMABUF register, well 16-bit reads instead 8-bit reads).
5.3.2.1
Hardware-Activated Context Switch Serial Channels
internal register manipulation involved context switch forced SVCACK* (Service Acknowledge input pins CD1284). There SVCACK* each service request type: SVCACKR* receive service requests, SVCACKT* transmit service requests, SVCACKM* modem signal-change service requests. Each these inputs special-case chip select. These cause CD1284 servicing that particular service request type requesting channel. Note that input activated service-acknowledge cycles. Instead, appropriate SVCACK* input DGRANT* inputs used. Later this section, DGRANT* discussed description about daisy-chaining CD1284 with more CD1400s. Figure shows generalized logic diagram hardware interface SVCACK* inputs. service acknowledge, SVCACK* address locations accessed instead location. CPU, service-acknowledge cycle read cycle. data that CD1284 places SVCACK* during read cycle contents appropriate Interrupt Vector register (RIVR, TIVR MIVR). These IVRs associated with active service-acknowledge input (SVCACKR*, SVCACKT*, SVCACKM*). upper five bits whatever previously loaded into LIVR CPU. lower three bits supplied CD1284 indicate type interrupt (vector). When CD1284 ready post service request serial channel, copies upper five bits LIVR into appropriate vector register (RIVR, TIVR, MIVR), then places request type vector lower three bits. Table shows assignment request type bits.
CD1284 IEEE 1284-Compatible Parallel Interface Controller
Figure Control Signal Generation
AD[6:0]
CD1284
SVCACKR* ADDRESS ADDRESS DECODE LOGIC SVCACKT* SVCACKM* SVCACKP* DATA
DB[7:0] DGRANT* CONTROL
R/W*
Table Request-Type Assignments
used Group Modem signal change service request Group Transmit data service request Group Received good data service request Parallel port state-machine requests service (refer Section 5.4) Parallel port data pipeline request service (refer Section 5.4) Both parallel port state-machine data pipeline request service (refer Section 5.4) Group Received exception data service request Request Type
transmit modem service-acknowledge cycles, data lower three bits redundant software because corresponding acknowledge occurred. These bits important case serial receive-data service acknowledge because they provide indication whether request `good' data exception data. They important parallel port because they indicate state-machine data pipeline both) requesting service. value contained upper five bits LIVR used number purposes. primary purpose LIVR source software vector used system index into interrupt dispatch table. However, systems that cannot this need these bits purpose. multiple-CD1284 designs that daisy-chaining, logical value place these bits chip identification number. This detailed daisy-chaining description Section 5.3.4.
IEEE 1284-Compatible Parallel Interface Controller CD1284
Another these bits channel encoding. This applicable single-CD1284 design design using daisy-chaining (requiring unique address range each device). This applies where value LIVR vector hardware interrupt response necessary. Since each channel LIVR, these five bits have unique value identifying channel. There need read RICR, TICR, MICR find channel number; single operation, determines both type interrupt number channel requesting service. With five bits available, systems with small numbers CD1284s able encode both channel number chip identification number LIVR. Once acknowledge procedure complete, CD1284 ready serviced type interrupt acknowledged. example, interrupt receive good data, would read RDCR determine number characters available receive FIFO. then reads same number characters, successive reads, from RDSR. Other tasks, such disabling future interrupts changing channel parameters, could also performed this time. Once tasks involved servicing interrupt complete, more operation performed. inform CD1284 that service acknowledge complete, writes dummy value EOSRR. Although data written does matter, write operation important. This write forces internal context switch back normal operating mode.
5.3.2.2
Summary Interrupt Driven Service Requests, Serial Channels
actions that occur during interrupt request/service are:
senses service request from CD1284 service-request outputs through
interrupt request input.
responds performing read cycle activate appropriate SVCACK* input
pin.
decodes value read from vector register during step decides type
service request necessary).
reads R/T/M/ICR determine channel number. services request (load transmit FIFO, read receive FIFO, on). writes dummy value EOSRR terminate service routine.
5.3.2.3 Common Service Acknowledge
method hardware-activated, service-acknowledge request common service acknowledge. this method, SVCACKx* inputs tied together driven from same source. this configuration, CD1284 internally prioritizes acknowledge receive, transmit, parallel, modem. device both receive parallel request pending, common acknowledge causes respond with vector receiver. Then subsequent service acknowledge allows parallel channel request serviced.
5.3.2.4
Software-Activated Context Switch Serial Channels
possible, manipulation some internal registers, cause context switch without activating SVCACK* hardware inputs. method same used poll-mode- CD1284 design. Once detected service request through interrupt response circuitry, follows same procedures that polling method uses when detects active service request. Refer context switching description following section.
CD1284 IEEE 1284-Compatible Parallel Interface Controller
reason design might make this method that limited board space available additional hardware address decoding required generate four SVCACK* DGRANT* control signals. advantage that system need constantly poll CD1284 active service requests. interrupted when request posted, then examines internal CD1284 registers determine source channel number generating request. this method, four SVCACK* DGRANT* input pins inactive (logic `1'). This prevents possible false activation service-acknowledge cycle that occurs noise. Terminate these pins with resistor (approximately hardwired VCC.
5.3.3
Serial Service Request Polling
Poll mode, periodically checks CD1284 there active service requests. detects any, proceeds service them software-driven technique. There several registers within CD1284 specifically provided facilitate Poll-mode service-request detection acknowledgment. These SVRR, RIR, TIR, PIR, MIR, RIVR, TIVR, MIVR. Chapter provides detailed definitions these registers. SVRR master service-request register. least-significant three bits (bits SRM, SRT, SRR) reflect inverse state three service-request output pins (SVCREQM*, SVCREQT*, SVCREQR*). example, SRR[0] `1', indicates that there pending active serial receive data service request, that SVCREQR* output active (low). determine with single read CD1284 requires service which pins active. Each service request type interrupt request register: receive, transmit, modem. These special purpose registers used with force context switch start service-acknowledge procedure. When service request particular type pending, corresponding Interrupt Request register with appropriate data cause context switch requested type requesting channel. When ready service request, reads contents request register copies into CAR. This write into forces context switch CD1284 ready serviced. result same performing service-acknowledge cycle with SVCACK* pin. Each Interrupt Request registers provide channel number requesting service least-significant bits. most-significant three bits provide status control over internal interrupt sequencing. middle three bits contain code used hardware service-acknowledge cycle (write EOSRR) indicate type acknowledge cycle that ending. Each three registers unique code these three bits select proper service-acknowledge type, these meaningless Poll-mode operation. service-request operation, must inform CD1284 that request satisfied take service-request context. This done rewriting value that interrupt request register after clearing upper bits. with hardware-driven request/acknowledge procedure, Virtual registers should only accessed after context switch made. Their contents undefined until this time.
IEEE 1284-Compatible Parallel Interface Controller CD1284
5.3.3.1
Summary Serial Poll-Mode Service Requests
major steps involved Poll-mode sequence are: scans SVRR periodically, checking three least-significant bits. them true (`1'), service request active. Depending which service-request bits active, reads appropriate interrupt request register (RIR, TIR, MIR) copies contents into CAR. Performs service routine. Writes original contents interrupt request register back with most-significant bits cleared.
5.3.4
Daisy-Chaining Service Requests with CD1400s
CD1284 combined with other CD1284 CD1400 devices form systems with more than serial channels parallel channel. There number ways that these connected, provides more efficient sequence. This method allows CD1284s and/or CD1400s arbitrate between themselves. This mode only works hardware-activated service acknowledges being utilized. Fair Share mechanism functional parallel channel service-request (SVCREQP*) outputs. Therefore, CD1284s daisy-chained SVCREQP* SVCACKP* kept separate. serial channel requests acknowledges identical those CD1400 they connected equivalent requests acknowledges CD1284. CD1284 provides means daisy-chaining service request service acknowledgments more devices. This allows them arbitrate priorities between themselves regarding which post particular type service request. This Fair Share interrupt scheme. Figure page illustrates connection CD1284s enable Fair Share function. request outputs particular type from CD1284s (SVCREQR*, SVCREQT*, SVCREQM*) wire-OR'ed together form combined request each type; SVCREQP* each kept separate. This allows both devices monitor state others output. (SVCACKR*, SVCACKT*, SVCACKM*) connected together form acknowledge each type. Note, SVCACKP* driven individually. DGRANT* input first CD1284 connected ground; DPASS* output first CD1284 drives DGRANT* input second.
CD1284 IEEE 1284-Compatible Parallel Interface Controller
Figure CD1284 Daisy-Chain Connections
SVCREQP* SVCREQM* SVCREQT* SVCREQR* DGRANT* DPASS*
SVCREQP* SVCREQM* SVCREQT* SVCREQR* DPASS* DGRANT*
CYCLE ERROR
ADDRESS DECODE LOGIC
SVCACKP* SVCACKM* SVCACKT* SVCACKR*
SVCACKP* SVCACKM* SVCACKT* SVCACKR*
Before serial request service particular type posted, checks current state request output that type. inactive, indicating that other CD1284 driving that level, request posted; otherwise waits. This guarantees that each CD1284 opportunity have request type serviced when required. When acknowledges request, both CD1284s receive acknowledge through SVCACK*. However, only first receives DGRANT*. there active request this type pending, CD1284 takes acknowledge drives vector register (RIVR, TIVR, MIVR) onto data bus. first device does have request pending, passes DGRANT* input second CD1284 through DPASS* output. Assuming that second device active request pending, takes acknowledge drives Vector register onto data bus. previously mentioned, upper five bits LIVR reflects what loaded into them during initialization CD1284s. These bits used unique chip identification number determine which CD1284 responded service acknowledge. These five bits binary LIVRs first CD1284, binary those second. able test determine which device responded. Some examples serviceacknowledge software routines that show performing this task provided Chapter 6.0. common service acknowledge described Section 5.3.2.3 page also usable daisychained environments. this case, common acknowledge applied serviceacknowledge inputs devices chain. daisy-grant ripples down chain until requesting device receives acknowledge. Note: CD1284 further down chain requesting service receiver chain requesting service transmitter, transmit request serviced first since precedes receive requester. Thus, Fair Share mechanism functional this configuration.
IEEE 1284-Compatible Parallel Interface Controller CD1284
CD1284 fairness override, Unfair (PACR[0]). this set, Fair Share function device defeated posts requests service regardless state external service-request signal. Even when device chain asserting request particular type, another device needs post request, proceeds regardless current state request because fair bits forced true. upstream from device already posting request pipeline responded previous request from downstream device, then upstream device accepts acknowledge arrival overrides priority normally given device that made first request. This useful system designs that wire-OR request signals together, rather than using external gate, since these cases, without overriding fairness request type within device holds request different type. example, existing transmit request prevents device from posting receive request. Note: (IMPORTANT) CD1284 chain pending request, daisy-grant passes last none respond. This causes cycle hang DTACK* generated). only time this happens when error condition outside CD1284s cause respond request that made. mechanism provided terminate abort cycle this error occurs. This accomplished with timeout circuitry. Otherwise DPASS* output last CD1284 activates abort condition. Other devices, such CD1400, share daisy-chain mechanism connected DPASS* output last CD1284 chain. actual implementation system-dependent, important provide some know that cycle complete normally device responds acknowledge cycle.
Parallel Port Service Requests
parallel port service-request structure CD1284 slightly different from that serial ports. These differences highlighted this section. Service requests derive from internal sources: data pipeline parallel port state machine (see Figure page 45). data pipeline internal service request becomes active, Pipeline (PIR[5]) set; likewise, parallel port state machine internal service request becomes active, PPort (PIR[6]) set. Internal service requests from these sources monitored through Pipeline PPort bits microcode running internal MPU. When either both) these bits detected active, microcode sets PPireq (PIR[7]). PPireq also mirrored (SVRR[3]). SVRR useful polled systems because allows detection service requests, well parallel port service requests with single register read operation. Both internal sources service requests within parallel channel have their enable functions. Interrupts from data pipeline enabled through PFCR; interrupts from parallel port state machine enabled through PCIER. PFCR enable bits: normal interrupts (such tagged data being received), data errors (such write holding register that already holds data). first type interrupt enabled through IntEn (PFCR[4]). second type interrupt enabled through ErrEn (PFCR[1]). Note that IntEn must ErrEn generate interrupt; however, need enable error interrupts does require notification these types errors. error interrupt generated DataErr (PFSR[0]) non-zero. this case, indicates cause error interrupt. parallel channel-control state machine generate types interrupts. Each these enable PCIER:
CD1284 IEEE 1284-Compatible Parallel Interface Controller
NegCh negotiation changes SigCh signal changes port status inputs (Manual mode only) EPPAW protocol address writes DirCh direction changes parallel channel IDReq slave requests from remote master. nINIT initialization pulses from master (Compatibility mode only)
these bits set, based mode operation. NegCh interrupt issued whenever remote master performs protocol change, such moving from Compatibility mode ECP; examines determine state parallel interface. Signal changes identified reading SSR. response EPPAW interrupt, would read retrieve value that written during address write cycle.
IEEE 1284-Compatible Parallel Interface Controller CD1284
Figure Interrupt Generation Logic
KEY:[]= Currentmode Interface extensibility request value (see IEEE1284 Spec. more details) (register name[x]) that PCIER[1] PCIER, FAILED (INVALID EXTCODE) [COMPATIBLE MODE] NSR=0x41 TERMINATION [COMPATIBLE NEG-OK MODE]
IDREQ PCIER[1] IDREQ PCISR[1]
NEG-OK
NSR=0x82
NSR=0x89[RN REQUEST]{04} NSR=0x8B[RB REQUEST]{05} NSR=0x8D[ECP REQUEST]{14} NSR=0x8F[ECP REQUEST]{34} NEGCH NSR=0x16 (EPP) PCIER[5] NSR=0x18 (RN) NSR=0x19 (RN-ID) NSR=0x1A (RB) NSR=0x1B (RB-ID) NSR=0x1C (ECP) NSR=0x1D (ECP-ID) NSR=0x1E (ECP-RLE) NSR=0x1F (ECP-RLE-ID)
NSR=0x46 (EPP) NSR=0x48 (RN) NSR=0x49 (RN-ID) NSR=0x4A (RB) NSR=0x4B (RB-ID) NSR=0x4C (ECP) NSR=0x4D (ECP-ID) NSR=0x4E (ECP-RLE) NSR=0x4F (ECP-RLE-ID) FAILED MODE ENABLED [COMPATIBLE MODE]
NSR=0x86[EPP MODE]{40} NSR=0x88[RN MODE] {00} NSR=0x8A[RB NSR=0x22 MODE]{01} NSR=0x8C[ECP RLE]{10} NSR=0x8E[ECP RLE]{30}
NEGCH PCISR[5]
HOST-TIMEOUT HOST RESPONDED OVER SEC.) [COMPATIBLE MODE]
INVALID/ImedTerm HOST VIOLATED HANDSHAKING SEQUENCE [COMPATIBLE MODE]
requests will fail either negotiation type disabled NER. Other negotiations will also fail negotiation type disabled.
immediate termination from Host will generate this interrupt
CD1284 IEEE 1284-Compatible Parallel Interface Controller
Figure Interrupt Generation Logic (Continued)
A1284 signal transition from lowto-high, A1284(ODR[3]) nInit signal transition from low-to-high, nInit(ODR[2]) HstBsy signal transition from lowto-high, HstBsy(ODR[1]) HstClk signal transition from lowto-high, HstClk(ODR[0]) Interface must COMPATIBLE MODE when MANMD (PCR.7) MANMD have affect
MANMD (PCR[7]) SIGCH (PCIER[4])
SIGCH (PCISR[4])
A1284 signal transition from high-to-low, A1284(ZDR[3])
nInit signal transition from high low, nInit(ZDR[2])
HstBsy signal transition from highto-low, HstBsy(ZDR[1])
HstClk signal transition from high-to-low, HstClk(ZDR[0])
Host reversed direction interface from ECPforward ECP-reverse driving nReverseRequest (nInit) signal low.
address received parallel port EPPAW (PCIER[3])
EPPAW (PCISR[3]) DIRCH (PCISR[2])
Host changed direction interface from ECPreverse ECP-forward driving nReverseRequest (nInit) signal high. (PCISR[5]) (PCISR[4]) (PCISR[3]) NEGCH SIGCH EPPAW
Compatible mode, host requested peripheral re-initialize itself (nInit went low). nInit (PCIER[0]) INTEN (PFCR[4])
(PCISR[2]) (PCISR[1]) (PCISR[0]) DIRCH IDREQ NINIT
NINIT (PCISR[0])
PPORT (PIR[6])
IEEE 1284-Compatible Parallel Interface Controller CD1284
Figure Interrupt Generation Logic (Continued)
DMAwrerr (DER[7]) (DMAACK* DMAREQ*) DMArderr (DER[6]) (DMAACK* DMAREQ*) Bufwrerr (DER[5]) (write non-empty DMABUF) Bufrderr (DER[4]) (Read from empty DMABUF) ErrEn (PFCR[1]) DataErr (PFSR[0])
HR1wrerr (DER[3]) (write nonempty HR1)
HR1rderr (DER[2]) (Read from empty HR1))
HR2wrerr (DER[1]) (Write nonempty HR2)
HR2rderr (DER[0]) (Read from empty HR2) Interface forward direction, PFHR2 full, PFHR1 empty, Timeout (PFSR[5]) set.
OneChar (PFSR[1])
Stale (PFSR[3]) transitions from false true and: DataErr (PFSR[0]) disabled. OneChar (PFSR[1]) Timeout (PFSR[5]) enabled, DMABUF empty (else, DMAREQ* generated, then timeout interrupt generated when DMABUF empty cycles complete. IntEn (PFCR[4])
Timeout (PFSR[5])
Pipeline (PIR[5])
PPort (PIR[6])
Pipeline (PIR[5])
PPireq (PIR[7]) (SVRR[3])
CD1284 IEEE 1284-Compatible Parallel Interface Controller
direction change (DirCh) interrupt occurs when remote master reversed interface from forward reverse reverse forward. IDReq interrupt generated when remote master issues Request command during IEEE 1284 negotiations. normal response local send string after reversing direction data pipeline setting DMAdir `1'. interrupt-driven system, with serial channel requests, SVCREQP* output normally connects local interrupt control inputs. also OR'ed together, through external gate, with serial request outputs produce single interrupt request local CPU. interrupt service routine scans SVRR determines actual source interrupt. parallel channel same Vector register arrangement serial channels. LIVR must initialized local same manner serial channels; upper five bits defined local value appropriate system design. lower three bits should initialized zero during programming LIVR, however they `don't cares' masked PIVR provide vector indicating source type request from parallel channel. Access parallel channel LIVR made first setting `x'00', making Channel Zero register accessible. Since LIVR read/write register, local read time. When read during normal read cycle, returns original value written When service acknowledge performed, upper five bits LIVR copied into PIVR. encoding three least-significant bits PIVR during service acknowledge cycle indicates which functional blocks parallel channel requesting service follows:
(Bit (Bit (Bit Requestor Channel control state machine Data pipeline Both
encoding parallel channel service-request status designed using remaining unused states CD1400: `100', `101', `110'. other states these three bits already used indicate serial interrupt status RIVR, TIVR, MIVR.
5.4.1
Hardware-Activated Context Switch, Parallel
When conditions within parallel channel require attention, request made SVCREQP* output. system interrupt driven, this output would connected interrupt generation circuitry. hardware-activated service-acknowledge system, responds request activating SVCACKP* input (along with DGRANT* DS*) same manner serial channels; input used must remain inactive (high). CD1284 responds SVCACKP* cycle driving contents PIVR onto data with IT2-IT0 encoded shown above. SVCACK cycle also places device correct context service parallel channel request. vector supplied PIVR indicates which block parallel channel requested service; cause request indicated Request Status registers each: PCISR channel control state-machine block and/or PFSR data pipeline block. Refer Chapter detailed descriptions various status bits these registers.
IEEE 1284-Compatible Parallel Interface Controller CD1284
cycle that activates SVCACKP* input also removes active SVCREQP* output. request output inactive until after terminates acknowledge routine writing EOSRR. with serial channels, this dummy operation data written `don't care'. purpose write clear internal logic current request context allow generate another request when need arises. Until this write occurs, further service requests made from parallel channel. When detects write EOSRR, zeros-out PIVR preparation next service-request cycle.
5.4.2
Software-Activated Context Switch, Parallel
Software-activated acknowledges parallel channel differ somewhat from those serial channels. start software acknowledge parallel channel same serial channels: copies contents into (after first saving current contents CAR) device context. However, this point methods (serial versus parallel) diverge. read either LIVR PIVR read status from status registers Parallel Port register set) determine which parallel channel blocks requesting service, copy into just load with `x'00') context, then proceed service that request. Once satisfied request needs parallel channel, must toggle IntEn (PFCR[4]) clear PIR. Toggling IntEn clears PPort Pipeline bits PPIreq (PIR[7]). This action informs clean PIVR remove external request. software should then restore previous contents exit service routine. PPIreq cleared time CPU. system design requires request removed quickly, procedure performed beginning polled service routine. waits until service routine, clears itself terminates service manner described, letting
Serial Data Reception Transmission
CD1284 serial channels, each with receiver transmitter. Although receiver transmitter pair associated with each channel, many respects they operate independently, sharing only parameter settings regarding character format including length, parity type any, number stop bits. Each receiver transmitter baud rate generation function, allowing channel send rate receive another. Shared independent parameters shown following diagram.
RECEIVER BAUD RATE TRANSMITTER BAUD RATE PARITY CHARACTER LENGTH STOP BITS PRESCALE PERIOD REGISTER FIFO THRESH TIMEOUT
CD1284 IEEE 1284-Compatible Parallel Interface Controller
Channel service needs, such empty transmit FIFO, indicated three service-request indicators: receivers, transmitters, modem signal changes. internal processor (MPU) scans each channel sequentially service needs, posting request when detects particular type. continues Fair Share scheme used external daisy-chain configuration allowing channel post another request type until other channels have posted their requests that type, any. example, channel currently being serviced transmit request channel three pending, request from channel three posted before channel able make another request transmit service. Each receiver transmitter 12-character FIFO. receiver additional character holding locations: Receive Character Holding Receiver Shift registers. transmitter also additional locations, Transmitter Holding Transmitter Shift registers. receive FIFO programmable threshold that sets level which service request posted. When data reaches this FIFO-full threshold, request made empty FIFO (for details Section 5.5.1). Receive FIFOs also have programmable threshold that, when reached, causes output deasserted (see flow-control description). asynchronous serial data protocol, message consists `character,' made bits, either high low, representing value. character from five eight bits plus optional parity bracketed start stop bit. Each time duration that sets data transmission rate baud rate. start indicates beginning character bitstream indicated transition from logic logic (mark space) transmission media. start lasts `bit-time' immediately followed data bits (8:5), parity any, stop bit. previously discussed, CD1284 incorporates special hardware receive transmit each bit. These `bit engines'. They perform timing associated with sending receiving serial data bit. engine behaves differently depending whether sending receiving. When complete received, engine interrupts that handle character level. This usually entails addition character being assembled. transmitting, transmit engine interrupt causes give next transmit. engine interrupt occurs time that timed engine, thus removing that duty from MPU.
5.5.1
Receiver Operation
Each channel programmed receive characters with several different parameters, such character length, parity, number stop bits, FIFO threshold, baud rate. Each receiver independent other receiver. also different baud rate from corresponding transmitter. Before valid data received, must each channel programming desired operational parameters COR1-COR5, BRRR, RCOR, RBPR. Once these registers set, channel enabled issuing receiver enable command through enabling service requests SRER. Once receiver enabled, engine begins scan input valid start bit. does this detecting falling edge transition input. When transition detected, engine delays until middle programmed time rechecks input. input still low, start considered valid character assembly begins. each subsequent full time, input checked level recorded value next bit. center time, input returns mark state, then start considered invalid engine returns start detect mode.
IEEE 1284-Compatible Parallel Interface Controller CD1284
Following valid start bit, engine begins receiving data bits. programmed number bits, following bits checked parity enabled) valid stop bit. valid stop defined mark logic input. valid stop detected, framing error noted character. After properly assembled framing error) character been received, checked several special conditions (see Section Section 5.7) overrun condition before placed receive FIFO. errors special character processing required, character considered `good' data placed directly FIFO. errors exist, placed FIFO `exception' data along with status indicating type error. each good character placed FIFO, RDCR (Receive Data Count register) updated reflect number good characters currently FIFO. receive FIFO programmable threshold determine level where CD1284 requests receive data service. This level programmed through RxTh[3:0] bits (COR3[3:0]). threshold number characters from Note: This only sets level where CD1284 posts service request depth FIFO. When responds receive good data service request, read number characters FIFO, from zero number indicated RDCR before exiting service routine. number read zero, CD1284 posts another request service almost immediately. number characters read less than number indicated RDCR, enough that number FIFO falls below threshold, request made until threshold once again exceeded. Since circularly scans channels, another channel post receive service request before this channel opportunity, this request service posted `almost immediately'.
5.5.2
Receiver Timer Operations
Also associated with each receiver FIFO timer that duration RTPR. This timer provides services relation receive FIFO operation: timeout prevent `stale' data FIFO timeout after last character removed from FIFO. first type, type occurs receive FIFO does reach threshold before programmed time period expires. second type, type occurs timer expires data been placed FIFO after last character removed this NNDT Data Timeout) service request. timer driven prescaled clock selected Global register set. This timer loaded with value contained RTPR each time character placed receive FIFO when last character removed from FIFO. Each `tick' prescaler decrements timer. timer reaches zero receiver interrupts enabled, generates receive data service request valid timeout condition.
Type
there characters FIFO threshold level been reached, good data service request posted when timer expires. This function provided prevent data from remaining FIFO long (potentially infinite) periods time because remote send enough data fill FIFO threshold level. This timeout cannot disabled.
CD1284 IEEE 1284-Compatible Parallel Interface Controller
Type
there data FIFO when timer expires NNDT service request enabled SRER, receive exception service request posted with status indicating timeout condition. This timeout optional provided that driver software detect possible block data allow buffers flushed higher, operating system level. NNDT posted only first occurrence timeout after FIFO becomes empty. Also note that NNDT timer started last character removed from FIFO exception character, such break parity error. Figure page shows timer process evaluation performed when timer reaches zero.
5.5.3
Receive Exceptions
Several conditions cause CD1284 post receive exception service request. exception condition occurs, bytes placed receive FIFO. first byte contains status indicating type error; second byte contains data. Exception data sent event time. That there separate service request each character received with special conditions. when exception condition occurs receive FIFO contains good data, good data receive service request immediately posted upon receipt data. This happens regardless number characters FIFO programmed threshold. This allows remove data FIFO ahead exception data that CD1284 post service request error condition. Once service-acknowledge procedure good data terminated, service request posted exception data. When acknowledges receive exception service request, first reads RDSR determine status then retrieve data. Reading data optional: FIFO read twice during service routine, CD1284 updates internal FIFO pointers appropriately discards second byte. Note: need actually read data from FIFO during exception service acknowledge FIFO pointers correctly updated service routine, discarding both status data. this way, must least read status permanently lost.) Another special case exception data handling received line break conditions. line break character with start bit, data, parity stop bit. this case, null (`0') character placed FIFO with break condition indicated accompanying status, receive exception service request posted. However, regardless length break, only character placed FIFO. Resumption normal character reception causes data again placed FIFO.
IEEE 1284-Compatible Parallel Interface Controller CD1284
Figure FIFO Timer Processing
FROM OTHER BACKGROUND PROCESSING
BACKGROUND SCANNING DETECTS CHARACTER ARRIVED TIMER CHARACTER FIFO RELOAD TIMER FIFO EMPTY RESUME BACKGROUND SCANNING LOOP POST RECEIVE `GOOD DATA' SERVICE REQUEST
DATA TIMEOUT ENABLED
DATA INTERNAL FLAG ARMED CLEAR NONEWDATA INTERNAL FLAG
POST RECEIVE EXCEPTION SERVICE REQUEST
RESUME BACKGROUND SCANNING LOOP
CD1284 IEEE 1284-Compatible Parallel Interface Controller
5.5.4
Transmitter Operation
Each serial channels CD1284 capable transmitting characters with number programmable characteristics such length, parity, baud rate. channels operate independently settings have effect operation other. After being reset from either hardware (RESET* input pin) software master reset command CCR), transmitters disabled with output held logic condition. This `off' `mark' condition asynchronous protocol. Before operation transmitter begin, must program appropriate parameters CORs, TCOR, TBPR. Once these registers set, channel enabled issuing transmit enable command through CCR, enabling service requests setting appropriate transmit enable request bits SRER. channel then immediately posts transmit service request since FIFO empty. responds request loading characters into transmit FIFO through after places CD1284 Service-Request Acknowledge mode (see description procedures Section 5.2.3). transmitter does begin transmitting characters until terminates service routine writes EOSRR. Transmission begins sending start logic `0') followed five eight data bits (depending programmed value), least-significant first. last data followed appropriate parity bit, enabled, minimum stop bit. transmission handled transmit engine with sending each requested. there still characters FIFO, next transmitted immediately after last stop previous character. This process continues until characters FIFO transmitted. that time CD1284 posts service request more data. There actually transmit character holding locations each channel: FIFO, Transmitter Holding register, Transmitter Shift register. CD1284 programmed per-channel basis request transmit data when conditions exist: When last character FIFO transferred holding register, When last data last character shifted Transmitter Shift register. Option number allows character transmit times reload FIFO prevent transmit data underrun. This normal mode operation. Option number ensures that transmitter empty before reconfiguring channel. likely that transmitter underrun occurs option number selected, unless sufficiently fast respond transmit service request reload FIFO during transmission stop bit(s) last character. transmitter underruns, continues send stop bits (mark) until more data placed FIFO. Normally, when string characters greater than being transmitted, software programs CD1284 transmitter post service request when FIFO empty. When last data send placed FIFO, service request enable changed that requests made after last character sent. This notifies that data transmitted before disabling channel. channel disabled without first being emptied, characters other than currently being transmitted held transmitter enters marking state. channel subsequently reenabled, remaining data transmitted.
IEEE 1284-Compatible Parallel Interface Controller CD1284
transmitter capable performing several special functions such break generation, intercharacter delays, automatic flow control. These functions discussed Section 5.6, Section 5.7, Section 5.8. with receiver, transmitter timer associated with This timer generates timing embedded transmit commands that send line breaks inter-character delays. Whenever detects embedded transmit command specifying delay command, this timer loaded with value contained parameter byte. Then timer decremented each tick (prescaler timer) until reaches zero. that time, delay terminates unless next character FIFO beginning another delay command sequence.
Flow Control
data communications applications, data sent from system another protocol. Most systems have method buffering data transmission reception. asynchronous protocol, there protocol level determine length data transmission. Therefore, normally possible designate buffer area handle entire length transmission. Also, hardware receiving data generally limited amount buffer area usually FIFO and, does unload data fast enough, buffer FIFO overflow. these reasons, methods provided stop remote from sending data until there space receive data. This known flow control. Flow control in-band out-of-band. In-band flow control uses special characters that sent stop data transmission. Out-of-band flow control signals outside serial data channel that perform same function: RTS* (Request Send) CTS* (Clear Send) signal set, DSR* (Data Ready) DTR* (Data Terminal Ready) signals. CD1284 supports manual flow control built-in capabilities automatic and/or semiautomatic (depending direction options) implementation without intervention.
5.6.1
In-Band Flow Control
In-band flow control implemented special characters imbedded serial data stream; request that transmission stop request that data transmission resume. character selected, although conventionally, (x'11) XOFF (x'13) characters selected ASCII character being used. XOFF designates character used stop data transmission. determines character used resume transmission. Whether these characters used, CD1284 allows characters value appropriate system design value programmed SCHR1 SCHR2 (Special Character register SCHR1 defines character SCHR2 defines XOFF character. These registers must initialized CPU; default value loaded during device reset `x'00'.
5.6.2
Receiver In-Band Flow Control
When senses that sender requires flow-control receive buffer filling fast service, request remote stop transmission transmitter sending XOFF character. This accomplished issuing send special character command through CCR. CD1284 then transmits character programmed SCHR2.
CD1284 IEEE 1284-Compatible Parallel Interface Controller
previously discussed, send special character command preemptive data currently transmit FIFO. XOFF character transmitted immediately after current character character Transmitter Holding register sent maximum delay character times). When again ready start receiving characters, character sent another send special character command. this time, CD1284 issued command send character programmed SCHR1. Send special character commands override flow-control remote CD1284. example, even CD1284 transmitter shut remote, still send flow control characters. current state flow-control condition always made available through CCSR. addition enabled/disabled status receiver transmitter, CCSR displays flow-control status. bits CCSR pertain receiver flow control, RxFloff RxFlon. Whenever issues send special character (send XOFF) command, CD1284 sets RxFloff bit, indicating request remote stop transmission. When issues send special character (send XON) command, RxFlon RxFloff reset. RxFlon remains until first character received after transmitted. Table shows encoding RxFloff RxFlon. Table CCSR[6:5] Encoding
RxFloff RxFlon Encoded Status Transmission resumes, receiver enabled/disabled, receiver default reset state. sent, transmission restarted. XOFF sent. used.
RxFloff RxFlon cleared whenever receiver disabled enabled, regardless state flow control when disable/enable occurred. Note: Regardless current state RxFloff, CD1284 continues receive characters. remote ignores slow respond XOFF character, there overrun condition occur.
5.6.2.1
Transmitter In-Band Flow Control
CD1284 automatically flow control transmitter when receives XOFF characters, programmed SCHR1 SCHR2. There control bits COR2 COR3 enable disable various aspects automatic flow control. Special-character detection must enabled through SCD12 (COR3[4]) flow-control characters acted upon. When SCD12 set, CD1284 scans received characters match with special characters programmed SCHR1-SCHR2.
IEEE 1284-Compatible Parallel Interface Controller CD1284
enabled SCD12 character matching contents SCHR2 received (the XOFF character), CD1284 checks that automatic transmit in-band flow control enabled COR2[6]. this function enabled, CD1284 stops transmission after current transmitting character character Transmitter Holding register, any, sent. enabled, CD1284 also attempts match against errored characters. This function enabled CMOE (COR5[5]). COR2[7] enables (Implied mode), which determines character that restarts transmission after stop automatic flow control. (COR2[7]) `0', only programmed character (SCHR1) restart transmitter; other characters received placed FIFO. reset, character received restarts data transmission. TxIBE (COR2[6]) must active automatic flow control, otherwise (COR2[7]) effect. with receiver flow control, determine current state transmitter through TXFloff TxFlon (CCSR[2:1]). When automatic in-band flow control enabled CD1284 receives XOFF character, TxFloff set. When character received, TxFlon set. Once transmission resumes, TxFlon cleared. encoding TxFloff TxFlon shown Table Table CCSR[2:1] Encoding
TxFloff TxFlon Encoded Status Transmission resumes, transmitter enabled/disabled, transmitter default reset state. received, transmission restarted. XOFF received, transmission stopped. used.
TxFloff TxFlon cleared whenever transmitter disabled enabled, regardless state flow control when disable/enable occurred. This feature force transmission resume regardless remote-initiated flow control. final aspect automatic in-band flow control (Flow Control Transparency). enabled/disabled COR3[5] determines remote-initiated flow control transparent CPU. set, addition stopping transmission when XOFF character received, CD1284 places received XOFF character receive FIFO informs with receive exception service request. When character received, also sent exception service request, then restarts data transmission. enabled, received flow control characters control transmission, discarded instead being placed FIFO. does require know when transmit data been stopped, this reduce number service requests that must handled. Table summarizes control bits CORs that enable various modes in-band flow control.
CD1284 IEEE 1284-Compatible Parallel Interface Controller
Table Control Bits
Name SCD12 TxIBE Register COR3 COR3 COR2 COR2 Function Enables recognition special characters Enables transparent flow control Enables automatic transmitter inband flow control Enables implied mode
5.6.3
Out-of-Band Flow Control
Flow control also accomplished through modem handshake signal pairs RTS/CTS DSR/DTR. These called out-of-band because they external data channel. CD1284 programmed automatically respond generate out-of-band flow control through these signals.
5.6.3.1
Receiver Out-of-Band Flow Control
Along with receiver FIFO threshold that sets level where CD1284 posts service request, another threshold determine when automatically asserts/deasserts DTR*. This threshold enabled DTRth[3:0] bits (MCOR1[3:0]). level number characters from threshold zero disables function DTR* controlled device. function receiver enabled, CD1284 automatically asserts DTR* output whenever number characters receive FIFO less than programmed number. Once level reaches threshold, DTR* deasserted. DTR* held deasserted state until removes enough characters from FIFO lower level below threshold. receiver operate properly, threshold must value equal higher than receiver service-request threshold. levels were reversed, normal character reception could completed because DTR* would always deasserted before receive FIFO threshold reached. would then receive data service request until receive FIFO timeout reached. This would result serial data transmission performance limitation. DTR* output also manually controlled through MSVR2[1]. Setting this asserts DTR* output.
5.6.3.2
Transmitter Out-of-Band Flow Control
Transmitter out-of-band flow control implemented with three modem control signals: RTS* output CTS* DSR* inputs. RTS* output programmed automatically asserted whenever there data transmit FIFO transmitter cleared send. CTS* DSR* enabled automatically control transmitter. Automatic Output enabled RtsAO (COR2[2]). RtsAO set, CD1284 automatically asserts RTS* output when there data FIFO send. When data sent FIFO empty, RTS* deasserted until places more data FIFO. RTSAO required remote, must manually control RTS* output through MSVR1[0].
IEEE 1284-Compatible Parallel Interface Controller CD1284
CTS* input also monitored CD1284 transmitter enable. functions enabled setting CtsAE (COR2[1]). CtsAE set, character transmission occurs only when CTS* input signal asserted. signal deasserted during active transmission, current character plus character Transmitter Holding register transmitted transmission ceases. Thus, minimum maximum characters transmitted after control signal deasserted. Transmission resumes when signal(s) reasserted. send special character command does sample CTS* DSR* inputs. opts send special characters, character transmitted regardless state these inputs. This preferable still flow control remote even being flow controlled. state CTS* DSR* important, they should tested through MSVR1[7:6] before special character send command issued.
5.6.4
Modem Signals General-Purpose
Each channel CD1284 four pins that used either modem-control generalpurpose input/output pins. modem signal names assigned these four pins provide easy reference system designers. fact, they simply general-purpose inputs outputs automatic out-of-band flow-control used) individually controlled MSVRs. Since they general-purpose, system designers connect pins suit application.
DCE, Application
When system software design opts automatic out-of-band flow control, then signal naming convention longer holds true some cases, depending device used DTE. this case, these pins within CD1284, connect them accordingly, disregard their names. RTS* CTS* pins associated with transmitter; DTR* DSR* pins associated with receiver. Table shows Intel recommended signal hook-up automatic out-of-band flow control. Table Out-of-Band Connections
CTS* RTS* RTS* CTS* CD1284 Pins DTR* RTS* CTS* Out-of-Band Flow Control Signal remote transmit implemented this direction Request remote permission transmit Enable transmitter
example, CD1284 designed automatic out-of-band flow control, connect DTR* remote CTS* input. CD1284 side, then connect CD1284 CTS* output remote CTS* input. Note, automatic out-of-band flow control implemented, activity DTR* DSR* implement function assigned those signal names signaling conventions CCITT (and other) standards organization. These names only apply these pins they under program control under automatic CD1284 control. fact, defined function enables modem off-line, depending state pin. automatic flow
CD1284 IEEE 1284-Compatible Parallel Interface Controller
control used, then DTR* goes inactive when receive FIFO reaches programmed threshold, causing modem drop connection (carrier) remote, this correct this function. Table Modem Control Functions
Modem Control Pins RTS* CTS* DTR* DSR* Function Request send (general-purpose output) Clear send (general-purpose input) Data terminal ready (carrier detect/generalpurpose input/output) Data ready (general-purpose input) Carrier detect (general-purpose input) Ring indicator (general-purpose input)
Modem pins implemented ports accessible either CD1284 internal microcode host. modem pins connected directly transmit receive hardware. When user programs out-of-band modem functions active, CD1284 microcode reads from writes these pins. Specifically, when RTS* CTS* used transmit flow control, CD1284 microcode asserts RTS* senses CTS*, required (Table 19). Also, when receive FIFO full, DTR* negated. host must reassert DTR* inadvertently. Note: host `locked out' accessing these bits; ensure that these bits written when auto out-of-band flow control enabled could cause system malfunction. user directly control RTS* DTR* probe state CTS*, CD*, DSR* inputs through MSVR. Since host accessing these pins directly, there delay ability detect level change. CD1284 programmed detect level changes generate service requests when level changes occur. does this firmware reading DTR* comparing them previously stored value. This function performed main timing loop firmware; maximum time required detect level change worst-case conditions approximately When CD1284 performing this function, modem pins periodically sampled rather than continuously monitored. this they have minimal sensitivity noise, desirable feature data communication applications. However, extremely noisy applications, reread modem line that caused modem signal change service request verify changed malfunctioning. This eliminates even slightest possibility noise pulse causing erratic operation. When CD1284 monitoring modem pins control transmit receive functions, does rely previously stored value, instead checks pins appropriate time. Thus, there very little delay this response. example, before deciding transmit another character, examines CTS* that time. CD1284 makes this decision when moving characters from FIFO Holding register, from Holding register Shift register. Note that logical sense modem bits inverted; that write MSVR1 MSVR2 causes output nominal zero volts. Likewise, low-voltage input sensed `1'.
IEEE 1284-Compatible Parallel Interface Controller CD1284
5.6.4.1
Generating Service Requests with Modem Pins
CD1284 generate service requests when input pins changes state. Either both edges detected setting bits MCOR1 MCOR2. each pin, user individually enable on-to-off off-to-on transition detection inputs. When CD1284 detects such transition, corresponding set. corresponding channel set, CD1284 asserts SVCREQM* output. user must clear during service request service routine before writing EOIR. CD1284 performs this task reading modem input signals comparing current value with value read last pass through outer scanning loop. Because this lowest-priority event CD1284 scanning loop, changes detected unless they several hundred microseconds long. example, modem input pins used detect closing switch. However, consider relatively slow speed response when using modem input pins this purpose. CD1284 does latch modem input signals.
5.6.4.2
Using Modem Pins General-Purpose
Since modem pins directly accessed host, they used general-purpose pins they needed flow control modem interfacing. Simply read from write these pins with port.
Receive Special Character Processing
CD1284 several ways send special characters process these characters when received. Some special characters have fixed definitions others user-defined. Figure page defines processing that CD1284 performs receive data. This flow chart illustrates special character handling process.
5.7.1
UNIX Character Processing
CD1284 incorporates special character processing particular benefit systems designed UNIX operating system. processing performs some functions normally handled `line discipline' part serial device driver program. This provides higher overall performance serial communication than could otherwise obtained because character manipulation occurs hardware level without interaction. This processing includes (carriage return) (new line) substitution, programmable response errored characters (framing, parity overrun errors), LNext function ISTRIP. Each type processing optional enabled/disabled with control bits CORs following sections describe each these functions.
5.7.1.1
Line-Terminating Characters
CD1284 programmed perform automatic substitution characters both received transmitted data. Received character processing five unique substitutions based value IGNCR, ICRNL, INLCR (COR4[7:5]); some combinations cause identical actions.
CD1284 IEEE 1284-Compatible Parallel Interface Controller
nothing function enabled Received changed Received changed Received change changed Received discarded Received discarded; changed Received discarded Received discarded; changed
5.7.1.2
Errored Character Processing
CD1284 easily manage received characters with errors (such parity, framing, overrun). none special processing functions enabled, errored characters delivered through receive exception service request. defined PEH[2:0] bits (COR4[2:0]), these characters handled following ways:
Parity errors ignored character placed FIFO good data given
other received good data.
errored character replaced with NULL (x'00) character FIFO. errored character replaced FIFO with 3-byte string x'FF-NULL-character.
this mode enabled actual good x'FF character received, replaced FIFO with character sequence x'FF-x'FF.
errored character discarded.
Received breaks handled differently from other errored characters. They processed, based settings IGNBRK -BRKINT bits (COR4[4:3]),
Reported errored character received exception service request. Replaced with good NULL (x'00) character FIFO. Discarded.
5.7.1.3 LNext
LNext (Literal Next) allows `escaping' ignoring special meaning special characters considers them normal data. escape character defined value register. CD1284 receives this character, places next character FIFO without further processing. example, this allows flow-control character received without causing actual flow-control activity. LNext enabled operate characters received with errors (such parity, framing, overrun), otherwise errored characters handled normally next character escaped.
5.7.1.4
ISTRIP
ISTRIP simple function that, enabled, resets most-significant (bit received good characters. character parity framing error, ISTRIP function does nothing character sent normal receive exception service request.
IEEE 1284-Compatible Parallel Interface Controller CD1284
5.7.2
Non-UNIX Receive Special Character Processing
addition UNIX special-character processing, CD1284 provides other special character recognition capabilities. CD1284 four registers that define special characters, SCHR1- SCHR4. SCHR1 SCHR2, used flow-control activities (see Section 5.6). SCHR3 SCHR4 define additional special characters that CD1284 scan receive data stream. Recognition special characters enabled SCD34 (COR3[6]). either these characters received, special character detect (receive exception) service request sent. Note that automatic in-band flow control enabled, SCHR1 SCHR2 still used special characters. They detected reported receive exceptions, they cause flow-control activities envoked. range detect function another special character function. this mode enabled (COR3[7] set), CD1284 compares received characters against values SCRL SCRH registers. character received falls between these values (inclusive), special character detect service request posted. status shown RDSR indicates which special character recognition conditions were caused receive exception service request.
CD1284 IEEE 1284-Compatible Parallel Interface Controller
Figure CD1284 Receive Character Processing
CHARACTER RECEIVED
PARITY, FRAMING, OVERRUN ERROR
ERRORED CHAR FLAG
BREAK
BREAK FLAG
CHAR MATCH ERROR ENABLED
ISTRIP ENABLED
SCHR12 ENABLED
LNEXT FLAG
CLEAR LNEXT FLAG
LNEXT MODE ENABLED
CHAR LNEXT
LNEXT FLAG
IEEE 1284-Compatible Parallel Interface Controller CD1284
Figure CD1284 Receive Character Processing (Continued)
XOFF CHARACTER
CHARACTER FLOW
TOGGLE FLOW STATE
CHARACTER
CLEAR FLOW
IMPLIED MODE
CLEAR FLOW FLOW CONTROL TRANSPARENCY DONE
SCHR34 ENABLED
CHARACTER MATCH
ENABLED
CHARACTER RANGE
SPECIAL CHARACTER EXCEPTION
DONE
CD1284 IEEE 1284-Compatible Parallel Interface Controller
Figure CD1284 Receive Character Processing (Continued)
CR/NL PROCESSING ENABLED
CHAR
COR4[7:5] action Discard Discard Discard Discard
PARITY ERROR HANDLING `100'
PARITY ERROR FLAG
CHAR X'FF CHAR FIFO
CHAR FIFO
PARITY ERROR FLAG PARITY ERROR HANDLING `011' FIFO
FF,00, CHAR FIFO
PARITY ERROR HANDLING `010' DISCARD CHAR
PARITY ERROR HANDLING `001' CHAR FIFO
POST EXCEPTION SERVICE REQUEST
BREAK FLAG CHAR FIFO
BREAK PROCESSING MODE `11' DISCARD CHAR
BREAK PROCESSING MODE `10' FIFO
POST EXCEPTION SERVICE REQUEST
DONE
IEEE 1284-Compatible Parallel Interface Controller CD1284
Transmit Special Character Processing
CD1284 also provides some special character handling transmit side embedded transmit commands direct commands transmit predefined special characters. Figure page illustrates process special character handling.
5.8.1
Line Terminating Characters
transmit, there four possible substitutions based setting flags, ONLCR OCRNL bits (COR5[1:0]):
nothing function enabled Change <CR> characters <NL> Change <NL> characters <CR> <NL> characters changed
When both flags (`11'), only translation occurs that changed changed CRNL.
5.8.2
Embedded Transmit Commands
CD1284 special feature that optionally allows specific `escape' character sequences transmit data stream interpreted commands. These called ETCs (embedded transmit commands) enabled COR2[5]. These sequences insert programmed time delays between characters generate line break transmit data output. enabled, detected when two- three-character escape sequence detected transmit FIFO. escape-character sequence comprised special escape character followed command character optional count delay period. escape character all-zero character (null ASCII character map). Five commands supported command set:
x'81 x'82 x'xx x'83 x'01-x'3F
Send Character
This command sequence allows character sent alone. Thus, this `escapes' escape when desired send null character.
x'81 Send BREAK
This sequence forces transmitter enter line-break condition least character time. Several conditions control continuation and/or termination line break.
CD1284 IEEE 1284-Compatible Parallel Interface Controller
there more data FIFO following send break command, break continues
indefinitely until terminated stop break command.
there insert delay command (see next command) immediately following send
break command, break duration value programmed delay command. other character FIFO immediately following send break command carries `implied' end-of-break condition, causing break terminated next character sent.
x'82
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