Quad 2-Input NAND Gate MC54/74HC00A identical pinout LS00. device
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Quad 2-Input NAND Gate
MC54/74HC00A identical pinout LS00. device inputs compatible with Standard CMOS outputs; with pullup resistors, they compatible with LSTTL outputs.
MC54/74HC00A
SUFFIX CERAMIC PACKAGE CASE 632-08
Output Drive Capability: LSTTL Loads Outputs Directly Interface CMOS, NMOS Operating Voltage Range: Input Current: High Noise Immunity Characteristic CMOS Devices Compliance With JEDEC Standard Requirements Chip Complexity: FETs Equivalent Gates
SUFFIX PLASTIC PACKAGE CASE 646-06
SUFFIX SOIC PACKAGE CASE 751A-03
LOGIC DIAGRAM
SUFFIX TSSOP PACKAGE CASE 948G-01
ORDERING INFORMATION MC54HCXXAJ MC74HCXXAN MC74HCXXAD MC74HCXXADT Ceramic Plastic SOIC TSSOP
FUNCTION TABLE
Inputs Output
Pinout: 14-Lead Packages (Top View)
10/95
Motorola, Inc. 1995
MC54/74HC00A
MAXIMUM RATINGS*
Symbol Parameter Value Unit Supply Voltage (Referenced GND) Input Voltage (Referenced GND) Vout Output Voltage (Referenced GND) Input Current, Iout Output Current, Supply Current, Pins Power Dissipation Still Air, Plastic Ceramic SOIC Package TSSOP Package Storage Temperature Tstg
This device contains protection circuitry guard against damage high static voltages electric fields. However, precautions must taken avoid applications voltage higher than maximum rated voltages this high-impedance circuit. proper operation, Vout should constrained range (Vin Vout) VCC. Unused inputs must always tied appropriate logic voltage level (e.g., either VCC). Unused outputs must left open.
Lead Temperature, from Case Seconds Plastic DIP, SOIC TSSOP Package Ceramic
Maximum Ratings those values beyond which damage device occur. Functional operation should restricted Recommended Operating Conditions. Derating Plastic DIP: mW/_C from 125_C Ceramic DIP: mW/_C from 100_ 125_C SOIC Package: mW/_C from 125_C TSSOP Package: mW/_C from 125_C high frequency heavy load considerations, Chapter Motorola High-Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Unit Supply Voltage (Referenced GND) Vin, Vout Input Voltage, Output Voltage (Referenced GND) Operating Temperature, Package Types Input Rise Fall Time (Figure 1000
High-Speed CMOS Logic Data DL129
MC54/74HC00A
CHARACTERISTICS (Voltages Referenced GND)
|Iout| 2.4mA |Iout| 4.0mA |Iout| 5.2mA |Iout| 2.4mA |Iout| 4.0mA |Iout| 5.2mA Guaranteed Limit 25°C 1.50 2.10 3.15 4.20 0.50 0.90 1.35 1.80 2.48 3.98 5.48 0.26 0.26 0.26 ±0.1 85°C 1.50 2.10 3.15 4.20 0.50 0.90 1.35 1.80 2.34 3.84 5.34 0.33 0.33 0.33 ±1.0 125°C 1.50 2.10 3.15 4.20 0.50 0.90 1.35 1.80 2.20 3.70 5.20 0.40 0.40 0.40 ±1.0 Unit
Symbol
Parameter Minimum High-Level Input Voltage
Condition Vout 0.1V -0.1V |Iout| 20µA
Maximum Low-Level Input Voltage
Vout 0.1V 0.1V |Iout| 20µA
Minimum High-Level Output Voltage
|Iout| 20µA =VIH
Maximum Low-Level Output Voltage
|Iout| 20µA
Maximum Input Leakage Current Maximum Quiescent Supply Current (per Package)
Iout
NOTE: Information typical parametric values found Chapter Motorola High-Speed CMOS Data Book (DL129/D).
CHARACTERISTICS Input
Symbol tPLH, tPHL Parameter Maximum Propagation Delay, Input Output (Figures Guaranteed Limit 25°C 85°C 125°C Unit
tTLH, tTHL
Maximum Output Transition Time, Output (Figures
Maximum Input Capacitance
NOTE: propagation delays with loads other than information typical parametric values, Chapter Motorola High- Speed CMOS Data Book (DL129/D). Typical 25°C, Power Dissipation Capacitance (Per Buffer)* Used determine no-load dynamic power consumption: VCC2f VCC. load considerations, Chapter Motorola High-Speed CMOS Data Book (DL129/D).
High-Speed CMOS Logic Data DL129
MC54/74HC00A
tPLH OUTPUT tTLH
INPUT
tPHL
tTHL
Figure Switching Waveforms
TEST POINT OUTPUT DEVICE UNDER TEST
*Includes probe capacitance
Figure Test Circuit
Figure Expanded Logic Diagram (1/4 Device)
High-Speed CMOS Logic Data DL129
MC54/74HC00A
OUTLINE DIMENSIONS
SUFFIX CERAMIC PACKAGE CASE 632-08 ISSUE
-A14 NOTES: DIMENSIONING TOLERANCING ANSI Y14.5M, 1982. CONTROLLING DIMENSION: INCH. DIMENSION CENTER LEAD WHEN FORMED PARALLEL. DIMESNION NARROW 0.76 (0.030) WHERE LEAD ENTERS CERAMIC BODY. INCHES 0.750 0.785 0.245 0.280 0.155 0.200 0.015 0.020 0.055 0.065 0.100 0.008 0.015 0.125 0.170 0.300 0.020 0.040 MILLIMETERS 19.05 19.94 7.11 6.23 5.08 3.94 0.50 0.39 1.65 1.40 2.54 0.38 0.21 4.31 3.18 7.62 0.51 1.01
-TSEATING PLANE
0.25 (0.010)
0.25 (0.010)
SUFFIX PLASTIC PACKAGE CASE 646-06 ISSUE
NOTES: LEADS WITHIN 0.13 (0.005) RADIUS TRUE POSITION SEATING PLANE MAXIMUM MATERIAL CONDITION. DIMENSION CENTER LEADS WHEN FORMED PARALLEL. DIMENSION DOES INCLUDE MOLD FLASH. ROUNDED CORNERS OPTIONAL. INCHES 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 0.052 0.095 0.008 0.015 0.115 0.135 0.300 0.015 0.039 MILLIMETERS 18.16 19.56 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 1.32 2.41 0.20 0.38 2.92 3.43 7.62 0.39 1.01
SEATING PLANE
High-Speed CMOS Logic Data DL129
MC54/74HC00A
OUTLINE DIMENSIONS
SUFFIX PLASTIC SOIC PACKAGE CASE 751A-03 ISSUE
NOTES: DIMENSIONING TOLERANCING ANSI Y14.5M, 1982. CONTROLLING DIMENSION: MILLIMETER. DIMENSIONS INCLUDE MOLD PROTRUSION. MAXIMUM MOLD PROTRUSION 0.15 (0.006) SIDE. DIMENSION DOES INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL 0.127 (0.005) TOTAL EXCESS DIMENSION MAXIMUM MATERIAL CONDITION.
0.25 (0.010)
SEATING PLANE
0.25 (0.010)
MILLIMETERS 8.75 8.55 4.00 3.80 1.75 1.35 0.49 0.35 1.25 0.40 1.27 0.25 0.19 0.25 0.10 5.80 6.20 0.25 0.50
INCHES 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 0.008 0.009 0.004 0.009 0.228 0.244 0.010 0.019
SUFFIX PLASTIC TSSOP PACKAGE CASE 948G-01 ISSUE
NOTES: DIMENSIONING TOLERANCING ANSI Y14.5M, 1982. CONTROLLING DIMENSION: MILLIMETER. DIMENSION DOES INCLUDE MOLD FLASH, PROTRUSIONS GATE BURRS. MOLD FLASH GATE BURRS SHALL EXCEED 0.15 (0.006) SIDE. DIMENSION DOES INCLUDE INTERLEAD FLASH PROTRUSION. INTERLEAD FLASH PROTRUSION SHALL EXCEED 0.25 (0.010) SIDE. DIMENSION DOES INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL 0.08 (0.003) TOTAL EXCESS DIMENSION MAXIMUM MATERIAL CONDITION. TERMINAL NUMBERS SHOWN REFERENCE ONLY. DIMENSION DETERMINED DATUM PLANE -W-. MILLIMETERS 4.90 5.10 4.30 4.50 1.20 0.05 0.15 0.50 0.75 0.65 0.50 0.60 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 INCHES 0.193 0.200 0.169 0.177 0.047 0.002 0.006 0.020 0.030 0.026 0.020 0.024 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252
0.10 (0.004) 0.15 (0.006)
0.25 (0.010)
IDENT.
DETAIL
0.15 (0.006)
SECTION
0.10 (0.004) SEATING
PLANE
DETAIL
High-Speed CMOS Logic Data DL129
MC54/74HC00A
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High-Speed CMOS Logic Data DL129
CODELINE
*MC54/74HC00A/D*
MC54/74HC00A/D
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