SDRAM Unbuffered SODIMM 144pin Unbuffered SODIMM based 128Mb E-di
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64MB, 128MB Unbuffered SODIMM
SDRAM Unbuffered SODIMM
144pin Unbuffered SODIMM based 128Mb E-die 64-bit
Revision March. 2004
Rev. March. 2004
64MB, 128MB Unbuffered SODIMM
Revision History
Revision (November, 2002) First release Revision (May. 2003) Merged Spec. Revision (June. 2003) Correct Typo. Revision (February. 2004) Correct Typo. Revision (March. 2004) Corrected package dimension.
Rev. March. 2004
64MB, 128MB Unbuffered SODIMM
144Pin Unbuffered DIMM based 128Mb E-die (x16)
Ordering Information
Part Number M464S0924ETS-C(L)7A M464S1724ETS-C(L)7A Density 64MB 128MB Organization Component Composition 8Mx16(K4S281632E) 8Mx16( K4S281632E) Component Package 54-TSOPII 54-TSOPII
Height 1,000mil 1,250mil
Operating Frequencies
@CL3 Maximum Clock Frequency CL-tRCD-tRP(clock) 133MHz(7.5ns) 3-3-3 @CL2 100MHz(10ns) 2-2-2
Feature
Burst mode operation Auto self refresh capability (4096 Cycles/64ms) LVTTL compatible inputs outputs Single 3.3V 0.3V power supply cycle with address programs Latency (Access from column address) Burst length Full page) Data scramble (Sequential Interleave) inputs sampled positive going edge system clock Serial presence detect with EEPROM
Rev. March. 2004
64MB, 128MB Unbuffered SODIMM
CONFIGURATIONS (Front side/back side)
Front DQM0 DQM1 DQ10 DQ11 DQ12 DQ13 Back DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQM4 DQM5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 Front DQ14 DQ15 Back DQ46 DQ47 Front DQ21 DQ22 DQ23 A10/AP DQM2 DQM3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
Back DQ53 DQ54 DQ55 DQM6 DQM7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
Voltage
**CLK0 **CS0 **CS1 DQ16 DQ17 DQ18 DQ19 DQ20 **CKE0 **CKE1 *A12 *A13 **CLK1 DQ48 DQ49 DQ50 DQ51 DQ52
Note These pins used this module. 2.Pins 141,142 should system which does support SPD. 3.** About these pins, Refer Block Diagram each.
Description
Name DQ63 CLK0 CLK1 CKE0 CKE1 Select bank Data input/output Clock input Clock enable input Chip select input address strobe Column address strobe Function Address input (Multiplexed) DQM0 Name Write enable Power supply (3.3V) Ground Serial data Serial clock Dont connection Function
SAMSUNG ELECTRONICS CO., Ltd. reserves right change products specifications without notice.
Rev. March. 2004
64MB, 128MB Unbuffered SODIMM
CONFIGURATION DESCRIPTION
Name System clock Chip select Input Function Active positive going edge sample inputs.
Disables enables device operation masking enabling inputs except CLK, Masks system clock freeze operation from next clock cycle. should enabled least cycle prior command. Disable input buffers power down standby. should enabled 1CLK+tSS prior valid command. Row/column addresses multiplexed same pins. address RA11 Column address (x16 CA8) Selects bank activated during address latch time. Selects bank read/write during column address latch time. Latches addresses positive going edge with low. Enables access precharge. Latches column addresses positive going edge with low. Enables column access. Enables write operation precharge. Latches data starting from CAS, active. Makes data output Hi-Z, tSHZ after clock masks output. Blocks data input when active. (Byte masking) Data inputs/outputs multiplexed same pins. Power ground input buffers core logic.
Clock enable
Address
DQM0 VDD/VSS
Bank select address address strobe Column address strobe Write enable Data input/output mask Data input/output Power supply/ground
Rev. March. 2004
64MB, 128MB Unbuffered SODIMM
64MB, 8Mx64 Module (M464S0924ETS) (Populated bank SDRAM Module)
FUNCTIONAL BLOCK DIAGRAM
DQM0 DQM4 LDQM LDQM
DQM1
DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39
DQM5
UDQM
UDQM
DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
DQM2
DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47
DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
DQM6 LDQM
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23
DQM3
UDQM
LDQM
DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55
DQM7
UDQM
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
A11, CKE0
DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
SDRAM SDRAM SDRAM SDRAM SDRAM Every
DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
Serial
CLK0 CLK1 10pF
Three 0.1uF 0603Capacitors each
SDRAMs
Note zero jumper isolate from SDRAM pins non-256Mbit designs.
Rev. March. 2004
64MB, 128MB Unbuffered SODIMM
128MB, 16Mx64 Module (M464S1724ETS) (Populated bank SDRAM Module)
FUNCTIONAL BLOCK DIAGRAM
DQM0 LDQM LDQM
DQM4 LDQM LDQM
DQM1
UDQM
UDQM
DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39
DQM5
UDQM
UDQM
DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
DQM2
DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47
DQM6
DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
LDQM
LDQM
LDQM
LDQM
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23
DQM3
UDQM
UDQM
DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55
DQM7
UDQM
UDQM
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
A11, CKE0 CKE1
DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM
DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
Serial
Every SDRAM CLK0/1
U0/U4 U1/U5 U2/U6 U3/U7
Three 0603 Capacitors each
SDRAMs
Note zero jumper isolate from SDRAM pins non-256Mbit designs.
Rev. March. 2004
64MB, 128MB Unbuffered SODIMM
ABSOLUTE MAXIMUM RATINGS
Parameter Voltage relative Voltage supply relative Storage temperature Power dissipation Short circuit current Symbol VIN, VOUT VDD, VDDQ TSTG Value -1.0 -1.0 +150 component
Unit
Note Permanent device damage occur "ABSOLUTE MAXIMUM RATINGS" exceeded. Functional operation should restricted recommended operating condition. Exposure higher than recommended voltage extended periods time could affect device reliability.
OPERATING CONDITIONS CHARACTERISTICS
Recommended operating conditions (Voltage referenced 70°C) Parameter Supply voltage Input high voltage Input voltage Output high voltage Output voltage Input leakage current Symbol -0.3 VDDQ+0.3 Unit -2mA Note
Notes (max) 5.6V AC.The overshoot voltage duration 3ns. (min) -2.0V undershoot voltage duration 3ns. input VDDQ. Input leakage currents include Hi-Z output leakage bi-directional buffers with Tri-State outputs.
CAPACITANCE
(VDD 3.3V, 23°C, 1MHz, VREF 1.4V Symbol CIN1 CIN2 CIN3 CIN4 CIN5 CIN6 COUT M464S0924ETS M464S1724ETS Unit
Parameter Input capacitance A11, BA1) Input capacitance (RAS, CAS, Input capacitance (CKE0 CKE1) Input capacitance (CLK0 CLK1) Input capacitance (CS0 CS1) Input capacitance (DQM0 DQM7) Data input/output capacitance (DQ0 DQ63)
Rev. March. 2004
64MB, 128MB Unbuffered SODIMM
CHARACTERISTICS M464S0924ETS 64MB Module)
(Recommended operating condition unless otherwise noted, 70°C) Version Parameter Symbol Burst length tRC(min) VIL(max), 10ns VIL(max), VIH(min), VIH(min), 10ns Input signals changed time during 20ns VIH(min), VIL(max), Input signals stable VIL(max), 10ns VIL(max), VIH(min), VIH(min), 10ns Input signals changed time during 20ns VIH(min), VIL(max), Input signals stable Page burst 4Banks activated tCCD 2CLKs tRC(min) 0.2V Notes Measured with outputs open. Refresh period 64ms. Test Condition Operating current (One bank active) Precharge standby current power-down mode ICC1 ICC2P ICC2PS ICC2N Precharge standby current power-down mode ICC2NS Active standby current power-down mode ICC3P ICC3PS ICC3N ICC3NS
Unit
Note
Active standby current power-down mode (One bank active)
Operating current (Burst mode) Refresh current Self refresh current
ICC4
ICC5 ICC6
Rev. March. 2004
64MB, 128MB Unbuffered SODIMM
CHARACTERISTICS M464S1724ETS (16M 128MB Module)
(Recommended operating condition unless otherwise noted, 70°C) Version Parameter Symbol Burst length tRC(min) VIL(max), 10ns VIL(max), VIH(min), VIH(min), 10ns Input signals changed time during 20ns VIH(min), VIL(max), Input signals stable VIL(max), 10ns VIL(max), VIH(min), VIH(min), 10ns Input signals changed time during 20ns VIH(min), VIL(max), Input signals stable Page burst 4Banks activated tCCD 2CLKs tRC(min) 0.2V Notes Measured with outputs open. Refresh period 64ms. Test Condition Operating current (One bank active) Precharge standby current power-down mode ICC1 ICC2P ICC2PS ICC2N Precharge standby current power-down mode ICC2NS Active standby current power-down mode ICC3P ICC3PS ICC3N ICC3NS
Unit
Note
Active standby current power-down mode (One bank active)
Operating current (Burst mode) Refresh current Self refresh current
ICC4
ICC5 ICC6
Rev. March. 2004
64MB, 128MB Unbuffered SODIMM
OPERATING TEST CONDITIONS (VDD 3.3V 0.3V, 70°C)
Parameter input levels (Vih/Vil) Input timing measurement reference level Input rise fall time Output timing measurement reference level Output load condition Value 2.4/0.4 tr/tf Fig.
Unit
3.3V
1.4V
1200 Output 50pF (DC) 2.4V, -2mA (DC) 0.4V, Output
50pF
(Fig. output load circuit
(Fig. output load circuit
OPERATING PARAMETER
operating conditions unless otherwise noted) Parameter active active delay delay precharge time active time cycle time Last data precharge Last data Active delay Last data col. address delay Last data burst stop Col. address col. address delay Number valid output data Symbol tRRD(min) tRCD(min) tRP(min) tRAS(min) tRAS(max) tRC(min) tRDL(min) tDAL(min) tCDL(min) tBDL(min) tCCD(min) latency=3 latency=2 Version Unit Note
Notes minimum number clock cycles determined dividing minimum time required with clock cycle time then rounding next higher integer. Minimum delay required complete write. parts allow every cycle column address change. case precharge interrupt, auto precharge read burst stop.
Rev. March. 2004
64MB, 128MB Unbuffered SODIMM
CHARACTERISTICS operating conditions unless otherwise noted) REFER INDIVIDUAL COMPONENET, WHOLE MODULE.
Parameter cycle time valid output delay Output data hold time latency=3 latency=2 latency=3 latency=2 latency=3 latency=2 Symbol 1000 Unit
Note
tSAC
tSLZ tSHZ
high pulse width pulse width Input setup time Input hold time output Low-Z output Hi-Z latency=3 latency=2
Notes Parameters depend programmed latency. clock rising time longer than 1ns, (tr/2-0.5)ns should added parameter. Assumed input rise fall time 1ns. longer than 1ns, transient time compensation should considered, i.e., [(tr tf)/2-1]ns should added parameter.
Rev. March. 2004
64MB, 128MB Unbuffered SODIMM
SIMPLIFIED TRUTH TABLE
Command Register Mode register Auto refresh Refresh Entry Self refresh Exit
CKEn-1 CKEn BA0,1 A10/AP
(V=Valid, X=Dont care, H=Logic high, L=Logic low)
Note
code
address
Column address
Bank active addr. Read column address Write column address Burst stop Precharge Bank selection banks Entry Exit Entry Precharge power down mode Exit operation command Auto precharge disable Auto precharge enable Auto precharge disable Auto precharge enable
Column address
Clock suspend active power down
Notes Code Operand code Program keys. MRS) issued only banks precharge state. command issued after clock cycles MRS. Auto refresh functions same refresh DRAM. automatical precharge without precharge command meant "Auto". Auto/self refresh issued only banks precharge state. Bank select addresses. both "Low" read, write, active precharge, bank selected. "High" "Low" read, write, active precharge, bank selected. "Low" "High" read, write, active precharge, bank selected. both "High" read, write, active precharge, bank selected. A10/AP "High" precharge, ignored banks selected. During burst read write with auto precharge, read/write command issued. Another bank read/write command issued after burst. active associated bank issued after burst. Burst stop command valid every burst length. sampled positive going edge masks data-in very (Write latency makes Hi-Z state data-out cycles after. (Read latency
Rev. March. 2004
64MB, 128MB Unbuffered SODIMM
PACKAGE DIMENSIONS 8Mx64 (M464S0924ETS)
Units Inches (Millimeters)
2.66 (67.56) 2.50 (63.60) 0.16 0.039 (4.00 0.10) 0.24 (6.0) 0.79 (20.00) 0.078 (2.00 Min) 1.00 (25.40) 0.024 0.001 (0.600 0.050) 0.008 ±0.006 (0.200 ±0.150) 0.03 (0.80 TYP)
0.13 (3.30)
0.91 (23.20)
0.10 (2.50)
0.18 (4.60) 0.083 (2.10)
1.29 (32.80)
0.07 (1.80)
0.15 (3.70)
0.150 (3.80 Max) (3.20 Min) (4.00 Min) 0.125 0.157 0.16 0.0039 (4.00 0.10) 0.06 0.0039 (1.50 0.1)
0.04 0.0039 (1.00 0.10)
Detail
(2.540 Min)
0.100
Detail
Tolerances 0.006(.15) unless otherwise specified used device 8Mx16 SDRAM, TSOPII SDRAM Part K4S281632E
Rev. March. 2004
64MB, 128MB Unbuffered SODIMM
PACKAGE DIMENSIONS 16Mx64 (M464S1724ETS)
Units Inches (Millimeters)
2.66 (67.56) 2.50 (63.60) 0.16 0.039 (4.00 0.10) 0.24 (6.0) 0.79 (20.00) 0.078 (2.00 Min) 1.25 (31.75) 0.024 0.001 (0.600 0.050) 0.008 ±0.006 (0.200 ±0.150) 0.03 (0.80 TYP)
0.13 (3.30)
0.91 (23.20)
0.10 (2.50)
0.18 (4.60) 0.083 (2.10)
1.29 (32.80)
0.07 (1.80)
0.15 (3.70)
0.150 (3.80 Max) (3.20 Min) (4.00 Min) 0.125 0.157 0.16 0.0039 (4.00 0.10) 0.06 0.0039 (1.50 0.1)
0.04 0.0039 (1.00 0.10)
Detail
(2.540 Min)
0.100
Detail
Tolerances ±.006(.15) unless otherwise specified used device 8Mx16 SDRAM, TSOPII SDRAM Part K4S281632E
Rev. March. 2004
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