Programmable Logic Device Family September 2001, ver. Featur
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APEX
Programmable Logic Device Family
September 2001, ver.
Features.
Industry's first programmable logic device (PLD) incorporating system-on-a-programmable-chip (SOPC) integration MultiCorearchitecture integrating look-up table (LUT) logic, product-term logic, embedded memory logic used register-intensive functions Embedded system block (ESB) used implement memory functions, including first-in first-out (FIFO) buffers, dual-port RAM, content-addressable memory (CAM) implementation product-term logic used combinatorial-intensive functions High density 30,000 million typical gates (see Tables 51,840 logic elements (LEs) 442,368 bits that used without reducing available logic 3,456 product-term-based macrocells Note EP20K100
263,000
Table APEX Device Features Feature
Maximum system gates Typical gates ESBs Maximum bits Maximum macrocells Maximum user pins
EP20K30E EP20K60E
113,000 162,000
EP20K100E
263,000
EP20K160E
404,000
EP20K200
526,000
EP20K200E
526,000
30,000 1,200 24,576
60,000 2,560 32,768
100,000 4,160 53,248
100,000 4,160 53,248
160,000 6,400 81,920
200,000 8,320 106,496
200,000 8,320 106,496
Altera Corporation
A-DS-APEX20K-04.1
APEX Programmable Logic Device Family
Table APEX Device Features Feature
Maximum system gates Typical gates ESBs Maximum bits Maximum macrocells Maximum user pins Note tables:
Note EP20K400E
1,052,000 400,000 16,640 212,992 1,664
EP20K300E
728,000 300,000 11,520 147,456 1,152
EP20K400
1,052,000 400,000 16,640 212,992 1,664
EP20K600E
1,537,000 600,000 24,320 311,296 2,432
EP20K1000E
1,772,000 1,000,000 38,400 327,680 2,560
EP20K1500E
2,392,000 1,500,000 51,840 442,368 3,456
embedded IEEE Std. 1149.1 Joint Test Action Group (JTAG) boundary-scan circuitry contributes 57,000 additional gates.
.and More Features
Designed low-power operation 1.8-V 2.5-V supply voltage (see Table MultiVoltI/O interface support interface with 1.8-V, 2.5-V, 3.3-V, 5.0-V devices (see Table offering programmable power-saving mode
Table APEX Supply Voltages Feature EP20K100 EP20K200 EP20K400 Device EP20K30E EP20K60E EP20K100E EP20K160E EP20K200E EP20K300E EP20K400E EP20K600E EP20K1000E EP20K1500E
Internal supply voltage (VCCINT) MultiVolt interface voltage levels (VCCIO) Notes:
Certain APEX devices 5.0-V tolerant. "MultiVolt Interface" page details. APEX 20KE devices 5.0-V tolerant using external resistor.
Altera Corporation
APEX Programmable Logic Device Family Data Sheet
Flexible clock management circuitry with four phase-locked loops (PLLs) Built-in low-skew clock tree eight global clock signals ClockLockfeature reducing clock delay skew ClockBoostfeature providing clock multiplication division ClockShiftprogrammable clock phase delay shifting Powerful features Compliant with peripheral component interconnect Special Interest Group (PCI SIG) Local Specification, Revision 3.3-V operation bits Support high-speed external memories, including SDRAM SRAM (ZBT trademark Integrated Device Technology, Inc.) Bidirectional performance (tCO tSU) LVDS performance Mbits channel Direct connection from pins local interconnect providing fast times complex logic MultiVolt interface support interface with 1.8-V, 2.5-V, 3.3-V, 5.0-V devices (see Table Programmable clamp VCCIO Individual tri-state output enable control each Programmable output slew-rate control reduce switching noise Support advanced standards, including low-voltage differential signaling (LVDS), LVPECL, PCI-X, AGP, CTT, stubseries terminated logic (SSTL-3 SSTL-2), Gunning transceiver logic plus (GTL+), high-speed terminated logic (HSTL Class Pull-up pins before during configuration Advanced interconnect structure Four-level hierarchical FastTrack® Interconnect structure providing fast, predictable interconnect delays Dedicated carry chain that implements arithmetic functions such fast adders, counters, comparators (automatically used software tools megafunctions) Dedicated cascade chain that implements high-speed, high-fan-in logic functions (automatically used software tools megafunctions) Interleaved local interconnect allows drive other through fast local interconnect Advanced packaging options Available variety packages with 1,020 pins (see Tables through FineLine BGApackages maximize board space efficiency Advanced software support Software design support automatic place-and-route provided Altera® QuartusII development system
Altera Corporation
APEX Programmable Logic Device Family
Windows-based PCs, SPARCstations, 9000 Series 700/800 workstations Altera MegaCore® functions Altera Megafunction Partners Program (AMPPSM) megafunctions NativeLinkintegration with popular synthesis, simulation, timing analysis tools Quartus SignalTapembedded logic analyzer simplifies in-system design evaluation giving access internal nodes during device operation Supports popular revision-control software packages including PVCS, Revision Control System (RCS), Source Code Control System (SCCS Notes (1),
Table APEX QFP, Package Options Count Device 144-Pin TQFP
208-Pin PQFP RQFP
240-Pin PQFP RQFP
356-Pin 652-Pin 655-Pin
EP20K30E EP20K60E EP20K100 EP20K100E EP20K160E EP20K200 EP20K200E EP20K300E EP20K400 EP20K400E EP20K600E EP20K1000E EP20K1500E
Altera Corporation
APEX Programmable Logic Device Family
Table APEX FineLine Package Options Count Device
EP20K30E EP20K60E EP20K100 EP20K100E EP20K160E EP20K200 EP20K200E EP20K300E EP20K400 EP20K400E EP20K600E EP20K1000E EP20K1500E Notes tables:
Notes (1), 1,020
counts include dedicated input clock pins. APEX device package types include thin quad flat pack (TQFP), plastic quad flat pack (PQFP), power quad flat pack (RQFP), 1.27-mm pitch ball-grid array (BGA), 1.00-mm pitch FineLine BGA, pin-grid array (PGA) packages. This device uses thermally enhanced package, which taller than regular package. Consult Altera Device Package Information Data Sheet detailed package size information.
Table APEX QFP, Package Sizes Feature
Pitch (mm) Area (mm2) Length Width
144-Pin TQFP 208-Pin 240-Pin 356-Pin 652-Pin 655-Pin
0.50 0.50 30.4 30.4 0.50 1,218 34.9 34.9 1.27 1,225 1.27 2,025 3,906 62.5 62.5
Table APEX FineLine Package Sizes Feature
Pitch (mm) Area (mm2) Length Width
1.00
1.00
1.00
1.00
1,020
1.00 1,089
Altera Corporation
APEX Programmable Logic Device Family
General Description
APEX20K devices first PLDs designed with MultiCore architecture, which combines strengths LUT-based productterm-based devices with enhanced memory structure. LUT-based logic provides optimized performance efficiency data-path, registerintensive, mathematical, digital signal processing (DSP) designs. Product-term-based logic optimized complex combinatorial paths, such complex state machines. LUT- product-term-based logic combined with memory functions wide variety MegaCore AMPP functions make APEX device architecture uniquely suited system-on-a-programmable-chip designs. Applications historically requiring combination LUT-, product-term-, memory-based devices integrated into APEX device. APEX 20KE devices superset APEX devices include additional features such advanced standard support, CAM, additional global clocks, enhanced ClockLock clock circuitry. addition, APEX 20KE devices extend APEX family million gates. APEX 20KE devices denoted with suffix device name (e.g., EP20K1000E device APEX 20KE device). Table compares features included APEX APEX 20KE devices.
Altera Corporation
APEX Programmable Logic Device Family
Table Comparison APEX APEX 20KE Features Feature
MultiCore system integration SignalTap logic analysis 32/64-Bit, 33-MHz 32/64-Bit, 66-MHz MultiVolt
APEX Devices
Full support Full support Full compliance speed grades 2.5-V 3.3-V VCCIO VCCIO selected device Certain devices 5.0-V tolerant Clock delay reduction clock multiplication
APEX 20KE Devices
Full support Full support Full compliance speed grades Full compliance speed grade 1.8-V, 2.5-V, 3.3-V VCCIO VCCIO selected block-by-block 5.0-V tolerant with external resistor Clock delay reduction clock multiplication Drive ClockLock output off-chip External clock feedback ClockShift LVDS support four PLLs ClockShift, clock phase adjustment Eight 1.8-V, 2.5-V, 3.3-V, 5.0-V 2.5-V 3.3-V PCI-X 3.3-V Advanced Graphics Port (AGP) Center terminated (CTT) GTL+ LVCMOS LVTTL True-LVDS LVPECL data pins EP20K300E larger devices) LVDS LVPECL clock pins FineLine devices) LVDS LVPECL data pins Mbps speed grade devices) HSTL Class PCI-X SSTL-2 Class SSTL-3 Class Dual-port FIFO
ClockLock support
Dedicated clock input pins standard support 2.5-V, 3.3-V, 5.0-V 3.3-V Low-voltage complementary metal-oxide semiconductor (LVCMOS) Low-voltage transistor-to-transistor logic (LVTTL)
Memory support
Dual-port FIFO
Altera Corporation
APEX Programmable Logic Device Family
APEX devices reconfigurable 100% tested prior shipment. result, test vectors have generated fault coverage purposes. Instead, designer focus simulation design verification. addition, designer does need manage inventories different application-specific integrated circuit (ASIC) designs; APEX devices configured board specific functionality required. APEX devices configured system power-up with data stored Altera serial configuration device provided system controller. Altera offers in-system programmability (ISP)-capable EPC1, EPC2, EPC16 configuration devices, which configure APEX devices serial data stream. Moreover, APEX devices contain optimized interface that permits microprocessors configure APEX devices serially parallel, synchronously asynchronously. interface also enables microprocessors treat APEX devices memory configure device writing virtual memory location, making reconfiguration easy. After APEX device been configured, reconfigured in-circuit resetting device loading data. Real-time changes made during system operation, enabling innovative reconfigurable computing applications. APEX devices supported Altera Quartus development system, single, integrated package that offers schematic design entry, compilation logic synthesis, full simulation worst-case timing analysis, SignalTap logic analysis, device configuration. Quartus software runs Windows-based PCs, SPARCstations, 9000 Series 700/800 workstations. Quartus software provides NativeLink interfaces other industrystandard UNIX workstation-based tools. example, designers invoke Quartus software from within third-party design tools. Further, Quartus software contains built-in optimized synthesis libraries; synthesis tools these libraries optimize designs APEX devices. example, Synopsys Design Compiler library, supplied with Quartus development system, includes DesignWare functions optimized APEX architecture.
Altera Corporation
APEX Programmable Logic Device Family
Functional Description
APEX devices incorporate LUT-based logic, product-term-based logic, memory into device. Signal interconnections within APEX devices well from device pins) provided FastTrack Interconnect-a series fast, continuous column channels that entire length width device. Each element (IOE) located each column FastTrack Interconnect. Each contains bidirectional buffer register that used either input output register feed input, output, bidirectional signals. When used with dedicated clock pin, these registers provide exceptional performance. IOEs provide variety features, such 3.3-V, 64-bit, 66-MHz compliance; JTAG support; slew-rate control; tri-state buffers. APEX 20KE devices offer enhanced support, including support 1.8-V I/O, 2.5-V I/O, LVCMOS, LVTTL, LVPECL, 3.3-V PCI, PCI-X, LVDS, GTL+, SSTL-2, SSTL-3, HSTL, CTT, 3.3-V standards. implement variety memory functions, including CAM, RAM, dual-port RAM, ROM, FIFO functions. Embedding memory directly into improves performance reduces area compared distributed-RAM implementations. Moreover, abundance cascadable ESBs ensures that APEX device implement multiple wide memory blocks high-density designs. ESB's high speed ensures implement small memory blocks without speed penalty. abundance ESBs ensures that designers create many different-sized memory blocks system requires. Figure shows overview APEX device.
Figure APEX Device Block Diagram
Clock Management Circuitry
ClockLock
FastTrack Interconnect
Four-input data path functions. Product-term integration high-speed control logic state machines.
Product Term Memory
Product Term Memory
Product Term Memory
Product Term Memory
Product Term Memory
Product Term Memory
Product Term Memory
Product Term Memory
IOEs support PCI, GTL+, SSTL-3, LVDS, other standards.
Flexible integration embedded memory, including CAM, RAM, ROM, FIFO, other memory functions.
Altera Corporation
APEX Programmable Logic Device Family
APEX devices provide dedicated clock pins four dedicated input pins that drive register control inputs. These signals ensure efficient distribution high-speed, low-skew control signals. These signals dedicated routing channels provide short delays skews. Four dedicated inputs drive four global signals. These four global signals also driven internal logic, providing ideal solution clock divider internally generated asynchronous clear signals with high fan-out. dedicated clock pins featured APEX devices also feed logic. devices also feature ClockLock ClockBoost clock management circuitry. APEX 20KE devices provide additional dedicated clock pins, total four dedicated clock pins.
MegaLAB Structure
APEX devices constructed from series MegaLABstructures. Each MegaLAB structure contains group logic array blocks (LABs), ESB, MegaLAB interconnect, which routes signals within MegaLAB structure. EP20K30E device LABs, EP20K60E through EP20K600E devices have LABs, EP20K1000E EP20K1500E devices have LABs. Signals routed between MegaLAB structures pins FastTrack Interconnect. addition, edge LABs driven pins through local interconnect. Figure shows MegaLAB structure. Figure MegaLAB Structure
MegaLAB Interconnect
Adjacent IOEs
LE10
LE10
LE10
Local Interconnect
LABs
Altera Corporation
APEX Programmable Logic Device Family
Logic Array Block
Each consists LEs, LEs' associated carry cascade chains, control signals, local interconnect. local interconnect transfers signals between same adjacent LABs, IOEs, ESBs. Quartus Compiler places associated logic within adjacent LABs, allowing fast local interconnect high performance. Figure shows APEX LAB. APEX devices interleaved structure. This structure allows each drive local interconnect areas. This feature minimizes MegaLAB FastTrack interconnect, providing higher performance flexibility. Each drive other through fast local interconnect. Figure Structure
Interconnect
MegaLAB Interconnect
drive local MegaLAB, row, column interconnects.
To/From Adjacent LAB, ESB, IOEs To/From Adjacent LAB, ESB, IOEs
Local Interconnect
Column Interconnect driven local interconnect areas. These drive local interconnect areas.
Altera Corporation
APEX Programmable Logic Device Family
Each contains dedicated logic driving control signals ESBs. control signals include clock, clock enable, asynchronous clear, asynchronous preset, asynchronous load, synchronous clear, synchronous load signals. maximum control signals used time. Although synchronous load clear signals generally used when implementing counters, they also used with other functions. Each clocks clock enable signals. Each LAB's clock clock enable signals linked (e.g., particular using CLK1 will also CLKENA1). with same clock different clock enable signals either both clock signals placed into separate LABs. both rising falling edges clock used LAB, both LABwide clock signals used. LAB-wide control signals generated from local interconnect, global signals, dedicated clock pins. inherent skew FastTrack Interconnect enables used clock distribution. Figure shows control signal generation circuit. Figure Control Signal Generation
Dedicated Clocks Global Signals Local Interconnect Local Interconnect Local Interconnect Local Interconnect SYNCLOAD LABCLKENA2 SYNCCLR LABCLK2 LABCLKENA1 LABCLR1
LABCLK1
LABCLR2
Notes:
APEX 20KE devices have four dedicated clocks. LABCLR1 LABCLR2 signals also control asynchronous load asynchronous preset within LAB. SYNCCLR signal generated local interconnect global signals.
Altera Corporation
APEX Programmable Logic Device Family
Logic Element
smallest unit logic APEX architecture, compact provides efficient logic usage. Each contains four-input LUT, which function generator that quickly implement function four variables. addition, each contains programmable register carry cascade chains. Each drives local interconnect, MegaLAB interconnect, FastTrack Interconnect routing structures. Figure Figure APEX Logic Element
Register Bypass
LAB-wide LAB-wide Synchronous Synchronous Load Clear Cascade-In
Carry-In
Packed Register Select Programmable Register
FastTrack Interconnect, MegaLAB Interconnect, Local Interconnect
data1 data2 data3 data4
Look-Up Table (LUT)
Carry Chain
Cascade Chain
Synchronous Load Clear Logic
CLRN FastTrack Interconnect, MegaLAB Interconnect, Local Interconnect
labclr1 labclr2 Chip-Wide Reset
Asynchronous Clear/Preset/ Load Logic
Clock Clock Enable Select labclk1 labclk2
labclkena1 labclkena2 Carry-Out Cascade-Out
Each LE's programmable register configured operation. register's clock clear control signals driven global signals, general-purpose pins, internal logic. combinatorial functions, register bypassed output drives outputs
Altera Corporation
APEX Programmable Logic Device Family
Each outputs that drive local, MegaLAB, FastTrack Interconnect routing structure. Each output driven independently LUT's register's output. example, drive output while register drives other output. This feature, called register packing, improves device utilization because register used unrelated functions. also drive registered unregistered versions output. APEX architecture provides types dedicated high-speed data paths that connect adjacent without using local interconnect paths: carry chains cascade chains. carry chain supports high-speed arithmetic functions such counters adders, while cascade chain implements wide-input functions such equality comparators with minimum delay. Carry cascade chains connect through LABs same MegaLAB structure.
Carry Chain
carry chain provides very fast carry-forward function between LEs. carry-in signal from lower-order drives forward into higherorder carry chain, feeds into both next portion carry chain. This feature allows APEX architecture implement high-speed counters, adders, comparators arbitrary width. Carry chain logic created automatically Quartus software Compiler during design processing, manually designer during design entry. Parameterized functions such library parameterized modules (LPM) DesignWare functions automatically take advantage carry chains appropriate functions. Quartus software Compiler creates carry chains longer than linking LABs together automatically. enhanced fitting, long carry chain skips alternate LABs MegaLAB structure. carry chain longer than skips either from even-numbered next evennumbered LAB, from odd-numbered next oddnumbered LAB. example, last first upper-left MegaLAB structure carries first third MegaLAB structure. Figure shows n-bit full adder implemented with carry chain. portion generates bits using input signals carry-in signal; routed output register bypassed simple adders used accumulator functions. Another portion carry chain logic generates carry-out signal, which routed directly carryin signal next-higher-order bit. final carry-out signal routed where driven onto local, MegaLAB, FastTrack Interconnect routing structures.
Altera Corporation
APEX Programmable Logic Device Family
Figure APEX Carry Chain
Carry-In
Register
Carry Chain
Register
Carry Chain
Register
Carry Chain
Register
Carry-Out
Carry Chain
Altera Corporation
APEX Programmable Logic Device Family
Cascade Chain
With cascade chain, APEX architecture implement functions with very wide fan-in. Adjacent LUTs compute portions function parallel; cascade chain serially connects intermediate values. cascade chain logical logical (via Morgan's inversion) connect outputs adjacent LEs. Each additional provides four more inputs effective width function, with short cascade delay. Cascade chain logic created automatically Quartus software Compiler during design processing, manually designer during design entry. Cascade chains longer than implemented automatically linking LABs together. enhanced fitting, long cascade chain skips alternate LABs MegaLAB structure. cascade chain longer than skips either from even-numbered next even-numbered LAB, from odd-numbered next odd-numbered LAB. example, last first upper-left MegaLAB structure carries first third MegaLAB structure. Figure shows cascade function connect adjacent form functions with wide fan-in. Figure APEX Cascade Chain
Cascade Chain Cascade Chain
d[3.0]
d[3.0]
d[7.4]
d[7.4]
d[(4n 1).(4n
d[(4n 1).(4n
Altera Corporation
APEX Programmable Logic Device Family
Operating Modes
APEX operate following three modes:
Normal mode Arithmetic mode Counter mode
Each mode uses resources differently. each mode, seven available inputs LE-the four data inputs from local interconnect, feedback from programmable register, carry-in cascade-in from previous LE-are directed different destinations implement desired logic function. LAB-wide signals provide clock, asynchronous clear, asynchronous preset, asynchronous load, synchronous clear, synchronous load, clock enable control register. These LAB-wide signals available modes. Quartus software, conjunction with parameterized functions such DesignWare functions, automatically chooses appropriate mode common functions such counters, adders, multipliers. required, designer also create special-purpose functions that specify which operating mode optimal performance. Figure shows operating modes.
Altera Corporation
APEX Programmable Logic Device Family
Figure APEX Operating Modes
Normal Mode
Carry-In data1 data2 data3 data4 4-Input
LAB-Wide Clock Enable Cascade-In LE-Out
LE-Out
CLRN
Cascade-Out
Arithmetic Mode
Carry-In Cascade-In
LAB-Wide Clock Enable LE-Out
data1 data2
3-Input 3-Input Carry-Out
LE-Out
CLRN
Cascade-Out
Counter Mode
Cascade-In Carry-In
LAB-Wide Synchronous Load
LAB-Wide Synchronous Clear LAB-Wide Clock Enable LE-Out
data1 data2 data3 (data) 3-Input Carry-Out Cascade-Out
3-Input
LE-Out
CLRN
Notes:
normal mode support register packing. There LAB-wide clock enables LAB. When using carry-in normal mode, packed register feature unavailable. register feedback multiplexer available each LAB. DATA1 DATA2 input signals supply counter enable, down control, register feedback signals other than second LAB. LAB-wide synchronous clear wide synchronous load affect registers LAB.
Altera Corporation
APEX Programmable Logic Device Family
Normal Mode normal mode suitable general logic applications, combinatorial functions, wide decoding functions that take advantage cascade chain. normal mode, four data inputs from local interconnect carry-in inputs four-input LUT. Quartus software Compiler automatically selects carry-in DATA3 signal inputs LUT. output combined with cascade-in signal form cascade chain through cascade-out signal. normal mode support packed registers. Arithmetic Mode arithmetic mode ideal implementing adders, accumulators, comparators. arithmetic mode uses 3-input LUTs. computes three-input function; other generates carry output. shown Figure first uses carry-in signal data inputs from local interconnect generate combinatorial registered output. example, when implementing adder, this output three signals: DATA1, DATA2, carry-in. second uses same three signals generate carry-out signal, thereby creating carry chain. arithmetic mode also supports simultaneous cascade chain. arithmetic mode drive registered unregistered versions output. Quartus software implements parameterized functions that arithmetic mode automatically where appropriate; designer does need specify carry chain will used. Counter Mode counter mode offers clock enable, counter enable, synchronous up/down control, synchronous clear, synchronous load options. counter enable synchronous up/down control signals generated from data inputs local interconnect. synchronous clear synchronous load options LAB-wide signals that affect registers LAB. Consequently, counter mode, other that must used part same counter used combinatorial function. Quartus software automatically places registers that used counter into other LABs.
Altera Corporation
APEX Programmable Logic Device Family
counter mode uses three-input LUTs: generates counter data, other generates fast carry bit. 2-to-1 multiplexer provides synchronous loading, another gate provides synchronous clearing. cascade function used counter mode, synchronous clear load overrides signal carried cascade chain. synchronous clear overrides synchronous load. arithmetic mode drive registered unregistered versions output.
Clear Preset Logic Control
Logic register's clear preset signals controlled LAB-wide signals. directly supports asynchronous clear function. Quartus software Compiler NOT-gate push-back technique emulate asynchronous preset. Moreover, Quartus software Compiler programmable NOT-gate push-back technique emulate simultaneous preset clear asynchronous load. However, this technique uses three additional register. emulation performed automatically when design compiled. Registers that emulate simultaneous preset load will enter unknown state upon power-up when chip-wide reset asserted. addition clear preset modes, APEX devices provide chip-wide reset (DEV_CLRn) that resets registers device. this controlled through option Quartus software that before compilation. chip-wide reset overrides other control signals. Registers using asynchronous preset preset when chip-wide reset asserted; this effect results from inversion technique used implement asynchronous preset.
FastTrack Interconnect
APEX architecture, connections between LEs, ESBs, pins provided FastTrack Interconnect. FastTrack Interconnect series continuous horizontal vertical routing channels that traverse device. This global routing structure provides predictable performance, even complex designs. contrast, segmented routing FPGAs requires switch matrices connect variable number routing paths, increasing delays between logic resources reducing performance. FastTrack Interconnect consists column interconnect channels that span entire device. interconnect routes signals throughout MegaLAB structures; column interconnect routes signals throughout column MegaLAB structures. When using column interconnect, IOE, drive other IOE, device. Figure
Altera Corporation
APEX Programmable Logic Device Family
Figure APEX Interconnect Structure
Interconnect
MegaLAB
MegaLAB
MegaLAB
MegaLAB
MegaLAB
MegaLAB
MegaLAB
MegaLAB
Column Interconnect
Column Interconnect
MegaLAB
MegaLAB
MegaLAB
MegaLAB
line driven directly LEs, IOEs, ESBs that row. Further, column line drive line, allowing IOE, drive elements different column interconnect. interconnect drives MegaLAB interconnect drive LEs, IOEs, ESBs particular MegaLAB structure. column line directly driven LEs, IOEs, ESBs that column. column line device's left right edge also driven IOEs. column line used route signals from another. column line drive line; also drive MegaLAB interconnect directly, allowing faster connections between rows. Figure shows FastTrack Interconnect uses local interconnect drive within MegaLAB structures.
Altera Corporation
APEX Programmable Logic Device Family
Figure FastTrack Connection Local Interconnect
MegaLAB MegaLAB Column
Column Interconnect Drives MegaLAB Interconnect
MegaLAB Interconnect
MegaLAB Interconnect Drives Local Interconnect
Column
Altera Corporation
APEX Programmable Logic Device Family
Figure shows intersection column interconnect, these forms interconnects drive each other. Figure Driving FastTrack Interconnect
Interconnect
MegaLAB Interconnect
Column Interconnect
Local Interconnect
APEX 20KE devices include enhanced interconnect structure faster routing input signals with high fan-out. Column pins drive FastRow interconnect, which routes signals directly into local interconnect without having drive through MegaLAB interconnect. FastRow lines traverse MegaLAB structures. Also, these pins drive local interconnect directly fast setup times. EP20K300E larger devices, FastRow interconnect drives MegaLABs left corner, MegaLABs right corner, MegaLABS bottom left corner, MegaLABs bottom right corner. EP20K200E smaller devices, FastRow interconnect drives MegaLABs MegaLABs bottom device. devices, FastRow interconnect drives local interconnect appropriate MegaLABs except interconnect areas left right MegaLAB. Pins using FastRow interconnect achieve faster set-up time, signal does need MegaLab interconnect line reach destination Figure shows FastRow interconnect.
Altera Corporation
APEX Programmable Logic Device Family
Figure APEX 20KE FastRow Interconnect
FastRow Interconnect
FastRow Interconnect Drives Local Interconnect MegaLAB Structures
Select Vertical Pins Drive Local Interconnect FastRow Interconnect
Local Interconnect
MegaLAB
LABs
MegaLAB
Table summarizes various elements APEX architecture drive each other.
Altera Corporation
APEX Programmable Logic Device Family
Table APEX Routing Scheme Source
Column Column Local Interconnect MegaLAB Interconnect FastTrack Interconnect Column FastTrack Interconnect FastRow Interconnect Note:
This connection supported APEX 20KE devices only.
Destination
Local MegaLAB Interconnect Interconnect Column FastRow FastTrack FastTrack Interconnect Interconnect Interconnect
Product-Term Logic
product-term portion MultiCore architecture implemented with ESB. configured block macrocells ESB-by-ESB basis. Each inputs from adjacent local interconnect; therefore, driven MegaLAB interconnect adjacent LAB. Also, nine macrocells feed back into through local interconnect higher performance. Dedicated clock pins, global signals, additional inputs from local interconnect drive control signals. product-term mode, each contains macrocells. Each macrocell consists product terms programmable register. Figure shows product-term mode.
Altera Corporation
APEX Programmable Logic Device Family
Figure Product-Term Logic
Dedicated Clocks Global Signals
MegaLAB Interconnect
Macrocell Inputs (1-16) CLK[1.0] ENA[1.0] CLRN[1.0] Column Interconnect
From Adjacent
Local Interconnect
Note:
APEX 20KE devices have four dedicated clocks.
Macrocells
APEX macrocells configured individually either sequential combinatorial logic operation. macrocell consists three functional blocks: logic array, product-term select matrix, programmable register. Combinatorial logic implemented product terms. productterm select matrix allocates these product terms either primary logic inputs gates) implement combinatorial functions, parallel expanders used increase logic available another macrocell. product term inverted; Quartus software uses this feature perform DeMorgan's inversion more efficient implementation wide functions. Quartus software Compiler NOT-gate push-back technique emulate asynchronous preset. Figure shows APEX macrocell.
Altera Corporation
APEX Programmable Logic Device Family
Figure APEX Macrocell
ESB-Wide ESB-Wide ESB-Wide Clears Clock Enables Clocks Parallel Logic Expanders (From Other Macrocells)
Programmable Register
ProductTerm Select Matrix
Output
Clock/ Enable Select
CLRN
Signals from Local Interconnect
Clear Select
registered functions, each macrocell register programmed individually implement operation with programmable clock control. register bypassed combinatorial operation. During design entry, designer specifies desired register type; Quartus software then selects most efficient register operation each registered function optimize resource utilization. Quartus software other synthesis tools also select most efficient register operation automatically when synthesizing designs. Each programmable register clocked ESB-wide clocks. ESB-wide clocks generated from device dedicated clock pins, global signals, local interconnect. Each clock also associated clock enable, generated from local interconnect. clock clock enable signals related particular ESB; macrocell using clock also uses associated clock enable. both rising falling edges clock used ESB, both ESB-wide clock signals used.
Altera Corporation
APEX Programmable Logic Device Family
programmable register also supports asynchronous clear function. Within ESB, asynchronous clears generated from global signals local interconnect. Each macrocell either choose between asynchronous clear signals choose cleared. Either clear signals inverted within ESB. Figure shows control logic when implementing product-terms. Figure Product-Term Mode Control Logic
Dedicated Clocks Global Signals Local Interconnect Local Interconnect Local Interconnect Local Interconnect
CLK2
CLKENA2
CLK1
CLKENA1 CLR2
CLR1
Note:
APEX 20KE devices have four dedicated clocks.
Parallel Expanders
Parallel expanders unused product terms that allocated neighboring macrocell implement fast, complex logic functions. Parallel expanders allow product terms feed macrocell logic directly, with product terms provided macrocell parallel expanders provided neighboring macrocells ESB. Quartus software Compiler allocate sets parallel expanders macrocells automatically. Each parallel expanders incurs small, incremental timing delay. Figure shows APEX parallel expanders.
Altera Corporation
APEX Programmable Logic Device Family
Figure APEX Parallel Expanders
From Previous Macrocell
ProductTerm Select Matrix
Macrocell ProductTerm Logic Parallel Expander Switch
ProductTerm Select Matrix
Macrocell ProductTerm Logic Parallel Expander Switch
Signals from Local Interconnect
Next Macrocell
Embedded System Block
implement various types memory blocks, including dual-port RAM, ROM, FIFO, blocks. includes input output registers; input registers synchronize writes, output registers pipeline designs improve system performance. offers dual-port mode, which supports simultaneous reads writes different clock frequencies. Figure shows block diagram. Figure Block Diagram
wraddress[] data[] wren inclock inclocken inaclr rdaddress[] rden outclock outclocken outaclr
Altera Corporation
APEX Programmable Logic Device Family
ESBs implement synchronous RAM, which easier than asynchronous RAM. circuit using asynchronous must generate write enable (WE) signal, while ensuring that data address signals meet setup hold time specifications relative signal. contrast, ESB's synchronous generates signal self-timed with respect global clock. Circuits using ESB's selftimed must only meet setup hold time specifications global clock. inputs driven adjacent local interconnect, which turn driven MegaLAB FastTrack Interconnect. Because driven local interconnect, adjacent drive directly fast memory access. outputs drive MegaLAB FastTrack Interconnect. addition, outputs, nine which unique output lines, drive local interconnect fast connection adjacent fast feedback product-term logic. When implementing memory, each configured following sizes: 1,024 2,048 combining multiple ESBs, Quartus software implements larger memory blocks automatically. example, blocks combined form block, blocks combined form block. Memory performance does degrade memory blocks 2,048 words deep. Each implement 2,048-word-deep memory; ESBs used parallel, eliminating need external control logic associated delays. create high-speed memory block that more than 2,048 words deep, ESBs drive tri-state lines. Each tri-state line connects ESBs column MegaLAB structures, drives MegaLAB interconnect column FastTrack Interconnect throughout column. Each incorporates programmable decoder activate tri-state driver appropriately. instance, implement 8,192-word-deep memory, four ESBs used. Eleven address lines drive memory, more drive tri-state decoder. Depending which 2,048-word memory page selected, appropriate driver turned driving output tri-state line. Quartus software automatically combines ESBs with tri-state lines form deeper memory blocks. internal tri-state control logic designed avoid internal contention floating lines. Figure
Altera Corporation
APEX Programmable Logic Device Family
Figure Deep Memory Block Implemented with Multiple ESBs
Address Decoder
System Logic
implements forms dual-port memory: read/write clock mode input/output clock mode. also used bidirectional, dual-port memory applications which ports read write simultaneously. implement this type dual-port memory, four ESBs used support simultaneous reads writes. This functionality shown Figure Figure APEX Implementing Dual-Port
Port address_a[] data_a[] we_a clkena_a Clock Port address_b[] data_b[] we_b clkena_b Clock
Altera Corporation
APEX Programmable Logic Device Family
Read/Write Clock Mode
read/write clock mode contains clocks. clock controls registers associated with writing: data input, write address. other clock controls registers associated with reading: read enable (RE), read address, data output. also supports clock enable asynchronous clear signals; these signals also control read write registers independently. Read/write clock mode commonly used applications where reads writes occur different system frequencies. Figure shows read/write clock mode. Figure Read/Write Clock Mode
Dedicated Inputs Global Signals Dedicated Clocks RAM/ROM Data 1,024 2,048 Data
Note
data[
MegaLAB, FastTrack Local Interconnect
rdaddress[
Read Address
wraddress[
Write Address
rden
Read Enable
wren
outclken
Write Enable
inclken
inclock
Write Pulse Generator
outclock
Notes:
registers cleared asynchronously local interconnect signals, global signals, chip-wide reset. APEX 20KE devices have four dedicated clocks.
Altera Corporation
APEX Programmable Logic Device Family
Input/Output Clock Mode
input/output clock mode contains clocks. clock controls registers inputs into ESB: data input, read address, write address. other clock controls data output registers. also supports clock enable asynchronous clear signals; these signals also control reading writing registers independently. Input/output clock mode commonly used applications where reads writes occur same system frequency, require different clock enable signals input output registers. Figure shows input/output clock mode. Figure Input/Output Clock Mode
Dedicated Inputs Global Signals Dedicated Clocks RAM/ROM Data 1,024 2,048 Data
Notes (1),
data[
MegaLAB, FastTrack Local Interconnect
rdaddress[
Read Address
wraddress[
Write Address
rden
Read Enable
wren
outclken
Write Enable
inclken
inclock
Write Pulse Generator
outclock
Notes:
registers cleared asynchronously local interconnect signals, global signals, chip-wide reset. APEX 20KE devices have four dedicated clocks.
Altera Corporation
APEX Programmable Logic Device Family
Single-Port Mode
APEX also supports single-port mode, which used when simultaneous reads writes required. Figure Figure Single-Port Mode
Dedicated Inputs Global Signals Dedicated Clocks RAM/ROM Data 1,024 2,048 Data
Note
data[
MegaLAB, FastTrack Local Interconnect
address[
Address
wren
outclken
Write Enable
inclken
inclock
Write Pulse Generator
outclock
Notes:
registers asynchronously cleared local interconnect signals, global signals, chip-wide reset. APEX 20KE devices have four dedicated clocks.
Content-Addressable Memory
APEX 20KE devices, implement CAM. thought inverse RAM. When read, outputs data given address. Conversely, outputs address given data word. example, data FA12 stored address outputs when FA12 driven into used high-speed search operations. When searching data within block, search performed serially. Thus, finding particular data word take many cycles. searches addresses parallel outputs address storing particular word. When match found, match flag high. Figure shows block diagram.
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APEX Programmable Logic Device Family
Figure APEX 20KE Block Diagram
wraddress[] data[] wren inclock inclocken inaclr data_address[] match outclock outclocken outaclr
used application requiring high-speed searches, such networking, communications, data compression, cache management. APEX 20KE on-chip provides faster system performance than traditional discrete CAM. Integrating logic into APEX 20KE device eliminates off-chip on-chip delays, improving system performance. When mode, implements 32-word, 32-bit CAM. Wider deeper implemented combining multiple CAMs with some ancillary logic implemented LEs. Quartus software combines ESBs automatically create larger CAMs. supports writing "don't care" bits into words memory. "don't-care" used mask comparisons; "don't-care" effect matches. output encoded unencoded. When encoded, outputs encoded address data's location. instance, data located address output When unencoded, uses outputs show location data over clock cycles. this case, data located address 12th output line goes high. When using unencoded outputs, clock cycles required read output because 16-bit output used show status words. encoded output better suited designs that ensure duplicate data written into CAM. duplicate data written into locations, CAM's output will incorrect. contain duplicate data, unencoded output better solution; with unencoded outputs distinguish multiple data locations. pre-loaded with data during configuration, written during system operation. most cases, clock cycles required write each word into CAM. When "don't-care" bits used, third clock cycle required.
Altera Corporation
APEX Programmable Logic Device Family
more information APEX 20KE devices CAM, Application Note (Implementing High-Speed Search Applications with APEX CAM).
Driving Signals
ESBs provide flexible options driving control signals. Different clocks used inputs outputs. Registers inserted independently data input, data output, read address, write address, signals. global signals local interconnect drive signals. global signals, dedicated clock pins, local interconnect drive clock signals. Because drive local interconnect, control signals clock, clock enable, asynchronous clear signals. Figure shows control signal generation logic. Figure Control Signal Generation
Dedicated Clocks Global Signals Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect RDEN
INCLKENA
OUTCLKENA
WREN INCLOCK
OUTCLOCK
INCLR OUTCLR
Note:
APEX 20KE devices have four dedicated clocks.
local interconnect, which driven adjacent (for high-speed connection ESB) MegaLAB interconnect. drive local, MegaLAB, FastTrack Interconnect routing structure drive IOEs same MegaLAB structure anywhere device.
Altera Corporation
APEX Programmable Logic Device Family
Implementing Logic
addition implementing logic with product terms, implement logic functions when programmed with read-only pattern during configuration, creating large LUT. With LUTs, combinatorial functions implemented looking results, rather than computing them. This implementation combinatorial functions faster than using algorithms implemented general logic, performance advantage that further enhanced fast access times ESBs. large capacity ESBs enables designers implement complex functions logic level without routing delays associated with linked distributed blocks. Parameterized functions such functions take advantage automatically. Further, Quartus software implement portions design with ESBs where appropriate.
Programmable Speed/Power Control
APEX ESBs offer high-speed mode that supports very fast operation ESB-by-ESB basis. When high speed required, this feature turned reduce ESB's power dissipation 50%. ESBs that power incur nominal timing delay adder. This Turbo Bitoption available ESBs that implement product-term logic memory functions. that used will powered down that does consume current. Designers program each APEX device either high-speed low-power operation. result, speed-critical paths design high speed, while remaining paths operate reduced power.
Structure
APEX contains bidirectional buffer register that used either input register external data requiring fast setup times, output register data requiring fast clock-to-output performance. IOEs used input, output, bidirectional pins. fast bidirectional timing, registers using local routing improve setup times timing. Quartus software Compiler uses programmable inversion option invert signals from column interconnect automatically where appropriate. Because APEX offers output enable pin, Quartus software Compiler emulate open-drain operation efficiently. APEX includes programmable delays that activated ensure zero hold times, minimum clock-to-output times, input register-to-core register transfers, core-to-output register transfers. path which directly drives register require delay ensure zero hold time, whereas path which drives register through combinatorial logic require delay.
Altera Corporation
APEX Programmable Logic Device Family
Table describes APEX programmable delays their logic options Quartus software. Table APEX Programmable Delay Chains Programmable Delays
Input core delay Input input register delay Core output register delay Output register delay
Quartus Logic Option
Decrease input delay internal cells Decrease input delay input register Decrease input delay output register Increase delay output
Quartus software Compiler program these delays automatically minimize setup time while providing zero hold time. Figure shows fast bidirectional I/Os implemented APEX devices. register APEX programmed power-up high after configuration complete. programmed power-up low, asynchronous clear control register. programmed power-up high, register cannot asynchronously cleared preset. This feature useful cases where APEX device controls active-low input another device; prevents inadvertent activation input upon power-up.
Altera Corporation
APEX Programmable Logic Device Family
Figure APEX Bidirectional Registers
Row, Column, Local Interconnect Dedicated Clock Inputs Peripheral Control
Note
Dedicated Inputs
Register
CLRN
Chip-Wide Reset
OE[7.0]
Chip-Wide Output Enable
VCCIO
Input Core Delay Core Output Register Delay Input Input Register Delay CLK[1.0] CLRN Output Register Output Register CODelay
Optional Clamp
Open-Drain Output Slew-Rate Control
CLK[3.2] ENA[5.0]
CLRn[1.0]
Chip-Wide Reset Input Register
CLRN
Chip-Wide Reset
Note:
output enable input registers registers adjacent bidirectional pin.
Altera Corporation
APEX Programmable Logic Device Family
APEX 20KE devices include enhanced IOE, which drives FastRow interconnect. FastRow interconnect connects column directly local interconnect within MegaLAB structures. This feature provides fast setup times pins that drive high fan-outs with complex logic, such designs. fast bidirectional timing, registers using local routing improve setup times timing. APEX 20KE also includes direct support open-drain operation, giving faster clock-to-output open-drain signals. Some programmable delays APEX 20KE offer multiple levels delay fine-tune setup hold time requirements. Quartus software Compiler these delays automatically minimize setup time while providing zero hold time. Table describes APEX 20KE programmable delays their logic options Quartus software. Table APEX 20KE Programmable Delay Chains Programmable Delays
Input Core Delay Input Input Register Delay Core Output Register Delay Output Register Delay Clock Enable Delay
Quartus Logic Option
Decrease input delay internal cells Decrease input delay input registers Decrease input delay output register Increase delay output Increase clock enable delay
register APEX 20KE programmed power-up high after configuration complete. programmed power-up low, asynchronous clear control register. programmed power-up high, asynchronous preset control register. Figure shows fast bidirectional pins implemented APEX 20KE devices. This feature useful cases where APEX 20KE device controls active-low input another device; prevents inadvertent activation input upon power-up.
Altera Corporation
APEX Programmable Logic Device Family
Figure APEX 20KE Bidirectional Registers
Row, Column, FastRow, Dedicated Local Interconnect Clock Inputs Dedicated Inputs Peripheral Control
Notes (1),
Register
CLRN
Chip-Wide Reset
OE[7.0]
Chip-Wide Output Enable
Input Core Delay Input Core Delay Core Output Register Delay Input Input Register Delay CLK[1.0] Output Register Output Register Delay
VCCIO
Optional Clamp
Open-Drain Output Slew-Rate Control
CLRN/
CLK[3.0] ENA[5.0] Clock Enable Delay CLRn[1.0]
Chip-Wide Reset Input Register
CLRN
Input Core Delay
Chip-Wide Reset
Notes:
This programmable delay four settings: three levels delay. output enable input registers registers adjacent bidirectional pin.
Altera Corporation
APEX Programmable Logic Device Family
Each drives row, column, MegaLAB, local interconnect when used input bidirectional pin. drive local, MegaLAB, row, column interconnect; column drive column interconnect. Figure shows connects interconnect. Figure Connection Interconnect
Interconnect MegaLAB Interconnect
drive through row, column, MegaLAB interconnect.
Each drive local, MegaLAB, row, column interconnect. Each data signal driven local interconnect.
drive through local interconnect faster clock-to-output times.
Altera Corporation
APEX Programmable Logic Device Family
Figure shows column connects interconnect. Figure Column Connection Interconnect
Each drive column interconnect. APEX 20KE devices, IOEs also drive FastRow interconnect. Each data signal driven local interconnect.
drive through local interconnect faster clock-to-output times.
drive column through row, column, MegaLAB interconnect.
Column Interconnect
Interconnect
MegaLAB Interconnect
Dedicated Fast Pins
APEX 20KE devices incorporate enhancement support bidirectional pins with high internal fanout such control signals. These pins called Dedicated Fast pins (FAST1, FAST2, FAST3, FAST4) replace dedicated inputs. These pins used fast clock, clear, high fanout logic signal distribution. They also drive out. Dedicated Fast data output tri-state control driven local interconnect from adjacent MegaLAB high speed.
Altera Corporation
APEX Programmable Logic Device Family
Advanced Standard Support
APEX 20KE IOEs support following standards: LVTTL, LVCMOS, 1.8-V I/O, 2.5-V I/O, 3.3-V PCI, PCI-X, 3.3-V AGP, LVDS, LVPECL, GTL+, CTT, HSTL Class SSTL-3 Class SSTL-2 Class
more information standards supported APEX 20KE devices, Application Note (Using Selectable Standards Altera Devices). APEX 20KE device contains eight banks. packages, banks linked form four banks. banks directly support standards except LVDS LVPECL. banks support LVDS LVPECL with addition external resistors. addition, block within bank contains circuitry support high-speed True-LVDS LVPECL inputs, another block within particular bank supports high-speed True-LVDS LVPECL outputs. LVDS blocks support standards. Each bank VCCIO pins. single device support 1.8-V, 2.5-V, 3.3-V interfaces; each bank support different standard independently. Each bank also separate VREF level that each bank support terminated standards (such SSTL-3) independently. Within bank, terminated standards supported. EP20K300E larger APEX 20KE devices support LVDS interface data pins (smaller devices support LVDS clock pins, data pins). EP20K300E larger devices support LVDS interface data pins Mbit channel; EP20K400E devices larger with X-suffix ordering code serializer/deserializer circuit higher-speed support. Each bank support multiple standards with same VCCIO output pins. Each bank support voltage-referenced standard, support multiple standards with same VCCIO voltage level. example, when VCCIO bank support LVTTL, LVCMOS, 3.3-V PCI, SSTL-3 inputs outputs. When LVDS banks used LVDS banks, they support other standards. Figure shows arrangement APEX 20KE banks.
Altera Corporation
APEX Programmable Logic Device Family
Figure APEX 20KE Banks
Bank Bank
Bank Bank Regular Blocks Support LVTTL LVCMOS LVPECL HSTL Class GTL+ SSTL-2 Class SSTL-3 Class Individual Power LVDS/LVPECL Input Block
LVDS/LVPECL Output Block Bank
Bank
Bank
Bank
Notes:
first pins that border LVDS blocks only used input maintain acceptable noise level VCCIO plane. LVDS input output blocks used LVDS, they support standards used input, output, bidirectional pins with VCCIO
Power Sequencing Socketing
Because APEX APEX 20KE devices used mixedvoltage environment, they have been designed specifically tolerate possible power-up sequence. Therefore, VCCIO VCCINT power supplies powered order. Signals driven into APEX devices before during power-up without damaging device. addition, APEX devices drive during power-up. Once operating conditions reached device configured, APEX APEX 20KE devices operate specified user. Under socketing conditions, APEX 20KE devices will sustain damage, pins will drive out.
Altera Corporation
APEX Programmable Logic Device Family
MultiVolt Interface
APEX device architecture supports MultiVolt interface feature, which allows APEX devices packages interface with systems different supply voltages. devices have pins internal operation input buffers (VCCINT), another output drivers (VCCIO). APEX VCCINT pins must always connected power supply. With 2.5-V VCCINT level, input pins 2.5-V 3.3-V tolerant. Certain devices, identified suffix following speed grade ordering code (e.g., EP20K400BC652-1V), 5.0-V tolerant. VCCIO pins connected either 2.5-V 3.3-V power supply, depending output requirements. When VCCIO pins connected 2.5-V power supply, output levels compatible with 2.5-V systems. When VCCIO pins connected 3.3-V power supply, output high compatible with 3.3-V 5.0-V systems. Table summarizes 5.0-V tolerant APEX MultiVolt support. Table 5.0-V Tolerant APEX MultiVolt Support VCCIO
Notes:
clamping diode must disabled drive input with voltages higher than VCCIO. APEX devices with suffix 5.0-V tolerant. When VCCIO APEX device drive 2.5-V device with 3.3-V tolerant inputs.
Input Signals
v(1)
Output Signals
v(3)
v(1), v(1),
Open-drain output pins 5.0-V tolerant APEX devices (with pullup resistor 5.0-V supply) drive 5.0-V CMOS input pins that require When inactive, trace will pulled resistor. open-drain will only drive tri-state; will never drive high. rise time dependent value pullup resistor load impedance. current specification should considered when selecting pull-up resistor.
Altera Corporation
APEX Programmable Logic Device Family
APEX 20KE devices also support MultiVolt interface feature. APEX 20KE VCCINT pins must always connected 1.8-V power supply. With 1.8-V VCCINT level, input pins 1.8-V, 2.5-V, 3.3-V tolerant. VCCIO pins connected either 1.8-V, 2.5-V, 3.3-V power supply, depending standard requirements. When VCCIO pins connected 1.8-V power supply, output levels compatible with 1.8-V systems. When VCCIO pins connected 2.5-V power supply, output levels compatible with 2.5-V systems. When VCCIO pins connected 3.3-V power supply, output high compatible with 3.3-V 5.0-V systems. APEX 20KE device 5.0-V tolerant with addition resistor. Table summarizes APEX 20KE MultiVolt support. Table APEX 20KE MultiVolt Support VCCIO
Notes:
clamping diode must disabled drive input with voltages higher than VCCIO, except 5.0-V input case. APEX 20KE device made 5.0-V tolerant with addition external resistor. When VCCIO APEX 20KE device drive 2.5-V device with 3.3-V tolerant inputs.
Input Signals
Output Signals
v(1) v(1)
ClockLock ClockBoost Features
APEX devices support ClockLock ClockBoost clock management features, which implemented with PLLs. ClockLock circuitry uses synchronizing that reduces clock delay skew within device. This reduction minimizes clock-to-output setup times while maintaining zero hold times. ClockBoost circuitry, which provides clock multiplier, allows designer enhance device area efficiency sharing resources within device. ClockBoost circuitry allows designer distribute low-speed clock multiply that clock on-device. APEX devices include high-speed clock tree; unlike ASICs, user does have design optimize clock tree. ClockLock ClockBoost features work conjunction with APEX device's high-speed clock provide significant improvements system performance band-width. Devices with X-suffix ordering code include ClockLock circuit. ClockLock ClockBoost features APEX devices enabled through Quartus software. External devices required these features.
Altera Corporation
APEX Programmable Logic Device Family
designs that require both multiplied non-multiplied clock, clock trace board connected CLK2p. Table shows combinations supported ClockLock ClockBoost circuitry. CLK2p feed both ClockLock ClockBoost circuitry APEX device. However, when both circuits used, other clock (CLK1p) cannot used. Table Multiplication Factor Combinations Clock
Clock
APEX 20KE ClockLock Feature
APEX 20KE devices include enhanced ClockLock feature set. These devices include four PLLs, which used independently. PLLs designed either general-purpose LVDS devices that support LVDS pins). remaining PLLs designed general-purpose use. EP20K200E smaller devices have PLLs; EP20K300E larger devices have four PLLs. following sections describe some features offered APEX 20KE PLLs.
External Feedback
ClockLock circuit's output driven off-chip clock other devices system; further, feedback loop routed off-chip. This feature allows designer exercise fine control over interface between APEX 20KE device another high-speed device, such SDRAM.
Clock Multiplication
APEX 20KE ClockBoost circuit multiply divide clocks programmable number. clock multiplied m/(n m/(n where range from 160, vrange from Clock multiplication division used time-domain multiplexing other functions, which reduce design requirements.
Altera Corporation
APEX Programmable Logic Device Family
Clock Phase Delay Adjustment
APEX 20KE ClockShift feature allows clock phase delay adjusted. clock phase adjusted steps. clock delay adjusted increase decrease clock delay arbitrary amount, clock period.
LVDS Support
PLLs designed support LVDS interface. When using LVDS, clock runs slower rate than data transfer rate. Thus, PLLs used multiply clock internally capture LVDS data. example, clock support megabits second (Mbps) LVDS data transfer. this example, multiplies incoming clock eight support high-speed data transfer. PLLs EP20K400E larger devices high-speed LVDS interfacing.
Lock Signals
APEX 20KE ClockLock circuitry supports individual LOCK signals. LOCK signal drives high when ClockLock circuit locked onto input clock. LOCK signals optional each ClockLock circuit; when used, they pins.
ClockLock ClockBoost Timing Parameters
ClockLock ClockBoost circuitry function properly, incoming clock must meet certain requirements. these specifications met, circuitry lock onto incoming clock, which generates erroneous clock within device. clock generated ClockLock ClockBoost circuitry must also meet certain specifications. incoming clock meets these requirements during configuration, APEX ClockLock ClockBoost circuitry will lock onto clock during configuration. circuit will ready immediately after configuration. APEX 20KE devices, clock input standard programmable, cannot respond clock until device configured. locks onto input clock soon configuration complete. Figure shows incoming generated clock specifications. more information ClockLock ClockBoost circuitry, Application Note 115: Using ClockLock ClockBoost Features APEX Devices.
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APEX Programmable Logic Device Family
Figure Specifications Incoming Generated Clocks
parameter refers nominal input clock period; parameter refers nominal output clock period.
CLK1, CLK2 CLK4 INDUTY CLKDEV
Input Clock
OUTDUTY
INCLKSTB
ClockLock Generated Clock
JITTER
JITTER
Table summarizes APEX ClockLock ClockBoost parameters speed-grade devices. Table APEX ClockLock ClockBoost Parameters Speed-Grade Devices (Part Symbol
fOUT fCLK1 fCLK2 fCLK4 tOUTDUTY
Parameter
Output frequency Input clock frequency (ClockBoost clock multiplication factor equals Input clock frequency (ClockBoost clock multiplication factor equals Input clock frequency (ClockBoost clock multiplication factor equals Duty cycle ClockLock/ClockBoost-generated clock Input deviation from user specification Quartus software (ClockBoost clock multiplication factor equals Input rise time Input fall time
Unit
fCLKDEV
25,000
Altera Corporation
APEX Programmable Logic Device Family
Table APEX ClockLock ClockBoost Parameters Speed-Grade Devices (Part Symbol
tLOCK
Parameter
Time required ClockLock/ClockBoost acquire lock(4) Skew delay between related ClockLock/ClockBoost-generated clocks Jitter ClockLock/ClockBoostgenerated clock Input clock stability (measured between adjacent clocks)
Unit
tSKEW
tJITTER tINCLKSTB
Notes:
input frequency range EP20K100-1X device multiplication MHz. input clock specifications must met. lock onto incoming clock clock specifications met, creating erroneous clock within device. During device configuration, ClockLock ClockBoost circuitry configured first. incoming clock supplied during configuration, ClockLock ClockBoost circuitry locks during configuration, because lock time less than configuration time. jitter specification measured under long-term observation. input clock stability tJITTER
Altera Corporation
APEX Programmable Logic Device Family
Table summarizes APEX ClockLock ClockBoost parameters speed grade devices. Table APEX ClockLock ClockBoost Parameters Speed Grade Devices Symbol
fOUT CLK1 CLK2 CLK4 OUTDUTY CLKDEV
Parameter
Output frequency Input clock frequency (ClockBoost clock multiplication factor equals Input clock frequency (ClockBoost clock multiplication factor equals Input clock frequency (ClockBoost clock multiplication factor equals Duty cycle ClockLock/ClockBoostgenerated clock Input deviation from user specification Quartus software (ClockBoost clock multiplication factor equals one) Input rise time Input fall time Time required ClockLock/ ClockBoost acquire lock Skew delay between related ClockLock/ ClockBoost-generated clock Jitter ClockLock/ ClockBoostgenerated clock Input clock stability (measured between adjacent clocks)
25,000
Unit
LOCK
SKEW
JITTER INCLKSTB
Notes:
implement ClockLock ClockBoost circuitry with Quartus software, designers must specify input frequency. Quartus software tunes ClockLock ClockBoost circuitry this frequency. fCLKDEV parameter specifies much incoming clock differ from specified frequency during device operation. Simulation does reflect this parameter. Twenty-five thousand parts million (PPM) equates 2.5% input clock period. During device configuration, ClockLock ClockBoost circuitry configured before rest device. incoming clock supplied during configuration, ClockLock ClockBoost circuitry locks during configuration because tLOCK value less than time required configuration. tJITTER specification measured under long-term observation.
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APEX Programmable Logic Device Family
Tables summarize ClockLock ClockBoost parameters APEX 20KE devices. Table APEX 20KE ClockLock ClockBoost Parameters Symbol
INDUTY INJITTER tOUTJITTER tOUTDUTY tLOCK (2),
Note
input period 0.35% output period
Parameter
Input rise time Input fall time Input duty cycle Input jitter peak-to-peak Jitter ClockLock ClockBoostgenerated clock Duty cycle ClockLock ClockBoost-generated clock Time required ClockLock ClockBoost acquire lock
Condition
Unit
peak-topeak
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APEX Programmable Logic Device Family
Table APEX 20KE Clock Input Output Parameters Symbol Parameter Standard
Note Speed Grade
Speed Grade
Units
fVCO fCLOCK0 fCLOCK1 fCLOCK0_EXT
Voltage controlled oscillator operating range Clock0 output frequency internal Clock1 output frequency internal Output clock frequency external clock0 output 3.3-V LVTTL 2.5-V LVTTL 1.8-V LVTTL GTL+ SSTL-2 Class SSTL-2 Class SSTL-3 Class SSTL-3 Class LVDS
fCLOCK1_EXT
Output clock frequency external clock1 output
3.3-V LVTTL 2.5-V LVTTL 1.8-V LVTTL GTL+ SSTL-2 Class SSTL-2 Class SSTL-3 Class SSTL-3 Class LVDS
Input clock frequency
3.3-V LVTTL 2.5-V LVTTL 1.8-V LVTTL GTL+ SSTL-2 Class SSTL-2 Class SSTL-3 Class SSTL-3 Class LVDS
Notes tables:
input clock specifications must met. lock onto incoming clock clock specifications met, creating erroneous clock within device. maximum lock time 2000 input clock cycles, whichever occurs first. Before configuration, circuits disable powered down. During configuration, PLLs still disabled. PLLs begin lock once device user mode. clock enable feature used, lock begins once CLKLK_ENA goes high user mode. operating range fVCO LVDS mode.
Altera Corporation
APEX Programmable Logic Device Family
SignalTap Embedded Logic Analyzer
APEX devices include device enhancements support SignalTap embedded logic analyzer. including this circuitry, APEX device provides ability monitor design operation over period time through IEEE Std. 1149.1 (JTAG) circuitry; designer analyze internal logic speed without bringing internal signals pins. This feature particularly important advanced packages such FineLine packages because adding connection during debugging process difficult after board designed manufactured. APEX devices provide JTAG circuitry that complies with IEEE Std. 1149.1-1990 specification. JTAG boundary-scan testing performed before after configuration, during configuration. APEX devices also JTAG port configuration with Quartus software with hardware using either Files (.jam) Byte-Code Files (.jbc). Finally, APEX devices JTAG port monitor logic operation device with SignalTap embedded logic analyzer. APEX devices support JTAG instructions shown Table Although EP20K1500E devices support JTAG BYPASS SignalTap instructions, they support boundary-scan testing JTAG port configuration.
IEEE Std. 1149.1 (JTAG) Boundary-Scan Support
Table APEX JTAG Instructions JTAG Instruction
SAMPLE/PRELOAD
Description
Allows snapshot signals device pins captured examined during normal device operation, permits initial data pattern output device pins. Also used SignalTap embedded logic analyzer. Allows external circuitry board-level interconnections tested forcing test pattern output pins capturing test results input pins. Places 1-bit bypass register between pins, which allows data pass synchronously through selected devices adjacent devices during normal device operation. Selects 32-bit USERCODE register places between pins, allowing USERCODE serially shifted TDO. Selects IDCODE register places between TDO, allowing IDCODE serially shifted TDO. Used when configuring APEX device JTAG port with MasterBlasteror ByteBlasterMVdownload cable, when using File Byte-Code File embedded processor. Monitors internal device operation with SignalTap embedded logic analyzer.
EXTEST BYPASS USERCODE IDCODE Instructions
SignalTap Instructions Note:
EP20K1500E device supports JTAG BYPASS instruction SignalTap instructions.
Altera Corporation
APEX Programmable Logic Device Family
APEX device instruction register length bits. APEX device USERCODE register length bits. Tables show boundary-scan register length device IDCODE information APEX devices. Table APEX Boundary-Scan Register Length Device
EP20K30E EP20K60E EP20K100 EP20K100E EP20K160E EP20K200 EP20K200E EP20K300E EP20K400 EP20K400E EP20K600E EP20K1000E EP20K1500E Note:
This device does support JTAG boundary scan testing.
Boundary-Scan Register Length
1,176 1,164 1,266 1,536 1,506 1,806 2,190
Altera Corporation
APEX Programmable Logic Device Family
Table 32-Bit APEX Device IDCODE Device Version Bits)
EP20K30E EP20K60E EP20K100 EP20K100E EP20K160E EP20K200 EP20K200E EP20K300E EP20K400 EP20K400E EP20K600E EP20K1000E Notes:
most significant (MSB) left. IDCODE's least significant (LSB) always
IDCODE Bits) Part Number Bits)
1000 0000 0011 0000 1000 0000 0110 0000 0000 0100 0001 0110 1000 0001 0000 0000 1000 0001 0110 0000 0000 1000 0011 0010 1000 0010 0000 0000 1000 0011 0000 0000 0001 0110 0110 0100 1000 0100 0000 0000 1000 0110 0000 0000 1001 0000 0000 0000
Manufacturer Identity Bits)
0110 1110 0110 1110 0110 1110 0110 1110 0110 1110 0110 1110 0110 1110 0110 1110 0110 1110 0110 1110 0110 1110 0110 1110
Bit)
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
Figure shows timing requirements JTAG signals. Figure APEX JTAG Waveforms
tJPZX tJSSU Signal Captured Signal Driven tJSH JPCO JPXZ JPSU
tJSZX
tJSCO
tJSXZ
Altera Corporation
APEX Programmable Logic Device Family
Table shows JTAG timing parameters values APEX devices. Table APEX JTAG Timing Parameters Values Symbol
tJCP tJCH tJCL tJPSU tJPH tJPCO tJPZX tJPXZ tJSSU tJSH tJSCO tJSZX tJSXZ clock period clock high time clock time JTAG port setup time JTAG port hold time JTAG port clock output JTAG port high impedance valid output JTAG port valid output high impedance Capture register setup time Capture register hold time Update register clock output Update register high impedance valid output Update register valid output high impedance
Parameter
Unit
more information, following documents:
Application Note (IEEE Std. 1149.1 (JTAG) Boundary-Scan Testing Altera Devices) Programming Test Language Specification
Generic Testing
Each APEX device functionally tested. Complete testing each configurable static random access memory (SRAM) logic functionality ensures 100% yield. test measurements APEX devices made under conditions equivalent those shown Figure Multiple test patterns used configure devices during stages production flow.
Altera Corporation
APEX Programmable Logic Device Family
Figure APEX Test Conditions
Power supply transients affect measurements. Simultaneous transitions Device Output multiple outputs should avoided accurate measurement. Threshold tests must performed under conditions. Large-amplitude, fast-ground-current transients normally occur device Device input rise fall outputs discharge load capacitances. times When these transients flow through parasitic inductance between device ground test system ground, significant reductions observable noise immunity result.
Test System
(includes capacitance)
Operating Conditions
Tables through provide information absolute maximum ratings, recommended operating conditions, operating conditions, capacitance 2.5-V APEX devices. Note
-0.5 -0.5 -0.5 bias Under bias PQFP, RQFP, TQFP, packages, under bias Ceramic packages, under bias
Table APEX Device Absolute Maximum Ratings Symbol
CCINT CCIO input voltage output current, Storage temperature Ambient temperature Junction temperature
Parameter
Supply voltage
Conditions
With respect ground
Unit
Altera Corporation
APEX Programmable Logic Device Family
Table APEX Device Recommended Operating Conditions Symbol
CCINT CCIO
Parameter
Supply voltage internal logic input buffers (3),
Conditions
2.375 (2.375) 3.00 (3.00) 2.375 (2.375) -0.5
2.625 (2.625) 3.60 (3.60) 2.625 (2.625) CCIO
Unit
Supply voltage output buffers, 3.3-V (3), operation Supply voltage output buffers, 2.5-V (3), operation
Input voltage Output voltage Junction temperature Input rise time (10% 90%) Input fall time (90% 10%)
(2), commercial industrial
Table APEX Device Operating Conditions (Part Symbol
Notes (6),
0.8, VCCIO
Parameter
High-level LVTTL, LVCMOS, 3.3-V input voltage Low-level LVTTL, LVCMOS, 3.3-V input voltage 3.3-V high-level LVTTL output voltage 3.3-V high-level LVCMOS output voltage
Conditions
Unit
1.7, VCCIO -0.5 CCIO 3.00 -0.1 CCIO 3.00 CCIO VCCIO
3.3-V high-level output voltage -0.5 CCIO 3.00 3.60 2.5-V high-level output voltage -0.1 CCIO 2.30 CCIO 2.30 CCIO 2.30
Altera Corporation
APEX Programmable Logic Device Family
Table APEX Device Operating Conditions (Part Symbol
Notes (6),
VCCIO
Parameter
3.3-V low-level LVTTL output voltage 3.3-V low-level LVCMOS output voltage
Conditions
CCIO 3.00 (10) CCIO 3.00 (10)
Unit
3.3-V low-level output voltage CCIO 3.00 3.60 (10) 2.5-V low-level output voltage CCIO 2.30 (10) CCIO 2.30 (10) CCIO 2.30 (10) Input leakage current Tri-stated leakage current supply current (standby) (All ESBs power-down mode) -0.5 (11) -0.5 (11) ground, load, toggling inputs, speed grade ground, load, toggling inputs, speed grades CONF Value pull-up resistor before during configuration CCIO (12) CCIO 2.375 (12)
Table APEX Device Capacitance Symbol
CINCLK COUT
Note (13) Conditions
Parameter
Input capacitance Input capacitance dedicated clock Output capacitance
Unit
VOUT
Altera Corporation
APEX Programmable Logic Device Family Data Sheet Notes tables:
(10) (11) (12) (13) Operating Requirements Altera Devices Data Sheet. Minimum input -0.5 During transitions, inputs undershoot -2.0 overshoot input currents less than periods shorter than Numbers parentheses industrial-temperature-range devices. Maximum rise time must rise monotonically. pins, including dedicated inputs, clock, I/O, JTAG pins, driven before VCCINT VCCIO powered. Typical values CCINT CCIO These values specified under APEX device recommended operating conditions, shown Table page APEX input buffers compatible with 2.5-V 3.3-V (LVTTL LVCMOS) signals. Additionally, input buffers 3.3-V compliant when VCCIO VCCINT meet relationship shown Figure page parameter refers high-level TTL, PCI, CMOS output current. parameter refers low-level TTL, PCI, CMOS output current. This parameter applies open-drain pins well output pins. This value specified normal device operation. value vary during power-up. pull-up resistance values will lower external source drives higher than VCCIO. Capacitance sample-tested only.
Tables through provide information absolute maximum ratings, recommended operating conditions, operating conditions, capacitance 5.0-V tolerant APEX devices. These devices identified suffix following speed grade ordering code (e.g., EP20K400BC652-1V). Table APEX 5.0-V Tolerant Device Absolute Maximum Ratings Symbol
CCINT VCCIO IOUT TSTG TAMB input voltage output current, Storage temperature Ambient temperature Junction temperature bias Under bias PQFP, RQFP, TQFP, packages, under bias Ceramic packages, under bias
Note
-0.5 -0.5 -2.0
Parameter
Supply voltage
Conditions
With respect ground
5.75
Unit
Altera Corporation
APEX Programmable Logic Device Family
Table APEX 5.0-V Tolerant Device Recommended Operating Conditions Symbol
CCINT CCIO
Parameter
Supply voltage internal logic input buffers (3),
Conditions
2.375 (2.375)
2.625 (2.625)
Unit
Supply voltage output buffers, (3), 3.3-V operation Supply voltage output buffers, (3), 2.5-V operation
3.00 (3.00) 3.60 (3.60) 2.375 (2.375) -0.5 2.625 (2.625) 5.75 VCCIO
Input voltage Output voltage Junction temperature
(2), commercial industrial
Input rise time Input fall time
Table APEX 5.0-V Tolerant Device Operating Conditions (Part Symbol
Notes (6),
5.75 0.8, VCCIO
Parameter
High-level input voltage Low-level input voltage 3.3-V high-level output voltage 3.3-V high-level CMOS output voltage
Conditions
1.7, VCCIO -0.5
Unit
CCIO 3.00 -0.1 CCIO 3.00
CCIO VCCIO
3.3-V high-level output voltage -0.5 CCIO 3.00 3.60 2.5-V high-level output voltage -0.1 CCIO 2.30 CCIO 2.30 CCIO 2.30
Altera Corporation
APEX Programmable Logic Device Family
Table APEX 5.0-V Tolerant Device Operating Conditions (Part Symbol
Notes (6),
0.45 VCCIO
Parameter
Conditions
Unit
3.3-V low-level output voltage CCIO 3.00 (10) 3.3-V low-level CMOS output voltage CCIO 3.00 (10)
3.3-V low-level output voltage CCIO 3.00 3.60 (10) 2.5-V low-level output voltage CCIO 2.30 (10) CCIO 2.30 (10) CCIO 2.30 (10) Input leakage current Tri-stated leakage current supply current (standby) (All ESBs power-down mode) 5.75 -0.5 5.75 -0.5 ground, load, toggling inputs, speed grade (11) ground, load, toggling inputs, speed grades (11) CONF Value pull-up resistor before during configuration CCIO (12) CCIO 2.375 (12)
Table APEX 5.0-V Tolerant Device Capacitance Symbol
CINCLK COUT
Note (13)
Parameter
Input capacitance Input capacitance dedicated clock Output capacitance
Conditions
VOUT
Unit
Altera Corporation
APEX Programmable Logic Device Family Data Sheet Notes tables:
(10) (11) (12) (13) Operating Requirements Altera Devices Data Sheet. Minimum input -0.5 During transitions, inputs undershoot -2.0 overshoot 5.75 input currents less than periods shorter than Numbers parentheses industrial-temperature-range devices. Maximum rise time must rise monotonically. pins, including dedicated inputs, clock I/O, JTAG pins, driven before VCCINT VCCIO powered. Typical values VCCINT VCCIO These values specified APEX device recommended operating conditions, shown Table page APEX input buffers compatible with 2.5-V 3.3-V (LVTTL LVCMOS) signals. Additionally, input buffers 3.3-V compliant when VCCIO VCCINT meet relationship shown Figure page parameter refers high-level TTL, CMOS output current. parameter refers low-level TTL, PCI, CMOS output current. This parameter applies open-drain pins well output pins. This value specified normal device operation. value vary during power-up. pull-up resistance values will lower external source drives higher than VCCIO. Capacitance sample-tested only.
Tables through provide information absolute maximum ratings, recommended operating conditions, operating conditions, capacitance 1.8-V APEX 20KE devices. Table APEX 20KE Device Absolute Maximum Ratings Symbol
CCINT CCIO input voltage output current, Storage temperature Ambient temperature Junction temperature bias Under bias PQFP, RQFP, TQFP, packages, under bias Ceramic packages, under bias
Note
-0.5 -0.5 -0.5
Parameter
Supply voltage
Conditions
With respect ground
Unit
Altera Corporation
APEX Programmable Logic Device Family
Table APEX 20KE Device Recommended Operating Conditions Symbol
CCINT CCIO
Parameter
Supply voltage internal logic input buffers (3),
Conditions
1.71 (1.71) 3.00 (3.00) 2.375 (2.375) 1.71 (1.71) -0.5
1.89 (1.89) 3.60 (3.60) 2.625 (2.625) 1.89 (1.89) CCIO
Unit
Supply voltage output buffers, 3.3-V (3), operation Supply voltage output buffers, 2.5-V (3), operation Supply voltage output buffers, 1.8-V (3), operation
Input voltage Output voltage Junction temperature Input rise time Input fall time
(2), commercial industrial
Altera Corporation
APEX Programmable Logic Device Family
Table APEX 20KE Device Operating Conditions Symbol
Notes (6), (7),
1.7, VCCIO -0.5
Parameter
High-level LVTTL, CMOS, 3.3-V input voltage Low-level LVTTL, CMOS, 3.3-V input voltage 3.3-V high-level LVTTL output voltage 3.3-V high-level LVCMOS output voltage
Conditions
0.8, VCCIO
Unit
CCIO 3.00 -0.1 CCIO 3.00
CCIO VCCIO VCCIO
3.3-V high-level output voltage -0.5 CCIO 3.00 3.60 2.5-V high-level output voltage -0.1 CCIO 2.30 CCIO 2.30 CCIO 2.30 3.3-V low-level LVTTL output voltage 3.3-V low-level LVCMOS output voltage CCIO 3.00 (10) CCIO 3.00 (10)
3.3-V low-level output voltage CCIO 3.00 3.60 (10) 2.5-V low-level output voltage CCIO 2.30 (10) CCIO 2.30 (10) CCIO 2.30 (10) Input leakage current Tri-stated leakage current supply current (standby) (All ESBs power-down mode) -0.5 (11) -0.5 (11) ground, load, toggling inputs, speed grade ground, load, toggling inputs, speed grades CONF Value pull-up resistor before during configuration CCIO (12) CCIO 2.375 (12) CCIO 1.71 (12)
Altera Corporation
APEX Programmable Logic Device Family
Operating Specifications APEX 20KE standards, please refer Application Note (Using Selectable Standards Altera Devices). Note (13) Conditions
VOUT
Table APEX 20KE Device Capacitance Symbol
CINCLK COUT
Parameter
Input capacitance Input capacitance dedicated clock Output capacitance
Unit
Notes tables:
Operating Requirements Altera Devices Data Sheet. Minimum input -0.5 During transitions, inputs undershoot -0.5 overshoot input currents less than periods shorter than Numbers parentheses industrial-temperature-range devices. Maximum rise time must rise monotonically. pins, including dedicated inputs, clock, I/O, JTAG pins, driven before VCCINT VCCIO powered. Typical values CCINT CCIO These values specified under APEX 20KE device recommended operating conditions, shown Table page Refer Application Note (Using Selectable Standards Altera Devices) VIH, VIL, VOH, VOL, parameters when VCCIO APEX 20KE input buffers compatible with 1.8-V, 2.5-V 3.3-V (LVTTL LVCMOS) signals. Additionally, input buffers 3.3-V compliant. Input buffers also meet specifications GTL+, CTT, AGP, SSTL-2, SSTL-3, HSTL. parameter refers high-level TTL, PCI, CMOS output current. parameter refers low-level TTL, PCI, CMOS output current. This parameter applies open-drain pins well output pins. This value specified normal device operation. value vary during power-up. pull-up resistance values will lower external source drives higher than VCCIO. Capacitance sample-tested only.
(10) (11) (12) (13) (14)
Figure shows relationship between VCCIO VCCINT 3.3-V compliance APEX devices.
Altera Corporation
APEX Programmable Logic Device Family
Figure Relationship between VCCIO VCCINT 3.3-V Compliance
VCCINT
PCI-Compliant Region
VCCIO
Figure shows typical output drive characteristics APEX devices with 3.3-V 2.5-V VCCIO. output driver compatible with 3.3-V Local Specification, Revision (when VCCIO pins connected tolerant APEX devices speed grade compliant over operating conditions. Figure Output Drive Characteristics APEX Device
Note
Typical Output Current (mA)
VCCINT VCCIO Room Temperature
Typical Output Current (mA)
VCCINT VCCIO Room Temperature
Output Voltage
Output Voltage
Note:
These transient (AC) currents.
Altera Corporation
APEX Programmable Logic Device Family
Figure shows output drive characteristics APEX 20KE devices. Figure Output Drive Characteristics APEX 20KE Devices
Typical Output Current (mA) VCCINT VCCIO Room Temperature
Note
Typical Output Current (mA)
VCCINT VCCIO 2.5V Room Temperature
Output Voltage
Output Voltage
Typical Output Current (mA) VCCINT 1.8V VCCIO 1.8V Room Temperature
Output Voltage
Note:
These transient (AC) currents.
Altera Corporation
APEX Programmable Logic Device Family
Timing Model
high-performance FastTrack MegaLAB interconnect routing resources ensure predictable performance, accurate simulation, accurate timing analysis. This predictable performance contrasts with that FPGAs, which segmented connection scheme therefore have unpredictable performance. specifications always representative worst-case supply voltage junction temperature conditions. output-pin-timing specifications reported maximum driver strength. Figure shows fMAX timing model APEX devices. Figure APEX fMAX Timing Model
tLUT
Routing Delay
F1-4 F5-20 tF20+
tESBRC tESBWC tESBWESU tESBDATASU tESBADDRSU tESBDATACO1 tESBDATACO2 tESBDD tPTERMSU tPTERMCO
Figure shows fMAX timing model APEX 20KE devices. These parameters used estimate fMAX multipule levels logic. Quartus software timing analysis should used more accurate timing information.
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APEX Programmable Logic Device Family
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APEX Programmable Logic Device Family
Figure APEX 20KE fMAX Timing Model
Routing Delay
F1-4 F5-20 F20+
ESBARC ESBSRC ESBAWC ESBSWC ESBWASU ESBWDSU ESBSRASU ESBSWDSU ESBWDH ESBRASU ESBRAH ESBWESU ESBWEH ESBDATASU ESBWADDRSU ESBRADDRSU ESBDATACO1 ESBDATACO2 ESBDD PTERMSU PTERMCO
Altera Corporation
APEX Programmable Logic Device Family
Figures show asynchronous synchronous timing waveforms, respectively, macroparameters Table Figure Asynchronous Timing Waveforms
Asynchronous Read
Rdaddress
tESBARC
Data-Out
Asynchronous Write
tESBWP tESBWDSU tESBWDH
Data-In
din0
tESBWASU tESBWCCOMB
din1
tESBWAH
Wraddress
tESBDD
Data-Out
din0
din1
dout2
Altera Corporation
APEX Programmable Logic Device Family
Figure Synchronous Timing Waveforms
Synchronous Read
Rdaddress
tESBDATASU
tESBDATAH
tESBARC
tESBDATACO2
Data-Out
Synchronous Write (ESB Output Registers Used)
Data-In
din1
din2
din3
Wraddress
tESBWESU tESBDATASU
tESBDATAH
tESBWEH
tESBSWC tESBDATACO1
Data-Out
dout0
dout1
din1
din2
din3
din2
Figure shows timing model bidirectional timing.
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APEX Programmable Logic Device Family
Figure Synchronous Bidirectional External Timing
Register Dedicated Clock
tXZBIDIR tZXBIDIR tOUTCOBIDIR
Bidirectional
CLRN
Output Register
CLRN
Register
tINSUBIDIR tINHBIDIR
Input Register
CLRN
Notes:
output enable input registers registers adjacent bidirectional pin. output enable register with "Output Enable Routing= Signal-Pin" option Quartus software. adjacent input register with "Decrease Input Delay Internal Cells= Off". This maintains zero hold time adjacent registers while giving fast, position independent setup time. faster setup time with zero hold time possible setting "Decrease Input Delay Internal Cells= moving input register farther away from bi-directional pin. exact position where zero hold occurs with minimum setup time, varies with device density speed grade.
Table describes fMAX timing parameters shown Figure Table APEX fMAX Timing Parameters Symbol
tLUT tESBRC tESBWC tESBWESU tESBDATASU tESBADDRSU tESBDATACO1 tESBDATACO2 register setup time before clock register hold time after clock register clock-to-output delay delay data-in Asynchronous read cycle time Asynchronous write cycle time setup time before clock when using input register data setup time before clock when using input register address setup time before clock when using input registers clock-to-output delay when using output registers clock-to-output delay without output registers Altera Corporation
(Part Parameter
APEX Programmable Logic Device Family
Table APEX fMAX Timing Parameters Symbol
tESBDD tPTERMSU tPTERMCO tF1-4 tF5-20 tF20+ tCLRP tPREP tESBCH tESBCL tESBWP tESBRP
(Part Parameter
data-in data-out delay mode macrocell input non-registered output macrocell register setup time before clock macrocell register clock-to-output delay Fanout delay using local interconnect Fanout delay using MegaLab Interconnect Fanout delay using FastTrack Interconnect Minimum clock high time from clock Minimum clock time from clock clear pulse width preset pulse width Clock high time Clock time Write pulse width Read pulse width
Tables describe APEX external timing parameters. Table APEX External Timing Parameters Symbol
tINSU tINH tOUTCO
Note Conditions
Clock Parameter
Setup time with global clock register Hold time with global clock register Clock-to-output delay with global clock register
Table APEX External Bidirectional Timing Parameters Symbol
tINSUBIDIR tINHBIDIR tOUTCOBIDIR tXZBIDIR tZXBIDIR Note tables:
These timing parameters sample-tested only.
Note Condition
Parameter
Setup time bidirectional pins with global clock same-row samecolumn register Hold time bidirectional pins with global clock same-row samecolumn register Clock-to-output delay bidirectional pins with global clock register Synchronous output buffer disable delay Synchronous output buffer enable delay, slow slew rate
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APEX Programmable Logic Device Family
Table through show APEX 20KE ESB, routing, functional timing microparameters fMAX timing model. Table APEX 20KE Timing Microparameters Symbol
tLUT
Parameter
register setup time before clock register hold time after clock register clock-to-output delay delay data-in data-out
Table APEX 20KE Timing Microparameters Symbol
tESBARC tESBSRC tESBAWC tESBSWC tESBWASU tESBWAH tESBWDSU tESBWDH tESBRASU tESBRAH tESBWESU tESBWEH tESBDATASU tESBWADDRSU tESBRADDRSU tESBDATACO1 tESBDATACO2 tESBDD tPTERMSU tPTERMCO
Parameter
Asynchronous read cycle time Synchronous read cycle time Asynchronous write cycle time Synchronous write cycle time write address setup time with respect write address hold time with respect data setup time with respect data hold time with respect read address setup time with respect read address hold time with respect setup time before clock when using input register hold time after clock when using input register data setup time before clock when using input register write address setup time before clock when using input registers read address setup time before clock when using input registers clock-to-output delay when using output registers clock-to-output delay without output registers data-in data-out delay mode Macrocell input non-registered output Macrocell register setup time before clock Macrocell register clock-to-output delay
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APEX Programmable Logic Device Family
Table APEX 20KE Routing Timing Microparameters Symbol
tF1-4 tF5-20 tF20+
Note
Parameter
Fanout delay using Local Interconnect Fanout delay estimate using MegaLab Interconnect Fanout delay estimate using FastTrack Interconnect
Table APEX 20KE Functional Timing Microparameters Symbol
TCLRP TPREP TESBCH TESBCL TESBWP TESBRP Note Table:
These parameters worst-case values typical applications. Post-compilation timing simulation timing analysis required determine actual worst-case performance.
Parameter
Minimum clock high time from clock Minimum clock time from clock clear Pulse Width preset pulse width Clock high time Clock time Write pulse width Read pulse width
Tables describe APEX 20KE external timing parameters. Table APEX 20KE External Timing Parameters Symbol
tINSU tINH tOUTCO tINSUPLL tINHPLL tOUTCOPLL
Note Conditions
Clock Parameter
Setup time with global clock input register Hold time with global clock input register Clock-to-output delay with global clock output register Setup time with clock input register Hold time with clock input register Clock-to-output delay with clock output register
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APEX Programmable Logic Device Family
Table APEX 20KE External Bidirectional Timing Parameters Symbol
tINSUBIDIR tINHBIDIR tOUTCOBIDIR tXZBIDIR tZXBIDIR tINSUBIDIRPLL tINHBIDIRPLL tOUTCOBIDIRPLL tXZBIDIRPLL tZXBIDIRPLL Note tables:
These timing parameters sample-tested only.
Note Condition
Parameter
Setup time bi-directional pins with global clock adjacent Input Register Hold time bi-directional pins with global clock LabB adjacent Input Register Clock-to-output delay bi-directional pins with global clock output register Synchronous Output Enable Register output buffer disable delay Synchronous Output Enable Register output buffer enable delay Setup time bi-directional pins with clock adjacent Input Register Hold time bi-directional pins with clock adjacent Input Register Clock-to-output delay bi-directional pins with clock output register Synchronous Output Enable Register output buffer disable delay with Synchronous Output Enable Register output buffer enable delay with
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APEX Programmable Logic Device Family
Tables through show fMAX timing parameters EP20K100, EP20K200, EP20K400 APEX devices. Table EP20K100 fMAX Timing Parameters Symbol Speed Grade
tLUT tESBRC tESBWC tESBWESU tESBDATASU tESBADDRSU tESBDATACO1 tESBDATACO2 tESBDD tPTERMSU tPTERMCO tF1-4 tF5-20 tF20+ tCLRP tPREP tESBCH tESBCL tESBWP tESBRP
Speed Grade
Speed Grade
Altera Corporation
APEX Programmable Logic Device Family
Table EP20K200 fMAX Timing Parameters Symbol Speed Grade
tLUT tESBRC tESBWC tESBWESU tESBDATASU tESBADDRSU tESBDATACO1 tESBDATACO2 tESBDD tPTERMSU tPTERMCO tF1-4 tF5-20 tF20+ tCLRP tPREP tESBCH tESBCL tESBWP tESBRP
Speed Grade
Speed Grade
Altera Corporation
APEX Programmable Logic Device Family
Table EP20K400 fMAX Timing Parameters Symbol Speed Grade
tLUT tESBRC tESBWC tESBWESU tESBDATASU tESBADDRSU tESBDATACO1 tESBDATACO2 tESBDD tPTERMSU tPTERMCO tF1-4 tF5-20 tF20+ tCLRP tPREP tESBCH tESBCL tESBWP tESBRP
Speed Grade
Speed Grade
Tables through show external external bidirectional timing parameter values EP20K100, EP20K200, EP20K400 APEX devices.
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APEX Programmable Logic Device Family
Table EP20K100 External Timing Parameters Symbol Speed Grade
tINSU tINH tOUTCO tINSU tINH tOUTCO
Speed Grade
Speed Grade
Unit
Table EP20K100 External Bidirectional Timing Parameters Symbol Speed Grade
tINSUBIDIR tINHBIDIR tOUTCOBIDIR tXZBIDIR tZXBIDIR tINSUBIDIR tINHBIDIR tOUTCOBIDIR tXZBIDIR tZXBIDIR
Speed Grade
Speed Grade
Unit
Table EP20K200 External Timing Parameters Symbol Speed Grade
tINSU tINH tOUTCO tINSU tINH tOUTCO
Speed Grade
Speed Grade
Unit
Altera Corporation
APEX Programmable Logic Device Family
Table EP20K200 External Bidirectional Timing Parameters Symbol Speed Grade
tINSUBIDIR tINHBIDIR tOUTCOBIDIR tXZBIDIR tZXBIDIR tINSUBIDIR tINHBIDIR tOUTCOBIDIR tXZBIDIR tZXBIDIR
Speed Grade
Speed Grade
Unit
Table EP20K400 External Timing Parameters Symbol Speed Grade
tINSU tINH tOUTCO tINSU tINH tOUTCO
Speed Grade
Speed Grade
Unit
Altera Corporation
APEX Programmable Logic Device Family
Table EP20K400 External Bidirectional Timing Parameters Symbol Speed Grade
tINSUBIDIR tINHBIDIR tOUTCOBIDIR tXZBIDIR tZXBIDIR tINSUBIDIR tINHBIDIR tOUTCOBIDIR tXZBIDIR tZXBIDIR Notes tables:
This parameter measured without using ClockLock ClockBoost circuits. This parameter measured using ClockLock ClockBoost circuits.
Speed Grade
Speed Grade
Unit
10.3 10.3
Tables through describe fMAX Timing Microparameters, fMAX Timing Microparameters, fMAX Routing Delays, Minimum Pulse Width Timing Parameters, External Timing Parameters, External Bidirectional Timing Parameters EP20K30E APEX 20KE devices. Table EP20K30E Fmax Timing Microparameters Symbol
tLUT 0.01 0.11 0.32 0.85
0.02 0.16
0.02 0.23 0.45 1.20
Unit
0.67 1.77
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APEX Programmable Logic Device Family
Table EP20K30E Fmax ESBTiming Microparameters Symbol
tESBARC tESBSRC tESBAWC tESBSWC tESBWASU tESBWAH tESBWDSU tESBWDH tESBRASU tESBRAH tESBWESU tESBWEH tESBDATASU tESBWADDRSU tESBRADDRSU tESBDATACO1 tESBDATACO2 tESBDD tPTERMSU tPTERMCO 1.04 1.13 1.77 0.00 1.95 0.00 1.96 0.00 1.80 0.00 0.07 0.30 0.37 1.11 2.65 3.88 1.91 1.71 1.34
2.03 2.58 3.88 4.08 2.49 0.00 2.74 0.00 2.75 0.00 2.73 0.00 0.48 0.80 0.90
2.86 3.49 5.45 5.35 3.68 0.00 4.05 0.00 4.07 0.00 4.28 0.00 1.17 1.64 1.78 1.32 3.73 5.45 2.69 2.82
4.24 5.02 8.08 7.48
Unit
1.67 5.53 8.08 3.98 1.69
Table EP20K30E Fmax Routing Delays Symbol
tF1-4 tF5-20 tF20+
0.24 1.03 1.42
0.27 1.14 1.54
0.31 1.30 1.77
Unit
Altera Corporation
APEX Programmable Logic Device Family
Table EP20K30E Minimum Pulse Width Timing Parameters Symbol
tCLRP tPREP tESBCH tESBCL tESBWP tESBRP 0.55 0.55 0.22 0.22 0.55 0.55 1.43 1.15
0.78 0.78 0.31 0.31 0.78 0.78 2.01 1.62
1.15 1.15 0.46 0.46 1.15 1.15 2.97 2.39
Unit
Table EP20K30E External Timing Parameters Symbol
tINSU tINH tOUTCO tINSUPLL tINHPLL tOUTCOPLL 2.02 0.00 2.00 2.11 0.00 0.50 2.60 4.88
2.13 0.00 2.00 2.23 0.00 0.50
2.24 0.00 5.36 2.00 2.88
Unit
5.88
Table EP20K30E External Bidirectional Timing Parameters Symbol
tINSUBIDIR tINHBIDIR tOUTCOBIDIR tXZBIDIR tZXBIDIR tINSUBIDIRPLL tINHBIDIRPLL tOUTCOBIDIRPLL tXZBIDIRPLL tZXBIDIRPLL 4.12 0.00 0.50 2.60 5.21 5.21 1.85 0.00 2.00 4.88 7.48 7.48 4.24 0.00 0.50 2.88 5.99 5.99
1.77 0.00 2.00
1.54 0.00 5.36 8.46 8.46 2.00
Unit
5.88 9.83 9.83
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APEX Programmable Logic Device Family
Tables through describe fMAX Timing Microparameters, fMAX Timing Microparameters, fMAX Routing Delays, Minimum Pulse Width Timing Parameters, External Timing Parameters, External Bidirectional Timing Parameters EP20K60E APEX 20KE devices. Table EP20K60E Fmax Timing Microparameters Symbol
tLUT 0.17 0.32 0.29 0.77
0.15 0.33
0.16 0.39 0.40 1.07
Unit
0.60 1.59
Table EP20K60E Fmax ESBTiming Microparameters Symbol
tESBARC tESBSRC tESBAWC tESBSWC tESBWASU tESBWAH tESBWDSU tESBWDH tESBRASU tESBRAH tESBWESU tESBWEH tESBDATASU tESBWADDRSU tESBRADDRSU tESBDATACO1 tESBDATACO2 tESBDD tPTERMSU tPTERMCO 0.99 1.07 1.59 0.00 1.75 0.00 1.76 0.00 1.68 0.00 0.08 0.29 0.36 1.06 2.39 3.50 1.72 1.56 1.26
1.83 2.46 3.50 3.77 2.23 0.00 2.46 0.00 2.47 0.00 2.49 0.00 0.43 0.72 0.81
2.57 3.26 4.90 4.90 3.29 0.00 3.62 0.00 3.64 0.00 3.87 0.00 1.04 1.46 1.58 1.24 3.35 4.90 2.41 2.55
3.79 4.61 7.23 6.79
Unit
1.55 4.94 7.23 3.56 1.08
Altera Corporation
APEX Programmable Logic Device Family
Table EP20K60E Fmax Routing Delays Symbol
tF1-4 tF5-20 tF20+
0.24 1.45 1.96
0.26 1.58 2.14
0.30 1.79 2.45
Unit
Table EP20K60E Minimum Pulse Width Timing Parameters Symbol
tCLRP tPREP tESBCH tESBCL tESBWP tESBRP 2.00 2.00 0.20 0.20 2.00 2.00 1.29 1.04
2.50 2.50 0.28 0.28 2.50 2.50 1.80 1.45
2.75 2.75 0.41 0.41 2.75 2.75 2.66 2.14
Unit
Table EP20K60E External Timing Parameters Symbol
tINSU tINH tOUTCO tINSUPLL tINHPLL tOUTCOPLL 2.03 0.00 2.00 1.12 0.00 0.50 3.37 4.84
2.12 0.00 2.00 1.15 0.00 0.50
2.23 0.00 5.31 2.00 3.69
Unit
5.81
Altera Corporation
APEX Programmable Logic Device Family
Table EP20K60E External Bidirectional Timing Parameters Symbol
tINSUBIDIR tINHBIDIR tOUTCOBIDIR tXZBIDIR tZXBIDIR tINSUBIDIRPLL tINHBIDIRPLL tOUTCOBIDIRPLL tXZBIDIRPLL tZXBIDIRPLL 3.44 0.00 0.50 3.37 5.00 5.00 2.77 0.00 2.00 4.84 6.47 6.47 3.24 0.00 0.50 3.69 5.82 5.82
2.91 0.00 2.00
3.11 0.00 5.31 7.44 7.44 2.00
Unit
5.81 8.65 8.65
Tables through describe fMAX Timing Microparameters, fMAX Timing Microparameters, fMAX Routing Delays, Minimum Pulse Width Timing Parameters, External Timing Parameters, External Bidirectional Timing Parameters EP20K100E APEX 20KE devices. Table EP20K100E Fmax Timing Microparameters Symbol
tLUT 0.25 0.25 0.28 0.80
0.25 0.25
0.25 0.25 0.28 0.95
Unit
0.34 1.13
Altera Corporation
APEX Programmable Logic Device Family
Table EP20K100E Fmax ESBTiming Microparameters Symbol
tESBARC tESBSRC tESBAWC tESBSWC tESBWASU tESBWAH tESBWDSU tESBWDH tESBRASU tESBRAH tESBWESU tESBWEH tESBDATASU tESBWADDRSU tESBRADDRSU tESBDATACO1 tESBDATACO2 tESBDD tPTERMSU tPTERMCO 1.11 1.19 0.56 0.48 0.71 .048 1.57 0.00 1.54 0.00 -0.16 0.12 0.17 1.20 2.54 3.06 1.73 1.26 1.40
1.61 2.57 0.52 3.17 6.41 0.54 0.80 0.54 1.75 0.00 1.72 0.00 -0.20 0.08 0.15
1.84 2.97 4.09 3.78 0.63 0.55 0.81 0.55 1.87 0.20 1.80 0.00 -0.20 0.13 0.19 1.39 2.99 3.56 2.02 1.38
1.97 3.20 4.39 4.09
Unit
1.52 3.22 3.85 2.20 1.08
Table EP20K100E Fmax Routing Delays Symbol
tF1-4 tF5-20 tF20+
0.24 1.04 1.12
0.27 1.26 1.36
0.29 1.52 1.86
Unit
Altera Corporation
APEX Programmable Logic Device Family
Table EP20K100E Minimum Pulse Width Timing Parameters Symbol
tCLRP tPREP tESBCH tESBCL tESBWP tESBRP 2.00 2.00 0.20 0.20 2.00 2.00 1.29 1.11
2.00 2.00 0.20 0.20 2.00 2.00 1.53 1.29
2.00 2.00 0.20 0.20 2.00 2.00 1.66 1.41
Unit
Table EP20K100E External Timing Parameters Symbol
tINSU tINH tOUTCO tINSUPLL tINHPLL tOUTCOPLL 2.23 0.00 2.00 1.58 0.00 0.50 2.96 4.86
2.32 0.00 2.00 1.66 0.00 0.50
2.43 0.00 5.35 2.00 3.29
Unit
5.84
Table EP20K100E External Bidirectional Timing Parameters Symbol
tINSUBIDIR tINHBIDIR tOUTCOBIDIR tXZBIDIR tZXBIDIR tINSUBIDIRPLL tINHBIDIRPLL tOUTCOBIDIRPLL tXZBIDIRPLL tZXBIDIRPLL 4.64 0.00 0.50 2.96 3.10 3.10 2.74 0.00 2.00 4.86 5.00 5.00 5.03 0.00 0.50 3.29 3.42 3.42
2.96 0.00 2.00
3.19 0.00 5.35 5.48 5.48 2.00
Unit
5.84 5.89 5.89
Altera Corporation
APEX Programmable Logic Device Family
Tables through describe fMAX Timing Microparameters, fMAX Timing Microparameters, fMAX Routing Delays, Minimum Pulse Width Timing Parameters, External Timing Parameters, External Bidirectional Timing Parameters EP20K160E APEX 20KE devices. Table EP20K160E Fmax Timing Microparameters Symbol
tLUT 0.22 0.22 0.25 0.69
0.24 0.24
0.26 0.26 0.31 0.88
Unit
0.35 1.12
Table EP20K160E Fmax ESBTiming Microparameters Symbol
tESBARC tESBSRC tESBAWC tESBSWC tESBWASU tESBWAH tESBWDSU tESBWDH tESBRASU tESBRAH tESBWESU tESBWEH tESBDATASU tESBWADDRSU tESBRADDRSU tESBDATACO1 tESBDATACO2 tESBDD tPTERMSU tPTERMCO 1.01 1.06 0.54 0.36 0.68 0.36 1.58 0.00 1.41 0.00 -0.02 0.14 0.21 1.04 2.15 2.69 1.55 1.23 1.32
1.65 2.21 3.04 2.81 0.66 0.45 0.81 0.45 1.87 0.00 1.71 0.00 -0.03 0.17 0.27
2.02 2.70 3.79 3.56 0.73 0.47 0.94 0.47 2.06 0.01 2.00 0.00 0.09 0.35 0.43 1.30 2.70 3.35 1.93 1.52
2.11 3.11 4.42 4.10
Unit
1.46 3.16 3.97 2.29 1.04
Altera Corporation
APEX Programmable Logic Device Family
Table EP20K160E Fmax Routing Delays Symbol
tF1-4 tF5-20 tF20+
0.25 1.00 1.95
0.26 1.18 2.19
0.28 1.35 2.30
Unit
Table EP20K160E Minimum Pulse Width Timing Parameters Symbol
tCLRP tPREP tESBCH tESBCL tESBWP tESBRP 1.34 1.34 0.18 0.18 1.34 1.34 1.15 0.93
1.43 1.43 0.19 0.19 1.43 1.43 1.45 1.15
1.55 1.55 0.21 0.21 1.55 1.55 1.73 1.38
Unit
Table EP20K160E External Timing Parameters Symbol
tINSU tINH tOUTCO tINSUPLL tINHPLL tOUTCOPLL 2.23 0.00 2.00 2.12 0.00 0.50 3.00 5.07
2.34 0.00 2.00 2.07 0.00 0.50
2.47 0.00 5.59 2.00 3.35
Unit
6.13
Altera Corporation
APEX Programmable Logic Device Family
Table EP20K160E External Bidirectional Timing Parameters Symbol
tINSUBIDIR tINHBIDIR tOUTCOBIDIR tXZBIDIR tZXBIDIR tINSUBIDIRPLL tINHBIDIRPLL tOUTCOBIDIRPLL tXZBIDIRPLL tZXBIDIRPLL 4.93 0.00 0.50 3.00 5.36 5.36 2.86 0.00 2.00 5.07 7.43 7.43 5.48 0.00 0.50 3.35 5.99 5.99
3.24 0.00 2.00
3.54 0.00 5.59 8.23 8.23 2.00
Unit
6.13 8.58 8.58
Tables through describe fMAX Timing Microparameters, fMAX Timing Microparameters, fMAX Routing Delays, Minimum Pulse Width Timing Parameters, External Timing Parameters, External Bidirectional Timing Parameters EP20K200E APEX 20KE devices. Table EP20K200E fMAX Timing Microparameters Symbol
tLUT 0.23 0.23 0.26 0.70
0.24 0.24
0.26 0.26 0.31 0.90
Unit
0.36 1.14
Altera Corporation
APEX Programmable Logic Device Family
Table EP20K200E fMAX Timing Microparameters Symbol
tESBARC tESBSRC tESBAWC tESBSWC tESBWASU tESBWAH tESBWDSU tESBWDH tESBRASU tESBRAH tESBWESU tESBWEH tESBDATASU tESBWADDRSU tESBRADDRSU tESBDATACO1 tESBDATACO2 tESBDD tPTERMSU tPTERMCO 1.00 1.10 0.55 0.36 0.69 0.36 1.61 0.00 1.42 0.00 -0.06 0.11 0.18 1.09 2.19 2.75 1.58 1.22 1.37
1.68 2.27 3.10 2.90 0.67 0.46 0.83 0.46 1.90 0.00 1.71 0.00 -0.07 0.13 0.23
2.06 2.77 3.86 3.67 0.74 0.48 0.95 0.48 2.09 0.01 2.01 0.00 0.05 0.31 0.39 1.35 2.75 3.41 1.97 1.51
2.24 3.18 4.50 4.21
Unit
1.51 3.22 4.03 2.33 1.09
Table EP20K200E fMAX Routing Delays Symbol
tF1-4 tF5-20 tF20+
0.25 1.02 1.99
0.27 1.20 2.23
0.29 1.41 2.53
Unit
Altera Corporation
APEX Programmable Logic Device Family
Table EP20K200E Minimum Pulse Width Timing Parameters Symbol
tCLRP tPREP tESBCH tESBCL tESBWP tESBRP 1.36 1.36 0.18 0.18 1.36 1.36 1.18 0.95
2.44 2.44 0.19 0.19 2.44 2.44 1.48 1.17
2.65 2.65 0.21 0.21 2.65 2.65 1.76 1.41
Unit
Table EP20K200E External Timing Parameters Symbol
tINSU tINH tOUTCO tINSUPLL tINHPLL tOUTCOPLL 2.24 0.00 2.00 2.13 0.00 0.50 3.01 5.12
2.35 0.00 2.00 2.07 0.00 0.50
2.47 0.00 5.62 2.00 3.36
Unit
6.11
Altera Corporation
APEX Programmable Logic Device Family
Table EP20K200E External Bidirectional Timing Parameters Symbol
tINSUBIDIR tINHBIDIR tOUTCOBIDIR tXZBIDIR tZXBIDIR tINSUBIDIRPLL tINHBIDIRPLL tOUTCOBIDIRPLL tXZBIDIRPLL tZXBIDIRPLL 3.30 0.00 0.50 3.01 5.40 5.40 2.81 0.00 2.00 5.12 7.51 7.51 3.64 0.00 0.50 3.36 6.05 6.05
3.19 0.00 2.00
3.54 0.00 5.62 8.32 8.32 2.00
Unit
6.11 8.67 8.67
Tables through describe fMAX Timing Microparameters, fMAX Timing Microparameters, fMAX Routing Delays, Minimum Pulse Width Timing Parameters, External Timing Parameters, External Bidirectional Timing Parameters EP20K300E APEX 20KE devices. Table EP20K300E fMAX Timing Microparameters Symbol
tLUT 0.16 0.31 0.28 0.79
0.17 0.33
0.18 0.38 0.38 1.07
Unit
0.51 1.43
Altera Corporation
APEX Programmable Logic Device Family
Table EP20K300E fMAX Timing Microparameters Symbol
tESBARC tESBSRC tESBAWC tESBSWC tESBWASU tESBWAH tESBWDSU tESBWDH tESBRASU tESBRAH tESBWESU tESBWEH tESBDATASU tESBWADDRSU tESBRADDRSU tESBDATACO1 tESBDATACO2 tESBDD tPTERMSU tPTERMCO 0.96 1.05 1.55 0.00 1.71 0.00 1.72 0.00 1.63 0.00 0.07 0.27 0.34 1.03 2.33 3.41 1.68 1.48 1.22
1.79 2.40 3.41 3.68 2.12 0.00 2.33 0.00 2.34 0.00 2.36 0.00 0.39 0.67 0.75
2.44 3.12 4.65 4.68 2.83 0.00 3.11 0.00 3.13 0.00 3.28 0.00 0.80 1.17 1.28 1.20 3.18 4.65 2.29 2.14
3.25 4.01 6.20 5.93
Unit
1.40 4.24 6.20 3.06 1.42
Table EP20K300E fMAX Routing Delays Symbol
tF1-4 tF5-20 tF20+
0.22 1.33 3.63
0.24 1.43 3.93
0.26 1.58 4.35
Unit
Altera Corporation
APEX Programmable Logic Device Family
Table EP20K300E Minimum Pulse Width Ti
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