ADSP-21532 Synchronous External Memory Controller with Glueless S

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ADSP-21532 Synchronous External Memory Controller with Glueless S

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Preliminary Technical DatFEATURES High-Performance Core 16-Bit MACs, 40-Bit ALUs, Four 8-Bit Video ALUs, 40-Bit Shifter RISC-Like Register Instruction Model Ease Programming Compiler-Friendly Support Advanced Debug, Trace, Performance- Monitoring Support On-chip Voltage Regulation from 2.25 Input V-Tolerant Case Temperature Range 160-Lead Mini-BGA Package MEMORY 116K Bytes On-Chip Memory: Bytes Instruction SRAM/Cache Bytes Instruction SRAM Bytes Instruction Bytes Data SRAM/Cache Bytes Scratchpad SRAM Memory Controller Memory Management Unit Providing Memory Protection
ADSP-21532
Synchronous External Memory Controller with Glueless SDRAM Support Asynchronous External Memory Controller with Glueless Support SRAM, FLASH, Flexible Memory Booting Options From SPI, External Memory, Internal PERIPHERALS Parallel Peripheral Interface (PPI) Port/GPIO, Supporting CCIR-656 Video Data Formats Dual-Channel, Full-Duplex Synchronous Serial Ports, Supporting Eight Stereo Channels SPI-compatible Port Three Timer/Counters with Support UART with Support IrDA® Event Handler Real-Time Clock Watchdog Timer Debug/JTAG Interface Chip Capable Frequency Multiplication
ADSP-21532 BLACKFIN BLOCK DIAGRAM
JTAG TEST EMULATION
CONTROLLE CORE TIMER
WATCHDOG TIME
VOLTAGE GULATOR
MICRO SIGNAL ARCHITE CTURE CORE
BYTES SRAM BYTE
REAL TIME CLOCK UART PORT IrDA
YSTEM INTERFACE UNIT
TIME TIMER1, TIMER2
CONTROLLE RIAL PORTS
BOOT
EXTERNAL PORT FLASH, SDRAM CONTROL
REV.
This information applies product under development. characteristics specifications subject change without notice. Analog Devices assumes obligation regarding future manufacturing unless otherwise agreed writing. Technology Way, P.O.Box 9106, Norwood, 02062-9106, U.S.A. Tel:781/329-4700 World Wide Site: http://www.analog.com Fax:781/326-8703 ©Analog Devices,Inc., 2001
PRELIMINARY TECHNICAL DATA ADSP-21532
General Note
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September 2001
This data sheet provides preliminary information ADSP-21532 BlackfinDSP1.
GENERAL DESCRIPTION
ADSP-21532 member Blackfin family products, incorporating Analog Devices/Intel Micro Signal Architecture (MSA). Blackfin DSPs combine dualMAC state-of-the-art engine, advantages clean, orthogonal RISC-like microprocessor instruction set, single-instruction, multiple-data (SIMD) multimedia capabilities into single instruction-set architecture. integrating rich industry-leading system peripherals memory, Blackfin DSPs platform choice next-generation applications that require RISC-like programmability, multimedia support leading-edge signal processing integrated DSP.
Portable Low-Power Architecture
general-purpose peripherals, ADSP-21532 contains high speed serial parallel ports interfacing variety audio, video, modem CODEC functions; interrupt controller flexible management interrupts from on-chip peripherals external sources; power management control functions tailor performance power characteristics processor system many application scenarios. peripherals, except general-purpose I/O, RealTime Clock, timers, supported flexible structure. There also separate memory channel dedicated data transfers between DSP's various memory spaces, including external SDRAM asynchronous memory. Multiple on-chip buses running provide adequate bandwidth keep processor core running along with activity onchip external peripherals. ADSP-21532 includes on-chip voltage regulator support Blackfin core Dynamic Power Management capability. voltage regulator provides range core voltage levels from single 2.25 input. voltage regulator bypassed user's discretion.
Core
Blackfin DSPs provide world-class power management performance compared other Digital Signal Processors. Blackfin DSPs designed Low-Power LowVoltage Design Methodology feature Dynamic Power Management, ability vary both voltage frequency operation significantly lower overall power consumption. Varying voltage frequency result three-fold reduction power consumption, comparison just varying frequency operation. This translates into longer battery life portable appliances.
System Integration
shown Figure page core contains multiplier/accumulators, ALU's, four video ALU's, shifter. computation units process 8-bit, 16-bit, 32-bit data from register file. compute register file contains eight 32-bit registers. When performing compute operations 16-bit operand data, register file operates independent 16-bit registers. operands compute operations come from multiported register file instruction constant fields. Each perform 16-bit 16-bit multiply each cycle, accumulating results into 40-bit accumulators. Signed unsigned formats, rounding, saturation supported. ALU's perform traditional arithmetic logical operations 16-bit 32-bit data. addition, many special instructions included accelerate various signal processing tasks. These include operations such field extract population count, modulo multiply, divide primitives, saturation rounding, sign/exponent detection. video instructions include byte alignment packing operations, 16-bit 8-bit adds with clipping, 8-bit average operations, 8-bit subtract/absolute value/accumulate (SAA) operations. Also provided compare/select vector search instructions. certain instructions, 16-bit operations performed simultaneously register pairs 16-bit high half 16-bit half compute register). also using second ALU, quad 16-bit operations possible. REV.
ADSP-21532 highly integrated system-on-a-chip solution next generation digital communication portable Internet appliances. combining industrystandard interfaces with high performance Digital Signal Processing core, users develop cost-effective solutions quickly without need costly external components. ADSP-21532 system peripherals include UART port, port, Serial ports (SPORTs), four general purpose Timers (three with capability), Real-Time Clock, Watchdog Timer, Parallel Peripheral Interface port.
ADSP-21532 Peripherals
ADSP-21532 contains rich peripherals connected core several high bandwidth buses, providing flexibility system configuration well excellent overall system performance. block diagram page general-purpose peripherals include functions such UART, Timers with (Pulse Width Modulation) pulse measurement capability, general purpose flag pins, Real-Time Clock, Watchdog Timer. This functions satisfies wide variety typical system support needs augmented system expansion capabilities part. addition these
Blackfin trademark Analog Devices, Inc.
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ADSP-21532
40-bit shifter perform shifts rotates used support normalization, field extract, field deposit instructions. program sequencer controls flow instruction execution, including instruction alignment decoding. program flow control, sequencer supports relative indirect conditional jumps (with static branch prediction), subroutine calls. Hardware provided support
zero-overhead looping. architecture fully interlocked, meaning that there visible pipeline effects when executing instructions with data dependencies. address arithmetic unit provides addresses simultaneous dual fetches from memory. unit contains multiported register file consisting four sets 32-bit Index, Modify, Length, Base registers (for circular buffering), eight additional 32-bit pointer registers (for Cstyle indexed stack manipulation).
HMET
CONT
RREL SHIF
Figure Core
Blackfin DSPs support modified Harvard architecture combination with hierarchical memory structure. Level (L1) memories those that typically operate full processor speed with little latency. level, instruction memory holds instructions only. data memories hold data, dedicated scratchpad data memory stores stack local variable information. addition, multiple memory blocks provided, offering configurable SRAM cache. Memory Management Unit (MMU) provides memory protection individual tasks that operating core protect system registers from unintended access. architecture provides three modes operation: user mode, supervisor mode, emulation mode. User mode restricted access certain system resources, thus
providing protected software environment, while supervisor mode unrestricted access system core resources. Blackfin instruction been optimized that 16-bit opcodes represent most frequently used instructions, resulting excellent compiled code density. Complex instructions encoded into 32-bit opcodes, representing fully featured multifunction instructions. Blackfin DSPs support limited multi-issue capability, where 32-bit instruction issued parallel with 16-bit instructions, allowing programmer many core resources single instruction cycle. Blackfin assembly language uses algebraic syntax ease coding readability. architecture been optimized conjunction with Ccompiler, resulting fast efficient software implementations.
REV.
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Memory Architecture
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ADSP-21532 views memory single unified byte address space, using 32-bit addresses. resources including internal memory, external memory, control registers occupy separate sections this common address space. memory portions this address space arranged hierarchical structure provide good cost/performance balance some very fast, low-latency onchip memory cache SRAM, larger, lower-cost performance off-chip memory systems. Figure
0xFFFF FFFF CORE REGISTERS BYTE) 0xFFE0 0000 SYSTEM REGISTERS BYTE) 0xFFC0 0000 RESERVED 0xFFB0 1000 SCRATCH SRAM BYTE) 0xFFB0 0000 RESERVED 0xFFA0 C000 INSTRUCTION (32K BYTE) 0xFFA1 4000 INSTRUCTION SRAM (48K BYTE) 0xFFA0 0000 RESERVED 0xFF90 4000 DATA BANK SRAM (16K BYTE) 0xFF90 0000 RESERVED 0xFF80 4000 DATA BANK SRAM (16K BYTE) 0xFF80 0000 RESERVED 0xEF00 0000 0x2040 0000 0x2030 0000 ASYNC MEMORY BANK BYTE) 0x2020 0000 ASYNC MEMORY BANK BYTE) 0x2010 0000 ASYNC MEMORY BANK BYTE) 0x2000 0000 RESERVED 0x0800 0000 SDRAM MEMORY (16M BYTE 128M BYTE) 0x0000 0000
EXTERNAL MEMORY INTERNAL MEMORY
first instruction memory consisting bytes SRAM which bytes configured four-way associative cache. first memory block also includes bytes user-definable ROM. This memory accessed full processor speed. second on-chip memory block data memory, consisting banks bytes each. Each data memory bank configured bytes SRAM, bytes two-way set-associative cache, bytes SRAM bytes cache. This memory block accessed full processor speed. third memory block byte scratchpad which runs same speed memories, only accessible data SRAM cannot configured cache memory.
External (Off-Chip) Memory
External memory accessed EBIU. This 16-bit interface provides glueless connection bank synchronous DRAM (SDRAM) well four banks asynchronous memory devices including FLASH, EPROM, ROM, SRAM, memory mapped devices. PC133-compliant SDRAM controller programmed interface 128M bytes SDRAM. asynchronous memory controller programmed control four banks devices with very flexible timing parameters wide variety devices. Each bank occupies byte segment regardless size devices used that these banks will only contiguous each fully populated with byte memory.
Memory Space
RESERVED ASYNC MEMORY BANK BYTE)
Figure ADSP-21532 Internal/External Memory
memory system primary highest-performance memory available Blackfin DSP. off-chip memory system, accessed through External Interface Unit (EBIU), provides expansion with SDRAM, flash memory, SRAM, optionally accessing 132M bytes physical memory. memory controller provides high-bandwidth data-movement capability. perform block transfers code data between internal memory external memory spaces.
Internal (On-chip) Memory
Blackfin DSPs define separate space. resources mapped through flat 32-bit address space. On-chip devices have their control registers mapped into memory-mapped registers (MMRs) addresses near byte address space. These separated into smaller blocks, which contains control MMRs core functions, other which contains registers needed setup control on-chip peripherals outside core. MMRs accessible only supervisor mode appear reserved space onchip peripherals.
Booting
ADSP-21532 three blocks on-chip memory providing high-bandwidth access core.
ADSP-21532 contains small boot kernel, which configures appropriate peripheral booting. ADSP21532 configured boot from boot memory space, starts executing from on-chip boot ROM. more information, "Booting Modes" page
Event Handling
event controller ADSP-21532 handles asynchronous synchronous events processor. ADSP-21532 provides event handling that supports both nesting prioritization. Nesting allows multiple event
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ADSP-21532
Entry
service routines active simultaneously. Prioritization ensures that servicing higher-priority event takes precedence over servicing lower-priority event. controller provides support five different types events: Emulation emulation event causes processor enter emulation mode, allowing command control processor JTAG interface. Reset This event resets processor. Non-Maskable Interrupt (NMI) event generated software watchdog timer input signal processor. event frequently used power-down indicator initiate orderly shutdown system. Exceptions Exceptions events that occur synchronously program flow (i.e., exception will taken before instruction allowed complete). Conditions such data alignment violations undefined instructions cause exceptions. Interrupts Interrupts events that occur asynchronously program flow. They caused input pins, timers, other peripherals. Each event type associated register hold return address associated return-from-event instruction. When event triggered, state processor saved supervisor stack. ADSP-21532 Event Controller consists stages, Core Event Controller (CEC) System Interrupt Controller (SIC). Core Event Controller works with System Interrupt Controller prioritize control system events. Conceptually, interrupts from peripherals enter into SIC, then routed directly into general-purpose interrupts CEC.
Core Event Controller (CEC)
Table Core Event Controller (CEC) Priority Highest) Event Class
Emulation/Test Control Reset Non-Maskable Interrupt Exceptions Global Interrupt Enable Hardware Error Core Timer General Interrupt General Interrupt General Interrupt General Interrupt General Interrupt General Interrupt General Interrupt General Interrupt General Interrupt
IVHW IVTMR IVG7 IVG8 IVG9 IVG10 IVG11 IVG12 IVG13 IVG14 IVG15
Table System Interrupt Controller (SIC) Peripheral Interrupt Event Default Mapping
supports nine general-purpose interrupts (IVG15-7), addition dedicated interrupt exception events. these general-purpose interrupts, lowest-priority interrupts (IVG15-14) recommended reserved software interrupt handlers, leaving seven prioritized interrupt inputs support peripherals ADSP-21532. Table describes inputs CEC, identifies their names Event Vector Table (EVT), lists their priorities.
System Interrupt Controller (SIC)
Real-Time Clock Interrupt Parallel Peripheral Interface Interrupt SPORT Interrupt SPORT Interrupt SPORT Interrupt SPORT Interrupt Interrupt UART Interrupt UART Interrupt Timer Interrupt Timer Interrupt Timer Interrupt GPIO Interrupt GPIO Interrupt Memory Interrupt Software Watchdog Timer Interrupt Software Interrupt Software Interrupt
IVG7 IVG7 IVG8 IVG8 IVG8 IVG8 IVG9 IVG10 IVG10 IVG11 IVG11 IVG11 IVG12 IVG12 IVG13 IVG13 IVG14 IVG15
System Interrupt Controller provides mapping routing events from many peripheral interrupt sources prioritized general-purpose interrupt inputs CEC. Although ADSP-21532 provides default mapping, user alter mappings priorities interrupt events writing appropriate values into Interrupt Assignment Registers (IAR). Table describes inputs into default mappings into CEC. REV.
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Event Control
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ADSP-21532 provides user with very flexible mechanism control processing events. CEC, three registers used coordinate control events. Each register bits wide: Interrupt Latch Register (ILAT) ILAT register indicates when events have been latched. appropriate when processor latched event cleared when event been accepted into system. This register updated automatically controller, written only when corresponding IMASK cleared. Interrupt Mask Register (IMASK) IMASK register controls masking unmasking individual events. When IMASK register, that event unmasked will processed system when asserted. cleared IMASK register masks event, preventing processor from servicing event even though event latched ILAT register. This register read written while supervisor mode. (Note that general-purpose interrupts globally enabled disabled with instructions, respectively.) Interrupt Pending Register (IPEND) IPEND register keeps track nested events. IPEND register indicates event currently active nested some level. This register updated automatically controller read while supervisor mode. allows further control event processing providing three 32-bit interrupt control status registers. Each register contains corresponding each peripheral interrupt events shown Table page Interrupt Mask Register (SIC_IMASK)- This register controls masking unmasking each peripheral interrupt event. When register, that peripheral event unmasked will processed system when asserted. cleared register masks peripheral event, preventing processor from servicing event. Interrupt Status Register (SIC_ISR) multiple peripherals mapped single event, this register allows software determine which peripheral event source triggered interrupt. indicates peripheral asserting interrupt, cleared indicates peripheral asserting event. Interrupt Wakeup Enable Register (SIC_IWR) enabling corresponding this register, each peripheral configured wake processor, should processor sleep (powered-down) mode when event generated. (For more information, "Dynamic Power Management" page
Because multiple interrupt sources single general-purpose interrupt, multiple pulse assertions occur simultaneously, before during interrupt processing interrupt event already detected this interrupt input. IPEND register contents monitored interrupt acknowledgement. appropriate ILAT register when interrupt rising edge detected (detection requires processor clock cycles). cleared when respective IPEND register set. IPEND indicates that event entered into processor pipeline. this point will recognize queue next rising edge event corresponding event input. minimum latency from rising edge transition general-purpose interrupt IPEND output asserted three processor clock cycles; however, latency much higher, depending activity within mode processor.
Controllers
ADSP-21532 multiple, independent controllers that support automated data transfers with minimal overhead core. transfers occur between ADSP-21532's internal memories DMA-capable peripherals. Additionally, transfers accomplished between DMA-capable peripherals external devices connected external memory interfaces, including SDRAM controller, asynchronous memory controller parallel peripheral interface. DMA-capable peripherals include SPORTs, port, UART, PPI. Each individual DMA-capable peripheral least dedicated channel. ADSP-21532 controller supports both 1-dimensional (1D) 2-dimensional (2D) transfers. transfer initialization implemented from registers from sets parameters called descriptor blocks. supports arbitrary column sizes 64Kbytes 64Kbytes arbitrary Y-modify values 32KBytes. addition, capability supports interleaved data streams. This feature especially useful video applications where data rates reduced only transferring active video. Examples types supported ADSP-21532 controller include: Single, linear buffer that stops upon completion Circular, auto-refreshing buffer that interrupts each full fractionally full buffer using linked list descriptors using array descriptors specifying only base address within common page addition dedicated peripheral channels, there separate memory channel provided transfers between various memories ADSP-21532 system. This enables transfers blocks data between
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ADSP-21532
memories-including external SDRAM, ROM, SRAM, flash memory-with minimal processor intervention.
Real-Time Clock
hardware reset interrogating status timer control register, which only upon watchdoggenerated reset. timer clocked system clock (SCLK), maximum frequency fSCLK.
Timers
ADSP-21532 Real-Time Clock (RTC) provides robust digital watch features, including current time, stopwatch, alarm. clocked 32.768 crystal external ADSP-21532. peripheral dedicated power supply pins, that remain powered clocked even when rest processor low-power state. provides several programmable interrupt options, including interrupt second, minute, hour, clock ticks, interrupt programmable stopwatch countdown, interrupt programmed alarm time. 32.768 input clock frequency divided down signal prescaler. counter function timer consists four counters: 60-second counter, 60-minute counter, 24-hour counter, 365-day counter. When enabled, alarm function generates interrupt when output timer matches programmed value alarm control register. There alarms: first alarm time day. second alarm time that day. stopwatch function counts down from programmed value, with one-minute resolution. When stopwatch enabled counter underflows, interrupt generated. Like other peripherals, wake ADSP21532 processor from low-power state upon generation interrupt.
Watchdog Timer
There four general-purpose programmable timer units ADSP-21532. Three timers have external that configured either Pulse Width Modulator (PWM) timer output, input clock timer, mechanism measuring pulse widths external events. These timers synchronized external clock input each other. timer units used conjunction with UART measure width pulses data stream provide auto-baud detect function serial channel. timers generate interrupts processor core providing periodic events synchronization, either processor clock count external signals. addition three general-purpose programmable timers, fourth timer also provided. This extra timer clocked internal processor clock typically used system tick clock generation operating system periodic interrupts.
Serial Ports (SPORTs)
ADSP-21532 incorporates dual-channel synchronous serial ports (SPORT0 SPORT1) serial multiprocessor communications. SPORTs support following features: capable operation. Bidirectional operation Each SPORT sets independent transmit receive pins, enabling eight channels stereo audio. Buffered (8-deep) transmit receive ports Each port data register transferring data words from other components shift registers shifting data data registers. Clocking Each transmit receive port either external serial clock generate own, frequencies ranging from (fSCLK/131070) (fSCLK/2) Word length Each SPORT supports serial data words from bits length, transferred most significant first. Framing Each transmit receive port with without frame sync signals each data word. Frame sync signals generated internally externally, active high low, with either pulsewidths early late frame sync.
ADSP-21532 includes 32-bit timer, which used implement software watchdog function. software watchdog improve system availability forcing processor known state through generation hardware reset, non-maskable interrupt (NMI), general-purpose interrupt, timer expires before being reset software. programmer initializes count value timer, enables appropriate interrupt, then enables timer. Thereafter, software must reload counter before counts zero from programmed value. This protects system from remaining unknown state where software, which would normally reset timer, stopped running external noise condition software error. configured generate hardware reset, timer programmed reset only ADSP-21532 CPU, both ADSP-21532 peripherals. After reset, software determine watchdog source
REV.
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Companding hardware Each SPORT perform A-law µ-law companding according recommendation G.711. Companding selected transmit and/or receive channel SPORT without additional latencies. operations with single-cycle overhead Each SPORT automatically receive transmit multiple buffers memory data. link chain sequences transfers between SPORT memory. Interrupts Each transmit receive port generates interrupt upon completing transfer data word after transferring entire data buffer buffers through DMA. Multichannel capability Each SPORT supports channels 1024 channel window compatible with H.100, H.110, MVIP-90, HMVIP standards.
Serial Peripheral Interface (SPI) Port
master mode, performs following sequence initiate transfers: Enables configures port's operation (data size, transfer format). Selects target slave with SPISELx output (reconfigured Programmable Flag pin). Defines more descriptors DSP's memory space (optional mode only). Enables engine specifies transfer direction (optional mode only). non-DMA mode only, reads writes port receive transmit data buffer. line generates programmed clock pulses simultaneously shifting data MOSI shifting data MISO. mode only, transfers continue until word count transitions from slave mode, performs following sequence port receive data from master transmitter: Enables configures slave port match operation parameters master (data size transfer format) transmitter. Defines generates receive descriptor DSP's memory space interrupt data transfer (optional mode only). Enables engine receive access (optional mode only). Starts receiving data appropriate edges after receiving chip select SPISS input (reconfigured Programmable Flag pin) from master. mode only, reception continues until word count transitions from continue queuing next descriptor. Slave mode transmit operation similar, except specifies data buffer memory from which transmit data, generates relinquishes control transmit descriptor, begins filling port's data buffer. controller isn't ready time transmit, transmit "zero" word.
UART Port
ADSP-21532 SPI-compatible port that enables processor communicate with multiple SPI-compatible devices. interface uses three pins transferring data: data pins (Master Output-Slave Input, MOSI, Master Input-Slave Output, MISO) clock (Serial Clock, SCK). chip select input (SPISS) lets other devices select DSP, seven chip select output pins (SPISEL7-1) select other devices. select pins reconfigured Programmable Flag pins. Using these pins, port provides full duplex, synchronous serial interface, which supports both master/slave modes multimaster environments. port's baud rate clock phase/polarities programmable (see Figure integrated controller, configurable support transmit receive data streams. SPI's controller only service unidirectional accesses given time.
SCLK Clock Rate SPIBAUD Figure Clock Rate Calculation
During transfers, port simultaneously transmits receives serially shifting data serial data lines. serial clock line synchronizes shifting sampling data serial data lines.
ADSP-21532 provides full-duplex Universal Asynchronous Receiver/Transmitter (UART) port, which fully compatible with PC-standard UARTs. UART port provides simplified UART interface other peripherals hosts, supporting full-duplex, DMA-supported, asynchronous transfers serial data. UART port includes
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support data bits; stop bits; none, even, parity. UART port supports modes operation: (Programmed I/O) processor sends receives data writing reading I/O-mapped UATX UARX registers, respectively. data double-buffered both transmit receive. (Direct Memory Access) controller transfers both transmit receive data. This reduces number frequency interrupts required transfer data from memory. UART dedicated channels, transmit receive. These channels have lower priority than most channels because their relatively service rates. UART port's baud rate (see Figure serial data format, error code generation status, interrupts programmable: Supporting rates ranging from (fSCLK/ 1048576) (fSCLK/16) bits second. Supporting data formats from to12 bits frame. Both transmit receive operations configured generate maskable interrupts processor.
SCLK UART Clock Rate Figure UART Clock Rate Calculation1
toggle flag values, register written order specify flag value. Reading flag status register allows software interrogate sense flags. Flag Interrupt Mask Registers Flag Interrupt Mask Registers allow each individual function interrupt processor. Similar Flag Control Registers that used clear individual flag values, Flag Interrupt Mask Register sets bits enable interrupt function, other Flag Interrupt Mask register clears bits disable interrupt function. pins defined inputs configured generate hardware interrupts, while output pins configured generate software interrupts. Flag Interrupt Sensitivity Registers Flag Interrupt Sensitivity Registers specify whether individual pins level- edge-sensitive specify-if edgesensitive-whether just rising edge both rising falling edges signal significant. register selects type sensitivity, register selects which edges significant edge-sensitivity.
Parallel Peripheral Interface
ADSP-21532 provides Parallel Peripheral Interface (PPI) that connect directly parallel converters, video encoders decoders, other generalpurpose peripherals. dedicated clock five dedicated data pins. additional data pins available re-configuring programmable flag pins. additional available Frame Sync signal. supports operating modes: general purpose mode CCIR mode. general-purpose mode, provides: Half-duplex, bi-directional data transfer with bits data. Shared pins configurable pins. Frame sync controls transfer. CCIR mode, provides: Half-duplex, bi-directional data transfer with bits data. Support embedded start line (SOL) start field (SOF) synchronization pulses. syncs control transfer. Programmable blanking interval support.
Dynamic Power Management
Where 65536
conjunction with general-purpose timer functions, autobaud detection supported. capabilities UART further extended with support Infrared Data Association (IrDA®) Serial Infrared Physical Layer Link Specification (SIR) protocol.
Programmable Flags (PFx)
ADSP-21532 bi-directional, general-purpose Programmable Flag (PF15-0) pins. Each programmable flag individually controlled manipulation flag control, status interrupt registers: Flag Direction Control Register Specifies direction each individual input output. Flag Control Status Registers ADSP-21532 employs "write modify" mechanism that allows combination individual flags modified single instruction, without affecting level other flags. Four control registers provided. register written order flag values, register written order clear flag values, register written order
ADSP-21532 provides four operating modes, each with different performance/power-dissipation profile. addition, Dynamic Power Management provides control functions dynamically alter processor core supply voltage, further reducing power dissipation. Control clocking each ADSP-21532 peripherals also reduces power consumption. Table summary power settings each mode.
REV.
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Full Operating Mode Maximum Performance
Full mode, enabled, bypassed, providing maximum operational frequency. This power-up default execution state which maximum performance achieved. processor core enabled peripherals full speed.
Active Operating Mode Moderate Power Savings
generated RTC. When Deep Sleep mode, assertion RESET asynchronous interrupt causes processor transition Full mode.
Power Savings
Active mode, bypassed. input clock (CLKIN) used generate clocks processor core (CCLK) peripherals (SCLK). When bypassed, CCLK runs CLKIN frequency. Significant power savings achieved this mode modifying multiplication ratio. change this ratio, appropriate values MSEL fields control register (PLL_CTL). lock counter (PLL LOCK_CNT) determines when multiplier ratio takes effect. When Active mode, system access appropriately configured memory supported.
Table Power Settings Bypassed Core Clock (CCLK) System Clock (SCLK)
shown Table ADSP-21532 supports three different power domains. multiple power domains maximizes flexibility, while maintaining compliance with industry standards conventions. isolating internal logic ADSP-21532 into power domain, separate from other I/O, processor take advantage Dynamic Power Management, without affecting other devices.
Table ADSP-21532 Power Domains Power Domain Range
internal logic, except internal logic crystal other
VDDINT VDDRTC VDDEXT
Full Active Sleep Deep Sleep
Enabled Enabled/ Disabled Enabled Disabled
Enabled Enabled Disabled Disabled
Enabled Enabled Enabled Disabled
power dissipated processor largely function clock frequency processor square operating voltage. example, reducing clock frequency results reduction power dissipation, while reducing voltage reduces power dissipation more than 40%. Further, these power savings additive-in that clock frequency power both reduced, power savings dramatic. Dynamic Power Management feature ADSP21532 allows both processor's input voltage (VDDINT) clock frequency (fCLK) dynamically controlled. explained above, savings power dissipation modeled following equations:
Mode
Sleep Operating Mode High Power Savings
Sleep mode reduces power dissipation disabling clock processor core (CCLK). system clock (SCLK), however, continue operate this mode. Typically external event activity will wake processor. When Sleep mode, assertion interrupt will cause processor sense value bypass (BYPASS) control register (PLL_CTL). bypass disabled, processor will transition Full mode. bypass enabled, processor will transition Active mode. When Sleep mode, system access memory supported.
Deep Sleep Operating Mode Maximum Power Savings
fCCLKRED DDINTRED Power Savings Factor DDINTNOM CCLKNOM
Power Savings Power Savings Factor 100%
where variables equations are: fCCLKNOM nominal core clock frequency fCCLKRED reduced core clock frequency VDDINTNOM nominal internal supply voltage VDDINTRED reduced internal supply voltage
Voltage Regulation
Deep Sleep mode maximizes power savings disabling clocks processor core (CCLK) synchronous systems (SCLK). Asynchronous systems, such RTC, still running will able access internal resources external memory. This powered-down mode only exited assertion reset interrupt (RESET) asynchronous interrupt
ADSP-21532 provides on-chip voltage regulator that generate internal voltage levels from external 2.25 supply. shown Figure minimal external components required complete power REV.
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ADSP-21532
management system. regulator controls internal logic voltage levels programmable with Voltage Regulator Control Register (VRCTL) increments regulator also disabled bypassed user's discretion.
maximum frequency system clock fSCLK. Note that divisor ratio must chosen limit system clock frequency maximum fSCLK. SSEL value changed dynamically without lock latencies writing appropriate values divisor register (PLL_DIV). core clock (CCLK) frequency also dynamically changed means CSEL[1:0] bits PLL_DIV register. Supported CCLK divider ratios shown Table This programmable core clock capability useful fast core frequency modifications.
Table Core Clock Ratios
INTERNAL CIRCUI
TANTALUM ELECTRO LYTIC
CERAMIC
2.25V 3.6V
EXTERNAL COMPONENTS VREF
Divider Signal Name Ratio CSEL[1:0] VCO/CCLK
Example Frequency Ratios CCLK
Booting Modes Figure Voltage Regulator Circuit Clock Signals
ADSP-21532 clocked external crystal circuit, sine wave input, buffered, shaped clock derived from external clock oscillator. This external clock connects DSP's CLKIN pin. CLKIN input cannot halted, changed, operated below specified frequency during normal operation. This clock signal should TTL-compatible signal. provides user-programmable multiplication input clock support external internal (DSP core) clock ratios. default multiplier 10x, controlled software runtime. on-chip peripherals operate rate system clock (SCLK). system clock frequency programmable means SSEL3-0 bits PLL_DIV register. values programmed into SSEL fields define divide ratio between output (VCO) system clock. SCLK divider values through Table illustrates typical system clock ratios:
Table System Clock Ratios Divider Signal Name Ratio SSEL3-0 VCO/SCLK Example Frequency Ratios (MHz) SCLK
ADSP-21532 three mechanisms (listed Table automatically loading internal instruction memory after reset. fourth mode provided execute from external memory, bypassing boot sequence.
Table Booting Modes BMODE2-0 Description
-111
Execute from 16-bit external memory (Bypass Boot ROM) Boot from 8-bit flash Boot from SPI0 serial (8-bit address range) Boot from SPI0 serial (16-bit address range) Boot from internal Reserved
BMODE pins Reset Configuration Register, sampled during power-on resets software-initiated resets, implement following modes: Execute from 16-bit external memory Execution starts from address 0x2000000 with 16-bit packing. boot bypassed this mode. Boot from 8-bit external FLASH memory 8-bit FLASH boot routine located boot memory space using Asynchronous Memory Bank configuration settings slowest device possible (3-cycle hold time; 15-cycle access times; 4-cycle setup).
0001 0110 1111
15:1
REV.
This information applies product under development. characteristics specifications subject change without notice. Analog Devices assumes obligation regarding future manufacturing unless otherwise agreed writing.
PRELIMINARY TECHNICAL DATA ADSP-21532
current information contact Analog Devices 800-262-5643
September 2001
Boot from serial EEPROM (8-bit addressable) uses output select single EPROM device, submits read command address 0x00, begins clocking data into beginning instruction memory. 8-bit addressable SPI-compatible EPROM must used. Boot from serial EEPROM (16-bit addressable) uses output select single EPROM device, submits read command address 0x0000, begins clocking data into beginning instruction memory. 16-bit addressable SPI-compatible EPROM must used. each boot modes, four-byte value first read from memory device. This value used specify subsequent number bytes read into beginning instruction memory. Once each loads complete, processor jumps beginning instruction memory begins execution. addition, Reset Configuration Register application code bypass normal boot sequence during software reset. this case, processor jumps directly beginning instruction memory. augment boot modes, secondary software loader provided that adds additional booting mechanisms. This secondary loader provides capability boot from 16-bit FLASH memory, fast FLASH, variable baud rate, other sources.
Instruction Description
registers, I/O, memory mapped into unified byte memory space providing simplified programming model. Microcontroller features, such arbitrary bitfield manipulation, insertion, extraction; integer operations 16-, 32-bit data-types; separate user supervisor stack pointers. Code density enhancements, which include intermixing 32-bit instructions mode switching, code segregation). Frequently used instructions encoded bits.
Development Tools
ADSP-21532 supported with complete CROSSCOREsoftware hardware development tools, including Analog Devices' emulators VisualDSP++® development environment. same emulator hardware that supports other Analog Devices DSPs also fully emulates ADSP-21532. VisualDSP++ project management environment lets programmers develop debug application. This environment includes easy-to-use assembler that based algebraic syntax, archiver (librarian/library builder), linker, loader, cycle-accurate instruction-level simulator, C/C++ compiler, C/C++ run-time library that includes mathematical functions. point these tools C/C++ code efficiency. compiler been developed efficient translation C/C++ code Blackfin assembly. Blackfin architectural features that improve efficiency compiled C/C++ code. Debugging both C/C++ assembly programs with VisualDSP++ debugger, programmers can: View mixed C/C++ assembly code (interleaved source object information) Insert breakpoints conditional breakpoints registers, memory, stacks Trace instruction execution Perform linear statistical profiling program execution Fill, dump, graphically plot contents memory Perform source level debugging Create custom debugger windows VisualDSP++ lets programmers define manage software development. dialog boxes property pages programmers configure manage
Blackfin family assembly language instruction employs algebraic syntax that designed ease coding readability. instructions have been specifically tuned provide flexible, densely encoded instruction that compiles very small final memory size. instruction also provides fully featured multifunction instructions that allow programmer many core resources single instruction. Coupled with many features more often seen microcontrollers, this instruction very efficient when compiling source code. addition, architecture supports both user (algorithm/application code) supervisor (O/S kernel, device drivers, debuggers, ISRs) modes operation, allowing multiple levels access core resources. assembly language, which takes advantage processor's unique architecture, offers following advantages: Seamlessly integrated DSP/CPU features optimized both 8-bit 16-bit operations. super-pipelined multi-issue load/store modifiedHarvard architecture, which supports 16-bit four 8-bit load/store pointer updates cycle.
This information applies product under development. characteristics specifications subject change without notice. Analog Devices assumes obligation regarding future manufacturing unless otherwise agreed writing.
REV.
PRELIMINARY TECHNICAL DATA September 2001
current information contact Analog Devices 800-262-5643
ADSP-21532
development tools, including Color Syntax Highlighting VisualDSP++ editor. These capabilities permit programmers Control development tools process inputs generate outputs. Maintain one-to-one correspondence with tool's command line switches. VisualDSP++ Kernel (VDK) incorporates scheduling resource management tailored specifically address memory timing constraints programming. These capabilities enable engineers develop code more effectively, eliminating need start from very beginning, when developing application code. features include threads, critical unscheduled regions, semaphores, events, device flags. also supports priority-based, pre-emptive, cooperative timesliced scheduling approaches. addition, designed scalable. application does specific feature, support code that feature excluded from target system. Because library, developer decide whether not. integrated into VisualDSP++ development environment, also used with standard command-line tools. When used, development environment assists developer with many error-prone tasks assists managing system resources, automating generation various based objects, visualizing system state, when debugging application that uses VDK. Analog Devices' emulators IEEE 1149.1 JTAG test access port ADSP-21532 monitor control target board processor during emulation. emulator provides full-speed emulation, allowing inspection modification memory, registers, processor stacks. Nonintrusive in-circuit emulation assured processor's JTAG interface-the emulator does affect target system loading timing. addition software hardware development tools available from Analog Devices, third parties provide wide range tools supporting Blackfin family. Hardware tools include ADSP-21532 EZ-Kit standalone evaluation/development cards. Third Party software tools include libraries, real-time operating systems, block diagram design tools.
Designing Emulator-Compatible Board (Target)
registers. must halted send data commands, once operation been completed emulator, system running full speed with impact system timing. these emulators, target's design must include interface between Analog Devices' JTAG emulation header custom target board.
Target Board Header
emulator interface Analog Devices' JTAG 14-pin header, shown Figure page customer must supply this header target board order communicate with emulator. interface consists standard dual 0.025" square post header, 0.1" 0.1" spacing, with minimum post length 0.235". position used prevent from being inserted backwards. This must clipped target board. Also, clearance (length, width, height) around header must considered. Leave clearance least 0.15" 0.10" around length width header, reserve height clearance attach detach connector.
PIN) BTMS BTCK BTRST BTDI
TRST
VIEW
Figure JTAG Target Board Connector JTAG Equipped Analog Devices (Jumpers Place)
Analog Devices family emulators tools that every developer needs test debug hardware software systems. Analog Devices supplied IEEE 1149.1 JTAG Test Access Port (TAP) ADSP-21532. emulator uses access internal features DSP, allowing developer load code, breakpoints, observe variables, observe memory, examine REV.
seen Figure there sets signals header. There standard JTAG signals TMS, TCK, TDI, TDO, TRST, used emulation purposes (via emulator). There also secondary JTAG signals BTMS, BTCK, BTDI, BTRST that optionally used board-level (boundary scan) testing. When emulator connected this header, place jumpers across BTMS, BTCK, BTRST, BTDI shown Figure This holds JTAG signals correct state allow free. Remove jumpers when connecting emulator JTAG header.
This information applies product under development. characteristics specifications subject change without notice. Analog Devices assumes obligation regarding future manufacturing unless otherwise agreed writing.
PRELIMINARY TECHNICAL DATA ADSP-21532
current information contact Analog Devices 800-262-5643
September 2001
(www.analog.com)-use site search "EE-68". This document updated regularly keep pace with improvements emulator support.
Additional Information
PIN) BTMS BTCK BTDI
This data sheet provides general overview ADSP21532 architecture functionality. additional information Blackfin Family core architecture instruction set, Analog Devices' website.
DESCRIPTIONS
BTRST
TRST
ADSP-21532 definitions listed Table following pins asynchronous: ARDY, PF15-0, NMI, TRST, RESET, CLKIN, XTAL. Unused inputs should tied pulled VDDEXT GND. following symbols appear Type column Table Input, Output, Three-State, Power, Ground.
Table Descriptions Name Function
VIEW
Figure JTAG Target Board Connector with Local Boundary Scan JTAG Emulator Connector
Figure details dimensions JTAG connector 14-pin target end. Figure displays keep-out area target board header. keep-out area allows connector properly seat onto target board header. This board area should contain components (chips, resistors, capacitors, etc.). dimensions referenced center 0.25" square post pin.
Memory Interface A[19:1] D[15:0] /SDQM[1:0] Asynchronous Memory Control AMS3-0 ARDY Synchronous Memory Control SRAS SCAS SCKE CLKOUT SA10 Timers TMR0 TMR1 TMR2
Address Async/Sync Access Data Async/Sync Access Byte Enables/Data Masks Async/Sync Access Request Grant Grant Hang
0.64"
0.24" 0.88"
Figure JTAG Connector Dimensions
Bank Select Hardware Ready Control Output Enable Read Enable Write Enable
0.10"
0.15"
Figure JTAG Connector Keep-Out Area Design-for-Emulation Circuit Information
Address Strobe Column Address Strobe Write Enable Clock Enable Clock Output Bank Select Timer Timer Timer
details target board design issues including: single processor connections, multiprocessor scan chains, signal buffering, signal termination, emulator logic, EE-68: Analog Devices JTAG Emulation Technical Reference Analog Devices website
This information applies product under development. characteristics specifications subject change without notice. Analog Devices assumes obligation regarding future manufacturing unless otherwise agreed writing.
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PRELIMINARY TECHNICAL DATA September 2001
Name
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ADSP-21532
Function
Table Descriptions (Continued) Function
Table Descriptions (Continued) Name
Parallel Peripheral Interface Port PF15-0 PPICLK Serial Ports RSCLK0 RFS0 DR0PRI DR0SEC TSCLK0 TFS0 DT0PRI DT0SEC RSCLK1 RFS1 DR1PRI DR1SEC TSCLK1 TFS1 DT1PRI DT1SEC Port MOSI MISO UART Port Real Time Clock RTXI RTXO JTAG Port TRST Clock CLKIN XTAL
Programmable Flag Pins/PPI Clock Sport0 Receive Serial Clock Sport0 Receive Frame Sync Sport0 Receive Data Primary Sport0 Receive Data Secondary Sport0 Transmit Serial Clock Sport0 Transmit Frame Sync Sport0 Transmit Data Primary Sport0 Transmit Data Secondary Sport1 Receive Serial Clock Sport1 Receive Frame Sync Sport1 Receive Data Primary Sport1 Receive Data Secondary Sport1 Transmit Serial Clock Sport1 Transmit Frame Sync Sport1 Transmit Data Primary Sport1 Transmit Data Secondary Master Slave Master Slave Clock UART Receive UART Transmit Crystal Input Crystal Output JTAG Clock JTAG Serial Data JTAG Serial Data JTAG Mode Select JTAG Reset Emulation Output Clock/Crystal Input Crystal Output
Mode Controls RESET BMODE2-0 Voltage Regulator VDDCRTL VREFFLT Supplies VDDEXT VDDINT
Reset Non-maskable Interrupt Boot Mode Strap External FET/BJT Drive Voltage Reference Filter Power Supply (3.3 nominal) Internal Power Supply (regulated from 2.25 Real Time Clock Power Supply (3.3 Nominal) External Ground
VDDRTC
REV.
This information applies product under development. characteristics specifications subject change without notice. Analog Devices assumes obligation regarding future manufacturing unless otherwise agreed writing.
PRELIMINARY TECHNICAL DATA ADSP-21532
current information contact Analog Devices 800-262-5643
September 2001
OUTLINE DIMENSIONS
Dimensions outline dimension figure page shown millimeters.
160-LEAD METRIC PLASTIC BALL GRID ARRAY (MINI-BGA) (CA-160)
12.10 12.00 11.90 BALL INDICATOR 10.40
0.80
CORNER INDEX AREA
VIEW
0.80 0.80 BALL PITCH BOTTOM VIEW 1.00 0.85 0.43 0.25
1.40
DETAIL
SEATING PLANE
NOTES DIMENSIONS MILLIMETERS. ACTUAL POSITION BALL GRID WITHIN 0.15 IDEAL POSITION RELATIVE PACKAGE EDGES. ACTUAL POSITION EACH BALL WITHIN 0.08 IDEAL POSITION RELATIVE BALL GRID. CENTER DIMENSIONS NOMINAL.
0.10 0.55 0.50 COPLANARITY 0.45 BALL DIAMETER
DETAIL
ORDERING GUIDE Table Part Number Case Temperature Range Instruction Rate Operating Voltage
ADSP-21532SKCA-300
On-chip voltage regulation from 2.25 input
This information applies product under development. characteristics specifications subject change without notice. Analog Devices assumes obligation regarding future manufacturing unless otherwise agreed writing.
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ADSP-21532 Synchronous External Memory Controller with Glueless S

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