ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFOs Descriptions GM16C
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GM16C550
ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFOs
Descriptions GM16C550 asynchronous communications element (ACE) that functionally equivalent GM16C450, addition-ally incorporates 16byte FIFOs available both transmitter receiver, activated placing device FIFO mode. After reset, registers GM16C550 identical those GM16C450. UART performs serial-to-parallel conversion data characters received from peripheral device MODEM, parallel-to- serial conversion data characters received from CPU. read complete status UART time during functional operation. Status information reported includes type condition transfer operations being performed UART, well error conditions (parity, overrun, framing, break interrupt).
Device Code Name Part Number GM16C550 GM16C550-44 GM16C550-48 3.3V PLCC LQFP Voltage
Configuration
RCLK SOUT -CS2 -BAUDQUT XTAL1 XTAL2 -DOSTR DOSTR RIDCDDSRCTSMR OUT1DTRRTSOUT2INTRPT RXRDYA0 ADSTXRDYDDISDISTR DISTR-
Features Compatible Industry Standard 16C550 Modem control signals include CTS, RTS,DSR DTR, Programmable serial characteristics 8-bit characters Even-, odd-, no-parity generation detection 11/2- 2-stop generation Baud rate generation 256K baud) byte FIFO reduces interrupts. Independent control transmit, receive, line status, data interrupts, FIFOs. Full status reporting capabilities Three-state, drive capabilities bi-directional data control bus. 40DIP/44PLCC/48LQFP
40DIP
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GM16C550
Characteristics 70°C, 5V/3.3V
Symbol
Parameter
Address Srobe Width Address Hold Time
Units
Note Note Note Note
Conditions
Delay from Address
Address Setup Time
Delay from Select
Chip Select Hold Time Chip Select Setup time
Delay from Chip Select Delay from Select
Data Hold Time Date Setup Time
Floating Data Delay
Master Reset Pulse Width Address Hold Time from Read Cycle Delay Chip Select Hold Time from Strobe Width Driver Enable/Disable Delay from Data Address Hold Time from Write Cycle Delay Chip Select Hold Time from
loading, Note Note Note loading, Note loading, Note Note External Clock (8.0 Max.) Exrternal Clock (8.9 Max.) Note
Strobe Width
Duration clock High Pulse Duration clock Pulse Read Cycle= Write Cycle=
Baud Generator
Baud Divisor Baud Output Positive Edge Delay Baud Output Negative Edge Delay Baud Output Time Baud Output Down Time
load load load load
GM16C550
Characteristics
Symbol
70°C 5V/3.3V
Parameter Units Conditions
Receiver
RINT
Delay from RBR/ LSR) Reset Interupt Delay from RCLK Sample Time Delay from Stop Interrupt
RCLK Cycles
load
SINT
Note
Transmitter
Delay from THR) Reset Interrupt Delay from IIR) Reset Interrupt (THRE) Delay from Initial INTR Reset Transmit Start Delay from Initial Write Interrupt Delay from Stop Interrupt (THRE) Delay from Start TXRDY Active Delay from Write TXRDY inactive
Baudout Cycles Baudout Cycles Baudout Cycles Baudout Cycles
load load
Note Note load load
Modem Control
Delay from MCR) Output Delay Reset Interrupt from MSR) Delay Interrupt from MODEM Input
load load load
Notes
Applicable only when tied low. FIFO mode (FCRO=1) trigger level interrupts, receiver data available indication, active RXRDY indica-tion overrun error indication will delayed RCLKs. Status indicators (PE, will delayed RCLKs after first byte been received. subsequently received bytes these indicators will updated immediately after RDRBR goes inactive. Timeout interrupt delayed RCLKs. Change discharge time determined VOL, external loading. 4.In FIFO mode RC=425 (minimum) between reads receiver FIFO status registers (interrupt identification register line status register). This delay will lengthened character time, minus last stop time transmitter interrupt delay circuit active (See FIFO Interrupt Mode Operatione)
GM16C550
Timing Waveforms (All timings referenced valid valid)
External Clock Input (8.0 Max.)
2.4V 0.4V 2.2V 0.8V 2.4V (Note 0.4V
Test Points
2.2V (Note 0.8V
Note 2.4V 0.4V levels voltages that inputs driven during testing. Note 2.2V 0.8V levels voltages which timing tests made.
BAUDOUT Timing
BAUD (÷1) BAUD (÷2)
BAUD (÷3) BAUD
2)XIN CYCLES
CTLES
GM16C550
Timing Waveforms
tADS
(Continued)
Write Cycle
A2,A1,A0
VALID tWA*
,CS1,CS0
VALID tSCW* tAW* tCSW* ACTIVE
ACTIVE
ACTIVE
DATA D0-D7 *Applicable Only When Tied Low.
VALID DATA
Read Cycle
tADS
VALID VALID tRA*
A2,A1,A0
,CS1,CS0
tCSR* tAR*
tRCS* ACTIVE
ACTIVE
tRDD tRDD
ACTIVE
DDIS
tRVD VALID DATA
DATA D0-D7
*Applicable Only When Tied Low.
GM16C550
Receiver Timing
RCKK CLKS SAMPLE
tSCD
RECEIVER INPUT DATA
START
DATA BITS(5-8) PARITY
STOP
SAMPLE
tSINT
INTERRUPT (DATA READY RCVR DISTR /DOSTR (READ DATA BUFFER RDLSR) ACTIVE
tRIN
Transmitter Timing
SERIAL (SOUT) INTERRUPT (THRE) START tiRS DISTR/DISTR (WR, THR) DISTR/DISTR
DATA(5-
START PARITY STOP(1 tSTI
IIR)
MODEM Comtrol Timing
DISTR/DISTR MCR) RTS. OUT1. OUT2
tMDO tMDO
CTS. DSR.
INTERRUPT DISTR/DISTR MSR)
tSIM tRIM tSIM
tRIM
tSIM
Note Write Cycle Timing Note Read Cycle Timing
GM16C550
Timing Waveforms (continued)
RAVR FIFO First byte (This Sets RDR)
DATA (5-6)
SAMPLE CLOCK TRIGGER LEVEL INTERRUPT (FCR6,7 0.0) INTERRUPT
STOP
FIFO ABOVE TRIGGER LEVEL NOTE tSINT FIFO BELOW TRIGGER LEVEL tRINT tRINT
ACTIVE
(RDLS
(RDRBR) ACTIVE
RCVR FIFO Byte Other Than First Byte (RDR Already Set)
SAMPLE CLOCK TIMEOUT TRIGGER LEVEL INTERRUPT FIFO ABOVE TRIGGER LEVEL NOTE tSINT BYTE FIFO tSINT (RDLSR) (RDRBR) ACTIVE tRINT (FIFO BELOW tRINT TRIGGER LEVEL)
INTERRUPT
ACTIVE PREVIOUS BYTE READ FROM FIFO
ACTIVE
Receiver Ready (pin FCRO FCRO FCRO (Mode
(RDRBR) ACTIVE NOTE
(FIRST BYTE)
STOP
SAMPLE
RXRDY tSINT NOTE tRINT
Note This reading last byte FIFO Note FCRO then Tsint RCLKs. timeout tSINT RCLKs.
GM16C550
Timing waveforms (Continued)
Receiver Ready (pin FCRO FCRO FCRO (Mode
(RDRBR) ACTIVE NOTE
(FIRST
STOP
SAMPLE
RXRDY tSINT NOTE tRINT
Note This reading last byte FIFO Note FCRO Tsint RCLKs.
RCVR FIFO Byte Other Than First Byte (RDR Already Set)
(WRTHR) BYTE
SOUT
DATA
PARITY
STOP
START
TXRDY tWXI tSXA
Transmitter Ready (pin FCRO (Mode
(WRTHR) BYTE
SOUT
DATA
PARITY
STOP
START
FIFO FULL TXRDY tWXI tSXA
GM16C550
INTERNAL BLOCK DIAGRAM
INTERNAL DATA D7-D0 RECEIVER FIFO RECEIVER BUFFER REGISTER RECEIVER SHIFT REGISTER (10)
(1-8)
DATA BUFFER
SELECT
(28) (27) (26)
LINE CONTROL REGISTER
RECEIVER TIMING CONTROL
RCLK
DDIS TXRDY XOUT RXRDY
(12) (13) (14) (25) (35) (22) (21) (19) (23) (24) (16) (17) (29) SELENT CONTROL LOGIC
DIVIOR LATCH(LS) BAUD GENERATOR DIVISOR LATCH(MS) (15) BAUDIUT
LINE STATUS REGISTER TRANSMITTER FIFO TRANSTMTTER HOLDING REGISTER
RECEIVER TIMING CONTROL
SELECT
TRANSTMTTER HOLDING REGISTER
(11)
SOUT
(32) MODEM CONTROL REGISTER (36) (33) MONDEM CONTROL LOGIC (37) (38) (39) (34) (31) INTERRUPT ENABLE REGISTER INTERRUPT CONTROL LOGIC (30)
OUT1 OUT2 INTR
POWER SUPPLY
(40) (20)
MODEM STATUS REGISTER
INTERRUPT REGISER
FIFO CONTROL REGISTER
GM16C550
Descriptions
following describes function UART pins. Some these descriptions reference internal circuits. following descriptions, represents logic nominal) high represents logic (+2.4V nominal). INPUT SIGNALS Chip Select (CS0, CS1, Pins 12-14: When high low, chip selected. This enable communication between UART CPU. positive edge active Address Strobe signal latches decoded chip select signals, completing chip selection. always low, valid chip selects should stabilize according parameter. Read (RD, Pins When high while chip selected, read status information data from selected UART register. Note: Only active input required transfer data from UART during read operation. Therefore either input permanently input permanently high, when used. Write (WR, When high while chip selected, write control words data into selected UART register. Note: Only active input required transfer data UART during write operation. Therefore, either input permanently input permanently high, when used. Address Strobe positive edge active Address Strobe signal latches Register Select (A0, Chip Select (CS0, CS1, CS2) signals. Note: active input required when Register Select (A0, signals stable duration read write operation. required, input permanently low. Register Select (A0, A2), Pins 26-28: Address signals connected these inputs select UART register read from write during data transfer. table registers addresses shown below. Note that state Divisor Latch Access (DLAB), which most significant Line Control Register, affects selection certain UART registers. DLAB must high system software access Baud Generator Divisor Latches. Master Reset (MR), When this input high clears registers (except Receiver Buffer, Transmitter Holding, Divisor Latches), control logic UART. state various output signals (SOUT, INTR, DTR) affected active input (Refer Table This input buffered with TTLcompatible Schmitt Trigger with 0.5V typical hysteresis. Receiver Clock (RCLK), This input baud rate clock receiver section chip. Ring Indicator When low, this indicates that telephone ringing signal received MODEM data set. signal MODEM status input Register Address Register Receiver Buffer (read) Transmitter Holding Register (Write) Interrupt Enable Interrupt Identification (read) FIFO Control (Write) Line Control MODEM Control Line Status MODEM Status Scratch Divisor Latch (least significant byte) Divisor Latch (most significant byte) Serial Input (SIN), Serial data input from communications link (peripheral device, MODEM, data set). Clear Send When low, this indicates that MODEM data ready exchange data. signal MODEM status input whose conditions tested reading (CTS) MODEM Status Register. complement signal. (DCTS) MODEM Status Register indicates whether input changed state since previous reading MODEM Status Register. effect Transmitter. Note: Whenever MODEM Status Register changes state, interrupt generated MODEM Status Interrupt enabled. Data Ready When low, this indicates that MODEM data ready establish communications link with UART. signal MODEM status input whose condition tested reading (DSR) MODEM Status Register. complement signal. (DDSR) MODEM Status Register indicates whether input changed state since previous reading MODEM Status Register. Note: Whenever MODEM Status Register changes state, interrupt generated MODEM Status interrupt enabled. Data Carrier Detect When low, indicates that data carrier been detected MODEM data set. signal MODEM status input whose condition tested Register. complement signal. (DDCD) MODEM Status Register indicates whether input changed state since previous reading MODEM Status Register. effect receiver. Note: Whenever MODEM Status Register changes state, interrupt generated MODEM Status Interrupt enabled. whose condition tested reading MODEM Status Register. complement signal. (TERI) MODEM DLAB
GM16C550
Status Register indicates whether input signal changed from high state since previous reading MODEM Status Register Note Whenever MODEM Status Register changes from high state, interrupt generated MODEM Status Interrupt enabled.
RXRDY Mode FIFO Mode (FCR0 when FRC3 trigger level timeout been reached, RXRDY will active. Once activated will inactive when there more characters FIFO holding register. TXRDY Mode GM16C450 Mode (FCR0 FIFO Mode (FCR FCR3 there characters XMIT FIFO XMIT hold register, TXRDY pin(24) will active. Once activated TXRDY will inactive after first character loaded into XMIT FIFO holding register. TXRDY Mode FIFO Mode (FCR0 when FCR3 there least unfilled position XMIT FIFO, will active. This will become inactive when XMIT FIFO completely full. Driver Disable (DDIS), this goes whenever reading data from UART. disable control direction data transceiver between UART. Baud BAUDOUT This clock signal from transmitter section UART. clock rate equal main reference oscillator frequency divided specified divisor Baud Generator Divisor Latches. BAUDOUT also used receiver section tying this output RCLK input chip. Interrupt (INTR), This goes high when-ever following interrupt types active high cognition enabled IER; Receiver Error Flag; Received Data Avail-able; timeout (FIFO Mode only); Transmitter Holding Register Empty; MODEM Status, INTR signal reset upon appropriate interrupt service Master Reset operation. Serial output (SOUT), Composite serial data output communications link (peripheral. MODEM data set). SOUT signal Marking (logic state upon Master Reset operation. INPUT OUTPUT SIGNALS Data (D7-D0) Bus, 1-8: This comprises eight TRI-state input/output lines. provides bidirectional communications between UART CPU, Data, control words. status information transferred D7-D0 Data Bus. External Clock Input/Output (XIN, XOUT), Pins These pins connect main timing reference (crystal signal clock) UART.
Vcc, supply. Vss, Ground(0V) reference. OUTPUT SIGNALS Data Terminal Ready When low, this informs MODEM data that UART ready establish communications link. output signal active programming (DTR) MODEM Control Register high level. Master Reset operation sets this signal inactive (high) state. Loop mode operation holds this signal inactive state. Request Send When low, this informs MODEM data that UART ready exchange data. output signal active programming (RTS) MODEM Control Register. Master Reset operation sets this signal inactive state. Loop node operation holds this signal inactive state. Output OUT1 This user-designed out-put active programming (OUT1) MODEM Control Register high level. Master Reset operation sets this signal inactive state. Loop Mode operation holds this signal inactive state. Output This user-designated output active programming (OUT2) MODEM Control Register high level. Master Reset operation sets this signal inactive (high) state. Loop mode operation holds this signal inactive state. TXRDY, RXRDY, Transmitter Receiver signaling available through pins 29). When operating FIFO mode, types signaling selected FCR3, When operating GM16C16450 Mode., only Mode allowed. Mode supports single transfer where transfer made between cycles. Mode supports multi-transfer where multiple transfers made continuously until RCVR FIFO been emptied XMIT FIFO been filled. RXRDY Mode When GM16C450 Mode (FCR0 FIFO Mode (FCRO RCR3 there least character RCVR FIFO RCVR holding register, RXRDY (29) will active. Once activated RXRCY will inactive when there more characters FIFO holding register.
GM16C550 TABLE UART Reset Configuration
Register Signal Interrupt Enable Register Interrupt Identification Register FIFO Control Line Control Register MODEM Control Register Line status Register MODEM Status Register SOUT INTR (RCVR Errs) INTR (RCVR Data Ready) INTR (THRE) INTR (Modem Status Changes)
OUT1
Reset Control Master Reset Master Reset Master Reset Master Reset Master Reset Master Reset Master Reset Master Reset Read LSR/MR Read RBR/MR Read IIR/Write THR/MR Read MSR/MR Master Reset Master Reset Master Reset Master Reset MR/RCR1-FCR0/ FCR0 MR/RCR1-FCR0/ FCR0
Reset State 0000 0000 (Note 0000 0001 0000 0000 0000 0000 0000 0000 0110 0000 xxxx 0000 (Note High High High High High Bits Bits
RCVR FIFO XMIT FIFO
Note Boldface bits Permanently low. Note Bits driven input signals.
TABLE Summary Registe
Register Address
Interrupt Enable Register FIFO Control Register (Write Only) FIFO Enable Word Length Select (WLS0) Data Terminal Ready (DTR) Data Ready (DR) Delta Clear Send (DCTS) Line Control Register MODEM Control Register Line Status Register MODEM Status Register Scratch Register Divisor Latch (LS) Divisor Latch (MS)
DLAB DLAB
Interrupt Enable Register
DLAB DLAB DLAB0
Receiver Buffer Register (Read Only) Enable Received Data Available Interupt (ERBFI) Enable Transmitter Holding Register Empty Interrupt (ETBEI) Enable Receiver Line Status Enable MODEM Status Interrupt (EDSSI) Reserved Even Parity Select (EPS) Stick Parity Loop Interrupt (Note Mode select Parity Enable (PEN) Out2 Framing Error (FE) Interrupt XMIT FIFO Reset Number Stop Bits (STB) Out1 Parity Error (PE) Trading Edge Ring Indicator (TERI) Interrupt RCVR FIFO Reset Word Length Select (WLS1) Request Send (RTS) Overrun Error (OE) Delta Data Ready (DDSR) Interrupt Pending
Transmitter Holding Register (Write Only)
Data
Data
Data
Data
Break Interrupt (BI) Transmitter Holding Register (THRE) Break Transmitter Empty (TEMT) Divisor Latch Access (DLA3) Error RCBR FIFO (Note2) Reserved FIFO3 enabled (note FIFO3 enabled (note RCVR Trigger (MSB) RCVR Trigger (LSB)
Data
Data
Data
Data
Data
Data
Delta Data Camer Delect (DDCD) Clear Send (CTS) Data Ready (DSR) Ring Indicator (RI) Data Camer Detect (DCD)
Data
Data
Data
Data
Data
Data
GM16C550
Note least significant seriously transmitted received Note 2:these bits always GM16C450 Mode
GM16C550 Registers
system programmer Access UART registers summarized Table CPU. These registers control UART operations including transmission reception data. Each register Table name reset state shown. summed). This Even Parity Select bit. When logic logic number logic transmitted checked data word bits Parity bit. When logic logic even number logic transmitted checked. This Stick Parity bit. When bit3, logic Parity transmitted checked logic logic then Parity transmitted checked logic logic Stick Parity disabled. This Break Control bit. causes break condition transmitted received UART. When logic serial output (SOUT) forced Spacing (logic state. break disabled setting logic Break Control acts only SOUT effect transmitted logic. Note This feature enables alert terminal during break. Transmitter used character timer accurately establish break duration. computer communications system. following sequence followed. erroneous extraneous characters will transmitted because break. Load character, response THRE. break after next THRE Wait transmitter idle. (TEMT clear break when normal transmission tired. During bread, Transmitter used character timer accurately establish break duration. This Divisor Latch Access (DLAB). must high (logic) access Divisor Latches Baud Generator during Read Write operation. must (logic access Receiver Buffer, Transmitter Holding Register, Interrupt Enable Register.
LINE CONTROL REGISTER
system programmer specifies format asynchronous data communications exchange Divisor Latch Access Line Control Register (LCR). programmer also read contents Line Control Register. read capability simplifies system programming eliminates need separate storage system memory LCR. Details each follow: These bits specify number bits each transmitted received serial character. encoding bits follows. Character Length Bits Bits Bits Bits This specifies number Stop bits transmitted received each serial character. logic Stop generated transmitted data. logic when 5-bit word length selected bits half Stop bits generated. logic When either 8bit word length selected, Stop generated. Receiver checks first Stop only, regardless number Stop selected. This Parity Enable bit. When logic Parity generated (transmit data) checked (receive data) between last data word Stop serial data. (The Parity used produce even number when data word bits Parity
Typical Clock Circuits
EXTERNAL CLOCK DRIVER
CLOCK BAUD GEN. LOGIC
CRYSTAL
XOUT CLOCK BAUD GEN. LOGIC
OPTIONAL OPTIONAL DRIVER CLOCK OUTPUT XOUT
GM16C550 Typical Crystal Oscillator Network
Crystal 3.1MHz 1.8MHz 1.5k 1.5k 10-30pF 10-30pF 40-60pF 40-60pF
TABLE III. Baud Rates Using 1.8432 Crystal Desired Baud Rate 134.5 1200 1800 2000 2400 3600 4800 7200 9600 19200 38400 56000 Decimal Divisor Used Generate Clock 2304 1536 1047 Percent Error Difference Between Desired Actual 0.026 0.058 0.69 2.86
GM16C550
TABLE Baud Rates Using 3.072 crystal Decimal Divisor Used Generate 3840 2560 1745 1428 1280 Percent Error Difference Between Desired Actual 0.026 0.034 0.312 0.628 1.23
Desired Baud Rate 134.5 1200 1800 2000 2400 3600 4800 7200 9600 19200 38400
TABLE Baud Rate Using 8MHz Crystal Decimal Divisor Used Generate 10000 6667 4545 3717 3333 1667 Percent Error Difference Between Desired Actual 0.005 0.010 0.013 0.010 0.020 0.040 0.080 0.080 0.160 0.080 0.160 0.644 0.160 0.160 0.160 0.790 2.344 2.344
Desired Baud Rate 134.5 1200 1800 2000 2400 3600 4800 7200 9600 19200 38400 56000 128000 256000
TABLE Interrupt Control Functions
FIFO Mode Only Interrupt Reset Function
Interrupt Type None None Interrupt Source Priorit Level Interrupt Reset Control
Interrupt Identification
Highest Receiver Line Status Overrun Error Parity Error Framing Error Break Interrupt
Reading Line Status Register
Receiver Data Available Trigger Level Reached
Second Received Data Available
Second Character Timeout Indication Third Transmitter Holding Register Empty Fourth MODEM Status
Reading Receiver Buffer Register FIFO Drops Below Trigger Level Reading Receiver Buffer Register
Characters Have Been Removed From Input RCVR FIFO During Last char. Times There Least char. During This Time Transmitter Holding Register Empty
Reading Register Source interrupt) Writing into Transmitter Holding Register
GM16C550
Clear Send Data Ready Ring Indicator Data Carrier Detect
Reading MODEM Status Register
GM16C550
PROGRAMMABLE BAUD GENERATOR
UART contains programmable Baud Generator that capable taking clock input from 4MHz highest input clock frequency recommended when divisor output frequency Baud Generator Baud [divisor (frequency input) (baud rate 8-bit latches store divisor 16-bit binary format. These Divisor Latches must loaded during initialization ensure proper operation Baud Generator. Upon loading either Divisor Latches, 16-bit Baud counter immediately loaded. Tables III, provide decimal divisors with crystal frequencies 1.8432 3.072MHz MHz, respectively. baud rates 38400 below, error obtain minimal. accuracy desired baud rate dependent crystal frequency chosen. Using divisor zero recommended. LINE STATUS REGISTER This register provides status information concerning data transfer. Table shows contents Line Status Register. Details each follow. This receiver Data Ready (DR) indicator. logic 1whenever complete incoming character been received transferred into Receiver Buffer Register FIFO. reset logic reading data Receiver Buffer Register FIFO. This Overrun Error (OE) indicator. indicates that data Receiver Buffer Register read before next character transferred into Receiver Buffer Register, thereby destroying previous character. indicator logic upon detection overrun condition reset whenever reads contents Line Status Register FIFO mode data continues fill FIFO beyond trigger level, overrun error will occur only been completely received shift register. indicated soon happens. character shift register overwritten, transferred FIFO. This Parity Error (PE) indicator. indicates that received data character does have correct even parity. selected even -parityselect bit. logic upon detection parity error reset logic whenever reads contents Line Status Register. FIFO mode this error associated with particular character when associated character FIFO. This Framing Error (FE) indicator. Bit3 indicates that received character have valid Stop bit. logic whenever Stop following last data parity detected logic (Spacing level). indicator reset whenever reads contents Line Status Register. FIFO mode this error associated with particular character FIFO applies This error revealed when associated character FIFO. UART will resynchronize after framing error. this assumes that framing error next start samples this "start" twice then takes "data". This Break Interrupt (BI) indicator. logic when ever received data input held spacing (logic) state longer than full word transmission time (that total time Start data bits Parity Stop bits). indicator reset whenever reads contents line Status Register. FIFO mode this error associated with particular character FIFO applies This error revealed when associated character FIFO. When break occurs only zero character loaded into FIFO. next character transfer enabled after goes marking state receives next valid start bit. Note: Bits through error conditions that produce Receiver Line Status interrupt whenever corresponding conditions detected interrupt enabled. This Transmitter Holding Register Empty (THRE) indicator. indicates that UART ready accept character transmission. addition, this causes UART issue interrupt when Transmit Holding Register Empty Interrupt enable high. THRE logic when character transferred from Transmitter Holding Register into Transmitter Shift Register. reset logic concurrently with loading Transmitter Holding Register CPU, FIFO mode this when XMIT FIFO empty; cleared when least byte written XMIT FIFO. This Transmitter Empty (TEMT) indicator. logic whenever Transmitter Holding Register (THR) Trans-mitter shift register (TSR) both empty. reset logic whenever either contains data character. FIFO mode this whenever transmitter FIFO shift register both empty. GM16C450 Mode this FIFO mode LSR7 when there least parity error, framing error break indication FIFO. LSR7 cleared when reads LSR, there subsequent errors FIFO. Note: Line Status Register intended read operations only. Writing this register recom-mended this operation only used factory testing. FIFO CONTROL REGISTER This write only register same location (the read only register). This register used enable FIFOs, RCVR FIFO trigger level, select type signaling.
GM16C550
Writing FCR0 enables both XMIT RCVR FIFOs. Resetting FCR0 will clear bytes both FIFOs. When changing from FIFO Mode GM16C450 Mode vice versa, data automatically cleared from FIFOs. This must when other bits written they will programmed. Writing FCR1 clears bytes RCVR FIFO resets counter logic shift register cleared. that written this position selfclearing. Writing FCR2 clears bytes XMIT FIFO resets counter logic shift register cleared. that written this position selfclearing. Setting will cause RXRDY TXRDY pins change from mode mode FCR0 (see description RXRDY TXRDY pins). Bit4, FCR4 FCR5 reserved future use. Bit6, FCR6 FCR7 used trigger level RCVR FIFO interrupt. RCVR FIFO Trigger Level (Bytes) These bits always logic These bits when FCR0 INTERRUPT ENABLE REGISTER This register enables five types UART interrupts. Each interrupt individually activate interrupt (INTR) output signal. possible totally disable interrupt system resetting bits through Interrupt Enable Register (IER). Similarly, setting bits register logic enables selected interrupt(s). Disabling interrupt prevents from being indicated active from activating INTR output signal. other system functions operate their normal manner, including setting Line Status MODEM Status Registers. Table shows contents IER. Details each follow. This enables Received Data Available Interrupt (and timeout interrupts FIFO mode) when logic1. This enables Receiver Line Status interrupt when logic This enables MODEM Status interrupt when logic through These four bits always logic MODEM CONTROL REGISTER This register controls interface with MODEM data peripheral device emulating MODEM). contents MODEM Control Register indicated Table described below. This controls Data Terminal Ready (DTR) output. When logic output forced logic When reset logic output forced logic Note: output UART applied inverting line driver (such GD75188) obtain proper polarity input succeeding MODEM data set. This controls Request Send (RTS) output. affects output manner identical that described above This controls output (OUT1) signal which auxillary user-designated output. affects OUT1 output manner identical that described above This controls output 2(OUT2) signal, which auxillary user-designated output affects OUT2 output manner identical that described above This provides local loopback feature Diagnostic testing UART. When logic following occur transmitter Serial output (SOUT) Marking (logic State; receiver Serial Input (SIN) disconnected; output Transmitter Shift
INTERRUPT IDENTIFICATION REGISTER order provide minimum software overhead during data character transfers, UART prioritizes interrupts into four levels records these interrupt Identification Register. four levels interrupt conditions order priority Receiver Line Status; Received Data Ready; Transmitter Holding Register Empty; MODEM Status. When accesses IIR, UART freezes interrupts indicates highest priority pending interrupt CPU. While this access occurring, UART records interrupts, access complete. Table shows contents IIR. Details each follow: This used prioritized interrupt environment indicate whether interrupt pending. When logic interrupt pending contents used pointer appropriate interrupt service routine. When logic interrupt pending. These used identify highest priority interrupt pending indicated Table GB16C450 Mode this FIFO mode this along with when timeout interrupt pending.
GM16C550
Register "looped back" into Receiver Shift Register input; four MODEM Control inputs disconnected; four MODEM Control outputs OUT1 internally connected four MODEM Control inputs, MODEM Control output pins forced their inactive state (high). diagnostic mode, data that transmitted immediately received. This feature allows processor verify transmitter received-data paths UART. diagnostic mode, receiver transmitter interrupts fully operational. Their sources external part. MODEM Control Interrupts also operational, interrupts sources lower four bits MODEM Control inputs. interrupts still controlled Interrupt Enable Register. Bits through These bits permanently logic MODEM STATUS REGISTER This register provides current state control lines from MODEM peripheral device) CPU. addition this current-state information, four bits MODEM Status Register provide change information. These bits logic Whenever control input from MODEM changes state. They reset logic whenever reads MODEM Status Register. contents MODEM Status Register indicated Table described below. This Delta Clear Send (DCTS) indicator. indicates that input chip changed state since last time read CPU. This Delta Data Ready (DDSR) indicator. indicates that input chip changed state since last tome read CPU. This Trailing Edge Ring Indicator (TERI) detector. indicates that input chip changed from high state. This Delta Data Carrier Detect (DDCD) indicator. indicates that input chip changed state. Note: Whenever logic MODEM Status Interrupt generated. This complement Clear Send input. 4(loop) this equivalent MCR. This complement Data Ready input. this equivalent MCR. This complement Ring Indicator. input. this equivalent OUT1 MCR. This complement Data Carrier Detect(DCD) input. this equivalent out2 MCR. SCRATCHPAD REGISTER This 8-bit Read/Write Register does control UART anyway. intended scratchpad register used programmer hold data temporarily. FIFO INTERRUPT MODE OPERATION When RCVR FIFO receiver interrupts enabled (FCR0 IER0 RCVR interrupts will occur follows: receive data available interrupts will issued when FIFO reached programmed trigger level; will cleared soon FIFO drops below programmed trigger level. receive data available indicate also occurs when FIFO trigger level reached, like interrupt cleared when FIFO drops below trigger level. receiver line status interrupt (IIR-06), before, higher priority than received data available (IIR-04) interrupt. data ready (LSR0)is soon character transferred from shift register RCVR FIFO. reset when FIFO empty. When RCVR FIFO receiver interrupts enabled, RCVR FIFO timeout interrupts will occur follows: FIFO timeout interrupt will occur, following conditions exist: least character FIFO most recent serial character received longer than continuous character times stop bits programmed second included this time delay). most recent read FIFO longer than 4continuous character times age. This will cause maximum character received interrupt issued delay 160ms 300BAUD with character. character times calculated using RCLK input clock signal (This makes delay proportional baudrate). When timeout interrupt occurred cleared timer rest when reads character from RCVR FIFO. When timeout interrupt occurred timeout timer reset after character received after reads RCVR FIFO. When XMIT FIFO transmitter interrupts enabled (FCR0=1, IER=1) XMIT interrupts will occur follows: transmitter holding register interrupt (02) occurs when XMIT FIFO empty; cleared soon transmitter holding register written characters written XMIT FIFO while servicing this interrupt) read.
GM16C550
transmitter FIFO empty indications will delayed character time minus last stop time whenever following occurs: THRE there have been least bytes same time transmit FIFO, since last THRE first transmitter interrupt affect changing FCR0 will immediate, enabled. Character timeout RCVR FIFO trigger level interrupts have same priority current received data available interrupt; XMIT FIFO empty same priority current transmitter holding register empty interrupt. FIFO POLLED MODE PRERATION With FCRQ resetting IER0, IER1, IER2, IER3 zero puts RCVR MITTER controlled separately either both polled mode operation. this mode user's program will check RCVR XMITTER status LSR. stated previously: LSR0 will long there byte FIFO. LSR1 LSR4 will specify which error(s) occurred. Character error status handled same when interrupt mode, affected since IER2=0. LSR5 will indicate when XMIT FIFO empty. LSR6 will indicate that both XMIT FIFO shift register empty. LSR7 will indicate whether there errors RCVR FIFO. There trigger level reached timeout condition indicated FIFO polled Mode, however, RCVR XMIT FIFOs still fully capable holding characters.
Application Circuit
SYSTEM
XTAL1 -A23 LATCH
ADDRESS DECODER RESET
XTAL2 RCLK SOUT GM16C550 DRIVERS RS-232-C INTERFACE
-D15
DATA BUFFER
DISTR DOSTR DISTR DOSTR D0-D15
INTRPT TXRDY DDIS RXRDY
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