SST39VF088 SST39VF0882.7V (x8) memory FEATURES: Organiz
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Mbit (x8) Multi-Purpose Flash
SST39VF088
SST39VF0882.7V (x8) memory
FEATURES:
Organized Single Voltage Read Write Operations 2.7-3.6V Superior Reliability Endurance: 100,000 Cycles (typical) Greater than years Data Retention Power Consumption (typical values MHz) Active Current: (typical) Standby Current: (typical) Sector-Erase Capability Uniform KByte sectors Block-Erase Capability Uniform KByte blocks Fast Read Access Time: Latched Address Data Fast Erase Byte-Program Sector-Erase Time: (typical) Block-Erase Time: (typical) Chip-Erase Time: (typical) Byte-Program Time: (typical) Chip Rewrite Time: seconds (typical) Automatic Write Timing Internal Generation End-of-Write Detection Toggle Data# Polling CMOS Compatibility JEDEC Standard Flash EEPROM Pinouts command sets Packages Available 48-lead TSOP (12mm 20mm)
PRODUCT DESCRIPTION
SST39VF088 device CMOS Multi-Purpose Flash (MPF) manufactured with SST's proprietary, high performance CMOS SuperFlash technology. split-gate cell design thick-oxide tunneling injector attain better reliability manufacturability compared with alternate approaches. SST39VF088 writes (Program Erase) with 2.7-3.6V power supply. conforms JEDEC standard pinouts memories. Featuring high performance Byte-Program, SST39VF088 device provides typical Byte-Program time µsec. devices Toggle Data# Polling indicate completion Program operation. protect against inadvertent write, they have on-chip hardware Software Data Protection schemes. Designed, manufactured, tested wide spectrum applications, these devices offered with guaranteed endurance 10,000 cycles. Data retention rated greater than years. SST39VF088 device suited applications that require convenient economical updating program, configuration, data memory. system applications, they significantly improve performance reliability, while lowering power consumption. They inherently less energy during Erase Program than alternative flash technologies. total energy consumed function applied voltage, current, time application. Since
©2003 Silicon Storage Technology, Inc. S71227-04-000 11/03 logo SuperFlash registered trademarks Silicon Storage Technology, Inc. trademark Silicon Storage Technology, Inc. These specifications subject change without notice.
given voltage range, SuperFlash technology uses less current program shorter erase time, total energy consumed during Erase Program operation less than alternative flash technologies. They also improve flexibility while lowering cost program, data, configuration storage applications. SuperFlash technology provides fixed Erase Program times, independent number Erase/Program cycles that have occurred. Therefore system software hardware does have modified de-rated necessary with alternative flash technologies, whose Erase Program times increase with accumulated Erase/Program cycles. meet high density, surface mount requirements, SST39VF088 offered 48-lead TSOP packaging. Figure assignments.
Mbit Multi-Purpose Flash SST39VF088
Device Operation
Commands used initiate memory operation functions device. Commands written device using standard microprocessor write sequences. command written asserting while keeping low. address latched falling edge CE#, whichever occurs last. data latched rising edge CE#, whichever occurs first.
Read
Read operation SST39VF088 controlled OE#, both have system obtain data from outputs. used device selection. When high, chip deselected only standby power consumed. output control used gate data from output pins. data high impedance state when either high. Refer Read cycle timing diagram further details (Figure
sequence with Block-Erase command (30H) block address (BA) last cycle. sector block address latched falling edge sixth pulse, while command (30H 50H) latched rising edge sixth pulse. internal Erase operation begins after sixth pulse. End-ofErase operation determined using either Data# Polling Toggle methods. Figures timing waveforms. commands issued during Sectoror Block-Erase operation ignored.
Chip-Erase Operation
SST39VF088 provides Chip-Erase operation, which allows user erase entire memory array state. This useful when entire device must quickly erased. Chip-Erase operation initiated executing sixbyte command sequence with Chip-Erase command (10H) address AAAH last byte sequence. Erase operation begins with rising edge sixth CE#, whichever occurs first. During Erase operation, only valid read Toggle Data# Polling. Table command sequence, Figure timing diagram, Figure flowchart. commands issued during Chip-Erase operation ignored.
Byte-Program Operation
SST39VF088 programmed byte-by-byte basis. Before programming, sector where byte exists must fully erased. Program operation accomplished three steps. first step three-byte load sequence Software Data Protection. second step load byte address byte data. During Byte-Program operation, addresses latched falling edge either WE#, whichever occurs last. data latched rising edge either WE#, whichever occurs first. third step internal Program operation which initiated after rising edge fourth CE#, whichever occurs first. Program operation, once initiated, will completed within Figures controlled Program operation timing diagrams Figure flowcharts. During Program operation, only valid reads Data# Polling Toggle Bit. During internal Program operation, host free perform additional tasks. commands issued during internal Program operation ignored.
Write Operation Status Detection
SST39VF088 provides software means detect completion write (Program Erase) cycle, order optimize system Write cycle time. software detection includes status bits: Data# Polling (DQ7) Toggle (DQ6). End-of-Write detection mode enabled after rising edge WE#, which initiates internal Program Erase operation. actual completion nonvolatile write asynchronous with system; therefore, either Data# Polling Toggle read simultaneous with completion Write cycle. this occurs, system possibly erroneous result, i.e., valid data appear conflict with either DQ6. order prevent spurious rejection, erroneous result occurs, software routine should include loop read accessed location additional times. both reads valid, then device completed Write cycle, otherwise rejection valid.
Sector/Block-Erase Operation
Sector- Block-) Erase operation allows system erase device sector-by-sector block-byblock) basis. SST39VF088 offers both Sector-Erase Block-Erase mode. sector architecture based uniform sector size KByte. Block-Erase mode based uniform block size KByte. SectorErase operation initiated executing six-byte command sequence with Sector-Erase command (50H) sector address (SA) last cycle. Block-Erase operation initiated executing six-byte command
©2003 Silicon Storage Technology, Inc.
S71227-04-000
11/03
Mbit Multi-Purpose Flash SST39VF088
Data# Polling (DQ7)
When SST39VF088 internal Program operation, attempt read will produce complement true data. Once Program operation completed, will produce true data. Note that even though have valid data immediately following completion internal Write operation, remaining data outputs still invalid: valid data entire data will appear subsequent successive Read cycles after interval During internal Erase operation, attempt read will produce `0'. Once internal Erase operation completed, will produce `1'. Data# Polling valid after rising edge fourth CE#) pulse Program operation. Sector-, Block- Chip-Erase, Data# Polling valid after rising edge sixth CE#) pulse. Figure Data# Polling timing diagram Figure flowchart.
Data Protection
SST39VF088 provides both hardware software features protect nonvolatile data from inadvertent writes.
Hardware Data Protection
Noise/Glitch Protection: pulse less than will initiate Write cycle. Power Up/Down Detection: Write operation inhibited when less than 1.5V. Write Inhibit Mode: Forcing low, high, high will inhibit Write operation. This prevents inadvertent writes during power-up power-down.
Software Data Protection (SDP)
SST39VF088 provides JEDEC approved Software Data Protection scheme data alteration operations, i.e., Program Erase. Program operation requires inclusion three-byte sequence. three-byte load sequence used initiate Program operation, providing optimal protection from inadvertent Write operations, e.g., during system power-up power-down. Erase operation requires inclusion six-byte sequence. SST39VF088 device shipped with Software Data Protection permanently enabled. Table specific software command codes. During command sequence, invalid commands will abort device Read mode within TRC.
Toggle (DQ6)
During internal Program Erase operation, consecutive attempts read will produce alternating i.e., toggling between When internal Program Erase operation completed, will stop toggling. device then ready next operation. Toggle valid after rising edge fourth CE#) pulse Program operation. Sector-, Block-, Chip-Erase, Toggle valid after rising edge sixth CE#) pulse. Figure Toggle timing diagram Figure flowchart.
©2003 Silicon Storage Technology, Inc.
S71227-04-000
11/03
Mbit Multi-Purpose Flash SST39VF088
Product Identification
Product Identification mode identifies device SST39VF088 manufacturer SST. This mode accessed software operations. Users Software Product Identification operation identify part (i.e., using device when using multiple manufacturers same socket. details, Table software operation, Figure Software Entry Read timing diagram Figure Software Entry command sequence flowchart. TABLE PRODUCT IDENTIFICATION
Address Manufacturer's Device SST39VF088 0001H
T1.0 1227
Product Identification Mode Exit
order return standard Read mode, Software Product Identification mode must exited. Exit accomplished issuing Software Exit command sequence, which returns device Read operation. This command also used reset device Read mode after inadvertent transient condition that apparently causes device behave abnormally, e.g., read correctly. Please note that Software Exit command ignored during internal Program Erase operation. Table software command codes Figure flowchart.
Data
0000H
FUNCTIONAL BLOCK DIAGRAM
X-Decoder
SuperFlash Memory
Memory Address
Address Buffer Latches Y-Decoder
1227 B1.0
Control Logic
Buffers Data Latches
©2003 Silicon Storage Technology, Inc.
S71227-04-000
11/03
Mbit Multi-Purpose Flash SST39VF088
Standard Pinout View
1227 48-tsop P01.0
FIGURE ASSIGNMENTS 48-LEAD TSOP TABLE DESCRIPTION
Symbol AMS1-A0 DQ7-DQ0 Name Address Inputs Data Input/output Functions provide memory addresses. During Sector-Erase AMS-A12 address lines will select sector. During Block-Erase AMS-A16 address lines will select block. output data during Read cycles receive input data during Write cycles. Data internally latched during Write cycle. outputs tri-state when high. activate device when low. gate data output buffers. control Write operations. provide power supply voltage: Unconnected pins.
T2.0 1227
Chip Enable Output Enable Write Enable Power Supply Ground Connection
2.7-3.6V SST39VF088
Most significant address SST39VF088
©2003 Silicon Storage Technology, Inc.
S71227-04-000
11/03
Mbit Multi-Purpose Flash SST39VF088
Preliminary Specifications TABLE OPERATION MODES SELECTION
Mode Read Program Erase Standby Write Inhibit Product Identification Software Mode Table
T3.0 1227
DOUT High High DOUT High DOUT
Address Sector Block address, Chip-Erase
VIH, other value.
TABLE SOFTWARE COMMAND SEQUENCE
Command Sequence Byte-Program Block-Erase Sector-Erase Chip-Erase Software Entry4,5 Software Exit6 Write Cycle Addr1 AAAH AAAH AAAH AAAH AAAH Data
T4.1 1227
Write Cycle Addr1 555H 555H 555H 555H 555H Data
Write Cycle Addr1 AAAH AAAH AAAH AAAH AAAH Data
Write Cycle Addr1 AAAH AAAH AAAH Data Data
Write Cycle Addr1 555H 555H 555H Data
Write Cycle Addr1 BAX3 SAX3 AAAH Data
Address format A14-A0 (Hex), Addresses A19-A15 VIH, other value, Command sequence. Program Byte address Sector-Erase; uses AMS-A12 address lines Block-Erase; uses AMS-A16 address lines Most significant address SST39VF088 device does remain Software Product mode powered down. With AMS-A1 Manufacturer's BFH, read with SST39VF088 Device D8H, read with Both Software Exit operations equivalent
©2003 Silicon Storage Technology, Inc.
S71227-04-000
11/03
Mbit Multi-Purpose Flash SST39VF088
Preliminary Specifications Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" cause permanent damage device. This stress rating only functional operation device these conditions conditions greater than those defined operational sections this data sheet implied. Exposure absolute maximum stress rating conditions affect device reliability.) Temperature Under Bias -55°C +125°C Storage Temperature -65°C +150°C Voltage Ground Potential -0.5V VDD+0.5V Transient Voltage (<20 Ground Potential -2.0V VDD+2.0V Voltage Ground Potential -0.5V 13.2V Package Power Dissipation Capability 25°C) 1.0W Surface Mount Lead Soldering Temperature Seconds) 240°C Output Short Circuit Current1
Outputs shorted more than second. more than output shorted time.
OPERATING RANGE
Range Commercial Industrial
SST39VF088
2.7-3.6V 2.7-3.6V +70°C
Ambient Temp -40°C +85°C
CONDITIONS
TEST
Input Rise/Fall Time Output Load Figures
©2003 Silicon Storage Technology, Inc.
S71227-04-000
11/03
Mbit Multi-Purpose Flash SST39VF088
Preliminary Specifications TABLE OPERATING CHARACTERISTICS 2.7-3.6V1
Limits Symbol Parameter Power Supply Current Read2 Program Erase VILC VIHC Standby Current Input Leakage Current Output Leakage Current Input Voltage Input Voltage (CMOS) Input High Voltage Input High Voltage (CMOS) Output Voltage Output High Voltage VDD-0.2 0.7VDD VDD-0.3 Units Test Conditions Address input=VILT/VIHT, MHz, VDD=VDD CE#=VIL, OE#=WE#=VIH, I/Os open CE#=WE#=VIL, OE#=VIH CE#=VIHC, VDD=VDD VIN=GND VDD, VDD=VDD VOUT=GND VDD, VDD=VDD VDD=VDD VDD=VDD VDD=VDD VDD=VDD IOL=100 VDD=VDD IOH=-100 VDD=VDD
T5.1 1227
Typical conditions Active Current shown front page data sheet average values 25°C (room temperature), 100% tested. current listed typically less than 2mA/MHz, with VIH. Typical
TABLE RECOMMENDED SYSTEM POWER-UP TIMINGS
Symbol TPU-READ1 TPU-WRITE
Parameter Power-up Read Operation Power-up Program/Erase Operation
Minimum
Units
T6.0 1227
This parameter measured only initial qualification after design process change that could affect this parameter.
TABLE CAPACITANCE
Parameter CI/O
25°C, Mhz, other pins open)
Description Capacitance Input Capacitance
Test Condition VI/O
Maximum
T7.0 1227
CIN1
This parameter measured only initial qualification after design process change that could affect this parameter.
TABLE RELIABILITY CHARACTERISTICS
Symbol NEND1,2 TDR1 ILTH1 Parameter Endurance Data Retention Latch Minimum Specification 10,000 Units Cycles Years Test Method JEDEC Standard A117 JEDEC Standard A103 JEDEC Standard
T8.0 1227
This parameter measured only initial qualification after design process change that could affect this parameter. NEND endurance rating qualified 10,000 cycle minimum whole device. sector- block-level rating would result higher minimum specification.
©2003 Silicon Storage Technology, Inc.
S71227-04-000
11/03
Mbit Multi-Purpose Flash SST39VF088
CHARACTERISTICS
TABLE READ CYCLE TIMING PARAMETERS 2.7-3.6V
SST39VF088-70 Symbol TCLZ1 TOLZ1 TCHZ
SST39VF088-90 Units
T9.0 1227
Parameter Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time Active Output Active Output High High-Z Output High High-Z Output Output Hold from Address Change
TOHZ1
This parameter measured only initial qualification after design process change that could affect this parameter.
TABLE PROGRAM/ERASE CYCLE TIMING PARAMETERS
Symbol TOES TOEH TWPH1 TCPH TSCE
Parameter Byte-Program Time Address Setup Time Address Hold Time Setup Time Hold Time High Setup Time High Hold Time Pulse Width Pulse Width Pulse Width High Pulse Width High Data Setup Time Data Hold Time Software Access Exit Time Sector-Erase Block-Erase Chip-Erase
Units
TIDA1
T10.0 1227
This parameter measured only initial qualification after design process change that could affect this parameter.
©2003 Silicon Storage Technology, Inc.
S71227-04-000
11/03
Mbit Multi-Purpose Flash SST39VF088
ADDRESS AMS-0
TOLZ
TOHZ TCHZ HIGH-Z DATA VALID
DQ7-0
HIGH-Z
TCLZ
DATA VALID
Note: Most significant address SST39VF088
1227 F02.1
FIGURE READ CYCLE TIMING DIAGRAM
INTERNAL PROGRAM OPERATION STARTS ADDRESS AMS-0 DQ7-0 DATA BYTE (ADDR/DATA) TWPH ADDR
1227 F03.2
Note: Most significant address SST39VF088
FIGURE CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
©2003 Silicon Storage Technology, Inc.
S71227-04-000
11/03
Mbit Multi-Purpose Flash SST39VF088
INTERNAL PROGRAM OPERATION STARTS ADDRESS AMS-0 DQ7-0 DATA BYTE (ADDR/DATA) TCPH ADDR
1227 F04.2
Note: Most significant address SST39VF088
FIGURE CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
ADDRESS AMS-0 TOEH TOES
DATA
DATA#
DATA#
DATA
1227 F05.1
Note: Most significant address SST39VF088
FIGURE DATA# POLLING TIMING DIAGRAM
©2003 Silicon Storage Technology, Inc.
S71227-04-000
11/03
Mbit Multi-Purpose Flash SST39VF088
ADDRESS AMS-0 TOEH TOES
READ CYCLES WITH SAME OUTPUTS
1227 F06.1
Note: Most significant address SST39VF088
FIGURE TOGGLE TIMING DIAGRAM
Six-byte Code Chip-Erase ADDRESS AMS-0
TSCE
DQ7-0
1227 F07.2
Note: device also supports controlled Chip-Erase operation. signals interchangeable long minimum timings met. (See Table Most significant address SST39VF088
FIGURE CONTROLLED CHIP-ERASE TIMING DIAGRAM
©2003 Silicon Storage Technology, Inc.
S71227-04-000
11/03
Mbit Multi-Purpose Flash SST39VF088
Six-Byte Code Block-Erase ADDRESS AMS-0
DQ7-0
Note: device also supports controlled Block-Erase operation. signals interchangeable long minimum timings met. (See Table Most significant address SST39VF088
1227 F08.2
FIGURE CONTROLLED BLOCK-ERASE TIMING DIAGRAM
Six-byte Code Sector-Erase ADDRESS AMS-0
DQ7-0
1227 F09.2
Note: device also supports controlled Sector-Erase operation. signals interchangeable long minimum timings met. (See Table Most significant address SST39VF088
FIGURE CONTROLLED SECTOR-ERASE TIMING DIAGRAM
©2003 Silicon Storage Technology, Inc.
S71227-04-000
11/03
Mbit Multi-Purpose Flash SST39VF088
THREE-BYTE SEQUENCE SOFTWARE ENTRY ADDRESS A14-0 0000 0001
TWPH DQ7-0
1227 F10.1
TIDA
Device
Note: Device SST39VF088
FIGURE SOFTWARE ENTRY
READ
©2003 Silicon Storage Technology, Inc.
S71227-04-000
11/03
Mbit Multi-Purpose Flash SST39VF088
VIHT
INPUT
REFERENCE POINTS
OUTPUT
VILT
1227 F12.0
test inputs driven VIHT (0.9 VDD) logic VILT (0.1 VDD) logic "0". Measurement reference points inputs outputs (0.5 VDD) (0.5 VDD). Input rise fall times (10% 90%)
Note: VINPUT Test VOUTPUT Test VIHT VINPUT HIGH Test VILT VINPUT Test
FIGURE INPUT/OUTPUT REFERENCE WAVEFORMS
TESTER
1227 F13.0
FIGURE TEST LOAD EXAMPLE
©2003 Silicon Storage Technology, Inc.
S71227-04-000
11/03
Mbit Multi-Purpose Flash SST39VF088
Start
Load data: Address: AAAH
Load data: Address: 555H
Load data: Address: AAAH
Load Byte Address/Byte Data
Wait Program (TBP, Data# Polling bit, Toggle operation) Program Completed
1227 F14.0
FIGURE BYTE-PROGRAM ALGORITHM
©2003 Silicon Storage Technology, Inc.
S71227-04-000
11/03
Mbit Multi-Purpose Flash SST39VF088
Internal Timer Program/Erase Initiated
Toggle Program/Erase Initiated
Data# Polling Program/Erase Initiated
Wait TBP, TSCE,
Read byte
Read
Program/Erase Completed
Read same byte
true data?
Does match? Program/Erase Completed
Program/Erase Completed
1227 F15.0
FIGURE WAIT OPTIONS
©2003 Silicon Storage Technology, Inc.
S71227-04-000
11/03
Mbit Multi-Purpose Flash SST39VF088
Software Product Entry Command Sequence
Software Exit Command Sequence
Load data: Address: AAAH
Load data: Address:
Load data: Address: 555H
Wait TIDA
Load data: Address: AAAH
Return normal operation
Wait TIDA
1227 F16.1
Read Software
FIGURE SOFTWARE COMMAND FLOWCHARTS
©2003 Silicon Storage Technology, Inc.
S71227-04-000
11/03
Mbit Multi-Purpose Flash SST39VF088
Chip-Erase Command Sequence Load data: Address: AAAH
Sector-Erase Command Sequence Load data: Address: AAAH
Block-Erase Command Sequence Load data: Address: AAAH
Load data: Address: 555H
Load data: Address: 555H
Load data: Address: 555H
Load data: Address: AAAH
Load data: Address: AAAH
Load data: Address: AAAH
Load data: Address: AAAH
Load data: Address: AAAH
Load data: Address: AAAH
Load data: Address: 555H
Load data: Address: 555H
Load data: Address: 555H
Load data: Address: AAAH
Load data: Address:
Load data: Address:
Wait TSCE
Wait
Wait
Chip erased
Sector erased
Block erased
1227 F17.0
FIGURE ERASE COMMAND SEQUENCE
©2003 Silicon Storage Technology, Inc.
S71227-04-000
11/03
Mbit Multi-Purpose Flash SST39VF088
PRODUCT ORDERING INFORMATION
XXXX Environmental Attribute non-Pb Package Modifier leads Package Type TSOP (type 12mm 20mm) Temperature Range Commercial +70°C Industrial -40°C +85°C Minimum Endurance 10,000 cycles Read Access Speed Device Density Mbit Voltage 2.7-3.6V Product Series Multi-Purpose Flash
Valid combinations SST39VF088 SST39VF088-70-4C-EK SST39VF088-70-4C-EKE SST39VF088-90-4C-EK SST39VF088-90-4C-EKE SST39VF088-70-4I-EK SST39VF088-70-4I-EKE SST39VF088-90-4I-EK SST39VF088-90-4I-EKE
Note: Valid combinations those products mass production will mass production. Consult your sales representative confirm availability valid combinations determine availability combinations.
©2003 Silicon Storage Technology, Inc.
S71227-04-000
11/03
Mbit Multi-Purpose Flash SST39VF088
PACKAGING DIAGRAMS
1.05 0.95 Identifier 0.50
12.20 11.80
0.27 0.17
18.50 18.30
0.15 0.05
DETAIL 1.20 max. 0.70 0.50 20.20 19.80 Note: Complies with JEDEC publication MO-142 dimensions, although some dimensions more stringent. linear dimensions millimeters (max/min). Coplanarity: Maximum allowable mold flash 0.15 package ends, 0.25 between leads. 0.70 0.50
48-tsop-EK-8
48-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) 12MM PACKAGE CODE:
20MM
TABLE REVISION HISTORY
Number Description Date 2003 2003 2003 2003 2003
Initial Release Corrected Byte-Program Cycle Data from Table page Corrected Byte-Program Cycle Data from Figures Auto Power feature references removed. (CE# toggled high achieves same effect.) 2004 Data Book
©2003 Silicon Storage Technology, Inc.
S71227-04-000
11/03
Mbit Multi-Purpose Flash SST39VF088
Silicon Storage Technology, Inc. 1171 Sonora Court Sunnyvale, 94086 Telephone 408-735-9110 408-735-9036 www.SuperFlash.com www.sst.com
©2003 Silicon Storage Technology, Inc. S71227-04-000 11/03
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