SINGLE-CHIP 9-PORT 10/100MBPS SWITCH CONTROLLER Rev. July 2004 Tr
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RTL8309SB
SINGLE-CHIP 9-PORT 10/100MBPS SWITCH CONTROLLER
Rev. July 2004 Track JATR-1076-21
RTL8309SB Datasheet
COPYRIGHT
©2004 Realtek Semiconductor Corp. rights reserved. part this document reproduced, transmitted, transcribed, stored retrieval system, translated into language form means without written permission Realtek Semiconductor Corp.
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USING THIS DOCUMENT
This document provides detailed user guidelines achieve best performance when implementing 2-layer board design with RTL8309SB Single-Chip 9-port 10/100Mbps Switch Controller. Though every effort been made assure that this document current accurate, more information have become available subsequent production this guide. that event, please contact your Realtek representative additional information that help development process.
Single-Chip 9-Port 10/100Mbps Switch Controller
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RTL8309SB Datasheet
REVISION HISTORY
Revision Release Date 2003/04/12 2003/05/15 Summary First release. Revised descriptions. Revised description Bi-color LED. Bi-color Reference Schematic figure. 3.3V items electrical characteristics. thermal operating range temperatures. Revised description Dis_VLAN. Revised description Max_Pause_Count. Revised default VLAN membership configuration Disable VLAN function register 16.11. Update default value Differential Service Code Point EEPROM registers. Update default value VLAN membership EERPOM. Update default value Address EEPROM. Update default value Port VLAN Index EEPROM. Revised definition port specification EEPROM registers. Revised definition port specification EEPROM registers. Removed Bypass function EEPROM. Removed Good Link Quality Threshold function EEPROM registers. explanation Indirect Access Data Register 17~20. Removed PHY0~PHY7 REG2 REG3 info. Update number ordering Description Table. Change term "Auto MDIX" "Crossover Detection auto correction". Removed feature IPv6.
2003/12/01
2004/06/10
2004/07/09
Single-Chip 9-Port 10/100Mbps Switch Controller
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RTL8309SB Datasheet
Table Contents
GENERAL DESCRIPTION.1 FEATURES.3 BLOCK DIAGRAM.4 ASSIGNMENTS DESCRIPTIONS 5.1. 5.2. 5.3. 5.4. 5.5. 5.6. 5.7. MEDIA CONNECTION PINS PORT INTERFACE PINS MISCELLANEOUS PINS PORT PINS SERIAL EEPROM PINS STRAPPING PINS.12 POWER PINS
EEPROM REGISTER DESCRIPTION 6.1. 6.1.1. 6.1.2. 6.1.3. 6.1.4. 6.1.5. 6.1.6. 6.1.7. 6.1.8. 6.2. 6.2.1. 6.2.2. 6.2.3. 6.2.4. 6.2.5. 6.2.6. 6.2.7. 6.2.8. GLOBAL CONTROL REGISTERS.17 Global Control Register0 Global Control Register1 Global Control Register2 Global Control Register3 Global Control Register4 Global Control Register5 Global Control Register6 Global Control Register7 PORT CONTROL PINS Port Control 0.20 Port Control 1.20 Port Control 2.21 Port Control 3.21 Port Control 4.21 Address.22 Port Control 0.23 Port Control 1.23 Track JATR-1076-21 Rev.
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RTL8309SB Datasheet
6.2.9. 6.2.10. 6.2.11. 6.2.12. 6.2.13. 6.2.14. 6.2.15. 6.2.16. 6.2.17. 6.2.18. 6.2.19. 6.2.20. 6.2.21. 6.2.22. 6.2.23. 6.2.24. 6.2.25. 6.2.26. 6.2.27. 6.2.28. 6.2.29. 6.3. 6.3.1. 6.3.2. 6.3.3. 6.3.4. 6.4. 6.4.1. 6.4.2. 6.4.3. 6.4.4. 6.4.5. 6.4.6. 6.4.7. 6.4.8. Port Control 2.24 Port Control 3.24 Port Control 4.24 Mask Port Control 0.25 Port Control 1.26 Port Control 2.26 Port Control 3.26 Port Control 4.27 Switch Address Port Control 0.28 Port Control 1.28 Port Control 2.29 Port Control 3.29 Port Control 4.29 Address Port Control 0.30 Port Control 1.30 Port Control 2.31 Port Control 3.31 Port Control 4.31 PORT CONTROL PINS.32 Port Control 0.32 Port Control 1.32 Port Control 2.33 Port Port.33 PORT CONTROL PINS Port Control 0.34 Port Control 1.34 Port Control 2.35 Port Control 3.35 Port Control 4.35 Port Control 0.36 Port Control 1.36 Port Control 2.36
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6.4.9. 6.4.10. 6.4.11. 6.4.12. 6.4.13. 6.4.14. 6.4.15. Port Control 3.37 Port Control 4.37 Port Control 0.38 Port Control 1.38 Port Control 2.38 Port Control 3.39 Port Control 4.39
REGISTERS DESCRIPTION 7.1. 7.1.1. 7.1.2. 7.1.3. 7.1.4. 7.1.5. 7.1.6. 7.1.7. 7.1.8. 7.1.9. 7.1.10. 7.1.11. 7.1.12. 7.1.13. 7.2. 7.2.1. 7.2.2. 7.2.3. 7.2.4. 7.2.5. 7.2.6. 7.2.7. 7.2.8. 7.2.9. 7.2.10. 7.2.11. REGISTERS Register Control.40 Register Status Register Auto-Negotiation Advertisement.42 Register Auto-Negotiation Link Partner Ability.42 Register Auto-Negotiation Expansion.43 Register Global Control 0.43 Register Global Control 1.45 Register Global Control 2.46 Register Global Control 3.46 Register Port Control 0.46 Register Port Control 1.48 Register Port Control VLAN Entry [A].48 Register VLAN Entry REGISTERS Register Control.49 Register Status Register Auto-Negotiation Advertisement.49 Register Auto-Negotiation Link Partner Ability.49 Register Auto-Negotiation Expansion.49 Register 16~17: Priority Address [A].49 Register 18~19: Priority Address [B].49 Register Port Control 0.50 Register Port Control 1.50 Register Port Control VLAN Entry [B].50 Register VLAN Entry
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7.3. 7.3.1. 7.3.2. 7.3.3. 7.3.4. 7.3.5. 7.3.6. 7.3.7. 7.3.8. 7.3.9. 7.3.10. 7.3.11. 7.4. 7.4.1. 7.4.2. 7.4.3. 7.4.4. 7.4.5. 7.4.6. 7.4.7. 7.4.8. 7.4.9. 7.4.10. 7.5. 7.5.1. 7.5.2. 7.5.3. 7.5.4. 7.5.5. 7.5.6. 7.5.7. 7.5.8. 7.5.9. 7.5.10. REGISTERS Register Control.50 Register Status Register Auto-Negotiation Advertisement.50 Register Auto-Negotiation Link Partner Ability.51 Register Auto-Negotiation Expansion.51 Register 16~17: Priority Mask Register 18~19: Priority Mask Register Port Control 0.51 Register Port Control 1.51 Register Port Control VLAN Entry [C].52 Register VLAN Entry [C].52 REGISTERS Register Control.52 Register Status Register Auto-Negotiation Advertisement.52 Register Auto-Negotiation Link Partner Ability.52 Register Auto-Negotiation Expansion.52 Register 16~18: Switch Address Register Port Control 0.53 Register Port Control 1.53 Register Port Control VLAN Entry Register VLAN Entry [D].53 REGISTERS Register Control.54 Register Status Register Auto-Negotiation Advertisement.54 Register Auto-Negotiation Link Partner Ability.54 Register Auto-Negotiation Expansion.54 Register 16~18: Address Register Port Control 0.54 Register Port Control 1.54 Register Port Control VLAN Entry [E].55 Register VLAN Entry
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7.6. 7.6.1. 7.6.2. 7.6.3. 7.6.4. 7.6.5. 7.6.6. 7.6.7. 7.6.8. 7.6.9. 7.6.10. 7.6.11. 7.6.12. 7.6.13. 7.7. 7.7.1. 7.7.2. 7.7.3. 7.7.4. 7.7.5. 7.7.6. 7.7.7. 7.7.8. 7.7.9. 7.8. 7.8.1. 7.8.2. 7.8.3. 7.8.4. 7.8.5. 7.8.6. 7.8.7. 7.8.8. 7.8.9. REGISTERS Register Control.55 Register Status Register Auto-Negotiation Advertisement.55 Register Auto-Negotiation Link Partner Ability.55 Register Auto-Negotiation Expansion.55 Register Port Control 0.56 Register Port Control VLAN Entry [I].57 Register VLAN Entry Register Port Port.57 Register Port Control 0.58 Register Port Control 1.58 Register Port Control VLAN Entry [F].58 Register VLAN Entry REGISTERS Register Control.59 Register Status Register Auto-Negotiation Advertisement.59 Register Auto-Negotiation Link Partner Ability.59 Register Auto-Negotiation Expansion.59 Register Port Control 0.59 Register Port Control 1.59 Register Port Control VLAN Entry Register VLAN Entry [G].60 REGISTERS Register Control.61 Register Status Register Auto-Negotiation Advertisement.61 Register Auto-Negotiation Link Partner Ability.61 Register Auto-Negotiation Expansion.61 Register indirect Access Control.61 Register 17~20: Indirect Access Data.62 Register Port Control 0.62 Register Port Control 1.62
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7.8.10. 7.8.11. 7.9. 7.9.1. 7.9.2. 7.9.3. 7.9.4. 7.9.5. Register Port Control VLAN Entry Register VLAN Entry [H].63 REGISTERS Register Control.63 Register Status Register Auto-Negotiation Advertisement.64 Port NWay Mode Port Force Mode
FUNCTIONAL DESCRIPTION.66 8.1. 8.1.1. 8.1.2. 8.1.3. 8.1.4. 8.1.5. 8.1.6. 8.1.7. 8.1.8. 8.1.9. 8.2. 8.2.1. 8.2.2. 8.2.3. 8.2.4. 8.2.5. 8.2.6. 8.3. 8.3.1. 8.3.2. 8.3.3. 8.3.4. 8.3.5. 8.3.6. 8.3.7. 8.3.8. PHYSICAL LAYER TRANSCEIVER FUNCTIONAL OVERVIEW Auto Negotiation 100Base-Tx Transmit Function 100Base-Tx Receive Function 10Base-T Transmit Function 10Base-T Receive Function Link Monitor.67 Power Saving Mode.67 Power-Down Mode.67 Auto Crossover Detection.68 SWITCH CORE FUNCTIONAL OVERVIEW.68 Address Search, Learning, Aging Flow Control Half Duplex Operation Backpressure Port Status Configuration Port (The Port) ADVANCED FUNCTIONALITY OVERVIEW Port-Based VLAN 802.1Q Tagged-VID based VLAN.76 Operation.77 Insert/Remove VLAN Priority Tag.78 Port (PVID) Port Trunking Address Translation Lookup Table Access.81 Track JATR-1076-21 Rev.
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RTL8309SB Datasheet
8.3.9. 8.3.10. 8.3.11. 8.3.12. 8.3.13. 8.3.14. 8.3.15. 8.3.16. 8.3.17. Serial Management Interface (SMI) Broadcast Storm Control Broadcast In/Out Drop EEPROM Configuration Interface 24LC02 Device Operation.83 Head-of-Line Blocking Port Diagnostic Loopback.85 Loop Detection LEDs (Light Emitting Diodes).87
CHARACTERISTICS 9.1. 9.2. 9.3. 9.4. 9.5. 9.6. ABSOLUTE MAXIMUM RATINGS.90 OPERATING RANGE CHARACTERISTICS CHARACTERISTICS DIGITAL TIMING CHARACTERISTICS THERMAL CHARACTERISTICS SYSTEM APPLICATIONS DESIGN LAYOUT GUIDE.96 MECHANICAL DIMENSIONS NOTES 128-PIN LQFP DIMENSIONS .100
12.1.
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RTL8309SB Datasheet
List Tables
Table Assignments.6 Table Media Connection Pins Table Port Interface Pins Table Miscellaneous Pins.9 Table Port Pins Table Serial EEPROM Pins Table Strapping Pins Table Power Pins Table Global Control Register0 Table Global Control Register1 Table Global Control Register2 Table Global Control Register3 Table Global Control Register4 Table Global Control Register5 Table Global Control Register6 Table Global Control Register7 Table Port Control 0.20 Table Port Control 1.20 Table Port Control 2.21 Table Port Control 3.21 Table Port Control 4.21 Table Address Table Port Control 0.23 Table Port Control 1.23 Table Port Control 2.24 Table Port Control 3.24 Table Port Control 4.24 Table Mask Table Port Control 0.25 Table Port Control 1.26 Table Port Control 2.26 Table Port Control 3.26 Table Port Control 4.27
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RTL8309SB Datasheet
Table Switch Address Table Port Control 0.28 Table Port Control 1.28 Table Port Control 2.29 Table Port Control 3.29 Table Port Control 4.29 Table Address.30 Table Port Control 0.30 Table Port Control 1.30 Table Port Control 2.31 Table Port Control 3.31 Table Port Control 4.31 Table Port Control Table Port Control Table Port Control Table Port Port.33 Table Port Control 0.34 Table Port Control 1.34 Table Port Control 2.35 Table Port Control 3.35 Table Port Control 4.35 Table Port Control 0.36 Table Port Control 1.36 Table Port Control 2.36 Table Port Control 3.37 Table Port Control 4.37 Table Port Control 0.38 Table Port Control 1.38 Table Port Control 2.38 Table Port Control 3.39 Table Port Control 4.39 Table Register Control Table Register Status Table Register Auto-Negotiation Advertisement.42 Table Register Auto-Negotiation Link Partner Ability
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RTL8309SB Datasheet
Table Register Auto-Negotiation Expansion Table Register Global Control Table Register Global Control Table Register Global Control Table Register Global Control Table Register Port Control Table Register Port Control Table Register Port Control VLAN Entry [A].48 Table Register VLAN Entry [A].48 Table Register 16~17: Priority Address Table Register 18~19: Priority Address Table Register Port Control VLAN Entry Table Register VLAN Entry Table Register 16~17: Priority Mask Table Register 18~19: Priority Mask Table Register Port Control VLAN Entry Table Register VLAN Entry Table Register 16~18: Switch Address Table Register Port Control VLAN Entry [D].53 Table Register VLAN Entry [D].53 Table Register 16~18: Address Table Register Port Control VLAN Entry Table Register VLAN Entry Table Register Port Control Table Register Port Control VLAN Entry Table Register VLAN Entry Table Register Port Port Table Register Port Control VLAN Entry Table Register VLAN Entry Table Register Port Control VLAN Entry [G].60 Table Register VLAN Entry [G].60 Table 100. Register Indirect Access Control Table 101. Register 17~20: Indirect Access Data Table 102. Register Port Control VLAN Entry [H].62 Table 103. Register VLAN Entry [H].63
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Table 104. Register Control Table 105. Register Status.64 Table 106. Register Auto-Negotiation Advertisement.64 Table 107. Port NWay Mode Table 108. Port Force Mode Table 109. 802.1Q VLAN Frame Format Table 110. IPv4 Frame Format Table 111. Read/Write Cycles.81 Table 112. Loop Frame Format Table 113. Speed Bi-Color Link/Act Truth Table Table 114. Absolute Maximum Ratings.90 Table 115. Operating Range Table 116. Characteristics Table 117. Characteristics.91 Table 118. Digital Timing Characteristics Table 119. Thermal Operating Range Table 120. Thermal Resistance.95
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RTL8309SB Datasheet
List Figures
Figure Block Diagram Figure Assignments Figure Port Application Figure Port Operating Mode Overview.72 Figure VLAN Grouping Example Figure Tagged Untagged Packet Forwarding When 802.1Q Aware VLAN Disabled Figure Outbound Process Figure Inbound Process.80 Figure Input Drop Output Drop Figure Start Stop Definition Figure Output Acknowledge Figure Random Read Figure Sequential Read.84 Figure Port Loopback Figure Loop Example Figure Floating Pull-down Pins Figure Two-Pin Bi-Color Floating Pull-high.88 Figure Two-Pin Bi-Color Pull-down.88 Figure Bi-Color Reference Schematic Figure Reception Data Timing MII/SNI/SMI Interface Figure Transmission Data Timing MII/SNI/SMI Interface.92 Figure Cross-section 128-Pin PQFP.94 Figure Application Transformer with Connected Central Figure Smith Termination
Single-Chip 9-Port 10/100Mbps Switch Controller
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RTL8309SB Datasheet
General Description
RTL8309SB 128-pin, ultra power, high-performance 8-port Fast Ethernet single-chip switch with extra port specific applications. integrates functions high speed switch system-including SRAM packet buffering, non-blocking switch fabric, address management, general interface, eight 10/100Base-TX transceivers, nine Media Access Controllers-into single 0.18µm CMOS device. provides compatibility with industry standard Ethernet Fast Ethernet devices. Only 25MHz crystal required; EEPROM optional save costs. embedded packet storage SRAM RTL8309SB features superior memory management technology efficiently utilize memory space. integrated 1024-entry look-up table stores address associated information 10-bit direct mapping scheme. table provides read/write access from interface, each entries configured static entry. static entry indicates that this entry controlled external management processor automatic aging learning entry will take place. prevent address mapping collisions, embedded 16entry Content-Addressable Memory (CAM) offers another memory space recording address when mapped entry lookup table occupied. each incoming packet, RTL8309SB searches entries lookup table 16-entry simultaneously. Then obtains correct destination port information determine which output port packet should forwarded aging time RTL8309SB around seconds (this sped 800µs EEPROM configuration). ninth port RTL8309SB implements module without transceiver provide interface connection with external specific applications. This interface mode, mode, mode work with external module routing engine application, module HomePNA application, other physical layer transceivers. order operate correctly, both sides connection must configured same speed, duplex, flow control settings. Four pins used ninth port force link status. This interface should 2.5V 3.3V compatible depending voltage supplied power VDDIO this interface. RTL8309SB capable preventing broadcast storms setting strapping pins upon system reset. When this function enabled, will drop broadcast packets after receiving continuous broadcast packets. This counter will reset every 800ms when RTL8309SB receives non-broadcast packet. RTL8309SB displays port status four indicators (with optional blinking time setting). These LEDs blink diagnostic purposes system reset time. RTL8309SB provides various type
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RTL8309SB Datasheet
combinations different applications. Eight combinations link, activity, speed, duplex, collision, available. Bi-color mode also supported Link/Act LED. RTL8309SB supports standard 802.3x flow control frames full duplex, optional backpressure half duplex. determines when invoke flow control mechanism checking availability system resources, including packet buffers transmitting queues. forwarding ports blocked, system resources unavailable, broadcast frames will dropped according system configuration. RTL8309SB support types dropping methods. input dropping method will forward broadcast packets output ports will drop these packets directly. output dropping method will forward broadcast packets non-blocked ports only. improve real-time multimedia networking applications, RTL8309SB supports four types (Quality Service). These based Port-based priority, 802.1p/Q VLAN priority tag, field IPv4 header, Specific address. Each output port supports weighted ratio highpriority low-priority queues bandwidth requirements different applications. RTL8309SB provides 802.1Q port-based VLAN operation separate logical connectivity from physical connectivity. Each port topology EEPROM upon reset after reset. RTL8309SB also provides options meet special application requirements. first option VLAN function, which used select broadcast frames VLANs only forward frames originating VLAN. second option Leaky VLAN function, which used select send unicast frames other VLANs only forward unicast frames originating VLAN. VLAN tags inserted removed per-port basis. router applications, router want know which input port this packet came from. RTL8309SB supports Port (PVID) each port insert PVID VLAN egress. this function, information carried VLAN will changed PVID. RTL8309SB also provides option admit VLAN tagged packet with specific PVID only. this function enabled, will drop non-tagged packets packets with incorrect PVID. Each physical layer channel consists 4B5B encoder/decoder, Manchester encoder/decoder, transmit output driver, scrambler/descrambler, output wave shaping, filters, digital adaptive equalizer, circuit, restoration circuit clock/data recovery. This integrated chip benefits from power consumption offers advanced functions with flexible configuration small workgroup switch, multimedia, real-time traffic mixed with other data type traffic, other applications.
Single-Chip 9-Port 10/100Mbps Switch Controller
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RTL8309SB Datasheet
Features
Integrates eight 10/100 transceivers nine units 10Base-T 100Base-TX. Embedded SRAM packet storage. On-chip 1024-entry look-up table direct mapping mode. Embedded 16-entry hash collision mapping. Provides read/write access look-up table entries interface. Provides non-blocking wire speed reception transmission. Flow control fully supported: Half-duplex: backpressure flow control. Full-duplex: IEEE 802.3x flow control. Support LEDs per-port various combinations comprehensive applications. Optional loop detection function with indicate existence loop. Supports loopback. LEDs blink upon reset diagnostics. Flexible system configuration strapping pins, EEPROM, interface. Optional crossover detection auto correction plug-and-play. Fully compliant with IEEE 802.3/802.3u. Optional Forwarding/Filtering reserved control frames (DID= 0180C2000003~0180C200000F). Optional Broadcast Input/Output Drop flow control. Optional maximum packet length 1536/1552 Bytes. Supports Power Reduction methods: Power saving mode (automatic cable detection). Power down mode (via register 0.11). Supports function: based Port-based priority 802.1p VLAN DiffServ/TOS field TCP/IP header address. Supports two-level priority queues with various weighting ratios. Queue service rate based weighted round robin algorithm. Optional auto turn Flow Control avoid head-of-line blocking. Supports interface connection external modes. mode router applications. mode router applications. mode HomePNA other applications. Flexible 802.1Q port/tag-based VLAN. Optional 802.1Q tag-VID aware function. Optional VLAN Ingress Admit Control. Optional VLAN Ingress Member filtering. Optional VLAN broadcast packet. Optional Leaky VLAN unicast packet. Optional 802.1P/Q insertion removal per-port basis (egress). 25MHz crystal input. 0.18µm, CMOS technology. 128-pin PQFP package. 1.8V core voltage. Independent power options 2.5V 3.3V interface.
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RTL8309SB Datasheet
Block Diagram
IBREF Waveform Shaping
RX+-[0] TX+-[0]
10Base-T 100Base-TX PHYceiver
10/100
Flow Control TX/RX FIFO
RTL8309SB
RX+-[1] TX+-[1]
10Base-T 100Base-TX PHYceiver
10/100
Flow Control TX/RX FIFO
RX+-[2] TX+-[2]
10Base-T 100Base-TX PHYceiver
10/100
Flow Control TX/RX FIFO
Look-up Table (1024-entries)
Switch Fabric, VLAN, QoS, Trunking
RX+-[3] TX+-[3]
10Base-T 100Base-TX PHYceiver
10/100
Flow Control TX/RX FIFO
Queue Management
RX+-[4] TX+-[4]
10Base-T 100Base-TX PHYceiver
10/100
Flow Control TX/RX FIFO Flow Control TX/RX FIFO
RX+-[5] TX+-[5]
10Base-T 100Base-TX PHYceiver
10/100
Buffer Management
RX+-[6] TX+-[6]
10Base-T 100Base-TX PHYceiver
10/100
Flow Control TX/RX FIFO
Packet Buffer
RX+-[7] TX+-[7]
10Base-T 100Base-TX PHYceiver
10/100
Flow Control TX/RX FIFO EEPROM Interface
Signal
Mode
Inter face
10/100
Flow Control TX/RX FIFO
Control Registers
Mode
Mode Select
P8MODE[1:0]
Figure Block Diagram Single-chip 9-port 10/100Mbps Switch Controller Track JATR-1076-21 Rev.
En_AutoXover/P1_LED[3] En_ANEG/P1_LED[2] En_FCTRL/P1_LED[1] En_BKPRS/P1_LED[0] VDDD VSSD Force_Duplex/P0_LED[3] Force_Speed/P0_LED[2] En_BRD_CTRL/P0_LED[1] En_RST_BLNK/P0_LED[0] EnEEPROM/LoopLED# VDDD VSSD Test VSSPLL VDDPLL Test IBREF VDDA TXON[0] TXOP[0] VSSA RXIP[0] RXIN[0]
Assignments
Single-chip 9-port 10/100Mbps Switch Controller Figure Assignments
RTL8309SB
VDDA VSSA TXON[1] TXOP[1] VSSA RXIP[1] RXIN[1] VDDA RXIN[2] RXIP[2] VSSA TXOP[2] TXON[2] VDDA TXON[3] TXOP[3] VSSA RXIP[3] RXIN[3] VDDA RXIN[4] RXIP[4] VSSA TXOP[4] TXON[4] VDDA TXON[5] TXOP[5] VSSA RXIP[5] RXIN[5] VDDA RXIN[6] RXIP[6] VSSA TXOP[6] TXON[6] VDDA MCOL/PCOL VSSIO VDDIO MTXD[3]/PRXD[3] MTXD[2]/PRXD[2] MTXD[1]/PRXD[1] MTXD[0]/PRXD[0] MTXEN/PRXDV MTXC/PRXC SDA_MDIO SCL_MDC VSSD VDDD MII_LNK_STA# MII_DUP_STA MII_SPD_STA MII_FCTRL_STA RESET# Test VDDA TXON[7] TXOP[7] VSSA RXIP[7] RXIN[7]
P2_LED[0]/MII_MODE[0] P2_LED[1]/MII_MODE[1] P2_LED[2]/LED_MODE[0] P2_LED[3]/LED_MODE[1] P3_LED[0]/LED_MODE[2] P3_LED[1]/Dis_Trunk VSSD VDDD P3_LED[2]/En_Forward P3_LED[3]/En_Defer P4_LED[0]/En_48pass1 P4_LED[1]/En_Agrs_Back P4_LED[2]/Max_Pkt_Len P4_LED[3]/Max_Pause_Count VSSD VDDD P5_LED[0]/Sel_PortPri[0] P5_LED[1]/Sel_PortPri[1] P5_LED[2]/Dis_VLAN_Pri P5_LED[3]/Dis_DS_Pri P6_LED[0]/QWeight[0] P6_LED[1]/QWeight[1] VSSD VDDD P6_LED[2]/Dis_VLAN P6_LED[3]/Dis_LeakyVLAN P7_LED[0]/Dis_ARPVLAN P7_LED[1]/LED_BLNK_TIME P7_LED[2]/Port_LED_LOC P7_LED[3]/Dis_FC_AutoOff VSSD VDDD MRXD[3]/PTXD[3] MRXD[2]/PTXD[2] MRXD[1]/PTXD[1] MRXD[0]/PTXD[0] MRXDV/PTXEN MRXC/PTXC
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RTL8309SB Datasheet
Codes used following tables: stands analog; stands digital, stands input; stands output. Table Assignments Name
VDDA, VSSA, TXON[1], TXOP[1], VSSA, RXIP[1], RXIN[1], VDDA, RXIN[2], RXIP[2], VSSA, TXOP[2], TXON[2], VDDA, TXON[3], TXOP[3], VSSA, RXIP[3], RXIN[3], VDDA, RXIN[4], RXIP[4], VSSA, TXOP[4], TXON[4], VDDA, TXON[5], TXOP[5], VSSA, RXIP[5], RXIN[5], VDDA, RXIN[6], RXIP[6], VSSA, TXOP[6], TXON[6], VDDA, RXIN[7], RXIP[7], VSSA, TXOP[7], TXON[7], VDDA, RESET# MII_FCTRL_STA, MII_SPD_STA, MII_DUP_STA, MII_LNK_STA#, VDDD, VSSD, SCL_MDC, SDA_MDIO, MTXC/PRXC, MTXEN/PRXDV, MTXD[0]/PRXD[0], MTXD[1]/PRXD[1], MTXD[2]/PRXD[2], MTXD[3]/PRXD[3], VDDIO, VSSIO, MCOL/PCOL
Type
AVDD AGND AGND AVDD AGND AVDD AGND AVDD AGND AVDD AGND AVDD AGND AVDD AGND AVDD
Name
MRXC PTXC MRXDV PTXDV, MRXD[0] PTXD[0], MRXD[1] PTXD[1], MRXD[2] PTXD[2], MRXD[3] PTXD[3], VDDD, VSSD, P7_LED[3] Dis_FC_AutoOff, P7_LED[2] Port_LED_LOC, P7_LED[1] LED_BLNK_TIME, P7_LED[0] Dis_ARPVLAN, P6_LED[3] Dis_LeakyVLAN, P6_LED[2] Dis_VLAN, VDDD, VSSD, P6_LED[1] QWeight[1], P6_LED[0] QWeight[0], P5_LED[3] Dis_DS_Pri, P5_LED[2] Dis_VLAN_Pri, P5_LED[1] Sel_PortPri[1], P5_LED[0] Sel_PortPri[0], VDDD, VSSD, P4_LED[3] Max_Pause_Count, P4_LED[2] Max_Pkt_Len, P4_LED[1] En_Agrs_Back, P4_LED[0] En_48pass1, P3_LED[3] En_Defer, P3_LED[2] En_Forward, VDDD, VSSD P3_LED[1] Dis_Trunk, P3_LED[0] LED_MODE[2], P2_LED[3] LED_MODE[1], P2_LED[2] LED_MODE[0], P2_LED[1] MII_MODE[1], P2_LED[0] MII_MODE[0], P1_LED[3] En_AutoXover, P1_LED[2] En_ANEG, P1_LED[1] En_FCTRL P1_LED[0] En_BKPRS, VDDD, VSSD P0_LED[3] Force_Duplex, P0_LED[2] Force_Speed, P0_LED[1] En_BRD_CTRL, P0_LED[0] En_RST_BLNK, LoopLED#,/EnEEPROM VDDD, VSSD, VSSPLL, VDDPLL, IBREF, VDDA, TXON[0], TXOP[0], VSSA, RXIP[0], RXIN[0],
100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127,
Type
DVDD DGND DVDD DGND DVDD DGND DVDD DGND DVDD DGND DVDD DGND AGND AVDD AVDD AGND
DVDD DGND DVDD DGND
Single-chip 9-port 10/100Mbps Switch Controller
Track JATR-1076-21 Rev.
RTL8309SB Datasheet
Descriptions
"Type" codes used following tables: stands analog; stands digital, stands input; stands output, `Ipu' stands input with internal pull-up. Upon reset: defined short time after hardware reset. After reset: defined time after specified "Upon Reset" time.
5.1. Media Connection Pins
Table Media Connection Pins Name RXIP[7:0] RXIN[7:0] 127, 125, Type Description Differential Receive Data Input shared 100Base-TX, 10Base-T connection transformer. Default
TXOP[7:0] TXON[7:0]
Differential Transmit Data Output shared 100Base-TX, 10Base-T connection transformer.
5.2. Port Interface Pins
external device either 2.5V 3.3V compatible depending power supplied VDDIO. input input/output pins listed below implement internal pull-high resistor. external pull-high resistor required these floating input pins reduce power consumption. Table Port Interface Pins Name MRXD[3:0] /PTXD[3:0] Type Description mode, these pins MRXD[3:0], receive data nibble. mode, these pins PTXD[3:0], transmit data nibble. mode, PTXD[0] serial transmit data. mode, this represents MRXDV, receive data valid. mode, this represents PTXEN, transmit enable. mode, this represents PTXEN, transmit enable. Default
MRXDV/PTXEN
Single-chip 9-port 10/100Mbps Switch Controller
Track JATR-1076-21 Rev.
RTL8309SB Datasheet
Name MRXC/PTXC Type Description Default mode, this represents MRXC/MII receive clock (acts input). MII/SNI mode, this represent PTXC/MII transmit clock (acts output). mode, this represents MCOL, collision detect (acts input). MII/SNI mode, this represents PCOL, collision detect (acts output). Output after reset. mode, these pins MTXD[3:0], transmit data MAC. mode, these pins PRXD[3:0], receive data MAC. mode, PRXD[0] serial receive data. PRXD[3:1] unused. mode, this represents MTXEN, transmit enable. mode, this represents PRXDV, receive data valid. mode, this represents PRXDV, receive data valid. mode, this represents MTXC, transmit clock (acts input). MII/SNI mode, this represents MRXC, MII/SNI receive clock (acts output). Input upon reset Select port (9th port) operating mode. 11=Tristate output. 10=MII mode. 01=MII mode. 00=SNI mode. Provides port (9th port) Link Status module MAC/MII PHY/SNI operation mode real time. This sets link status port module real-time. Provides port (9th port) duplex status module MAC/MII PHY/SNI operation mode real time. port operates full duplex mode port operates half duplex mode Provides port (9th port) speed status module MAC/MII PHY/SNI operation mode real time. port operates 100Mbps speed port operates 10Mbps speed application outlined below, this should left floating: HomePNA (MII mode), speed determined from HomePNA running 1Mbps. mode, speed fixed 10MHz clock rate. Provides port (9th port) flow control status module MAC/MII PHY/SNI operation mode real time. port flow control ability port does have flow control ability
MCOL/PCOL
MTXD[3:0] /PRXD[3:0]
MTXEN/PRXDV
MTXC/PRXC
MII_MODE[1:0] /P2_LED[1:0]
101,
MII_LNK_STA#
MII_DUP_STA
MII_SPD_STA
MII_FCTRL_STA
Single-chip 9-port 10/100Mbps Switch Controller
Track JATR-1076-21 Rev.
RTL8309SB Datasheet
5.3. Miscellaneous Pins
Table Miscellaneous Pins Name RESET# Type Description 25MHz crystal input. clock tolerance +-50ppm. 25MHz crystal output. Active reset signal. complete reset function, this must asserted least 10ms. After reset, about 30ms needed RTL8309SB complete internal test function initialization. Note: This Schmitt input pin. Control transmit output waveform Vpp. This should grounded through 2.0K resistor. Connected Floating normal operation. Default
IBREF
116,
5.4. Port Pins
Each port supports four pins status indication. indicated status these four pins changed setting different values strapping LED_MODE[2:0]. Note statuses represented active-low high depending input strapping, except Bi-color Link/Act Bi-color mode, whose polarity depends Bi-color Speed status. Note Those pins dual function pins: output input strapping. Table Port Pins Name P0_LED[0] P1_LED[0] P2_LED[0] P3_LED[0] P4_LED[0] P5_LED[0] P6_LED[0] P7_LED[0] Type 112, 106, Ipu/O 102, Description Output after reset used LED. Mode Speed =100 Mbps, =10Mbps) Mode Activity (Flash=Tx activity) Mode Speed =100 Mbps, =10Mbps) Mode Collision (Flash=Collision) Mode Reserved internal Mode RxAct+10/100 (Flash every 120ms=10Mbps activity, Flash every 43ms 100Mbps activity). Mode Duplex+Collision (On=Full, Off=Half with collision, Flash Collision) Mode Bi-color Speed. Polarity depends Bi-color Link+Activity status. Refer section 8.3.17 LEDs, page detailed information. Default
Single-chip 9-port 10/100Mbps Switch Controller
Track JATR-1076-21 Rev.
RTL8309SB Datasheet
Name P0_LED[1] P1_LED[1] P2_LED[1] P3_LED[1] P4_LED[1] P5_LED[1] P6_LED[1] P7_LED[1] Description Ipu/O Output after reset used LED. Mode Duplex+Collision (On=Full, Off=Half with collision, Flash Collision) Mode Speed =100 Mbps, =10Mbps) Mode Duplex (On=Full, Off=Half) Mode Duplex (On=Full, Off=Half) Mode Duplex+Collision (On=Full, Off=Half with collision, Flash Collision) Mode TxAct+10/100 (Flash every 120ms 10Mbps activity, Flash every 43ms 100Mbps activity) Mode 10Link+Act (On=Link 10Mbps, Off=No link 10Mbps, Flash=10Mbps activity) Mode Duplex+Collision (On=Full, Off=Half with collision, Flash Collision) 110, 104, Ipu/O Output after reset used LED. Mode Link+Act (On=Link, Off=No link, Flash=Tx activity) 100, Mode Link (On=Link, Off=No link) Mode Link+Act (On=Link, Off=No link, Flash=Tx activity) Mode Link+Act+Speed (On=Link, Off=No link, Flash every 120ms=10Mbps activity, flash every 43ms=100Mbps) Mode Link+Act+Speed (On=Link, Off=No link, Flash every 120ms=10Mbps activity, flash every 43ms=100Mbps) Mode Link (On=Link, Off=No link) Mode 100Link+Act (On=Link 100Mbps, Off=No link 100Mbps, Flash=100Mbps activity) Mode Bi-color Speed. Polarity depends Bi-color Link+Activity status. Refer section 8.3.17 LEDs, page detailed information. 109, 103, Ipu/O Output after reset used LED. Mode Reserved internal Mode Reserved internal Mode Reserved internal Mode Reserved internal Mode 10/100 =100 Mbps, =10Mbps) Mode Reserved internal Mode Reserved internal Mode Reserved internal Input upon reset Select display mode upon reset. LED_MODE[2:0]=111 Mode Speed, Duplex+Collision, Link+Act, Reserved LED_MODE[2:0]=110 Mode Activity, Speed, Link, Reserved LED_MODE[2:0]=101 Mode Speed, Duplex, Link+Act, Reserved LED_MODE[2:0]=100 Mode Collision, Duplex, Link+Act+Speed, Reserved LED_MODE[2:0]=011 Mode Reserved, Duplex+Collision, Link+Act+Speed, 10/100 LED_MODE[2:0]=010 Mode RxAct+10/100, TxAct+10/100, Link, Reserved LED_MODE[2:0]=001 Mode Duplex+Collision, 10Link+Act, 100Link+Act, Reserved. LEDM_ODE[2:0]=000 Mode Bi-color Speed, Duplex+Collision, Bi-color Link+Act, Reserved 111, 105, 101, Type Default
P0_LED[2] P1_LED[2] P2_LED[2] P3_LED[2] P4_LED[2] P5_LED[2] P6_LED[2] P7_LED[2]
P0_LED[3] P1_LED[3] P2_LED[3] P3_LED[3] P4_LED[3] P5_LED[3] P6_LED[3] P7_LED[3] LED_MODE[2] /P3_LED[0] LED_MODE[1] /P2_LED[3] LED_MODE[0] /P2_LED[2]
Single-chip 9-port 10/100Mbps Switch Controller
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RTL8309SB Datasheet
Name Port_LED_LOC /P7_LED[2] Description Ipu/O Input upon reset port location reversed. designs where LEDs placed opposite side phone jack Port LEDs assigned pins 109~112 Port LEDs assigned pins 103~106 Port LEDs assigned pins 99~102 Port LEDs assigned pins Port LEDs assigned pins 89~92 Port LEDs assigned pins 83~86 Port LEDs assigned pins Port LEDs assigned pins 73~76 Suitable designs where LEDs placed same side phone jack Port LEDs assigned pins 73~76 Port LEDs assigned pins Port LEDs assigned pins 83~86 Port LEDs assigned pins 89~92 Port LEDs assigned pins Port LEDs assigned pins 99~102 Port LEDs assigned pins 103~106 Port LEDs assigned pins 109~112 Ipu/O Output after reset LoopLED# used LED. Loop detection enabled, this indicates whether Network loop detected not. Otherwise, this function. Note: statuses represented active-low high depending input strapping. Input=1: Output 0=Network loop detected. 1=No loop. Input=0: Output 1=Network loop detected. loop. Type Default
LoopLED# /EnEEPROM
5.5. Serial EEPROM Pins
Table Serial EEPROM Pins Name EnEEPROM /LoopLED# SCL_MDC Type Ipu/O Description Input upon reset Enable loading serial EEPROM upon reset. Enable Serial EEPROM load upon reset Disable Serial EEPROM load upon reset EEPROM Serial Clock MDC. This three state when RESET#=0. When RTL8309SB detects EEPROM connected this becomes (output) load serial EEPROM upon reset. Then changes (input) after reset. this case, this should pulled high (VDDIO 2.5V/3.3V) external register. When RTL8309SB does detect EEPROM connected this (input). this case, needs external pull-high resistor, unless floated. Default
Single-chip 9-port 10/100Mbps Switch Controller
Track JATR-1076-21 Rev.
RTL8309SB Datasheet
Name SDA_MDIO Type Description EEPROM Serial Data Input/Output MDIO. This three state when RESET#=0. When RTL8309SB detects EEPROM connected this becomes (input/output) load serial EEPROM upon reset. changes MDIO (input/output) after reset. When RTL8309SB does detect EEPROM connected this MDIO (input/output). should pulled high external resistor. Default
5.6. Strapping Pins
Note: strapping pins dual function pins: output input strapping. table below covers strapping only. Port Pins, page settings. Table Strapping Pins Name En_ANEG /P1_LED[2] Type
Description Input upon reset Enable Auto-negotiation function. Enable auto-negotiation function (NWay mode) register 0.12 Disable auto-negotiation function (force mode) deselect register 0.12 Output after reset used LED. Input upon reset Enable flow control ability full duplex mode. NWay mode, this sets register 4.10, flow control function finally enabled based auto negotiation result. force mode, this will always enable flow control function Disable flow control function Output after reset used LED. Input upon reset Enable backpressure ability half duplex mode. Enable backpressure Disable backpressure Output after reset used LED. Force duplex mode. This sets Reg.0.8 influences contents Reg.4. Force full duplex auto-negotiation disabled Force half duplex auto-negotiation disabled Output after reset used LED. Force operating speed. This sets Reg.0.13 influences contents Reg.4. Force 100Mbps speed auto-negotiation disabled Force 10Mbps speed auto-negotiation disabled Output after reset used LED.
Default
En_FCTRL /P1_LED[1]
En_BKPRS /P1_LED[0]
Force_Duplex /P0_LED[3]
Force_Speed /P0_LED[2]
Single-chip 9-port 10/100Mbps Switch Controller
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RTL8309SB Datasheet
Name En_BRD_CTRL /P0_LED[1] Type
Description Input upon reset Disable Broadcast Storm Control. Disable Broadcast Storm Control
Enable Broadcast Storm Control
Default
En_RST_BLNK /P0_LED[0]
Output after reset used LED. Input upon reset Enable blinking LEDs upon reset. Enable power-on blinking diagnosis Disable power-on blinking Output after reset used LED. Input upon reset Enable Auto crossover detection. Enable auto crossover detection Disable auto crossover detection. only Output after reset used LED. Disable auto turn flow control ability. Disable Enable auto turn flow control ability priority queue seconds whenever port receives high priority frame. flow control ability will re-enabled this port does receive another high priority frame during this second duration Output after reset used LED. Input upon reset Enable forwarding 802.1D specified reserved group address frames. Forward reserved control packets with DID=01-80-C2-00-00-03 01-80-C2-00-00-0F Filter reserved control packets with DID=01-80-C2-00-00-03 01-80-C2-00-00-0F Output after reset used LED. Input upon reset Enable carrier sense defering function. Enable carrier sense deferring function half duplex backpressure Disable carrier sense deferring function half duplex backpressure Output after reset used LED. Enable pass mechanism. pass Continuously collides input packets then passes packet retain system resources avoid repeater partition when buffer full Continuously collides input packets avoid packet loss when buffer full Output after reset used LED. Input upon reset Enable aggressive back-off mechanism. Enable more aggressive back-off mechanism half duplex mode performance enhancement. back-off limitation will become this mode (default Disable aggressive back-off mechanism half duplex mode Output after reset used LED.
En_AutoXover /P1_LED[3]
Dis_FC_AtuoOff /P7_LED[3]
En_Forward /P3_LED[2]
En_Defer /P3_LED[3]
En_48pass1 /P4_LED[0]
En_Agrs_Back /P4_LED[1]
Single-chip 9-port 10/100Mbps Switch Controller
Track JATR-1076-21 Rev.
RTL8309SB Datasheet
Name Max_Pkt_Len /P4_LED[2] Type
Description Input upon reset Select maximum frame length. 1536 bytes 1552 bytes Output after reset used LED. Input upon reset Select Pause frame count during congested event. Generates maximum pause frames, even congestion still exists Continuously generates pause frames until congestion resolved Output after reset used LED. Disable Port Trunking function. Disable port trunking function Port port combined trunk Output after reset used LED. Input upon reset Select high priority port port-based priority QoS. Disable port-based priority function Select port high priority port Select port high priority port Select port high priority port Output after reset used LED. Input upon reset Disable 802.1p VLAN priority based QoS. Disable 802.1p priority classification ingress packets each port Enable 802.1p priority classification ingress packets each port. User priority field VLAN greater equal will considered high priority packet Output after reset used LED. Input upon reset Disable Diffserv priority based QoS. Disable diffserv priority classification ingress packets each port Enable diffserv priority classification ingress packets each port Output after reset used LED. Input upon reset Weighted round robin ratio priority queue. frame service ratio between high priority queue priority queue 11=16:1 10=Always high priority queue first 01=8:1 00=4:1 Output after reset used LED.
Default
Max_Pause_Count /P4_LED[3]
Dis_Trunk /P3_LED[1]
Sel_PortPri[1:0] /P5_LED[1:0]
Dis_VLAN_Pri /P5_LED[2]
Dis_DS_Pri /P5_LED[3]
QWeight[1:0] /P6_LED[1:0]
Single-chip 9-port 10/100Mbps Switch Controller
Track JATR-1076-21 Rev.
RTL8309SB Datasheet
Name Dis_VLAN /P6_LED[2] Type
Description Input upon reset Disable VLAN. Disable VLAN Enable VLAN. default VLAN membership configuration port overlapped with other ports form individual VLANs. default membership configuration modified setting internal registers interface EEPROM Output after reset used LED. Input upon reset Disable Leaky VLAN. Disable forwarding unicast frames other VLANs Enable forwarding unicast frames other VLANs Note: Broadcast multicast frames adhere VLAN configuration. Output after reset used LED. Input upon reset Disable broadcast VLANs. Disable broadcast broadcast packets VLANs Enable broadcast broadcast packets VLANs Output after reset used LED. Input upon reset Select blinking speed activity collision LED. 43ms then 43ms 120ms then 120ms Note: This only affects LEDs that configured mode Output after reset used LED.
Default
Dis_LeakyVLAN /P6_LED[3]
Dis_ARPVLAN /P7_LED[0]
LED_BLNK_TIME /P7_LED[1]
Single-chip 9-port 10/100Mbps Switch Controller
Track JATR-1076-21 Rev.
RTL8309SB Datasheet
5.7. Power Pins
Table Power Pins Name VDDD 95,107, 108, Type Description 1.8V digital power. Default
VSSD
Digital ground.
VDDIO VSSIO VDDPLL VSSPLL VDDA
2.5/3.3V digital interface. Digital ground interface. 1.8V analog power PLL. 1.8V analog ground PLL. 1.8V analog power (Used transmitters equalizers).
VSSA
Analog ground.
Single-chip 9-port 10/100Mbps Switch Controller
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RTL8309SB Datasheet
EEPROM Register Description
6.1. Global Control Registers
6.1.1. Global Control Register0
Table Global Control Register0 Name EEPROM existence Accept Error disable IEEE 802.3x transmit flow control enable IEEE 802.3x receive flow control enable Broadcast input output drop Aging enable Fast aging enable Byte.bit Description EEPROM does exist EEPROM exists Filter packets normal operation Switch packets including ones Invoke transmit flow control based auto-negotiation result Switch will enable transmit flow control When switch receives pause control frame, ability stop next transmission normal frame until timer expired based auto negotiation result Receive flow control enabled Broadcast input drop selected Broadcast output drop selected Enable aging function switch Disable aging function switch entry learned lookup table will aged updated within 800µs period Disable fast aging function. normal aging time RTL8309SB around 200~300 seconds Enable Address Translation Disable Address Translation Default
Enable Address Translation
6.1.2.
Global Control Register1
Table Global Control Register1 Byte.bit 1.7~1.5 Description Default Mode Speed, Duplex+Collision, Link+Act, Mode Activity, Speed, Link, Mode Speed, Duplex, Link+Act, Mode Collision, Duplex, Link+Act+Speed, Mode SQI, Duplex+Collision, Link+Act+Speed,10/100 Mode RxAct+10/100, TxAct+10/100, Link, Mode Duplex+Collision, 10Link+Act, 100Link+Act, Mode Duplex+Collision, Bi-color Speed, Bi-color Link+Act, Disable VLAN Enable VLAN Disable 802.1Q tagged-VID Aware function tagged-VID VLAN mapping tagged frames still Port-Based VLAN mapping priority-tagged untagged frame
Name Mode
Reserved Disable VLAN Disable 802.1Q aware VLAN
Single-chip 9-port 10/100Mbps Switch Controller
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RTL8309SB Datasheet
Name Disable VLAN member ingress filtering Disable VLAN admit control Byte.bit Description switch will drop received frame ingress port this packet included matched VLAN member switch will drop received frame ingress port this packet included matched VLAN member switch accepts frames received switch will only accept tagged frames will drop untagged frames Default
6.1.3.
Global Control Register2
Table Global Control Register2 Byte.bit Description default DiffServ code point listed below will considered high priority code point DiffServ priority function enabled 101110 001010, 010010, 011010, 100010 Network Control 111000, 110000 default DiffServ code point will considered priority Default
Name Enable default high priority DiffServ code point
Reserved
2.6~2.0
1111
6.1.4.
Global Control Register3
Table Global Control Register3 Byte.bit 3.7~3.5 Description Used classify priority incoming 802.1Q packets when 802.1p priority classification enabled. "User priority" compares against this value. Classify high priority Classify priority Combine port trunking port, trunking enabled strapping pin, Dis_Trunk Combine port trunking port, trunking enabled strapping pin, Dis_Trunk frame service ratio between high priority queue priority queue 11=16:1 10=always high priority queue first 01=8:1 00=4:1 switch will compare both source destination addresses incoming packet against value, address mask [A], classify priority packet switch will compare source destination addresses incoming packet against value, address mask switch will compare both source destination addresses incoming packet against value, address mask [B], classify priority packet switch will compare source destination addresses incoming packet against value, address mask Default
Name 802.1p base priority
Trunking port assignment
Queue weight
3.3~3.2
Disable priority address
Disable priority address
Single-chip 9-port 10/100Mbps Switch Controller
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RTL8309SB Datasheet 6.1.5. Global Control Register4
Table Global Control Register4 Name Enable Differential Service Code Point Reserved Differential Service Code Point Byte.bit Description Differential Service Priority enabled, this specifies differential service code point high priority Differential Service Priority enabled, this specifies differential service code point priority Used specify high priority differential service code point example, these bits "000000", incoming packets with field equal "000000" will considered high priority packets. Default
4.5~4.0
111111
6.1.6.
Global Control Register5
Table Global Control Register5 Byte.bit Description Differential Service Priority enabled, this specifies differential service code point high priority Differential Service Priority enabled, this specifies differential service code point priority Used specify high priority differential service code point example, these bits "111111", incoming packets with field equal "000000" will considered high priority packets. Default
Name Enable Differential Service Code Point Reserved Differential Service Code Point
5.5~5.0
111111
6.1.7.
Global Control Register6
Table Global Control Register6 Byte.bit 6.7~6.0 Description Default 0000 0001
Name Reserved
6.1.8.
Global Control Register7
Table Global Control Register7 Byte.bit Description Enable drop packet when SRAM full pass Disable drop packet when SRAM full pass This will result SRAM 90ppm compensation 65ppm compensation Disable loop detection function Enable loop detection function Lookup table accessible indirect access registers Lookup table accessible Default
Name Enable drop pass Reserved compensation Disable loop detection Reserved Lookup table accessible enable Reserved
7.1~7.0
Single-chip 9-port 10/100Mbps Switch Controller
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RTL8309SB Datasheet
6.2. Port Control Pins
6.2.1. Port Control
Table Port Control Name Reserved Speed Duplex ability Byte.bit 8.7~8.6 8.5~ Description auto negotiation mode: 11=MII Reg0.13=1, 0.8=1, 4.8=1, 4.7=1, 4.6=1, 4.5=1 10=MII Reg0.13=1, 0.8=0, 4.8=0, 4.7=1, 4.6=1, 4.5=1 01=MII Reg0.13=0, 0.8=1, 4.8=0, 4.7=0, 4.6=1, 4.5=1 00=MII Reg0.13=0, 0.8=0, 4.8=0, 4.7=0, 4.6=0, 4.5=1 Force mode: 11=MII Reg0.13=1, 0.8=1, 4.8=1, 4.7=0, 4.6=0, 4.5=0 10=MII Reg0.13=1, 0.8=0, 4.8=0, 4.7=1, 4.6=0, 4.5=0 01=MII Reg0.13=0, 0.8=1, 4.8=0, 4.7=0, 4.6=1, 4.5=0 00=MII Reg0.13=0, 0.8=0, 4.8=0, 4.7=0, 4.6=0, 4.5=1 Reserved Backpressure enable VLAN insertion removal 8.1~8.0 Enable port half duplex backpressure Disable port half duplex backpressure 11=Do insert remove VLAN tags to/from packet. 10=Insert PVID non-tagged packets. 01=Remove from tagged packets. 00=Replace with PVID tagged packets insert PVID non-tagged packets. Default
6.2.2.
Port Control
Table Port Control Byte.bit 9.7~9.6 Description Perform `local loopback', i.e. loop back MAC's back Normal operation switch will replace NULL with port bits) replacement NULL received packets tagged, switch will discard packets whose does match ingress port's PVID packets will dropped Disable 802.1p priority classification ingress packets port Enable 802.1p priority classification port Disable Diffserv priority classification ingress packets port Enable Diffserv priority classification Port Disable port priority function Enable port priority function. Ingress packets from port will classified high priority Default
Name Reserved Local loopback Null replacement Discard PVID packets Disable 802.1p priority Disable Diffserv priority Disable portbased priority
Single-chip 9-port 10/100Mbps Switch Controller
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RTL8309SB Datasheet 6.2.3. Port Control
Table Port Control Name Reserved Byte.bit 10.7~ 10.0 Description Default 1111 1000
6.2.4.
Port Control
Table Port Control Byte.bit 11.7~ 11.4 11.3 11.2 11.1 11.0 12.7~ 12.0 VLAN Entry This register along with byte 13.0 forms 9-bit field that specifies which ports members VLAN. destination address look fails, packets associated with this VLAN will forwarded ports specified this field. E.g., 0000 0001 means port this VLAN. Description Default 1111 0000 0001
Name Reserved Transmission enable Reception enable Learning enable Reserved VLAN membership [7:0]
Enable packet transmission port Disable packet transmission port Enable packet reception port Disable packet reception port Enable switch address learning capability Disable switch address learning capability
6.2.5.
Port Control
Table Port Control Byte.bit 13.7~ 13.4 Description port-based VLAN configuration, this register indexes port `Port VLAN Membership', which defined registers `VLAN Membership' "VLAN Membership". Port only communicate within membership. This register also indexes default Port (PVID) each port. PVID used insertion filtering tagged same PVID. Default 0000
Name Port VLAN index [3:0]
Reserved VLAN membership
13.3~ 13.1 13.0
This register along with byte 12.7~12.0 forms 9-bit field that specifies which ports members VLAN. destination address look fails, packets associated with this VLAN will forwarded ports specified this field. E.g., 0000 0001 means port this VLAN. VLAN Entry This register along with byte 15.3~15.0 defines IEEE 802.1Q 12-bit VLAN identifier VLAN
VLAN [7:0] Reserved VLAN [11:8]
14.7~ 14.0 15.7~ 15.4 15.3~ 15.0
0000 0000 1111 0000
This register along with byte 14.7~14.0 defines IEEE 802.1Q 12-bit VLAN identifier VLAN
Single-chip 9-port 10/100Mbps Switch Controller
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RTL8309SB Datasheet 6.2.6.
Name Address [16:23]
Address
Table Address Byte.bit 16.7~ 16.0 Description Address priority address enabled, switch will compare source address incoming packet against value, address mask [A], classify priority packet. Address priority address enabled, switch will compare source address incoming packet against value, address mask [A], classify priority packet. Address priority address enabled, switch will compare source address incoming packet against value, address mask [A], classify priority packet. Address priority address enabled, switch will compare source address incoming packet against value, address mask [A], classify priority packet. Address priority address enabled, switch will compare source address incoming packet against value, address mask [B], classify priority packet. Address priority address enabled, switch will compare source address incoming packet against value, address mask [B], classify priority packet. Address priority address enabled, switch will compare source address incoming packet against value, address mask [B], classify priority packet. Address priority address enabled, switch will compare source address incoming packet against value, address mask [B], classify priority packet. Default 0xff
Address [31:24]
17.7~ 17.0
0xff
Address [7:0]
18.7~ 18.0
0xff
Address [15:8]
19.7~ 19.0
0xff
Address [16:23]
20.7~ 20.0
0xff
Address [31:24]
21.7~ 21.0
0xff
Address [7:0]
22.7~ 22.0
0xff
Address [15:8]
23.7~ 23.0
0xff
Single-chip 9-port 10/100Mbps Switch Controller
Track JATR-1076-21 Rev.
RTL8309SB Datasheet 6.2.7. Port Control
Table Port Control Name Reserved Speed Duplex ability Byte.bit 24.7~ 24.6 24.5~ 24.4 Description Default
auto negotiation mode: 11=MII Reg0.13=1, 0.8=1, 4.8=1, 4.7=1, 4.6=1, 4.5=1 10=MII Reg0.13=1, 0.8=0, 4.8=0, 4.7=1, 4.6=1, 4.5=1 01=MII Reg0.13=0, 0.8=1, 4.8=0, 4.7=0, 4.6=1, 4.5=1 00=MII Reg0.13=0, 0.8=0, 4.8=0, 4.7=0, 4.6=0, 4.5=1 Force mode: 11=MII Reg0.13=1, 0.8=1, 4.8=1, 4.7=0, 4.6=0, 4.5=0 10=MII Reg0.13=1, 0.8=0, 4.8=0, 4.7=1, 4.6=0, 4.5=0 01=MII Reg0.13=0, 0.8=1, 4.8=0, 4.7=0, 4.6=1, 4.5=0 00=MII Reg0.13=0, 0.8=0, 4.8=0, 4.7=0, 4.6=0, 4.5=1
Reserved Backpressure enable VLAN insertion removal
24.3 24.2 24.1~ 24.0
Enable port half duplex backpressure Disable port half duplex backpressure 11=Do insert remove VLAN tags to/from packets. 10=Insert PVID non-tagged packets. 01=Remove from tagged packets. 00=Replace with PVID tagged packets insert PVID non-tagged packets.
6.2.8.
Port Control
Table Port Control Byte.bit Description 25.7 ~25.6 25.5 Perform `local loopback', i.e. loop back MAC's back Normal operation 25.4 switch will replace NULL with port bits) replacement NULL 25.3 received packets tagged, switch will discard packets whose does match ingress port's PVID packets will dropped 25.2 Disable 802.1p priority classification ingress packets port Enable 802.1p priority classification 25.1 Disable Diffserv priority classification ingress packets port Enable Diffserv priority classification 25.0 Disable port priority function Enable port priority function. Ingress packets from port will classified high priority Default
Name Reserved Local loopback Null replacement Discard PVID packets Disable 802.1p priority Disable Diffserv priority Disable portbased priority
Single-chip 9-port 10/100Mbps Switch Controller
Track JATR-1076-21 Rev.
RTL8309SB Datasheet 6.2.9. Port Control
Table Port Control Name Reserved Byte.bit Description 26.7~ 26.0 Default 1111 1000
6.2.10.
Port Control
Table Port Control Default 1111 0000 0010
Byte.bit Description 27.7~ 27.4 Transmission 27.3 Enable packet transmission port enable Disable packet transmission port Reception enable 27.2 Enable packet reception port Disable packet reception port Learning enable 27.1 Enable switch address learning capability Disable switch address learning capability Reserved 27.0 VLAN Entry VLAN 28.7~ This register along with byte 29.0 forms 9-bit field that specifies which membership 28.0 ports members VLAN. destination address look fails, [7:0] packets associated with this VLAN will forwarded ports specified this field. E.g., 0000 0001 means port this VLAN.
Name Reserved
6.2.11.
Port Control
Table Port Control Byte.bit Description 29.7~ port-based VLAN configuration, this register indexes port `Port 29.4 VLAN Membership', which defined registers `VLAN Membership' "VLAN Membership". Port only communicate within membership. This register also indexes default Port (PVID) each port. PVID used insertion filtering tagged same PVID. 29.3~ 29.1 29.0 This register along with byte 28.7~28.0 forms 9-bit field that specifies which ports members VLAN. destination address look fails, packets associated with this VLAN will forwarded ports specified this field. E.g., 0000 0001 means port this VLAN. VLAN Entry 30.7~ This register along with byte 31.3~31.0 defines IEEE 802.1Q 12-bit 30.0 VLAN identifier VLAN 31.7~ 31.4 31.3~ This register along with byte 30.7~30.0 defines IEEE 802.1Q 12-bit 31.0 VLAN identifier VLAN Default 0001
Name Port VLAN index [3:0]
Reserved VLAN membership
VLAN [7:0] Reserved VLAN [11:8]
0000 0001 1111 0000
Single-chip 9-port 10/100Mbps Switch Controller
Track JATR-1076-21 Rev.
RTL8309SB Datasheet 6.2.12.
Name Mask [16:23]
Mask
Table Mask Byte.bit Description 32.7~ 32.0 Mask priority address enabled, switch will compare source address incoming packet against value, address mask [A], classify priority packet. Mask priority address enabled, switch will compare source address incoming packet against value, address mask [A], classify priority packet. Mask priority address enabled, switch will compare source address incoming packet against value, address mask [A], classify priority packet. Mask priority address enabled, switch will compare source address incoming packet against value, address mask [A], classify priority packet. Mask priority address enabled, switch will compare source address incoming packet against value, address mask [B], classify priority packet. Mask priority address enabled, switch will compare source address incoming packet against value, address mask [B], classify priority packet. Mask priority address enabled, switch will compare source address incoming packet against value, address mask [B], classify priority packet. Mask priority address enabled, switch will compare source address incoming packet against value, address mask [B], classify priority packet. Default 0xff
Mask [31:24]
33.7~ 33.0
0xff
Mask [7:0]
34.7~ 34.0
0xff
Mask [15:8]
35.7~ 35.0
0xff
Mask [16:23]
36.7~ 36.0
0xff
Mask [31:24]
37.7~ 37.0
0xff
Mask [7:0]
38.7~ 38.0
0xff
Mask [15:8]
39.7~ 39.0
0xff
6.2.13.
Port Control
Table Port Control Byte.bit Description 40.7 ~40.6 40.5~ auto negotiation mode: 40.4 11=MII Reg0.13=1, 0.8=1, 4.8=1, 4.7=1, 4.6=1, 4.5=1 10=MII Reg0.13=1, 0.8=0, 4.8=0, 4.7=1, 4.6=1, 4.5=1 01=MII Reg0.13=0, 0.8=1, 4.8=0, 4.7=0, 4.6=1, 4.5=1 00=MII Reg0.13=0, 0.8=0, 4.8=0, 4.7=0, 4.6=0, 4.5=1 Force mode: 11=MII Reg0.13=1, 0.8=1, 4.8=1, 4.7=0, 4.6=0, 4.5=0 10=MII Reg0.13=1, 0.8=0, 4.8=0, 4.7=1, 4.6=0, 4.5=0 01=MII Reg0.13=0, 0.8=1, 4.8=0, 4.7=0, 4.6=1, 4.5=0 00=MII Reg0.13=0, 0.8=0, 4.8=0, 4.7=0, 4.6=0, 4.5=1 Default
Name Reserved Speed Duplex ability
Single-chip 9-port 10/100Mbps Switch Controller
Track JATR-1076-21 Rev.
RTL8309SB Datasheet
Name Reserved Backpressure enable VLAN insertion removal Byte.bit Description 40.3 40.2 Enable port half duplex backpressure Disable port half duplex backpressure 40.1~ 11=Do insert remove VLAN tags to/from packets. 40.0 10=Insert PVID non-tagged packets. 01=Remove from tagged packets. 00=Replace with PVID tagged packets insert PVID nontagged packets. Default
6.2.14.
Port Control
Table Port Control Byte.bit Description Default 41.7~ 41.6 41.5 Perform `local loopback', i.e. loop back MAC's back Normal operation 41.4 switch will replace NULL with port bits) replacement NULL 41.3 received packets tagged, switch will discard packets whose does match ingress port's PVID packets will dropped 41.2 Disable 802.1p priority classification ingress packets port Enable 802.1p priority classification 41.1 Disable Diffserv priority classification ingress packets port Enable Diffserv priority classification 41.0 Disable port priority function Enable port priority function. Ingress packets from port will classified high priority
Name Reserved Local loopback Null replacement Discard PVID packets Disable 802.1p priority Disable Diffserv priority Disable portbased priority
6.2.15.
Port Control
Table Port Control Byte.bit Description 42.7~ 42.0 Default 1111 1000
Name Reserved
6.2.16.
Port Control
Table Port Control Default 1111
Byte.bit Description 43.7~ 43.4 Transmission 43.3 Enable packet transmission port enable Disable packet transmission port Reception enable 43.2 Enable packet reception port Disable packet reception port Learning enable 43.1 Enable switch address learning capability Disable switch address learning capability Reserved 43.0
Name Reserved
Single-chip 9-port 10/100Mbps Switch Controller
Track JATR-1076-21 Rev.
RTL8309SB Datasheet
Name VLAN membership [7:0] Byte.bit Description 44.7~ 44.0 VLAN Entry This register along with byte 45.0 forms 9-bit field that specifies which ports members VLAN. destination address look fails, packets associated with this VLAN will forwarded ports specified this field. E.g., 0000 0001 means port this VLAN. Default 0000 0100
6.2.17.
Port Control
Table Port Control Byte.bit Description Default 45.7~ port-based VLAN configuration, this register indexes port `Port 0010 45.4 VLAN Membership', which defined registers `VLAN Membership' "VLAN Membership". Port only communicate within membership. This register also indexes default Port (PVID) each port. PVID used insertion filtering tagged same PVID. 45.3~ 45.1 45.0 This register along with byte 44.7~44.0 forms 9-bit field that specifies which ports members VLAN. destination address look fails, packets associated with this VLAN will forwarded ports specified this field. E.g., 0000 0001 means port this VLAN. VLAN Entry 46.7~ This register along with byte 47.3~47.0 defines IEEE 802.1Q 12-bit 0000 46.0 VLAN identifier VLAN 0010 47.7~ 1111 47.4 47.3~ This register along with byte 46.7~46.0 defines IEEE 802.1Q 12-bit 0000 47.0 VLAN identifier VLAN
Name Port VLAN index [3:0]
Reserved VLAN membership
VLAN [7:0] Reserved VLAN [11:8]
6.2.18.
Switch Address
Switch address used source address pause control frames.
Table Switch Address
Switch Address [47:40] Switch Address [39:32] Switch Address [31:24] Switch Address [23:16] Switch Address [15:8] Switch Address [7:0] 48.7~ 48.0 49.7~ 49.0 50.7~ 50.0 51.7~ 51.0 52.7~ 52.0 53.7~ 53.0 Switch Address Switch Address Byte Switch Address Byte Switch Address Byte Switch Address Byte Switch Address Byte Switch Address Byte 0x52 0x54 0x4C 0x83 0x09 0xB0
Single-chip 9-port 10/100Mbps Switch Controller
Track JATR-1076-21 Rev.
RTL8309SB Datasheet 6.2.19. Port Control
Table Port Control Name Reserved Speed Duplex ability Byte.bit Description 54.7~ 54.6 54.5~ auto negotiation mode: 54.4 11=MII Reg0.13=1, 0.8=1, 4.8=1, 4.7=1, 4.6=1, 4.5=1 10=MII Reg0.13=1, 0.8=0, 4.8=0, 4.7=1, 4.6=1, 4.5=1 01=MII Reg0.13=0, 0.8=1, 4.8=0, 4.7=0, 4.6=1, 4.5=1 00=MII Reg0.13=0, 0.8=0, 4.8=0, 4.7=0, 4.6=0, 4.5=1 Force mode: 11=MII Reg0.13=1, 0.8=1, 4.8=1, 4.7=0, 4.6=0, 4.5=0 10=MII Reg0.13=1, 0.8=0, 4.8=0, 4.7=1, 4.6=0, 4.5=0 01=MII Reg0.13=0, 0.8=1, 4.8=0, 4.7=0, 4.6=1, 4.5=0 00=MII Reg0.13=0, 0.8=0, 4.8=0, 4.7=0, 4.6=0, 4.5=1 Reserved Backpressure enable VLAN insertion removal 54.3 54.2 54.1~ 54.0 Enable port half duplex backpressure. Disable port half duplex backpressure. 11=Do insert remove VLAN tags to/from packets. 10=Insert PVID non-tagged packets. 01=Remove from tagged packets. 00=Replace with PVID tagged packets insert PVID non-tagged packets. Default
6.2.20.
Port Control
Table Port Control Byte.bit Description Default 55.7~ 55.6 55.5 Perform `local loopback', i.e. loop back MAC's back Normal operation 55.4 switch will replace NULL with port bits) replacement NULL 55.3 received packets tagged, switch will discard packets whose does match ingress port's PVID packets will dropped 55.2 Disable 802.1p priority classification ingress packets port Enable 802.1p priority classification 55.1 Disable Diffserv priority classification ingress packets port Enable Diffserv priority classification 55.0 Disable port priority function Enable port priority function. Ingress packets from port will classified high priority
Name Reserved Local loopback Null replacement Discard PVID packets Disable 802.1p priority Disable Diffserv priority Disable portbased priority
Single-chip 9-port 10/100Mbps Switch Controller
Track JATR-1076-21 Rev.
RTL8309SB Datasheet 6.2.21. Port Control
Table Port Control Name Reserved Byte.bit Description 56.7~ 56.0 Default 1111 1000
6.2.22.
Port Control
Table Port Control Byte.bit 57.7~ 57.4 57.3 57.2 57.1 57.0 58.7~ 58.0 VLAN Entry This register along with byte 59.0 forms 9-bit field that specifies which ports members VLAN. destination address look fails, packets associated with this VLAN will forwarded ports specified this field. E.g., 0000 0001 means port this VLAN. Description Default 1111 0000 1000
Name Reserved Transmission enable Reception enable Learning enable Reserved VLAN membership [7:0]
Enable packet transmission port Disable packet transmission port Enable packet reception port Disable packet reception port Enable switch address learning capability Disable switch address learning capability
6.2.23.
Port Control
Table Port Control Byte.bit Description Default 59.7~ port-based VLAN configuration, this register indexes port `Port 0011 59.4 VLAN Membership', which defined registers `VLAN Membership' "VLAN Membership". Port only communicate within membership. This register also indexes default Port (PVID) each port. PVID used insertion filtering tagged same PVID. 59.3~ 59.1 59.0 This register along with byte 58.7~58.0 forms 9-bit field that specifies which ports members VLAN. destination address look fails, packets associated with this VLAN will forwarded ports specified this field. E.g., 0000 0001 means port this VLAN. VLAN Entry 60.7~ This register along with byte 61.3~61.0 defines IEEE 802.1Q 12-bit 0000 60.0 VLAN identifier VLAN 0011 61.7~ 1111 61.4 61.3~ This register along with byte 60.7~60.0 defines IEEE 802.1Q 12-bit 0000 61.0 VLAN identifier VLAN
Name Port VLAN index [3:0]
Reserved VLAN membership
VLAN [7:0] Reserved VLAN [11:8]
Single-chip 9-port 10/100Mbps Switch Controller
Track JATR-1076-21 Rev.
RTL8309SB Datasheet 6.2.24. Address
Table Address Name Address [47:40] Address [39:32] Address [31:24] Address [23:16] Address [15:8] Address [7:0] Byte.bit 62.7~62.0 63.7~63.0 64.7~64.0 65.7~65.0 66.7~66.0 67.7~67.0 Description address byte address byte address byte address byte address byte address byte Default 0x05 0x42 0x2F 0x21 0x91 0x5C
address used source address address translation.
6.2.25.
Port Control
Table Port Control Byte.bit Description 68.7~ 68.6 68.5~ auto negotiation mode: 68.4 11=MII Reg0.13=1, 0.8=1, 4.8=1, 4.7=1, 4.6=1, 4.5=1 10=MII Reg0.13=1, 0.8=0, 4.8=0, 4.7=1, 4.6=1, 4.5=1 01=MII Reg0.13=0, 0.8=1, 4.8=0, 4.7=0, 4.6=1, 4.5=1 00=MII Reg0.13=0, 0.8=0, 4.8=0, 4.7=0, 4.6=0, 4.5=1 Force mode: 11=MII Reg0.13=1, 0.8=1, 4.8=1, 4.7=0, 4.6=0, 4.5=0 10=MII Reg0.13=1, 0.8=0, 4.8=0, 4.7=1, 4.6=0, 4.5=0 01=MII Reg0.13=0, 0.8=1, 4.8=0, 4.7=0, 4.6=1, 4.5=0 00=MII Reg0.13=0, 0.8=0, 4.8=0, 4.7=0, 4.6=0, 4.5=1 Default
Name Reserved Speed Duplex ability
Reserved Backpressure enable VLAN insertion removal
68.3 68.2 68.1~ 68.0
Enable port half duplex backpressure Disable port half duplex backpressure 11=Do insert remove VLAN tags to/from packet. 10=Insert PVID non-tagged packets. 01=Remove from tagged packets. 00=Replace with PVID tagged packets insert PVID non-tagged packets.
6.2.26.
Port Control
Table Port Control Byte.bit Description 69.7~ 68,6 69.5 Perform `local loopback', i.e. loop back MAC's back Normal operation 69.4 switch will replace NULL with port bits) replacement NULL 69.3 received packets tagged, switch will discard packets whose does match ingress port's PVID packets will dropped 69.2 Disable 802.1p priority classification ingress packets port Enable 802.1p priority classification Default
Name Reserved Local loopback Null replacement Discard PVID packets Disable 802.1p priority
Single-chip 9-port 10/100Mbps Switch Controller
Track JATR-1076-21 Rev.
RTL8309SB Datasheet
Name Disable Diffserv priority Disable portbased priority Byte.bit Description 69.1 Disable Diffserv priority classification ingress packets port Enable Diffserv priority classification 69.0 Disable port priority function Enable port priority function. Ingress packets port will classified high priority Default
6.2.27.
Port Control
Table Port Control Byte.bit Description 70.7~ 70.0 Default 1111 1000
Name Reserved
6.2.28.
Port Control
Table Port Control Default 1111 0001 0000
Byte.bit Description 71.7~ 71.4 Transmission 71.3 Enable packet transmission port enable Disable packet transmission port Reception enable 71.2 Enable packet reception port Disable packet reception port Learning enable 71.1 Enable switch address learning capability Disable switch address learning capability Reserved 71.0 VLAN Entry VLAN 72.7~ This register along with byte 73.0 forms 9-bit field that specifies which membership 72.0 ports members VLAN. destination address look fails, Bit[7:0] packets associated with this VLAN will forwarded ports specified this field. E.g., 0000 0001 means port this VLAN.
Name Reserved
6.2.29.
Port Control
Table Port Control Byte.bit Description Default 73.7~ port-based VLAN configuration, this register indexes port `Port 0100 73.4 VLAN Membership', which could defined registers `VLAN Membership' "VLAN Membership". Port only communicate within membership. This register also indexes default Port (PVID) each port. PVID used insertion filtering tagged same PVID. 73.3~ 73.1 73.0 This register along with byte 72.7~72.0 forms 9-bit field that specifies which ports members VLAN. destination address look fails, packets associated with this VLAN will forwarded ports specified this field. E.g., 0000 0001 means port this VLAN.
Name Port VLAN index [3:0]
Reserved VLAN membership Bit[8]
Single-chip 9-port 10/100Mbps Switch Controller
Track JATR-1076-21 Rev.
RTL8309SB Datasheet
Name VLAN [7:0] Reserved VLAN [11:8] Byte.bit Description 74.7~ 74.0 75.7~ 75.4 75.3~ 75.0 VLAN Entry This register along with byte 75.3~75.0 defines IEEE 802.1Q 12-bit VLAN identifier VLAN Default 0000 0100 1111 0000
This register along with byte 74.7~74.0 defines IEEE 802.1Q 12-bit VLAN identifier VLAN
6.3. Port Control Pins
6.3.1. Port Control
Table Port Control Name Reserved VLAN insertion removal Byte.bit Description 76.7~ 76.2 76.1~ 11=Do insert remove VLAN tags to/from packets. 76.0 10=Insert PVID non-tagged packets. 01=Remove from tagged packets. 00=Replace with PVID tagged packets insert PVID non-tagged packets. Default 1111
6.3.2.
Port Control
Table Port Control
Name Byte.bit Description Default Transmission 77.7 Enable packet transmission interface enable Disable packet transmission interface Reception enable 77.6 Enable packet reception interface Disable packet reception interface Learning enable 77.5 Enable switch address learning capability Disable switch address learning capability Enable 77.4 Enable local loop back function. switch will only forward local loopback broadcast packets from input output drop unicast packets from input other ports still forward packets port Disable local loop back function Disable 802.1p 77.3 Disable 802.1p priority classification ingress packets port priority Enable 802.1p priority classification Disable Diffserv 77.2 Disable Diffserv priority classification ingress packets port priority Enable Diffserv priority classification Disable port77.1 Disable port priority function based priority Enable port priority function. Ingress packets from port will classified high priority Reserved 77.0 VLAN Entry VLAN 78.7~ This register along with byte 79.0 forms 9-bit field that specifies which 1111 membership 78.0 ports members VLAN. destination address look fails, 1111 [7:0] packets associated with this VLAN will forwarded ports specified this field. E.g., 0000 0001 means port this VLAN. Single-chip 9-port 10/100Mbps Switch Controller Track JATR-1076-21 Rev.
RTL8309SB Datasheet 6.3.3. Port Control
Table Port Control Name Null replacement Discard PVID packets Byte.bit Description Default 79.7 switch will replace NULL with port bits) replacement NULL 79.6 received packets tagged, switch will discard packets with that does match ingress port default VID, which indexed port "Port-based VLAN index" packets will dropped 79.5 79.4~ port-based VLAN configuration, this register indexes port `Port 1000 79.1 VLAN Membership', which defined registers `VLAN Membership' `VLAN Membership'. Port only communicate within membership. This register also indexes default Port (PVID) each port. PVID used insertion filtering tagged same PVID. 79.0 This register along with byte 78.7~78.0 forms 9-bit field that specifies which ports members VLAN. destination address look fails, packets associated with this VLAN will forwarded ports specified this field. E.g., 0000 0001 means port this VLAN. VLAN Entry 80.7~ This register along with byte 81.3~81.0 defines IEEE 802.1Q 12-bit 0000 80.0 VLAN identifier VLAN 1000 81.7~ 1111 81.4 81.3~ This register along with byte 80.7~80.0 defines IEEE 802.1Q 12-bit 0000 81.0 VLAN identifier VLAN
Reserved Port VLAN index [3:0]
VLAN membership
VLAN [7:0] Reserved VLAN [11:8]
6.3.4.
Port Port
Table Port Port Byte.bit Description 82.7~ Specifies port RTL8309SB. 82.4 1000=MII Port Port 0111=Port Port 0110=Port Port 0101=Port Port 0100=Port Port 0011=Port Port 0010=Port Port 0001=Port Port 0000=Port Port 82.3~ Specifies port RTL8309SB. 82.0 1000=MII Port Port 0111=Port Port 0110=Port Port 0101=Port Port 0100=Port Port 0011=Port Port 0010=Port Port 0001=Port Port 0000=Port Port Default 0111
Name Port
Port
0000
Single-chip 9-port 10/100Mbps Switch Controller
Track JATR-1076-21 Rev.
RTL8309SB Datasheet
6.4. Port Control Pins
6.4.1. Port Control
Table Port Control Name Reserved Speed Duplex ability Byte.bit Description 83.7~ 83.6 83.5~ auto negotiation mode: 83.4 11=MII Reg0.13=1, 0.8=1, 4.8=1, 4.7=1, 4.6=1, 4.5=1 10=MII Reg0.13=1, 0.8=0, 4.8=0, 4.7=1, 4.6=1, 4.5=1 01=MII Reg0.13=0, 0.8=1, 4.8=0, 4.7=0, 4.6=1, 4.5=1 00=MII Reg0.13=0, 0.8=0, 4.8=0, 4.7=0, 4.6=0, 4.5=1 Force mode: 11=MII Reg0.13=1, 0.8=1, 4.8=1, 4.7=0, 4.6=0, 4.5=0 10=MII Reg0.13=1, 0.8=0, 4.8=0, 4.7=1, 4.6=0, 4.5=0 01=MII Reg0.13=0, 0.8=1, 4.8=0, 4.7=0, 4.6=1, 4.5=0 00=MII Reg0.13=0, 0.8=0, 4.8=0, 4.7=0, 4.6=0, 4.5=1 83.3 83.2 Enable port half duplex backpressure Disable port half duplex backpressure 83.1~ 11=Do insert remove VLAN tags to/from packet. 83.0 10=Insert PVID non-tagged packets. 01=Remove from tagged packets. 00=Replace with PVID tagged packets insert PVID non-tagged packets. Default
Reserved Backpressure enable VLAN insertion removal
6.4.2.
Port Control
Table Port Control Byte.bit Description Default 84.7~ 84.6 84.5 Perform `local loopback', i.e. loop back MAC's back Normal operation 84.4 switch will replace NULL with port bits) replacement NULL 84.3 received packets tagged, switch will discard packets whose does match ingress port's PVID packets will dropped 84.2 Disable 802.1p priority classification ingress packets port Enable 802.1p priority classification 84.1 Disable Diffserv priority classification ingress packets port Enable Diffserv priority classification 84.0 Disable port priority function Enable port priority function. Ingress packets from port will classified high priority
Name Reserved Local loopback Null replacement Discard PVID packets Disable 802.1p priority Disable Diffserv priority Disable portbased priority
Single-chip 9-port 10/100Mbps Switch Controller
Track JATR-1076-21 Rev.
RTL8309SB Datasheet 6.4.3. Port Control
Table Port Control Name Reserved Byte.bit Description 85.7~ 85.0 Default 1111 1000
6.4.4.
Port Control
Table Port Control Default 1111 0010 0000
Byte.bit Description 86.7~ 86.4 Transmission 86.3 Enable packet transmission port enable Disable packet transmission port Reception enable 86.2 Enable packet reception port Disable packet reception port Learning enable 86.1 Enable switch address learning capability Disable switch address learning capability Reserved 86.0 VLAN Entry VLAN 87.7~ This register, along with byte 88.0, forms 9-bit field that specifies which membership 87.0 ports members VLAN. destination address look fails, [7:0] packets associated with this VLAN will forwarded ports specified this field. E.g., 0000 0001 means port this VLAN.
Name Reserved
6.4.5.
Port Control
Table Port Control Byte.bit 88.7~88.4 Description Default port-based VLAN configuration, this register indexes port 0101 `Port VLAN Membership', which defined registers `VLAN Membership' `VLAN Membership'. Port only communicate within membership. This register also indexes default Port (PVID) each port. PVID used insertion filtering tagged same PVID. This register along with byte 87.7~87.0 forms 9-bit field that specifies which ports members VLAN. destination address look fails, packets associated with this VLAN will forwarded ports specified this field. E.g., 0000 0001 means port this VLAN. VLAN Entry This register along with byte 90.3~90.0 defines IEEE 802.1Q 120000 VLAN identifier VLAN 0101 1111 This register along with byte 89.7~89.0 defines IEEE 802.1Q 120000 VLAN identifier VLAN
Name Port VLAN index [3:0]
Reserved VLAN membership
88.3~88.1 88.0
VLAN [7:0] Reserved VLAN [11:8]
89.7~89.0 90.7~90.4 90.3~90.0
Single-chip 9-port 10/100Mbps Switch Controller
Track JATR-1076-21 Rev.
RTL8309SB Datasheet 6.4.6. Port Control
Table Port Control Name Reserved Speed Duplex ability Byte.bit 91.7~91.6 91.5~91.4 Description auto negotiation mode: 11=MII Reg0.13=1, 0.8=1, 4.8=1, 4.7=1, 4.6=1, 4.5=1 10=MII Reg0.13=1, 0.8=0, 4.8=0, 4.7=1, 4.6=1, 4.5=1 01=MII Reg0.13=0, 0.8=1, 4.8=0, 4.7=0, 4.6=1, 4.5=1 00=MII Reg0.13=0, 0.8=0, 4.8=0, 4.7=0, 4.6=0, 4.5=1 Force mode: 11=MII Reg0.13=1, 0.8=1, 4.8=1, 4.7=0, 4.6=0, 4.5=0 10=MII Reg0.13=1, 0.8=0, 4.8=0, 4.7=1, 4.6=0, 4.5=0 01=MII Reg0.13=0, 0.8=1, 4.8=0, 4.7=0, 4.6=1, 4.5=0 00=MII Reg0.13=0, 0.8=0, 4.8=0, 4.7=0, 4.6=0, 4.5=1 Reserved Backpressure enable VLAN insertion removal 91.3 91.2 91.1~91.0 Enable port half duplex backpressure Disable port half duplex backpressure 11=Do insert remove VLAN tags to/from packet. 10=Insert PVID non-tagged packets. 01=Remove from tagged packets. 00=Replace with PVID tagged packets insert PVID non-tagged packets. Default
6.4.7.
Port Control
Table Port Control Default
Byte.bit Description 92.7~92.6 92.5 Perform `local loopback', i.e. loop back MAC's back Normal operation Null 92.4 switch will replace NULL with port bits) replacement replacement NULL Discard 92.3 received packets tagged, switch will discard packets PVID packets whose does match ingress port's PVID packets will dropped Disable 802.1p 92.2 Disable 802.1p priority classification ingress packets port priority Enable 802.1p priority classification Disable Diffserv 92.1 Disable Diffserv priority classification ingress packets port priority Enable Diffserv priority classification Disable port-based 92.0 Disable port priority function priority Enable port priority function. Ingress packets from port will classified high priority
Name Reserved Local loopback
6.4.8.
Port Control
Table Port Control Byte.bit Description 93.7~93.0 Default 1111 1000
Name Reserved
Single-chip 9-port 10/100Mbps Switch Controller
Track JATR-1076-21 Rev.
RTL8309SB Datasheet 6.4.9. Port Control
Table Port Control Name Byte.bit Reserved 94.7~94.4 Transmission enable 94.3 Reception enable Learning enable Reserved VLAN membership [7:0] 94.2 94.1 94.0 95.7~95.0 VLAN Entry This register along with byte 96.0 forms 9-bit field that specifies which ports members VLAN. destination address look fails, packets associated with this VLAN will forwarded ports specified this field. E.g., 0000 0001 means port this VLAN. Description Enable packet transmission port Disable packet transmission port Enable packet reception port Disable packet reception port Enable switch address learning capability Disable switch address learning capability Default 1111 0100 0000
6.4.10.
Port Control
Table Port Control Byte.bit 96.7~96.4 Description Default port-based VLAN configuration, this register indexes port 0110 `Port VLAN Membership', which defined registers `VLAN Membership' "VLAN Membership". Port only communicate within membership. This register also indexes default Port (PVID) each port. PVID used insertion filtering tagged same PVID. This register along with byte 95.7~95.0 forms 9-bit field that specifies which ports members VLAN. destination address look fails, packets associated with this VLAN will forwarded ports specified this field. E.g., 0000 0001 means port this VLAN. VLAN Entry This register along with byte 98.3~98.0 defines IEEE 802.1Q 120000 VLAN identifier VLAN 0110 1111 This register along with byte 97.7~97.0 defines IEEE 802.1Q 120000 VLAN identifier VLAN
Name Port VLAN index [3:0]
Reserved VLAN membership
96.3~96.1 96.0
VLAN [7:0] Reserved VLAN [11:8]
97.7~97.0 98.7~98.4 98.3~98.0
Single-chip 9-port 10/100Mbps Switch Controller
Track JATR-1076-21 Rev.
RTL8309SB Datasheet 6.4.11. Port Control
Table Port Control Name Reserved Speed Duplex ability Byte.bit 99.7~99.6 99.5~99.4 Description auto negotiation mode: 11=MII Reg0.13=1, 0.8=1, 4.8=1, 4.7=1, 4.6=1, 4.5=1 10=MII Reg0.13=1, 0.8=0, 4.8=0, 4.7=1, 4.6=1, 4.5=1 01=MII Reg0.13=0, 0.8=1, 4.8=0, 4.7=0, 4.6=1, 4.5=1 00=MII Reg0.13=0, 0.8=0, 4.8=0, 4.7=0, 4.6=0, 4.5=1 Force mode: 11=MII Reg0.13=1, 0.8=1, 4.8=1, 4.7=0, 4.6=0, 4.5=0 10=MII Reg0.13=1, 0.8=0, 4.8=0, 4.7=1, 4.6=0, 4.5=0 01=MII Reg0.13=0, 0.8=1, 4.8=0, 4.7=0, 4.6=1, 4.5=0 00=MII Reg0.13=0, 0.8=0, 4.8=0, 4.7=0, 4.6=0, 4.5=1 Reserved Backpressure enable VLAN insertion removal 99.3 99.2 99.1~99.0 Enable port half duplex backpressure Disable port half duplex backpressure 11=Do insert remove VLAN tags to/from packet. 10=Insert PVID non-tagged packets. 01=Remove from tagged packets. Replace with PVID tagged packets insert PVID non-tagged packets. Default
6.4.12.
Port Control
Table Port Control Byte.bit Description Default 100.7~100.6 100.5 Perform `local loopback', i.e. loop back MAC's back Normal operation 100.4 switch will replace NULL with port bits) replacement NULL 100.3 received packets tagged, switch will discard packets whose does match ingress port's PVID packets will dropped 100.2 Disable 802.1p priority classification ingress packets port Enable 802.1p priority classification 100.1 Disable Diffserv priority classification ingress packets port Enable Diffserv priority classification 100.0 Disable port priority function Enable port priority function. Ingress packets from port will classified high priority
Name Reserved Local loopback Null replacement Discard PVID packets Disable 802.1p priority Disable Diffserv priority Disable port-based priority
6.4.13.
Port Control
Table Port Control Byte.bit Description 101.7~ 101.0 Default 1111 1000
Name Reserved
Single-chip 9-port 10/100Mbps Switch Controller
Track JATR-1076-21 Rev.
RTL8309SB Datasheet 6.4.14. Port Control
Table Port Control Name Reserved Byte.bit Description 102.7~ 102.4 Transmission 102.3 Enable packet transmission port enable Disable packet transmission port Reception enable 102.2 Enable packet reception port Disable packet reception port Learning enable 102.1 Enable switch address learning capability Disable switch address learning capability Reserved 102.0 VLAN Entry VLAN 103.7~ This register along with byte 104.0 forms 9-bit field that specifies which membership 103.0 ports members VLAN. destination address look fails, [7:0] packets associated with this VLAN will forwarded ports specified this field. E.g., 0000 0001 means port this VLAN. Default 1111 1000 0000
6.4.15.
Port Control
Table Port Control Byte.bit Description Default 104.7~ port-based VLAN configuration, this register indexes port `Port 0111 104.4 VLAN Membership', which defined registers `VLAN Membership' "VLAN Membership". Port only communicate within membership. This register also indexes default Port (PVID) each port. PVID used insertion filtering tagged same PVID. 104.3~ 104.1 104.0 This register along with byte 103.7~103.0 forms 9-bit field that specifies which ports members VLAN. destination address look fails, packets associated with this VLAN will forwarded ports specified this field. E.g., 0000 0001 means port this VLAN. VLAN Entry 105.7~ This register along with byte 106.3~106.0 defines IEEE 802.1Q 12-bit 0000 105.0 VLAN identifier VLAN 0111 106.7~ 1111 106.4 106.3~ This register along with byte 105.7~105.0 defines IEEE 802.1Q 12-bit 0000 106.0 VLAN identifier VLAN
Name Port VLAN index [3:0]
Reserved VLAN membership
VLAN [7:0] Reserved VLAN [11:8]
Single-chip 9-port 10/100Mbps Switch Controller
Track JATR-1076-21 Rev.
RTL8309SB Datasheet
Registers Description
Read Only Read/Write Latch until clear Latch High until clear Self Clearing
"Mode" codes used following tables:
7.1. Registers
7.1.1.
Reg.bit 0.15 0.14
Register Control
Table Register Control Name Reset Loopback (digital loopback) Speed Select Mode RW/SC Description reset. This self-clearing. Enable loopback. This will loopback ignore activity cable media Normal operation 100Mbps 10Mbps When NWay enabled, this reflects result autonegotiation (Read only). When NWay disabled, this strap option `Force_Speed' configured through (Read/Write). Enable auto-negotiation process Disable auto-negotiation process This through (Read/Write). Power down. functions will disabled except function Normal operation Electrically isolates from RMII/SMII. still able respond MDC/MDIO Normal operation Restart Auto-Negotiation process Normal operation Full duplex operation Half duplex operation When NWay enabled, this reflects result autonegotiation (Read only). When NWay disabled, this strap option `Force_Duplex' configured through (Read/Write). Default
0.13
0.12
Auto Negotiation Enable Power Down
0.11
En_ANEG strap option
0.10
Isolate
Restart Auto Negotiation Duplex Mode
RW/SC
0.[7:0]
Reserved
Single-chip 9-port 10/100Mbps Switch Controller
Track JATR-1076-21 Rev.
RTL8309SB Datasheet 7.1.2.
Reg.bit 1.15 1.14 1.13 1.12 1.11 1.[10:7]
Register Status
Table Register Status Name 100Base_T4 100Base_TX_FD 100Base_TX_HD 10Base_T_FD 10Base_T_HD Reserved Preamble Suppression Mode Description 100Base-T4 capability 100Base-TX full duplex capable 100Base-TX full duplex capable 100Base-TX half duplex capable 100Base-TX half duplex capable 10Base-TX full duplex capable 10Base-TX full duplex capable 10Base-TX half duplex capable 10Base-TX half duplex capable RTL8309SB will accept management frames with preamble suppressed. RTL8309SB accepts management frames without preamble. minimum preamble bits required first read/write transaction after reset. idle required between management transactions defined IEEE 802.3u specifications. Auto-negotiation process completed. Reg.4, valid this Auto-negotiation process completed Remote fault condition detected remote fault NWay auto-negotiation capable (permanently=1) Link established. link fails, this will until after reading this again Link failed Jabber detect enabled Jabber detect disabled jabber function disabled 100Base-TX operation. Jabber occurs when predefined excessively long packet detected 10Base-T. When duration TXEN exceeds jabber timer (21ms), transmission loopback function disabled starts blinking. After TXEN goes more than transmitter will re-enabled will stop blinking. Jabber detect supported only 10Base-T operation. Extended register capable (permanently=1) Default
Auto-negotiate Complete Remote Fault Auto-Negotiation Ability Link Status
RO/LH RO/LL
Jabber Detect
RO/LH
Extended Capability
Single-chip 9-port 10/100Mbps Switch Controller
Track JATR-1076-21 Rev.
RTL8309SB Datasheet 7.1.3. Register Auto-Negotiation Advertisement
Note: Whenever link ability RTL8309SB reconfigured, auto-negotiation process should executed again allow configuration take effect. Table Register Auto-Negotiation Advertisement Reg.bit 4.15 4.14 4.13 4.[12:11] 4.10 Name Next Page Acknowledge Remote Fault Reserved Pause Mode Description Next Page disabled (Permanently=0) Permanently=0. Advertises that RTL8309SB detected remote fault remote fault detected Advertises that RTL8309SB possesses 802.3x flow control capability flow control capability Technology supported (Permanently=0). 100Base-TX full duplex capable 100Base-TX full duplex capable 100Base-TX half duplex capable 100Base-TX half duplex capable 10Base-TX full duplex capable 10Base-TX full duplex capable 10Base-TX half duplex capable 10Base-TX half duplex capable [00001]=IEEE 802.3. Default En_FCTRL strap option 00001
4.[4:0]
100Base-T4 100Base-TX-FD 100Base-TX 10Base-T-FD 10Base-T Selector Field
7.1.4.
Reg.bit 5.15 5.14
Register Auto-Negotiation Link Partner Ability
Table Register Auto-Negotiation Link Partner Ability Name Next Page Acknowledge Mode Description Link partner desires Next Page transfer Link partner does desire Next Page transfer Link Partner acknowledges reception Fast Link Pulse (FLP) words acknowledged Link Partner Remote Fault indicated Link Partner remote fault indicated Link Partner Flow control supported Link Partner Flow control supported Link Partner 100Base-T4 supported Link Partner 100Base-T4 supported Link Partner 100Base-TX full duplex supported Link Partner 100Base-TX full duplex supported Link Partner Note: auto negotiation disabled this set, Reg0.13 Reg0.8 will after link established. 100Base-TX half duplex supported Link Partner 100Base-TX half duplex supported Link Partner Note: auto negotiation disabled this set, Reg0.13 will Reg0.8 will after link established. Default
5.13 5.[12:11] 5.10
Remote Fault Reserved Pause 100Base-T4 100Base-TX-FD
100Base-TX
Single-chip 9-port 10/100Mbps Switch Controller
Track JATR-1076-21 Rev.
RTL8309SB Datasheet
Reg.bit Name 10Base-T-FD Mode Description 10Base-TX full duplex supported Link Partner 10Base-TX full duplex supported Link Partner Note: auto negotiation disabled this set, Reg0.13 will Reg0.8 will after link established. 10Base-TX half duplex supported Link Partner 10Base-TX half duplex supported Link Partner Note: auto negotiation disabled this set, Reg0.13 Reg0.8 will after link established. [00001]=IEEE802.3. Default
10Base-T
5.[4:0]
Selector Field
00001
7.1.5.
Register Auto-Negotiation Expansion
Table Register Auto-Negotiation Expansion Name Reserved Parallel Detection Fault Link Partner Next Pageable Local Next Pageable Page Received Link Partner AutoNegotiation Able Mode Description fault been detected Parallel Detection function fault been detected Parallel Detection function Link Partner Next Pageable (permanently=0) RTL8309SB Next Pageable RTL8309SB Next Pageable Page been received Page been received NWay enabled, this means: Link Partner Auto-Negotiation able Link Partner Auto-Negotiation able Default
Reg.bit 6.[15:5]
(NWay) (Force)
7.1.6.
Register Global Control
Table Register Global Control Mode Description Mode Speed, Duplex+Collision, Link+Act, Mode Activity, Speed, Link, Mode Speed, Duplex, Link+Act, Mode Collision, Duplex, Link+Act+Speed, Mode SQI, Duplex+Collision, Link+Act+Speed,10/100. Mode RxAct+10/100, TxAct+10/100, Link, Mode Duplex+Collision, 10Link+Act, 100Link+Act, Mode Duplex+Collision, Bi-color Speed, Bi-color Link+Act, SQI. Soft reset. This self-clearing this RTL8309SB will reset registers except registers will load configurations from EEPROM strapping pins. Software reset designed provide convenient users change configuration SMI. After changing register values RTL8309SB (except registers) SMI, external device must execute soft reset order update configuration setting this Default
Reg.bit Name 16.[15:13] Mode
16.12
Software Reset
Single-chip 9-port 10/100Mbps Switch Controller
Track JATR-1076-21 Rev.
RTL8309SB Datasheet
Reg.bit 16.11 Name Disable VLAN Mode Description Disable VLAN Enable VLAN. default VLAN membership configuration internal register port overlapped with other ports form individual VLANs. This default membership configuration modified setting internal registers interface EEPROM. Disable 802.1Q tagged-VID Aware function. RTL8309SB will check tagged received frames perform tagged-VID VLAN mapping. Under this configuration, RTL8309SB only uses port VLAN index register perform Port-Based VLAN mapping Enable Member Filtering function VLAN Ingress Rule. RTL8309SB checks tagged received frames with VIDA[11:0]~VIDH[11:0] index member set, then performs VLAN mapping. RTL8309SB uses tagged-VID VLAN mapping tagged frames still uses port-based VLAN mapping priority-tagged untagged frames switch will drop received frame ingress port this packet included matched VLAN member set. will still forward packet VLAN members specified matched member set. This setting works both port-based tag-based VLAN configurations switch will drop received frame ingress port this packet included matched VLAN member switch accepts frames receives whether tagged untagged switch will only accept tagged frames will drop untagged frames EEPROM does exist (pin EnEEPROM=0 EnEEPROM=1 EEPROM does exist) EEPROM exists (pin EnEEPROM=1 EEPROM exists) Filter packets normal operation Switch packets including ones. This intended debugging purposes only Determines when invoke flow control based auto negotiation results Will enable transmit flow control matter what auto negotiation result When RTL8309SB receives pause control frame, ability stop next transmission normal frame until timer expired based auto negotiation result Will receive flow control matter what auto negotiation result Broadcast input drop selected Broadcast output drop selected Enable aging function Disable aging function. addresses learned lookup table will aged out. table full, last entry table will deleted make room entry Default
16.10
Disable 802.1Q aware VLAN
16.9
Disable VLAN member ingress filtering
16.8
Disable VLAN admit control
16.7
EEPROM existence Accept Error disable IEEE 802.3x transmit flow control enable IEEE 802.3x receive flow control enable
16.6
16.5
16.4
16.3 16.2
Broadcast input output drop Aging enable
Single-chip 9-port 10/100Mbps Switch Controller
Track JATR-1076-21 Rev.
RTL8309SB Datasheet
Reg.bit 16.1 Name Fast aging enable Mode Description Enable fast aging function. entry learned lookup table will aged updated within 800µs period Disable fast aging function Enable Address Translation function Disable Address Translation function Default
16.0
Enable Address Translation
7.1.7.
Register Global Control
Table Register Global Control Mode Description Classifies priority incoming 802.1Q packets, 802.1p priority classification enabled. `User priority' compared against this value. Classify high priority Classify priority Combine port trunking port, trunking enabled strapping `Dis_Trunk' Combine port trunking port, trunking enabled strapping `Dis_Trunk' frame service ratio between high priority queue priority queue 11=16:1 10=always high priority queue first 01=8:1 00=4:1 Compare both source destination address incoming packets against value, address mask [A], classify packet priority compare source destination address incoming packets against value address mask [A]' Compare both source destination address incoming packets against value, address mask [B], classify packet priority compare source destination address incoming packets against value address mask [B]' default DiffServ code point listed below will considered high priority code point DiffServ priority function enabled. 101110 001010, 010010, 011010, 100010 Network Control 111000, 110000 default DiffServ code point will considered priority Default
Reg.bit Name 17.[15:13] 802.1p base priority
17.12
Trunking port assignment
17.[11:10] Queue weight
17.9
Disable priority address
17.8
Disable priority address
17.7
Enable default high priority DiffServ code point
17.[6:0]
Reserved
1111111
Single-chip 9-port 10/100Mbps Switch Controller
Track JATR-1076-21 Rev.
RTL8309SB Datasheet 7.1.8.
Reg.bit 18.15
Register Global Control
Table Register Global Control Name Enable differential service code point Mode Description differential service priority enabled, this specifies differential service code point high priority differential service priority enabled, this specifies differential services code point priority Used specify high priority differential service code point example, these bits 111111, incoming packets with field equal 111111 will considered high priority packets. differential service priority enabled, this specifies differential services code point high priority differential service priority enabled, this specifies differential services code point priority Used specify high priority differential service code point example, these bits 000000, incoming packets with field equal 000000 will considered high priority packets. Default
18.14 Reserved 18.[13:8] Differential service code point
111111
18.7
Enable differential service code point Reserved Differential service code point
18.6 18.[5:0]
111111
7.1.9.
Reg.bit 19.15
Register Global Control
Table Register Global Control Name Enable drop pass Reserved compensation Disable loop detection Lookup table accessible enable Reserved Reserved Mode Description Enable drop packet after SRAM full pass Disable drop packet after SRAM full pass This will result SRAM 90ppm (InterPacketGap) compensation 65ppm (InterPacketGap) compensation Disable loop detection function Enable loop detection function Lookup table accessible indirect access registers Lookup table accessible Default
19.14 19.13 19.12 19.11 19.10 19.[9:0]
1100 0001
7.1.10.
Register Port Control
Table Register Port Control Mode Description Reserved. Perform `local loopback', i.e. loop MAC's back Normal operation switch will replace NULL with port bits) replacement NULL Default
Reg.bit Name 22.[15:14] Reserved 22.13 Local loopback 22.12 Null replacement
Single-chip 9-port 10/100Mbps Switch Controller
Track JATR-1076-21 Rev.
RTL8309SB Datasheet
Reg.bit 22.11 Name Discard PVID packets Mode Description received packets tagged, switch will discard packets with that does match ingress port default VID, which indexed port `Port-based VLAN index' packets will dropped Disable 802.1p priority classification ingress packets port Enable 802.1p priority classification Default
22.10
Disable 802.1p priority Disable Diffserv priority
Dis_VLAN_Pri
22.9
22.8
Disable port-based priority
22.[7:2] 22[1:0]
Reserved VLAN insertion removal
strap option Default Disable Diffserv priority classification ingress packets port Dis_DS_Pri Enable Diffserv priority classification strap option Default Disable port priority function Enable port priority function. Ingress packets from port will Sel_Port_Pri classified high priority strap option Default 1111111 11=Do insert remove VLAN tags to/from packets sent from this port. 10=The switch will VLAN tags packets they tagged. switch will tags packets already tagged. inserted ingress port's `Default tag', which indexed port `Port-based VLAN index'. 01=The switch will remove VLAN tags from packets, they tagged when these packets send from port switch will modify packets received without tags. 00=The switch will remove VLAN tags from packets then tags them. inserted ingress port's `Default tag', which indexed port `Port-based VLAN index'. This replacement processing tagged packets insertion untagged packets.
Single-chip 9-port 10/100Mbps Switch Controller
Track JATR-1076-21 Rev.
RTL8309SB Datasheet 7.1.11. Register Port Control
Table Register Port Control Reg.bit Name 23.[15:12] Reserved 23.11 Transmission enable 23.10 Reception enable 23.9 23.8 23[7:4] Learning enable Loop status Link quality Mode Description Enable packet transmission port Disable packet transmission port Enable packet reception port Disable packet reception port Enable switch address learning capability Disable switch address learning capability loop been detected port loop exists port 4-bit field indicating link quality receive twisted-pair fiber link. 0000: Highest link quality 1111: Lowest link quality Default 1111
23[3:0]
Reserved
1000
7.1.12.
Register Port Control VLAN Entry
Table Register Port Control VLAN Entry Description port-based VLAN configuration, this register indexes port `Port VLAN Membership', which defined registers `VLAN Membership' `VLAN Membership'. Port only communicate within membership. This register also indexes default Port (PVID) each port. PVID used insertion filtering tagged same PVID. This 9-bit field specifies which ports members VLAN destination address look fails, packet associated with this VLAN will broadcast ports specified this field. stands port stands port E.g., 0000 0001 means port this VLAN. Default 0000
Reg.bit Name Mode 24[15:12] Port VLAN index [3:0]
24.[11~9] Reserved 24.[8:0] VLAN Membership [8:0]
0000 0001
7.1.13.
Register VLAN Entry
Table Register VLAN Entry Mode Description Defines IEEE 802.1Q 12-bit VLAN identifier VLAN Default 1111 0000 0000 0000
Reg.bit Name 25.[15:12] Reserved 25[11:0] VLAN
Single-chip 9-port 10/100Mbps Switch Controller
Track JATR-1076-21 Rev.
RTL8309SB Datasheet
7.2. Registers
7.2.1. Register Control
This register same definition Register Control, page
7.2.2.
Register Status
This register same definition Register Status, page
7.2.3.
Register Auto-Negotiation Advertisement
This register same definition Register Auto-Negotiation Advertisement, page
7.2.4.
Register Auto-Negotiation Link Partner Ability
This register same definition Register Auto-Negotiation Link Partner Ability, page
7.2.5.
Register Auto-Negotiation Expansion
This register same definition Register Auto-Negotiation Expansion, page
7.2.6.
Reg.bit
Register 16~17: Priority Address
Table Register 16~17: Priority Address Name Address [31:16] Address [15:0] Mode Description switch will compare both source destination addresses incoming packet against value, address mask [A], classify priority packet. switch will both compare source destination addresses incoming packet against value, address mask [A], classify priority packet. Default 0xFFFF
0xFFFF
7.2.7.
Register 18~19: Priority Address
Table Register 18~19: Priority Address Mode Description switch will compare both source destination addresses incoming packet against value, address mask [B], classify priority packet, priority address enabled. switch will compare both source destination addresses incoming packet against value, address mask [B], classify priority packet, priority address enabled. Default 0xFFFF
Reg.bit Name Address [31:16]
Address [15:0]
0xFFFF
Single-chip 9-port 10/100Mbps Switch Controller
Track JATR-1076-21 Rev.
RTL8309SB Datasheet 7.2.8. Register Port Control
This register same definition Register Port Control page Note: 22.8 Sel_PortPri strap option port Default value 22.8
7.2.9.
Register Port Control
This register same definition Register Port Control page
7.2.10.
Register Port Control VLAN Entry
Table Register Port Control VLAN Entry Description port-based VLAN configuration, this register indexes port `Port VLAN Membership', which could defined registers `VLAN Membership' `VLAN Membership'. Port only communicate within membership. This register also indexes default Port (PVID) each port. PVID used insertion filtering tagged same PVID. This 9-bit field specifies which ports members VLAN destination address look fails, packets associated with this VLAN will forwarded ports specified this field. E.g., 0000 0001 means port this VLAN. Default 0001
Reg.bit Name Mode 24[15~12] Port VLAN index [3:0]
24.[11:9] Reserved 24.[8:0] VLAN Membership [8:0]
0000 0010
7.2.11.
Register VLAN Entry
Table Register VLAN Entry Mode Description Defines IEEE 802.1Q 12-bit VLAN identifier VLAN Default 1111 0000 0000 0001
Reg.bit Name 25.[15:12] Reserved 25[11:0] VLAN
7.3. Registers
7.3.1. Register Control
This register same definition Register Control, page
7.3.2.
Register Status
This register same definition Register Status, page
7.3.3.
Register Auto-Negotiation Advertisement
This register same definition Register Auto-Negotiation Advertisement, page Single-chip 9-port 10/100Mbps Switch Controller Track JATR-1076-21 Rev.
RTL8309SB Datasheet 7.3.4. Register Auto-Negotiation Link Partner Ability
This register same definition Register Auto-Negotiation Link Partner Ability, page
7.3.5.
Register Auto-Negotiation Expansion
This register same definition Register Auto-Negotiation Expansion, page
7.3.6.
Reg.bit
Register 16~17: Priority Mask
Table Register 16~17: Priority Mask Name Mask [31:16] Mask [15:0] Mode Description switch will compare both source destination addresses incoming packet against value, address mask [A], classify priority packet. switch will compare both source destination addresses incoming packet against value, address mask [A], classify priority packet. Default 0xFFFF
0xFFFF
7.3.7.
Reg.bit
Register 18~19: Priority Mask
Table Register 18~19: Priority Mask Name Mask [31:16] Mode Description switch will compare both source destination addresses incoming packet against value, address mask [B], classify priority packet, priority address enabled. switch will compare both source destination addresses incoming packet against value, address mask [B], classify priority packet, priority address enabled. Default 0xFFFF
Mask [15:0]
0xFFFF
7.3.8.
Register Port Control
This register same definition Register Port Control page Note: 22.8 Sel_PortPri strap option port Default value 22.8
7.3.9.
Register Port Control
This register same definition Register Port Control page
Single-chip 9-port 10/100Mbps Switch Controller
Track JATR-1076-21 Rev.
RTL8309SB Datasheet 7.3.10. Register Port Control VLAN Entry
Table Register Port Control VLAN Entry Reg.bit Name 24[15:12] Port VLAN Index [3:0] Mode Description port-based VLAN configuration, this register indexes port `Port VLAN Membership', which defined registers `VLAN Membership' `VLAN Membership'. Port only communicate within membership. This register also indexes default Port (PVID) each port. PVID used insertion filtering tagged same PVID. This bytes reserved used This 9-bit field
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