MICROPROCESSORS USER'S MANUAL Motorola reserves right make change
|
|
|
Top Searches for this datasheet
MC68020 MC68EC020
MICROPROCESSORS USER'S MANUAL
Motorola reserves right make changes without further notice products herein improve reliability, function design. Motorola does assume liability arising application product circuit described herein; neither does convey license under patent rights rights others. Motorola products designed, intended, authorized components systems intended surgical implant into body, other applications intended support sustain life, other application which failure Motorola product could create situation where personal injury death occur. Should Buyer purchase Motorola products such unintended unauthorized application, Buyer shall indemnify hold Motorola officers, employees, subsidiaries, affiliates, distributors harmless against claims, costs, damages, expenses, reasonable attorney fees arising directly indirectly, claim personal injury death associated with such unintended unauthorized use, even such claim alleges that Motorola negligent regarding design manufacture part. Motorola registered trademarks Motorola, Inc. Motorola, Inc. Equal Opportunity/Affirmative Action Employer.
MOTOROLA INC., 1992
PREFACE
M68020 User's Manual describes capabilities, operation, programming MC68020 32-bit, second-generation, enhanced microprocessor MC68EC020 32bit, second-generation, enhanced embedded microprocessor. Throughout this manual, "MC68020/EC020" used when information applies both MC68020 MC68EC020. "MC68020" "MC68EC020" used when information applies only MC68020 MC68EC020, respectively. detailed information MC68020 MC68EC020 instruction set, refer M68000PM/AD, M68000 Family Programmer's Reference Manual. This manual consists following sections: Section Section Section Section Section Section Section Section Section Section Section Appendix Introduction Processing States Signal Description On-Chip Cache Memory Operation Exception Processing Coprocessor Interface Description Instruction Execution Timing Applications Information Electrical Characteristics Ordering Information Mechanical Data Interfacing MC68EC020 Device That Supports Three-Wire Arbitration Protocol NOTE this manual, assert negate used specify forcing signal particular state. particular, assertion assert refer signal that active true; negation negate indicate signal that inactive false. These terms used independently voltage level (high low) that they represent.
MOTOROLA
M68020 USER'S MANUAL
9/29/95
SECTION OVERVIEW
TABLE CONTENTS
Paragraph Number Title Section Introduction 1.5.1 1.5.2 Features .1-2 Programming Model .1-4 Data Types Addressing Modes Overview .1-8 Instruction Overview 1-10 Virtual Memory Virtual Machine Concepts 1-10 Virtual Memory 1-10 Virtual Machine 1-12 Pipelined Architecture .1-12 Cache Memory .1-13 Section Processing States 2.1.1 2.1.2 2.1.3 2.3.1 2.3.2 Privilege Levels Supervisor Privilege Level .2-2 User Privilege Level .2-3 Changing Privilege Level Address Space Types .2-4 Exception Processing. Exception Vectors .2-5 Exception Stack Frame .2-6 Section Signal Description 3.10 3.11
MOTOROLA
Page Number
Signal Index .3-2 Function Code Signals (FC2-FC0) Address (A31-A0, MC68020)(A23-A0, MC68EC020) Data (D31-D0) .3-2 Transfer Size Signals (SIZ1, SIZ0) .3-2 Asynchronous Control Signals .3-4 Interrupt Control Signals.3-5 Arbitration Control Signals Exception Control Signals .3-6 Emulator Support Signal .3-7 Clock (CLK)
M68020 USER'S MANUAL
9/29/95
SECTION OVERVIEW
Rev.1.0
TABLE CONTENTS (Continued)
Paragraph Number 3.12 3.13 Title Page Number
Power Supply Connections Signal Summary. Section On-Chip Cache Memory
4.3.1 4.3.2
On-Chip Cache Organization Operation Cache Reset Cache Control Cache Control Register (CACR) .4-3 Cache Address Register (CAAR) Section Operation
5.1.1 5.1.2 5.1.3 5.1.4 5.1.5 5.1.6 5.1.7 5.2.1 5.2.2 5.2.3 5.2.4 5.2.5 5.2.6 5.2.7 5.3.1 5.3.2 5.3.3 5.4.1 5.4.1.1 5.4.1.2 5.4.1.3 5.4.2 5.4.3 5.5.1
viii
Transfer Signals. Control Signals Address Address Strobe Data Bus. Data Strobe Data Buffer Enable Cycle Termination Signals. Data Transfer Mechanism. Dynamic Sizing Misaligned Operands. 5-14 Effects Dynamic Sizing Operand Misalignment 5-20 Address, Size, Data Relationships 5-21 Cache Interactions 5-22 Operation 5-24 Synchronous Operation with DSACK1/DSACK0 5-24 Data Transfer Cycles .5-25 Read Cycle 5-26 Write Cycle 5-33 Read-Modify-Write Cycle. 5-39 Space Cycles 5-44 Interrupt Acknowledge Cycles .5-45 Interrupt Acknowledge Cycle-Terminated Normally 5-45 Autovector Interrupt Acknowledge Cycle 5-48 Spurious Interrupt Cycle 5-48 Breakpoint Acknowledge Cycle 5-50 Coprocessor Communication Cycles 5-53 Exception Control Cycles. 5-53 Errors 5-55
M68020 USER'S MANUAL MOTOROLA
9/29/95
SECTION OVERVIEW
TABLE CONTENTS (Continued)
Paragraph Number 5.5.2 5.5.3 5.5.4 5.7.1 5.7.1.1 5.7.1.2 5.7.1.3 5.7.1.4 5.7.2 5.7.2.1 5.7.2.2 5.7.2.3 Title Page Number
Retry Operation .5-56 Halt Operation.5-60 Double Fault 5-60 Synchronization.5-62 Arbitration .5-62 MC68020 Arbitration .5-63 Request (MC68020) .5-66 Grant (MC68020) .5-66 Grant Acknowledge (MC68020) .5-66 Arbitration Control (MC68020) .5-67 MC68EC020 Arbitration .5-70 Request (MC68EC020) .5-71 Grant (MC68EC020) .5-71 Arbitration Control (MC68EC020) .5-73 Reset Operation .5-76 Section Exception Processing
6.1.1 6.1.2 6.1.3 6.1.4 6.1.5 6.1.6 6.1.7 6.1.8 6.1.9 6.1.10 6.1.11 6.1.12 6.2.1 6.2.2 6.2.3
Exception Processing Sequence .6-1 Reset Exception.6-4 Error Exception .6-4 Address Error Exception. Instruction Trap Exception .6-6 Illegal Instruction Unimplemented Instruction Exceptions Privilege Violation Exception Trace Exception .6-9 Format Error Exception .6-10 Interrupt Exceptions .6-11 Breakpoint Instruction Exception 6-17 Multiple Exceptions.6-17 Return from Exception .6-19 Fault Recovery .6-21 Special Status Word (SSW).6-21 Using Software Complete Cycles .6-23 Completing Cycles with .6-24 Coprocessor Considerations .6-25 Exception Stack Frame Formats .6-25
MOTOROLA
M68020 USER'S MANUAL
9/29/95
SECTION OVERVIEW
Rev.1.0
TABLE CONTENTS (Continued)
Paragraph Number Title Section Coprocessor Interface Description 7.1.1 7.1.2 7.1.3 7.1.4 7.1.4.1 7.1.4.2 7.1.4.3 7.2.1 7.2.1.1 7.2.1.2 7.2.2 7.2.2.1 7.2.2.1.1 7.2.2.1.2 7.2.2.2 7.2.2.2.1 7.2.2.2.2 7.2.2.3 7.2.2.3.1 7.2.2.3.2 7.2.2.4 7.2.2.4.1 7.2.2.4.2 7.2.3 7.2.3.1 7.2.3.2 7.2.3.2.1 7.2.3.2.2 7.2.3.2.3 7.2.3.2.4 7.2.3.3 7.2.3.3.1 7.2.3.3.2 7.2.3.4 7.2.3.4.1 7.2.3.4.2
Page Number
Introduction .7-1 Interface Features Concurrent Operation Support .7-2 Coprocessor Instruction Format Coprocessor System Interface Coprocessor Classification Processor-Coprocessor Interface Coprocessor Interface Register Selection .7-6 Coprocessor Instruction Types .7-7 Coprocessor General Instructions Format Protocol. Coprocessor Conditional Instructions. 7-10 Branch Coprocessor Condition Instruction .7-12 Format 7-12 Protocol 7-12 Coprocessor Condition Instruction .7-13 Format 7-13 Protocol 7-14 Test Coprocessor Condition, Decrement, Branch Instruction 7-14 Format 7-14 Protocol 7-15 Trap Coprocessor Condition Instruction 7-15 Format 7-15 Protocol 7-16 Coprocessor Context Save Restore Instructions 7-16 Coprocessor Internal State Frames 7-17 Coprocessor Format Words. 7-18 Empty/Reset Format Word 7-18 Not-Ready Format Word .7-19 Invalid Format Word 7-19 Valid Format Word 7-20 Coprocessor Context Save Instruction 7-20 Format 7-20 Protocol 7-21 Coprocessor Context Restore Instruction 7-22 Format 7-22 Protocol 7-23 Coprocessor Interface Register 7-24
M68020 USER'S MANUAL MOTOROLA
9/29/95
SECTION OVERVIEW
TABLE CONTENTS (Continued)
Paragraph Number 7.3.1 7.3.2 7.3.3 7.3.4 7.3.5 7.3.6 7.3.7 7.3.8 7.3.9 7.3.10 7.3.11 7.4.1 7.4.2 7.4.3 7.4.4 7.4.5 7.4.6 7.4.7 7.4.8 7.4.9 7.4.10 7.4.11 7.4.12 7.4.13 7.4.14 7.4.15 7.4.16 7.4.17 7.4.18 7.4.19 7.4.20 7.5.1 7.5.1.1 7.5.1.2 7.5.1.3 7.5.1.4 7.5.1.5 7.5.2 7.5.2.1 7.5.2.2 Title Page Number
Response 7-24 Control 7-24 Save 7-25 Restore .7-25 Operation Word .7-25 Command .7-25 Condition .7-26 Operand 7-26 Register Select .7-27 Instruction Address .7-27 Operand Address .7-27 Coprocessor Response Primitives .7-27 ScanPC .7-28 Coprocessor Response Primitive General Format 7-28 Busy Primitive .7-30 Null Primitive 7-31 Supervisor Check Primitive .7-33 Transfer Operation Word Primitive .7-33 Transfer from Instruction Stream Primitive .7-34 Evaluate Transfer Effective Address Primitive 7-35 Evaluate Effective Address Transfer Data Primitive 7-35 Write Previously Evaluated Effective Address Primitive 7-37 Take Address Transfer Data Primitive.7-39 Transfer to/from Stack Primitive .7-40 Transfer Single Main Processor Register Primitive 7-40 Transfer Main Processor Control Register Primitive 7-41 Transfer Multiple Main Processor Registers Primitive 7-42 Transfer Multiple Coprocessor Registers Primitive .7-42 Transfer Status Register ScanPC Primitive. 7-44 Take Preinstruction Exception Primitive .7-45 Take Midinstruction Exception Primitive .7-47 Take Postinstruction Exception Primitive .7-48 Exceptions .7-49 Coprocessor-Detected Exceptions 7-49 Coprocessor-Detected Protocol Violations .7-50 Coprocessor-Detected Illegal Command Condition Words 7-51 Coprocessor Data-Processing-Related Exceptions .7-51 Coprocessor System-Related Exceptions .7-51 Format Errors .7-52 Main-Processor-Detected Exceptions 7-52 Protocol Violations 7-52 F-Line Emulator Exceptions .7-54
MOTOROLA
M68020 USER'S MANUAL
9/29/95
SECTION OVERVIEW
Rev.1.0
TABLE CONTENTS (Continued)
Paragraph Number 7.5.2.3 7.5.2.4 7.5.2.5 7.5.2.6 7.5.2.7 7.5.2.8 7.5.3 Title Page Number
Privilege Violations. 7-55 cpTRAPcc Instruction Traps 7-55 Trace Exceptions 7-55 Interrupts .7-56 Format Errors 7-57 Address Errors. 7-57 Coprocessor Reset .7-58 Coprocessor Summary 7-58 Section Instruction Execution Timing
8.1.1 8.1.2 8.1.3 8.1.4 8.1.5 8.2.1 8.2.2 8.2.3 8.2.4 8.2.5 8.2.6 8.2.7 8.2.8 8.2.9 8.2.10 8.2.11 8.2.12 8.2.13 8.2.14 8.2.15 8.2.16 8.2.17 8.2.18
Timing Estimation Factors Instruction Cache Prefetch Operand Misalignment Bus/Sequencer Concurrency. Instruction Execution Overlap Instruction Stream Timing Examples .8-4 Instruction Timing Tables Fetch Effective Address 8-13 Fetch Immediate Effective Address. 8-14 Calculate Effective Address 8-16 Calculate Immediate Effective Address. 8-17 Jump Effective Address. 8-19 MOVE Instruction 8-20 Special-Purpose MOVE Instruction 8-29 Arithmetic/Logical Instructions. 8-30 Immediate Arithmetic/Logical Instructions 8-31 Binary-Coded Decimal Operations 8-32 Single-Operand Instructions 8-33 Shift/Rotate Instructions 8-34 Manipulation Instructions 8-35 Field Manipulation Instructions. 8-36 Conditional Branch Instructions. 8-37 Control Instructions.8-38 Exception-Related Instructions .8-39 Save Restore Operations 8-40 Section Applications Information
Floating-Point Units .9-1 Byte Select Logic MC68020/EC020. Power Ground Considerations
M68020 USER'S MANUAL MOTOROLA
9/29/95
SECTION OVERVIEW
TABLE CONTENTS (Concluded)
Paragraph Number 9.7.1 9.7.2 9.8.1 9.8.2 Title Page Number
Clock Driver. 9-10 Memory Interface 9-11 Access Time Calculations .9-12 Module Support .9-14 Module Descriptor.9-14 Module Stack Frame 9-16 Access Levels .9-17 Module Call. 9-18 Module Return 9-19 Section Electrical Characteristics
10.1 10.2 10.2.1 10.2.2 10.3
Maximum Ratings 10-1 Thermal Considerations 10-1 MC68020 Thermal Characteristics Electrical Characteristics .10-2 MC68EC020 Thermal Characteristics Electrical Characteristics .10-4 Electrical Characteristics 10-5 Section Ordering Information Mechanical Data
11.1 11.1.1 11.1.2 11.2 11.2.1 11.2.2 11.2.3 11.2.4 11.2.5 11.2.6 11.2.7 11.2.8 11.2.9 11.2.10
Standard Ordering Information. 11-1 Standard MC68020 Ordering Information.11-1 Standard MC68EC020 Ordering Information 11-1 Assignments Package Dimensions 11-2 MC68020 Suffix-Pin Assignment .11-2 MC68020 Suffix-Package Dimensions 11-3 MC68020 Suffix-Package Dimensions. 11-4 MC68020 Suffix-Pin Assignment 11-5 MC68020 Suffix-Package Dimensions 11-6 MC68020 Suffix-Package Dimensions .11-7 MC68EC020 Suffix-Pin Assignment.11-8 MC68EC020 Suffix-Package Dimensions .11-9 MC68EC020 Suffix-Pin Assignment.11-10 MC68EC020 Suffix-Package Dimensions .11-11 Appendix Interfacing MC68EC020 Device That Supports Three-Wire Arbitration Protocol
MOTOROLA
M68020 USER'S MANUAL
xiii
9/29/95
SECTION OVERVIEW
Rev.1.0
LIST ILLUSTRATIONS
Figure Number 5-10 5-11 5-12 5-13 5-14 5-15 5-16 5-17 5-18 5-19 5-20 5-21 5-22 5-23
Title
Page Number
MC68020/EC020 Block Diagram User Programming Model Supervisor Programming Model Supplement Status Register (SR) Instruction Pipe .1-13 General Exception Stack Frame Functional Signal Groups .3-1 MC68020/EC020 On-Chip Cache Organization Cache Control Register .4-3 Cache Address Register Relationship between External Internal Signals. Input Sample Window Internal Operand Representation .5-6 MC68020/EC020 Interface Various Port Sizes Long-Word Operand Write Word Port Example. 5-10 Long-Word Operand Write Word Port Timing 5-11 Word Operand Write Byte Port Example 5-12 Word Operand Write Byte Port Timing. 5-13 Misaligned Long-Word Operand Write Word Port Example 5-14 Misaligned Long-Word Operand Write Word Port Timing. 5-15 Misaligned Long-Word Operand Read from Word Port Example 5-16 Misaligned Word Operand Write Word Port Example. 5-16 Misaligned Word Operand Write Word Port Timing 5-17 Misaligned Word Operand Read from Word Example 5-18 Misaligned Long-Word Operand Write Long-Word Port Example 5-18 Misaligned Long-Word Operand Write Long-Word Port Timing 5-19 Misaligned Long-Word Operand Read from Long-Word Port Example 5-20 Byte Enable Signal Generation 32-Bit Ports. 5-23 Long-Word Read Cycle Flowchart 5-26 Byte Read Cycle Flowchart .5-27 Byte Word Read Cycles-32-Bit Port 5-28 Long-Word Read-8-Bit Port 5-29 Long-Word Read-16- 32-Bit Ports 5-30
M68020 USER'S MANUAL MOTOROLA
9/29/95
SECTION OVERVIEW
LIST ILLUSTRATIONS (Continued)
Figure Number 5-24 5-25 5-26 5-27 5-28 5-29 5-30 5-31 5-32 5-33 5-34 5-35 5-36 5-37 5-38 5-39 5-40 5-41 5-42 5-43 5-44 5-45 5-46 5-47 5-48 5-49 5-50 5-51 5-52 Title Page Number
Write Cycle Flowchart .5-33 Read-Write-Read Cycles-32-Bit Port .5-34 Byte Word Write Cycles-32-Bit Port .5-35 Long-Word Operand Write-8-Bit Port .5-36 Long-Word Operand Write-16-Bit Port.5-37 Read-Modify-Write Cycle Flowchart .5-40 Byte Read-Modify-Write Cycle-32-Bit Port (TAS Instruction) 5-41 MC68020/EC020 Space Address Encoding .5-45 Interrupt Acknowledge Cycle Flowchart .5-46 Interrupt Acknowledge Cycle Timing. 5-47 Autovector Operation Timing .5-49 Breakpoint Acknowledge Cycle Flowchart .5-50 Breakpoint Acknowledge Cycle Timing .5-51 Breakpoint Acknowledge Cycle Timing (Exception Signaled) 5-52 Error without DSACK1/DSACK0 5-57 Late Error with DSACK1/DSACK0 5-58 Late Retry.5-59 Halt Operation Timing .5-61 MC68020 Arbitration Flowchart Single Request 5-64 MC68020 Arbitration Operation Timing Single Request 5-65 MC68020 Arbitration State Diagram 5-67 MC68020 Arbitration Operation Timing-Bus Inactive 5-69 MC68EC020 Arbitration Flowchart Single Request 5-71 MC68EC020 Arbitration Operation Timing Single Request 5-72 MC68EC020 Arbitration State Diagram .5-73 MC68EC020 Arbitration Operation Timing-Bus Inactive 5-75 Interface Three-Wire Two-Wire Arbitration .5-76 Initial Reset Operation Timing .5-77 RESET Instruction Timing .5-78 Reset Operation Flowchart .6-5 Interrupt Pending Procedure .6-12 Interrupt Recognition Examples .6-13 Assertion IPEND (MC68020 Only) .6-14 Interrupt Exception Processing Flowchart .6-15 Breakpoint Instruction Flowchart .6-18 Instruction Throwaway Four-Word Frame 6-20 Special Status Word Format 6-22 F-Line Coprocessor Instruction Operation Word. Asynchronous Non-DMA M68000 Coprocessor Interface Signal Usage MC68020/EC020 Space Address Encodings .7-6
MOTOROLA
M68020 USER'S MANUAL
9/29/95
SECTION OVERVIEW
Rev.1.0
LIST ILLUSTRATIONS (Continued)
Figure Number 7-10 7-11 7-12 7-13 7-14 7-15 7-16 7-17 7-18 7-19 7-20 7-21 7-22 7-23 7-24 7-25 7-26 7-27 7-28 7-29 7-30 7-31 7-32 7-33 7-34 7-35 7-36 7-37 7-38 7-39 7-40 7-41 7-42 7-43 7-44 Title Page Number
Coprocessor Address MC68020/EC020 Space Coprocessor Interface Register Coprocessor General Instruction Format (cpGEN) Coprocessor Interface Protocol General Category Instructions. 7-10 Coprocessor Interface Protocol Conditional Category Instructions 7-11 Branch Coprocessor Condition Instruction Format (cpBcc.W) 7-12 Branch Coprocessor Condition Instruction Format (cpBcc.L) 7-12 Coprocessor Condition Instruction Format (cpScc) 7-13 Test Coprocessor Condition, Decrement, Branch Instruction Format (cpDBcc). 7-14 Trap Coprocessor Condition Instruction Format (cpTRAPcc) 7-15 Coprocessor State Frame Format Memory .7-17 Coprocessor Context Save Instruction Format (cpSAVE) 7-20 Coprocessor Context Save Instruction Protocol 7-21 Coprocessor Context Restore Instruction Format (cpRESTORE) 7-22 Coprocessor Context Restore Instruction Protocol 7-23 Control Format .7-25 Condition Format .7-26 Operand Alignment Operand Accesses 7-26 Coprocessor Response Primitive Format 7-28 Busy Primitive Format 7-30 Null Primitive Format. 7-31 Supervisor Check Primitive Format. 7-33 Transfer Operation Word Primitive Format 7-33 Transfer from Instruction Stream Primitive Format 7-34 Evaluate Transfer Effective Address Primitive Format. 7-35 Evaluate Effective Address Transfer Data Primitive Format 7-35 Write Previously Evaluated Effective Address Primitive Format 7-37 Take Address Transfer Data Primitive Format .7-39 Transfer to/from Stack Primitive Format 7-40 Transfer Single Main Processor Register Primitive Format 7-40 Transfer Main Processor Control Register Primitive Format 7-41 Transfer Multiple Main Processor Registers Primitive Format 7-42 Register Select Mask Format .7-42 Transfer Multiple Coprocessor Registers Primitive Format. 7-43 Operand Format Memory Transfer -(An) 7-44 Transfer Status Register ScanPC Primitive Format. 7-44 Take Preinstruction Exception Primitive Format 7-45 MC68020/EC020 Preinstruction Stack Frame 7-46 Take Midinstruction Exception Primitive Format 7-47 MC68020/EC020 Midinstruction Stack Frame 7-47 Take Postinstruction Exception Primitive Format. 7-48
M68020 USER'S MANUAL
MOTOROLA
9/29/95
SECTION OVERVIEW
LIST ILLUSTRATIONS (Concluded)
Figure Number 7-45 9-10 9-11 9-12 9-13 10-1 10-2 10-3 10-4 10-5 Title Page Number
MC68020/EC020 Postinstruction Stack Frame. 7-48 Concurrent Instruction Execution Instruction Execution Instruction Timing Purposes Processor Activity Example .8-5 Processor Activity Example .8-6 Processor Activity Example .8-7 Processor Activity Example .8-8 32-Bit Data Coprocessor Connection.9-2 Chip Select Generation Chip Select Equations Cycle Timing Diagram .9-4 Example MC68020/EC020 Byte Select System Configuration MC68020/EC020 Byte Select Equations .9-8 High-Resolution Clock Controller 9-11 Alternate Clock Solution .9-11 Access Time Computation Diagram .9-12 Module Descriptor Format .9-15 Module Entry Word .9-15 Module Call Stack Frame .9-16 Access Level Control Registers .9-17 Drive Levels Test Points Specifications 10-6 Clock Input Timing Diagram 10-7 Read Cycle Timing Diagram .10-11 Write Cycle Timing Diagram. 10-12 Arbitration Timing Diagram .10-13 Arbitration Circuit-MC68EC020 (Two-Wire) (Three-Wire)
MOTOROLA
M68020 USER'S MANUAL
xvii
9/29/95
SECTION OVERVIEW
Rev.1.0
LIST TABLES
Table Number Title Page Number
Addressing Modes Instruction .1-11 Address Space Encodings Signal Index Signal Summary.
DSACK1/DSACK0 Encodings Results SIZ1, SIZ0 Signal Encoding Address Offset Encodings Data Requirements Read Cycles MC68020/EC020 Internal External Data Multiplexer- Write Cycles .5-9 Memory Alignment Port Size Influence Read/Write Cycles 5-20 Data Byte Enable Signals Byte, Word, Long-Word Ports 5-22 DSACK1/DSACK0, BERR, HALT Assertion Results 5-54
Exception Vector Assignments .6-3 Tracing Control Interrupt Levels Mask Values. 6-12 Exception Priority Groups 6-18 Exception Stack Frames 6-26 cpTRAPcc Opmode Encodings. 7-16 Coprocessor Format Word Encodings 7-18 Null Coprocessor Response Primitive Encodings. 7-32 Valid Effective Address Field Codes 7-36 Main Processor Control Register Select Codes. 7-41 Exceptions Related Primitive Processing 7-53 Examples Instruction Stream Execution Comparison Instruction Timings from Timing Tables 8-11 Observed Instruction Timings 8-11
xviii
M68020 USER'S MANUAL
MOTOROLA
9/29/95
SECTION OVERVIEW
LIST TABLES (Continued)
Table Number 10-1 10-2 10-3 10-4 Title Page Number
Data Activity Byte, Word, Long-Word Ports Assignments-MC68EC020 PPGA Suffix) .9-10 Assignments-MC68EC020 PQFP Sufffix). 9-10 Memory Access Time Equations 16.67 .9-13 Calculated tAVDV Values Operation Frequencies Less Than Equal Maximum Frequency Rating. 9-14 Access Status Register Codes. 9-18 Airflow-MC68020 CQFP Package .10-3 Power Rated Frequency Maximum 110°C) 10-3 Temperature Rise Board PD-MC68020 CQFP Package 10-3 Airflow-MC68EC020 PQFP Package 10-4
MOTOROLA
M68020 USER'S MANUAL
MC68020/EC020 ACRONYM LIST
CAAR CACR CMOS CQFP DDMA DRAM FPCP HCMOS IEEE LRAR NMOS PMMU PPGA PQFP VLSI
MOTOROLA
Binary-Coded Decimal Cache Address Register Cache Control Register Condition Code Register Coprocessor Interface Register Complementary Metal Oxide Semiconductor Central Processing Unit Ceramic Quad Flat Pack Dual-Channel Direct Memory Access Destination Function Code Register Direct Memory Access Dynamic Random Access Memory Floating-Point Coprocessor High-Density Complementary Metal Oxide Semiconductor Institute Electrical Electronic Engineers Interrupt Stack Pointer Lower Middle Byte Limited Rate Auto Request Least Significant Byte Memory Management Unit Microprocessor Unit Most Significant Byte Master Stack Pointer n-Type Metal Oxide Semiconductor Programmable Array Logic Program Counter Grid Array Paged Memory Management Unit Plastic Grid Array Plastic Quad Flat Pack Random Access Memory Source Function Code Register Stack Pointer Status Register Supervisor Stack Pointer Special Status Word Upper Middle Byte User Stack Pointer Vector Base Register Very Large Scale Integration
M68020 USER'S MANUAL
SECTION INTRODUCTION
MC68020 first full 32-bit implementation M68000 family microprocessors from Motorola. Using VLSI technology, MC68020 implemented with 32-bit registers data paths, 32-bit addresses, rich instruction set, versatile addressing modes. MC68020 object-code compatible with earlier members M68000 family added features addressing modes support high-level languages, on-chip instruction cache, flexible coprocessor interface with full IEEE floating-point support (the MC68881 MC68882). internal operations this microprocessor operate parallel, allowing multiple instructions executed concurrently. asynchronous structure MC68020 uses nonmultiplexed with bits address bits data. processor supports dynamic sizing mechanism that allows processor transfer operands from external devices while automatically determining device port size cycle-by-cycle basis. dynamic interface allows access devices differing data widths, addition eliminating data alignment restrictions. MC68EC020 economical high-performance embedded microprocessor based MC68020 been designed specifically suit needs embedded microprocessor market. major differences MC68EC020 MC68020 that MC68EC020 24-bit address does implement following signals: OCS, DBEN, IPEND BGACK Also, available packages frequencies differ MC68020 MC68EC020 (see Section Ordering Information Mechanical Data.) Unless otherwise stated, information this manual applies both MC68020 MC68EC020.
MOTOROLA
M68020 USER'S MANUAL
FEATURES
main features MC68020/EC020 follows: Object-Code Compatible with Earlier M68000 Microprocessors Addressing Mode Extensions Enhanced Support High-Level Languages Field Data Type Accelerates Bit-Oriented Applications-e.g., Video Graphics On-Chip Instruction Cache Faster Instruction Execution Coprocessor Interface Companion 32-Bit Peripherals-the MC68881 MC68882 Floating-Point Coprocessors MC68851 Paged Memory Management Unit Pipelined Architecture with High Degree Internal Parallelism Allowing Multiple Instructions Executed Concurrently High-Performance Asynchronous Nonmultiplexed Full Bits Dynamic Sizing Efficiently Supports 8-/16-/32-Bit Memories Peripherals Full Support Virtual Memory Virtual Machine Sixteen 32-Bit General-Purpose Data Address Registers 32-Bit Supervisor Stack Pointers Five Special-Purpose Control Registers Eighteen Addressing Modes Seven Data Types 4-Gbyte Direct Addressing Range MC68020 16-Mbyte Direct Addressing Range MC68EC020 Selection Processor Speeds MC68020: 16.67, 33.33 Selection Processor Speeds MCEC68020: 16.67 block diagram MC68020/EC020 shown Figure 1-1.
M68020 USER'S MANUAL
MOTOROLA
SEQUENCER CONTROL CONTROL STORE
INSTRUCTION PIPE STAGE STAGE STAGE CACHE HOLDING REGISTER (CAHR)
CONTROL LOGIC INSTRUCTION CACHE ADDRESS
INTERNAL DATA
32-BIT DATA PADS DATA
INSTRUCTION ADDRESS
EXECUTION UNIT
32-BIT
PROGRAM COUNTER SECTION ADDRESS SECTION DATA SECTION SIZE MULTIPLEXER
ADDRESS PADS
ADDRESS MISALIGNMENT MULTIPLEXER CONTROLLER WRITE PENDING BUFFER PREFETCH PENDING BUFFER
MICROBUS CONTROL LOGIC
CONTROL SIGNALS
24-Bit MC68EC020 Figure 1-1. MC68020/EC020 Block Diagram
MOTOROLA
M68020 USER'S MANUAL
PROGRAMMING MODEL
programming model MC68020/EC020 consists groups registers, user model supervisor model, that correspond user supervisor privilege levels, respectively. User programs executing user privilege level registers user model. System software executing supervisor level uses control registers supervisor level perform supervisor functions. shown programming models (see Figures 1-3), MC68020/EC020 32-bit general-purpose registers, 32-bit 32-bit SSPs, 16-bit 32-bit VBR, 3-bit alternate function code registers, 32-bit cache handling (address control) registers. user programming model remains unchanged from earlier M68000 family microprocessors. supervisor programming model supplements user programming model used exclusively MC68020/EC020 system programmers utilize supervisor privilege level implement sensitive operating system functions. supervisor programming model contains controls access enable special features MC68020/EC020. application software, written nonprivileged user level, migrates MC68020/EC020 from M68000 platform without modification. Registers D7-D0 data registers used field bits), byte bit), word bit), long-word bit), quad-word bit) operations. Registers A6-A0 USP, ISP, address registers that used software stack pointers base address registers. Register (shown Figure Figure 1-3) register designation that applies user privilege level either supervisor privilege level. supervisor privilege level, active stack pointer (interrupt master) called SSP. addition, address registers used word long-word operations. general-purpose registers (D7-D0, A7-A0) used index registers. contains address next instruction executed MC68020/EC020. During instruction execution exception processing, processor automatically increments contents places value appropriate.
M68020 USER'S MANUAL
MOTOROLA
DATA REGISTERS
ADDRESS REGISTERS
(USP) USER STACK POINTER PROGRAM COUNTER CONDITION CODE REGISTER
Figure 1-2. User Programming Model
MOTOROLA
M68020 USER'S MANUAL
(ISP) INTERRUPT STACK POINTER MASTER STACK POINTER STATUS REGISTER VECTOR BASE REGISTER ALTERNATE FUNCTION CODE REGISTERS CACHE CONTROL REGISTER CACHE ADDRESS REGISTER
A7'' (MSP)
(CCR)
CACR
CAAR
Figure 1-3. Supervisor Programming Model Supplement
M68020 USER'S MANUAL
MOTOROLA
(see Figure 1-4) stores processor status. contains condition codes that reflect results previous operation used conditional instruction execution program. condition codes extend (X), negative (N), zero (Z), overflow (V), carry (C). user byte, which contains condition codes, only portion information available user privilege level, referenced user programs. supervisor privilege level, software access entire including interrupt priority mask (three bits) control bits that indicate whether processor trace modes (T1, Supervisor user privilege level Master interrupt mode
USER BYTE (CONDITION CODE REGISTER)
SYSTEM BYTE
CARRY
TRACE ENABLE
INTERRUPT PRIORITY MASK
OVERFLOW ZERO
SUPERVISOR/USER LEVEL MASTER/INTERRUPT MODE
NEGATIVE EXTEND
Figure 1-4. Status Register (SR) contains base address exception vector table memory. displacement exception vector added value this register access vector table. alternate function code registers, DFC, contain 3-bit function codes. MC68020, function codes considered extensions 32-bit linear address that optionally provide many eight 4-Gbyte address spaces; MC68EC020, function codes considered extensions 24-bit linear address that optionally provide many eight 16-Mbyte address spaces. Function codes automatically generated processor select address spaces data program user supervisor privilege levels select address space processor functions (e.g., coprocessor communications). Registers used certain instructions explicitly specify function codes operations. CACR controls on-chip instruction cache MC68020/EC020. CAAR stores address cache control functions.
MOTOROLA
M68020 USER'S MANUAL
DATA TYPES ADDRESSING MODES OVERVIEW
detailed information data types addressing modes supported MC68020/EC020, refer M68000PM/AD, M68000 Family Programmer's Reference Manual. MC68020/EC020 supports seven basic data types: Bits Fields (Fields consecutive bits, 1-32 bits long) Digits (Packed: digits/byte, Unpacked: digit/byte) Byte Integers bits) Word Integers bits) Long-Word Integers bits) Quad-Word Integers bits) addition, MC68020/EC020 instruction supports operations other data types such memory addresses. coprocessor mechanism allows direct support floatingpoint operations with MC68881 MC68882 floating-point coprocessors well specialized user-defined data types functions. addressing modes listed Table include nine basic types: Register Direct Register Indirect Register Indirect with Index Memory Indirect Indirect with Displacement Indirect with Index Memory Indirect Absolute Immediate register indirect addressing modes have postincrement, predecrement, displacement, index capabilities. modes have index offset capabilities. Both modes extended provide indirect reference through memory. addition these addressing modes, many instructions implicitly specify CCR, stack pointer, and/or
M68020 USER'S MANUAL
MOTOROLA
Table 1-1. Addressing Modes
Addressing Modes Register Direct Data Address Register Indirect Address Address with Postincrement Address with Predecrement Address with Displacement Address Register Indirect with Index 8-Bit Displacement Base Displacement Memory Indirect Postindexed Preindexed Indirect with Displacement Indirect with Index 8-Bit Displacement Base Displacement Indirect Postindexed Preindexed Absolute Data Addressing Short Long Immediate NOTE: Syntax (An) (An)+ -(An) (bd, ([bd, An], ([bd, Xn], (bd, ([bd, PC], ([bd, Xn], (xxx).W (xxx).L #<data Data Register, D7-D0 Address Register, A7-A0 twos complement sign-extended displacement added part effective address calculation; size (d8) (d16 bits; when omitted, assemblers value zero. Address data register used index register; form Xn.SIZE *SCALE, where SIZE (indicates index register size) SCALE (index register multiplied SCALE); SIZE and/or SCALE optional. twos-complement base displacement; when present, size bits. Outer displacement added part effective address calculation after memory indirection; optional with size bits. Program Counter Immediate value bits Effective Address indirect access long-word address.
<data>
MOTOROLA
M68020 USER'S MANUAL
INSTRUCTION OVERVIEW
detailed information MC68020/EC020 instruction set, refer M68000PM/AD, M68000 Family Programmer's Reference Manual. instructions MC68020/EC020 instruction listed Table 1-2. instruction been tailored support structured high-level languages sophisticated operating systems. Many instructions operate bytes, words, long words, most instructions addressing modes.
VIRTUAL MEMORY VIRTUAL MACHINE CONCEPTS
full addressing range MC68020 Gbytes (4,294,967,296 bytes) each eight address spaces; full addressing range MC68EC020 Mbytes (16,777,216 bytes) each eight address spaces. Even though most systems implement smaller physical memory, system made appear have full Gbytes (MC68020) Mbytes (MC68EC020) memory available each user program using virtual memory techniques. virtual memory system, user program written large amount memory available, although physical memory actually present much smaller. Similarly, system designed allow user programs access devices that physically present system, such tape drives, disk drives, printers, terminals, forth. With proper software emulation, physical system appear other M68000 computer system user program, program given full access resources that emulated system. Such emulated system called virtual machine.
1.5.1 Virtual Memory
system that supports virtual memory limited amount high-speed physical memory that accessed directly processor maintains image much larger virtual memory secondary storage device such large-capacity disk drive. When processor attempts access location virtual memory that resident physical memory, page fault occurs. access that location temporarily suspended while necessary data fetched from secondary storage placed physical memory. suspended access then either restarted continued. MC68020/EC020 uses instruction continuation support virtual memory. When cycle terminated with error, microprocessor suspends current instruction executes virtual memory error handler. When error handler completed execution, returns control program that executing when error detected, reruns faulted cycle (when required), continues suspended instruction.
1-10
M68020 USER'S MANUAL
MOTOROLA
Table 1-2. Instruction
Mnemonic ABCD ADDA ADDI ADDQ ADDX ANDI ASL, BCHG BCLR BFCHG BFCLR BFEXTS BFEXTU BFFFO BFINS BFSET BFTST BKPT BSET BTST CALLM CAS2 CHK2 CMPA CMPI CMPM CMP2 DBcc DIVS, DIVSL DIVU, DIVUL EORI EXT, EXTB ILLEGAL LINK LSL, MOVE MOVEA MOVE MOVE Description Decimal with Extend Address Immediate Quick with Extend Logical Logical Immediate Arithmetic Shift Left Right Branch Conditionally Test Change Test Clear Test Field Change Test Field Clear Signed Field Extract Unsigned Field Extract Field Find First Field Insert Test Field Test Field Breakpoint Branch Always Test Branch Subroutine Test Call Module Compare Swap Operands Compare Swap Dual Operands Check Register Against Bound Check Register Against Upper Lower Bound Clear Compare Compare Address Compare Immediate Compare Memory Memory Compare Register Against Upper Lower Bounds Test Condition, Decrement Branch Signed Divide Unsigned Divide Logical Exclusive Logical Exclusive Immediate Exchange Registers Sign Extend Take Illegal Instruction Trap Jump Jump Subroutine Load Effective Address Link Allocate Logical Shift Left Right Move Move Address Move Condition Code Register Move Status Register Mnemonic MOVE MOVEC MOVEM MOVEP MOVEQ MOVES MULS MULU NBCD NEGX PACK RESET ROL, ROXL,ROXR RRTR SBCD STOP SUBA SUBI SUBQ SUBX SWAP TRAP TRAPcc TRAPV UNLK UNPK Description Move User Stack Pointer Move Control Register Move Multiple Registers Move Peripheral Move Quick Move Alternate Address Space Signed Multiply Unsigned Multiply Negate Decimal with Extend Negate Negate with Extend Operation Logical Complement Logical Inclusive Logical Inclusive Immediate Logical Inclusive Immediate Condition Codes Logical Inclusive Immediate Status Register Pack Push Effective Address Reset External Devices Rotate Left Right Rotate with Extend Left Right Return Deallocate Return from Exception Return from Module Return Restore Codes Return from Subroutine Subtract Decimal with Extend Conditionally Stop Subtract Subtract Address Subtract Immediate Subtract Quick Subtract with Extend Swap Register Words Test Operand Trap Trap Conditionally Trap Overflow Test Operand Unlink Unpack COPROCESSOR INSTRUCTIONS Description Branch Conditionally Test Coprocessor Condition, Decrement Branch Coprocessor General Instruction Restore Internal State Coprocessor Save Internal State Coprocessor Conditionally Trap Conditionally
Mnemonic cpBcc cpDBcc cpGEN cpRESTORE cpSAVE cpScc cpTRAPcc
MOTOROLA
M68020 USER'S MANUAL
1-11
1.5.2 Virtual Machine
typical virtual machine system development software, such operating system, machine also under development available programming use. virtual machine system, governing operating system emulates hardware machine allows software executed debugged though were running hardware. Since software controlled governing operating system, executed lower privilege level than governing operating system. Thus, attempts software virtual resources that physically present (and should emulated) trapped governing operating system performed software. MC68020/EC020 implementation virtual machine, virtual application runs user privilege level. governing operating system executes supervisor privilege level attempt operating system access supervisor resources execute privileged instructions causes trap governing operating system. Instruction continuation used support virtual devices memory-mapped input/output systems. Control data registers virtual device simulated memory map. access virtual register causes fault, function register emulated software.
PIPELINED ARCHITECTURE
MC68020/EC020 contains three-word instruction pipe where instruction opcodes decoded. shown Figure 1-5, instruction words (instruction operation words extension words) enter pipe stage proceed stages instruction word completely decoded when reaches stage pipe. Each stage status that reflects whether word stage loaded with data from cycle that terminated abnormally. Stages pipe only filled response specific prefetch requests issued sequencer. Words loaded into instruction pipe from cache holding register. Although individual stages pipe only bits wide, cache holding register bits wide contains entire long word. This long word obtained from instruction cache external response prefetch request from sequencer. When sequencer requests even-word (long-word-aligned) prefetch, entire long word accessed from instruction cache external loaded into cache holding register, high-order word also loaded into stage pipe. instruction word next sequential prefetch then accessed directly from cache holding register, external cycle instruction cache access required. cache holding register provides instruction words pipe regardless whether instruction cache enabled disabled.
1-12
M68020 USER'S MANUAL
MOTOROLA
INSTRUCTION PIPE CACHE HOLDING REGISTER
STAGE
STAGE
STAGE
SEQUENCER CONTROL UNIT INSTRUCTION FLOW FROM CACHE MEMORY
EXECUTION UNIT
Figure 1-5. Instruction Pipe sequencer either executing microinstructions awaiting completion accesses that necessary continue executing microcode. controller responsible activity. sequencer controls controller, instruction execution, internal processor operations such calculation effective addresses setting condition codes. sequencer initiates instruction word prefetches controls validation instruction words instruction pipe. Prefetch requests simultaneously submitted cache holding register, instruction cache, controller. Thus, even instruction cache disabled, instruction prefetch cache holding register cause external cycle aborted.
CACHE MEMORY
locality reference, instructions that used program have high probability being reused within short time. Additionally, instructions that reside proximity instructions currently also have high probability being utilized within short period. exploit these locality characteristics, MC68020/EC020 contains on-chip instruction cache. cache improves overall performance system reducing number cycles required processor fetch information from memory increasing bandwidth available other masters system.
MOTOROLA
M68020 USER'S MANUAL
1-13
SECTION PROCESSING STATES
This section describes processing states MC68020/EC020. describes functions bits supervisor portion actions taken processor response exception conditions. Unless processor halted, always either normal exception processing state. Whenever processor executing instructions fetching instructions operands, normal processing state. processor also normal processing state while storing instruction results communicating with coprocessor. NOTE Exception processing refers specifically transition from normal processing program normal processing system routines, interrupt routines, other exception handlers. Exception processing includes stacking operations, fetch exception vector, filling instruction pipe caused exception. Exception processing completed when execution first instruction exception handler routine begins. processor enters exception processing state when interrupt acknowledged, when instruction traced results trap, when some other exception condition arises. Execution certain instructions unusual conditions occurring during execution instruction cause exceptions. External conditions, such interrupts, errors, some coprocessor responses, also cause exceptions. Exception processing provides efficient transfer control handlers routines that process exceptions. catastrophic system failure occurs whenever processor receives error generates address error while exception processing state. This type failure halts processor. example, during exception processing error another error occurs, MC68020/EC020 completed transition normal processing completed saving internal state machine; therefore, processor assumes that system operational halts. Only external reset restart halted processor. (When processor executes STOP instruction, special type normal processing state-one without cycles. stopped, halted.)
MOTOROLA
M68020 USER'S MANUAL
PRIVILEGE LEVELS
processor operates privilege levels: user level supervisor level. supervisor level higher privileges than user level. processor coprocessor instructions permitted execute lower privileged user level, available supervisor level. This arrangement allows separation supervisor user supervisor protect system resources from uncontrolled access. S-bit used select either user supervisor privilege level either stack operations. processor identifies access (supervisor user mode) function codes that differentiation between supervisor level user level maintained. many systems, majority programs execute user level. User programs access only their code data areas restricted from accessing other information. operating system typically executes supervisor privilege level. access resources, performs overhead tasks user-level programs, coordinates user-level program activities.
2.1.1 Supervisor Privilege Level
supervisor level higher privilege level. privilege level determined S-bit S-bit set, supervisor privilege level applies, instructions executable. cycles instructions executed supervisor level normally classified supervisor references, values FC2-FC0 signals refer supervisor address spaces. multitasking operating system, more efficient have supervisor stack space associated with each user task separate stack space interrupt-associated tasks. MC68020/EC020 provides supervisor stacks, master interrupt; selects which active. When M-bit set, references implicitly address register seven (A7) explicitly, access MSP. operating system sets each task point task-related area supervisor data space. This arrangement separates task-related supervisor activity from asynchronous, I/O-related supervisor tasks that only coincidental currently executing task. separately maintain task control information each currently executing user task, software updates when task switch performed, providing efficient means transferring task-related stack items. other supervisor stack pointer, ISP, used interrupt control information workspace area interrupt handling routines require. When M-bit clear, MC68020/EC020 interrupt mode supervisor privilege level, operation same supervisor mode MC68000, MC68HC001, MC68008, MC68010. (The processor this mode after reset operation.) references access this mode.
M68020 USER'S MANUAL
MOTOROLA
value M-bit does affect execution privileged instructions; both master interrupt modes supervisor privilege level. Instructions that affect M-bit MOVE ANDI EORI RTE. Also, processor automatically saves M-bit value clears part exception processing interrupts. exception processing performed supervisor privilege level. cycles generated during exception processing supervisor references, stack accesses active SSP.
2.1.2 User Privilege Level
user level lower privilege level. privilege level determined S-bit S-bit clear, processor executes instructions user privilege level. Most instructions execute either privilege level, some instructions that have important system effects privileged only executed supervisor level. instance, user programs allowed execute STOP instruction RESET instruction. prevent user program from entering supervisor privilege level except controlled manner, instructions that alter S-bit privileged. TRAP instruction provides controlled access operating system services user programs. cycles instruction executed user privilege level classified user references, values FC2-FC0 signals specify user address spaces. While processor user level, references system stack pointer implicitly, address register seven (A7) explicitly, refer USP.
2.1.3 Changing Privilege Level
change from user supervisor privilege level, conditions that causes processor perform exception processing must occur. This causes change from user level supervisor level cause change from master mode interrupt mode. Exception processing saves current values bits (along with rest active supervisor stack, then sets S-bit, forcing processor into supervisor privilege level. When exception being processed interrupt M-bit set, M-bit cleared, putting processor into interrupt mode. Execution instructions continues supervisor level process exception condition. return user privilege level, system routine must execute following instructions: MOVE ANDI EORI RTE. These instructions execute supervisor privilege level modify S-bit After these instructions execute, instruction pipeline flushed refilled from appropriate address space. instruction returns program that executing when exception occurred. restores exception stack frame saved supervisor stack. frame
MOTOROLA
M68020 USER'S MANUAL
stack generated interrupt, trap, instruction exception, instruction restores values saved supervisor stack. processor then continues execution restored address privilege level determined S-bit restored frame stack generated fault (bus error address error exception), instruction restores entire saved processor state from stack.
ADDRESS SPACE TYPES
processor specifies target address space every cycle with FC2-FC0 signals according type access required. addition distinguishing between supervisor/user program/data, processor identify special processor cycles, such interrupt acknowledge cycle, memory management unit control accesses translate addresses appropriately. Table lists types accesses defined MC68020/EC020 corresponding values FC2-FC0 signals. Table 2-1. Address Space Encodings
Address Space (Undefined, Reserved) User Data Space User Program Space (Undefined, Reserved) (Undefined, Reserved) Supervisor Data Space Supervisor Program Space Space
Address space reserved user definition; reserved
future Motorola.
memory locations user program data accesses predefined; neither locations supervisor data space. During reset, first long words beginning memory location zero supervisor program space used processor initialization. other memory locations explicitly defined MC68020/EC020. function code selects address space. This special address space that does contain instructions operands reserved special processor functions. processor uses accesses this space communicate with external devices special purposes. example, M68000 processors space interrupt acknowledge cycles. MC68020/EC020 also generate space accesses breakpoint acknowledge coprocessor operations. Supervisor programs MOVES instruction access address spaces, including user spaces address space. Although MOVES instruction used generate space cycles, this interfere with proper system operation. Thus, MOVES access space should done with caution.
M68020 USER'S MANUAL MOTOROLA
EXCEPTION PROCESSING
exception defined special condition that preempts normal processing. Both internal external conditions cause exceptions. External conditions that cause exceptions interrupts from external devices, errors, coprocessor-detected errors, reset. Instructions, address errors, tracing, breakpoints internal conditions that cause exceptions. TRAP, TRAPcc, TRAPV, cpTRAPcc, CHK, CHK2, RTE, BKPT, CALLM, RTM, RESTORE, DIVS DIVU instructions generate exceptions part their normal execution. addition, illegal instructions, privilege violations, coprocessor protocol violations cause exceptions. Exception processing, which transition from normal processing program processing required exception condition, involves exception vector table exception stack frame. following paragraphs describe exception vectors generalized exception stack frame. Exception processing discussed detail Section Exception Processing. Coprocessor-detected exceptions discussed detail Section Coprocessor Interface Description.
2.3.1 Exception Vectors
contains base address 1024-byte exception vector table, which consists exception vectors. Exception vectors contain memory addresses routines that begin execution completion exception processing. These routines perform series operations appropriate corresponding exceptions. Because exception vectors contain memory addresses, each consists long word, except reset vector. reset vector consists long words: address used initialize address used initialize address exception vector derived from 8-bit vector number VBR. vector numbers some exceptions obtained from external device; others supplied automatically processor. processor multiplies vector number four calculate vector offset, which adds VBR. memory address vector. exception vectors located supervisor data space, except reset vector, which located supervisor program space. Only initial reset vector fixed processor's memory map; once initialization complete, there fixed assignments. Since provides base address vector table, vector table located anywhere memory; even dynamically relocated each task that executed operating system. Details exception processing provided Section Exception Processing, Table lists exception vector assignments.
MOTOROLA
M68020 USER'S MANUAL
2.3.2 Exception Stack Frame
Exception processing saves most volatile portion current processor context supervisor stack. This context organized format called exception stack frame. This information always includes copy vector offset vector, frame format field. frame format field identifies type stack frame. instruction uses value format field properly restore information stored stack frame deallocate stack space. general form exception stack frame illustrated Figure 2-1. Refer Section Exception Processing complete list exception stack frames.
STATUS REGISTER PROGRAM COUNTER FORMAT VECTOR OFFSET
ADDITIONAL PROCESSOR STATE INFORMATION WORDS, NEEDED)
Figure 2-1. General Exception Stack Frame
M68020 USER'S MANUAL
MOTOROLA
SECTION SIGNAL DESCRIPTION
This section contains brief descriptions input output signals their functional groups, shown Figure 3-1. Each signal explained brief paragraph with reference other sections that contain more detail about signal related operations. NOTE this section remainder manual, assert negate used specify forcing signal particular state. particular, assertion assert refer signal that active true; negation negate indicate signal that inactive false. These terms used independently voltage level (high low) that they represent.
IPL0 IPL1 ADDRESS DATA
FUNCTION CODES
FC2-FC0
**A31-A0
D31-D0 SIZ0
IPL2
*IPEND
AVEC
INTERRU CONTRO
TRANSFER SIZE
SIZ1
*OCS *ECS
ASYNCHRONOUS CONTROL MC68020
*BGACK
RESET HALT BERR
CONTRO
CONTRO
*DBEN
DSACK0 DSACK1 EMULATOR SUPPORT CDIS
Figure 3-1. Functional Signal Groups
MOTOROLA
M68020 USER'S MANUAL
SIGNAL INDEX
input output signals MC68020/EC020 listed Table 3-1. Both names mnemonics shown along with brief signal descriptions. Signals that implemented MC68020, MC68EC020, have asterisk preceding signal name Table 3-1. Also, note that address bits wide MC68020 bits wide MC68EC020. more detail each signal, refer paragraph this section named signal reference that paragraph description related operations. Timing specifications signals listed Table found Section Electrical Characteristics.
FUNCTION CODE SIGNALS (FC2-FC0)
These three-state outputs identify address space current cycle. Table shows relationships function code signals privilege levels address spaces. Refer Section Processing States more information.
ADDRESS (A31-A0, MC68020)(A23-A0, MC68EC020)
These three-state outputs provide address current cycle, except address space. Refer Section Processing States more information address space. most significant address signal MC68020; most significant address signal MC68EC020. upper eight bits (A31-A24) used internally MC68EC020 access internal instruction cache address tag. Refer Section Operation information address relationship operation.
DATA (D31-D0)
These three-state bidirectional signals provide general-purpose data path between MC68020/EC020 other devices. data transfer bits data cycle. most significant data bus. Refer Section Operation more information data relationship operation.
TRANSFER SIZE SIGNALS (SIZ1, SIZ0)
These three-state outputs indicate number bytes remaining transferred current cycle. Signals DSACK1, DSACK0, SIZ1, SIZ0 define number bits transferred data bus. Refer Section Operation more information SIZ1 SIZ0 their dynamic sizing.
M68020 USER'S MANUAL
MOTOROLA
Table 3-1. Signal Index
Signal Name Function Codes Address MC68020 MC68EC020 Data Size Mnemonic FC2-FC0 A31-A0 A23-A0 D31-D0 SIZ1, SIZ0 Function 3-bit function code used identify address space each cycle. 32-bit address 24-bit address 32-bit data used transfer bits data cycle. Indicates number bytes remaining transferred this cycle. These signals, together with define active sections data bus. Provides indication that cycle beginning. Identical operation that except that asserted only during first cycle operand transfer. Defines transfer processor read write. Provides indicator that current cycle part indivisible read-modify-write operation. Indicates that valid address bus. Indicates that valid data placed data external device been placed data MC68020/EC020. Provides enable signal external data buffers. response signals that indicate requested data transfer operation completed. addition, these lines indicate size external port cycle-by-cycle basis used asynchronous transfers. Provides encoded interrupt level processor. Indicates that interrupt pending. Requests autovector during interrupt acknowledge cycle. Indicates that external device requires mastership. Indicates that external device assume mastership. Indicates that external device assumed mastership. System reset. Indicates that processor should suspend activity that processor halted double fault. Indicates that erroneous operation being attempted. Statically disables on-chip cache assist emulator support. Clock input processor. Power supply. Ground connection.
*External Cycle Start *Operand Cycle Start
Read/Write Read-Modify-Write Cycle Address Strobe Data Strobe
DBEN DSACK1, DSACK0
*Data Buffer Enable
Data Transfer Size Acknowledge
Interrupt Priority Level
IPL2-IPL0 IPEND AVEC BGACK RESET HALT BERR CDIS
*Interrupt Pending
Autovector Request Grant
*Bus Grant Acknowledge
Reset Halt Error Cache Disable Clock Power Supply Ground
*This signal implemented MC68020 implemented MC68EC020.
MOTOROLA
M68020 USER'S MANUAL
ASYNCHRONOUS CONTROL SIGNALS
following signals control synchronous transfer operations MC68020/EC020. Note that OCS, ECS, DBEN implemented MC68020 implemented MC68EC020. Operand Cycle Start (OCS, MC68020 only) This output signal indicates beginning first external cycle instruction prefetch data operand transfer. asserted subsequent cycles that performed dynamic sizing operand misalignment. Refer Section Operation information about relationship operation.
implemented MC68EC020.
External Cycle Start (ECS, MC68020 only) This output signal indicates beginning cycle type. Refer Section Operation information about relationship operation.
implemented MC68EC020.
Read/Write This three-state output signal defines type cycle. high level indicates read cycle; level indicates write cycle. Refer Section Operation information about relationship operation. Read-Modify-Write Cycle (RMC) This three-state output signal identifies current cycle part indivisible read-modify-write operation; remains asserted during cycles readmodify-write operation. Refer Section Operation information about relationship operation. Address Strobe (AS) This three-state output signal indicates that valid address address bus. FC2-FC0, SIZ1, SIZ0, signals also valid when asserted. Refer Section Operation information about relationship operation. Data Strobe (DS) During read cycle, this three-state output signal indicates that external device should place valid data data bus. During write cycle, indicates that MC68020/EC020 placed valid data bus. During two-clock synchronous write cycles, MC68020/EC020 does assert Refer Section Operation more information about relationship operation.
M68020 USER'S MANUAL
MOTOROLA
Data Buffer Enable (DBEN, MC68020 only) This output signal enable signal external data buffers. This signal required systems. Refer Section Operation more information about relationship DBEN operation.
DBEN implemented MC68EC020.
Data Transfer Size Acknowledge (DSACK1, DSACK0) These input signals indicate completion requested data transfer operation. addition, they indicate size external port completion each cycle. These signals apply only asynchronous cycles. Refer Section Operation more information these signals their relationship dynamic sizing.
INTERRUPT CONTROL SIGNALS
following signals interrupt control signals MC68020/EC020. Note that IPEND implemented MC68020 implemented MC68EC020. Interrupt Priority Level Signals (IPL2-IPL0) These input signals provide indication interrupt condition encoding interrupt level from peripheral external prioritizing circuitry. IPL2 most significant level number. example, since IPL2-IPL0 signals active low, IPL2-IPL0 equal corresponds interrupt request interrupt level Refer Section Exception Processing information MC68020/EC020 interrupts. Interrupt Pending (IPEND, MC68020 only) This output signal indicates that interrupt request exceeding current interrupt priority mask been recognized internally. This output external devices (coprocessors other masters, example) predict processor operation following instruction boundaries. Refer Section Exception Processing interrupt information. Also, refer Section Operation information related interrupts.
IPEND implemented MC68EC020.
Autovector (AVEC) This input signal indicates that MC68020/EC020 should generate automatic vector during interrupt acknowledge cycle. Refer Section Operation more information about automatic vectors.
MOTOROLA
M68020 USER'S MANUAL
ARBITRATION CONTROL SIGNALS
following signals arbitration control signals used determine which device system master. Note that BGACK implemented MC68020 implemented MC68EC020. Request (BR) This input signal indicates that external device needs become master. typically "wire-ORed" input (but does need constructed from open-collector devices). Refer Section Operation more information MC68020 arbitration. Refer Section Operation Appendix Interfacing MC68EC020 Device That Supports Three-Wire Arbitration Protocol more information MC68EC020 arbitration. Grant (BG) This output signal indicates that MC68020/EC020 will release ownership when current processor cycle completes. Refer Section Operation more information MC68020 arbitration. Refer Section Operation Appendix Interfacing MC68EC020 Device That Supports ThreeWire Arbitration Protocol more information MC68EC020 arbitration. Grant Acknowledge (BGACK, MC68020 only) This input signal indicates that external device become master. Refer Section Operation more information MC68020 arbitration. Refer Section Operation Appendix Interfacing MC68EC020 Device That Supports Three-Wire Arbitration Protocol more information MC68EC020 arbitration.
BGACK implemented MC68EC020.
EXCEPTION CONTROL SIGNALS
following signals exception control signals MC68020/EC020. Reset (RESET) This bidirectional open-drain signal used initiate system reset. external reset signal resets MC68020/EC020 well external devices. reset signal from processor (asserted part RESET instruction) resets external devices only; internal state processor altered. Refer Section Operation description reset operation Section Exception Processing information about reset exception.
M68020 USER'S MANUAL
MOTOROLA
Halt (HALT) assertion this bidirectional open-drain signal indicates that processor should suspend activity when used with BERR that processor should retry current cycle. Refer Section Operation description effects HALT operations. When processor stopped executing instructions double fault condition, HALT line asserted processor indicate external devices that processor stopped. Error (BERR) This input signal indicates that invalid operation being attempted when used with HALT, that processor should retry current cycle. Refer Section Operation description effects BERR operations.
3.10 EMULATOR SUPPORT SIGNAL
following signal supports emulation providing means emulator disable on-chip cache supplying internal status information emulator. Refer Section Coprocessor Interface Description more detailed information emulation support. Cache Disable (CDIS) This input signal statically disables on-chip cache assist emulator support. Refer Section On-Chip Cache Memory information about cache; refer Section Applications Information description this signal emulator. CDIS does flush instruction cache; entries remain unaltered become available again when CDIS negated.
3.11 CLOCK (CLK)
signal clock input MC68020/EC020. This TTL-compatible signal should gated time while power applied processor. Refer Section Applications Information suggestions clock generation. Refer Section Electrical Characteristics electrical characteristics.
3.12 POWER SUPPLY CONNECTIONS
MC68020/EC020 requires connection power supply, positive with respect ground. connections grouped supply adequate current various sections processor. ground connections similarly grouped. Section Ordering Information Mechanical Data describes groupings ground connections, Section Applications Information describes typical power supply interface.
MOTOROLA
M68020 USER'S MANUAL
3.13 SIGNAL SUMMARY
Table provides summary characteristics signals discussed this section. Signal names preceded asterisk implemented MC68020 implemented MC68EC020. Table 3-2. Signal Summary
Signal Function Function Codes Address MC68020 MC68EC020 Data Transfer Size *Operand Cycle Start *External Cycle Start Read/Write Read-Modify-Write Cycle Address Strobe Data Strobe *Data Buffer Enable Data Transfer Size Acknowledge Interrupt Priority Level *Interrupt Pending Autovector Request Grant *Bus Grant Acknowledge Reset Halt Error Cache Disable Clock Power Supply Ground Signal Name FC2-FC0 A31-A0 A23-A0 D31-D0 SIZ1, SIZ0 Input/Output Output Output Output Output Output Output Output Output Input Input Output Input Input Output Input Input/Output Input/Output Input Input Input Input Input High High High/Low Input/Output Output Output Active State High High Three-State
DBEN DSACK1, DSACK0 IPL2-IPL0 IPEND AVEC BGACK RESET HALT BERR CDIS
*This signal implemented MC68020 implemented MC68EC020. Open-drain
M68020 USER'S MANUAL
MOTOROLA
SECTION ON-CHIP CACHE MEMORY
MC68020/EC020 incorporates on-chip cache memory means improving performance. cache implemented instruction cache used store instruction stream prefetch accesses from main memory. increase instruction throughput results when instruction words required program available on-chip cache time required access them external eliminated. systems with more than master (e.g., processor device), reduced external activity increases overall performance increasing availability external devices without degrading performance MC68020/EC020.
ON-CHIP CACHE ORGANIZATION OPERATION
MC68020/EC020 on-chip instruction cache direct-mapped cache long-word entries. Each cache entry consists field (A31-A8 FC2), valid bit, bits (two words) instruction data. Figure shows block diagram on-chip cache organization. Externally, MC68EC020 does upper eight bits address (A31-A24), addresses $FF000000 $00000000 from MC68EC020 appear same. However, MC68EC020 does A31-A24 internally instruction cache address tag, addresses $FF000000 $00000000 appear different MC68EC020 instruction cache. MC68020, MC68030/EC030, MC68040/EC040 bits address externally. maintain object-code upgrade compatibility when designing with MC68EC020, upper eight bits should considered part address when assigning address spaces hardware. When enabled, MC68020/EC020 instruction cache used store instruction prefetches (instruction words extension words) they requested CPU. Instruction prefetches normally requested from sequential memory addresses except when change program flow occurs (e.g., branch taken) when instruction executed that modify these cases, instruction pipe automatically flushed refilled.
MOTOROLA
M68020 USER'S MANUAL
MC68020/EC020 PREFETCH ADDRESS INDEX
WORD WORD
SELECT WORD
SELECT
REPLACE VALID
REPLACEMENT DATA INSTRUCTION PATH ENTRY COMPARATOR LINE CACHE CONTROL
Figure 4-1. MC68020/EC020 On-Chip Cache Organization When instruction fetch occurs, cache enabled) first checked determine word required cache. This check achieved first using index field (A7-A2) access address index into on-chip cache. This index selects entries cache. Next, A31-A8 compared selected entry. (Note that MC68EC020, A31-A24 used internal on-chip cache comparison.) there match valid set, cache occurs. then used select proper word from cache entry, cycle ends. there match valid clear, cache miss occurs, instruction fetched from external memory. This instruction automatically written into cache entry, valid unless F-bit CACR set. Since processor always prefetches instructions externally with long-word-aligned cycles, both words entry will updated, regardless which word caused miss. NOTE Data accesses cached, regardless their associated address space.
M68020 USER'S MANUAL
MOTOROLA
CACHE RESET
During processor reset, cache cleared resetting valid bits. bits CACR also cleared.
CACHE CONTROL
Only MC68020/EC020 cache control circuitry directly access cache array, supervisor program bits CACR exercise control over cache operations. supervisor level also access CAAR, which contains address cache entry cleared. System hardware assert CDIS signal disable cache. assertion CDIS disables cache, regardless state E-bit CACR. CDIS primarily intended in-circuit emulators.
4.3.1 Cache Control Register (CACR)
CACR, shown Figure 4-2, 32-bit register than written read MOVEC instruction indirectly modified reset. Four bits (3-0) control instruction cache. Bits 31-4 reserved Motorola definition. They read zeros ignored when written. future compatibility, writes should these bits.
Figure 4-2. Cache Control Register
C-Clear Cache C-bit clear entries instruction cache. Operating systems other software this clear instructions from cache prior context switch. processor clears valid bits instruction cache when MOVEC instruction sets C-bit. C-bit always read zero. CE-Clear Entry Cache clear entry instruction cache. index field CAAR (see Figure 4-3), corresponding index long-word select portion address, specifies entry cleared. processor clears only specified long word clearing valid entry when MOVEC instruction sets bit, regardless states bits. always read zero.
MOTOROLA
M68020 USER'S MANUAL
F-Freeze Cache F-bit freeze instruction cache. When F-bit cache miss occurs, entry line) replaced. When F-bit clear, cache miss causes entry line) filled. reset operation clears F-bit. E-Enable Cache E-bit enable instruction cache. When clear, instruction cache disabled. reset operation clears E-bit. supervisor normally enables instruction cache, clear E-bit system debugging emulation, required. Disabling instruction cache does flush entries. cache reenabled, previously valid entries remain valid used.
4.3.2 Cache Address Register (CAAR)
format 32-bit CAAR shown Figure 4-3.
RESERVED INDEX
RESERVED
Figure 4-3. Cache Address Register
Bits 31-8, 0-Reserved These bits reserved Motorola. Index Field index field contains address "clear cache entry" operations. bits this field, which correspond A7-A2, specify index long word cache line.
M68020 USER'S MANUAL
MOTOROLA
SECTION OPERATION
This section provides functional description bus, signals that control cycles provided data transfer operations. also describes error halt conditions, arbitration, reset operation. Operation same whether processor external device master; names descriptions cycles from point view master. exact timing specifications, refer Section Electrical Characteristics. MC68020/EC020 architecture supports byte, word, long-word operands, allowing access 16-, 32-bit data ports through asynchronous cycles controlled DSACK1 DSACK0 input signals. MC68020/EC020 allows byte, word, long-word operands located memory byte boundary. misaligned transfer, more than cycle required complete transfer, regardless port size. port less than bits wide, multiple cycles required operand transfer either misalignment port width smaller than operand size. Instruction words their associated extension words must aligned word boundaries. user should aware that misalignment word long-word operands cause MC68020/EC020 perform multiple cycles operand transfer; therefore, processor performance optimized word long-word memory operands aligned word long-word boundaries, respectively.
TRANSFER SIGNALS
transfers information between MC68020/EC020 external memory, coprocessor, peripheral device. External devices accept provide bits, bits, bits parallel must follow handshake protocol described this section. maximum number bits accepted provided during transfer defined port width. MC68020/EC020 contains address that specifies address transfer data that transfers data. Control signals indicate beginning cycle, address space size transfer, type cycle. selected device then controls length cycle with signal(s) used terminate cycle. Strobe signals, address another data bus, indicate validity address provide timing information data. operates asynchronous mode port width. control input signals internally synchronized MC68020/EC020 clock, introducing delay. This delay time period required MC68020/EC020 sample input signal, synchronize input internal clocks processor, determine whether
MOTOROLA M68020 USER'S MANUAL
input high low. Figure shows relationship between clock signal, typical input, associated internal signal. Furthermore, inputs, processor latches level input during sample window around falling edge clock signal. This window illustrated Figure 5-2. ensure that input signal recognized specific falling edge clock, that input must stable during sample window. input transitions during window, level recognized processor predictable; however, processor always resolves latched level either logic high logic before using addition meeting input setup hold times deterministic operation, input signals must obey protocols described this section.
SYNC DELAY
Figure 5-1. Relationship between External Internal Signals
SAMPLE WINDOW
Figure 5-2. Input Sample Window
5.1.1 Control Signals
MC68020/EC020 initiates cycle driving A1-A0, SIZ1, SIZ0, FC2-FC0, outputs. However, MC68020/EC020 finds required instruction onchip cache, processor aborts cycle before asserting AS.The assertion ensures that cycle been aborted these internal conditions.
M68020 USER'S MANUAL MOTOROLA
When initiating cycle, MC68020 asserts addition A1-A0, SIZ1, SIZ0, FC2-FC0, used initiate various timing sequences that eventually qualified with Qualification with required since, case internal cache hit, cycle aborted after been asserted. During first MC68020 external cycle operand transfer, asserted with ECS. When several cycles required transfer entire operand, asserted only beginning first external cycle. With respect OCS, "operand" entity required execution unit, whether program data item. Note that implemented MC68EC020. FC2-FC0 signals select eight address spaces (see Table 2-1) which address applies. Five address spaces presently defined. remaining three, reserved user definition, reserved Motorola future use. FC2-FC0 valid while asserted. SIZ1 SIZ0 signals indicate number bytes remaining transferred during operand cycle (consisting more cycles) during cache fill operation from device with port size that less than bits. Table lists encoding SIZ1 SIZ0. SIZ1 SIZ0 valid while asserted. signal determines direction transfer during cycle. When required, this signal changes state beginning cycle valid while asserted. only transitions when write cycle preceded read cycle vice versa. This signal remain consecutive write cycles. signal asserted beginning first cycle read-modify-write operation remains asserted until completion final cycle operation. signal guaranteed negated before state cycle following read-modify-write operation.
5.1.2 Address
A31-A0 (for MC68020) A23-A0 (for MC68EC020) define address byte most significant byte) transferred during cycle. processor places address beginning cycle. address valid while asserted. MC68EC020, A31-A24 used internally, externally.
5.1.3 Address Strobe
timing signal that indicates validity address address many control signals. asserted one-half clock after beginning cycle.
5.1.4 Data
D31-D0 comprise bidirectional, nonmultiplexed parallel that contains data being transferred from processor. read write operation transfer bits data (one, two, three, four bytes) cycle. During read cycle, data latched processor last falling edge clock that cycle.
MOTOROLA
M68020 USER'S MANUAL
write cycle, bits data driven, regardless port width operand size. processor places data data one-half clock cycle after asserted write cycle.
5.1.5 Data Strobe
timing signal that applies data bus. read cycle, processor asserts signal external device place data bus. asserted same time during read cycle. write cycle, notifies external device that data written valid. processor asserts full clock cycle after assertion during write cycle.
5.1.6 Data Buffer Enable
MC68020 DBEN signal used enable external data buffers while data present data bus. During read operation, DBEN asserted clock cycle after beginning cycle negated negated. write operation, DBEN asserted time asserted held active duration cycle. Note that DBEN implemented MC68020 implemented MC68EC020.
5.1.7 Cycle Termination Signals
During cycles, external devices assert DSACK1/DSACK0 part protocol. During read cycle, DSACK1/DSACK0 assertion signals processor terminate cycle latch data. During write cycle, assertion DSACK1/DSACK0 indicates that external device successfully stored data that cycle terminate. DSACK1/DSACK0 also indicate processor size port cycle just completed, shown Table 5-1. Refer 5.3.1 Read Cycle timing relationships DSACK1/DSACK0. BERR signal also cycle termination indicator used absence DSACK1/DSACK0 indicate error condition. also asserted conjunction with DSACK1/DSACK0 indicate error condition, provided meets appropriate timing described this section Section Electrical Characteristics. Additionally, BERR HALT signals asserted together indicate retry termination. Again, BERR HALT signals simultaneously asserted lieu conjunction with, DSACK1/DSACK0 signals. Finally, AVEC signal used terminate interrupt acknowledge cycles, indicating that MC68020/EC020 should generate vector number locate interrupt handler routine. AVEC ignored during other cycles.
M68020 USER'S MANUAL
MOTOROLA
DATA TRANSFER MECHANISM
MC68020/EC020 architecture supports byte, word, long-word operands allowing access 16-, 32-bit data ports through asynchronous cycles controlled DSACK1/DSACK0. Byte, word, long-word operands located byte boundary, misaligned transfers require additional cycles, regardless port size.
5.2.1 Dynamic Sizing
MC68020/EC020 dynamically interprets port size addressed device during each cycle, allowing operand transfers from 16-, 32-bit ports. During operand transfer cycle, slave device signals port size (byte, word, long word) indicates completion cycle processor with DSACK1/DSACK0 signals. Refer Table DSACK1/DSACK0 encodings assertion results. Table 5-1. DSACK1/DSACK0 Encodings Results
DSACK1
Negated Negated Asserted Asserted
DSACK0
Negated Asserted Negated Asserted
Result Insert Wait States Current Cycle Complete Cycle-Data Port Size Bits Complete Cycle-Data Port Size Bits Complete Cycle-Data Port Size Bits
example, processor executing instruction that reads long-word operand from long-word-aligned address, attempts read bits during first cycle. (Refer 5.2.2 Misaligned Operands case word byte address.) port responds that bits wide, MC68020/EC020 latches bits data continues with next operation. port responds that bits wide, MC68020/EC020 latches bits valid data runs another cycle obtain other bits. operation 8-bit port similar, requires four read cycles. addressed device uses DSACK1/DSACK0 signals indicate port width. instance, 32-bit device always returns DSACK1/DSACK0 32-bit port, regardless whether cycle byte, word, long-word operation. Dynamic sizing requires that portion data used transfer from particular port size fixed. 32-bit port must reside D31-D0, 16-bit port must reside D32-D16, 8-bit port must reside D31-D24. This requirement minimizes number cycles needed transfer data 16-bit ports ensures that MC68020/EC020 correctly transfers valid data. MC68020/EC020 always attempts transfer maximum amount data cycles; longword operation, always assumes that port bits wide when beginning cycle. bytes operands designated shown Figure 5-3. most significant byte long-word operand OP0; least significant byte OP3. bytes wordlength operand (most significant) OP3. single byte byte-length operand OP3. These designations used figures descriptions that follow.
MOTOROLA M68020 USER'S MANUAL
LONG-WORD OPERAND WORD OPERAND BYTE OPERAND
Figure 5-3. Internal Operand Representation Figure shows required organization data ports MC68020/EC020 16-, 32-bit devices. four bytes shown Figure connected through internal data data multiplexer external data bus. This path means through which MC68020/EC020 supports dynamic sizing operand misalignment. Refer 5.2.2 Misaligned Operands definition misaligned operand. data multiplexer establishes necessary connections different combinations address data sizes.
REGISTER
MULTIPLEXER
ROUTING DUPLICATION INTERNAL MC68020/EC020 D15-D8 D7-D0 EXTERNAL
EXTERNAL DATA ADDRESS xxxxxxx0
D31-
D23-D16
BYTE
BYTE
BYTE
BYTE
32-BIT PORT
INCREASING MEMORY ADDRESSES
xxxxxxx0
BYTE BYTE
BYTE BYTE
16-BIT PORT
xxxxxxx0
BYTE BYTE BYTE BYTE 8-BIT PORT
Figure 5-4. MC68020/EC020 Interface Various Port Sizes
M68020 USER'S MANUAL
MOTOROLA
multiplexer takes four bytes 32-bit routes them their required positions. example, routed D31-D24, would normal case, routed other byte position support misaligned transfer. same true operand bytes. positioning bytes determined SIZ1, SIZ0, outputs. SIZ1 SIZ0 outputs indicate remaining number bytes transferred during current cycle, listed Table 5-2. Table 5-2. SIZ1, SIZ0 Signal Encoding
SIZ1 Negated Asserted Asserted Negated SIZ0 Asserted Negated Asserted Negated Size Byte Word Bytes Long Word
number bytes transferred during write read cycle equal less than size indicated SIZ1 SIZ0 outputs, depending port width operand alignment. example, during first cycle long-word transfer word port, SIZ1 SIZ0 outputs indicate that four bytes transferred, although only bytes moved that cycle. A1-A0 also affect operation data multiplexer. During operand transfer, A31-A2 (for MC68020) A23-A2 (for MC68EC020) indicate long-word base address that portion operand accessed; indicate byte offset from base. Table lists encodings corresponding byte offsets from long-word base. Table 5-3. Address Offset Encodings
Negated Negated Asserted Asserted Negated Asserted Negated Asserted Offset Bytes Byte Bytes Bytes
MOTOROLA
M68020 USER'S MANUAL
Table lists bytes required data read cycles. entries shown OP3, OP2, OP1, portions requested operand that read written during that cycle defined SIZ1, SIZ0, cycle. Table 5-4. Data Requirements Read Cycles
Transfer Size Size Address Long-Word Port External Data Bytes Required D31-D24 D23-D16 D15-D8 D7-D0 Word Port External Data Bytes Required D31-D24 D23-D16 Byte Port External Data Bytes Required D31-D24
SIZ1 Byte Word Bytes Long Word
SIZ0
M68020 USER'S MANUAL
MOTOROLA
Table lists combinations SIZ1, SIZ0, corresponding pattern data transfer write cycles from internal multiplexer MC68020/EC020 external data bus. Table 5-5. MC68020/EC020 Internal External Data Multiplexer-Write Cycles
Transfer Size Size Address External Data Connection D31-D24 D23-D16 D15-D8 OP2* OP1* D7-D0 OP0*
SIZ1 Byte Word Bytes Long Word
SIZ0
*Due current implementation, this byte output never used.
Don't care NOTE: tables external data refer particular byte operand that written that section data bus.
MOTOROLA
M68020 USER'S MANUAL
Figure shows transfer (write) long-word operand word port. first cycle, MC68020/EC020 places four operand bytes external bus. Since address long-word aligned this example, multiplexer follows pattern entry Table corresponding SIZ0, SIZ1, 0000. port latches data D31-D16, asserts DSACK1 (DSACK0 remains negated), processor terminates cycle. then starts cycle with SIZ1, SIZ0, 1010 transfer remaining bits. SIZ1 SIZ0 indicate that word remains transferred; indicate that word corresponds offset from base address. multiplexer follows pattern corresponding this configuration SIZ1, SIZ0, places least significant bytes long word word portion (D31-D16). cycle transfers remaining bytes word-sized port. Figure shows timing transfer signals this operation.
LONG-WORD OPERAND
DATA
WORD MEMORY SIZ1
MC68020/EC020 SIZ0
MEMORY CONTROL DSACK1 DSACK0
Figure 5-5. Long-Word Operand Write Word Port Example
5-10
M68020 USER'S MANUAL
MOTOROLA
A31-A2
FC2-FC0
SIZ1
SIZ0
DSACK1
DSACK0
DBEN
D31-D24
D23-D16
WORD WRITE
WORD WRITE
LONG-WORD OPERAND WRITE 16-BIT PORT
MC68EC020, A23-A2. This signal does apply MC68EC020. Figure 5-6. Long-Word Operand Write Word Port Timing
MOTOROLA
M68020 USER'S MANUAL
5-11
Figure shows word write 8-bit port. Like preceding example, this example requires cycles. Each cycle transfers single byte. SIZ1 SIZ0 first cycle specify bytes; second cycle, byte. Figure shows associated transfer signal timing.
WORD OPERAND
DATA
BYTE MEMORY
MC68020/EC020 SIZ1 SIZ0
MEMORY CONTROL DSACK1 DSACK0
Figure 5-7. Word Operand Write Byte Port Example
5-12
M68020 USER'S MANUAL
MOTOROLA
A31-A2
FC2-FC0
SIZ1
SIZ0
DSACK1
DSACK0
DBEN
D31-D24
D23-D16
D15-D8
D7-D0 BYTE WRITE WORD OPERAND WRITE BYTE WRITE
MC68EC020, A23-A2. This signal does apply MC68EC020. Figure 5-8. Word Operand Write Byte Port Timing
MOTOROLA M68020 USER'S MANUAL 5-13
5.2.2 Misaligned Operands
Since operands reside byte boundary, they misaligned. byte operand properly aligned address; word operand misaligned address; long word misaligned address that evenly divisible four. MC68000, MC68008, MC68010 implementations allow long-word transfers oddword boundaries force exceptions word long-word operand transfers attempted odd-byte addresses. Although MC68020/EC020 does enforce alignment restrictions data operands (including relative data addresses), some performance degradation occurs when additional cycles required long-word word operands that misaligned. maximum performance, data items should aligned their natural boundaries. instruction words extension words must reside word boundaries. Attempting prefetch instruction word address causes address error exception. Figure shows transfer (write) long-word operand address wordorganized memory, which requires three cycles. first cycle, SIZ1 SIZ0 specify long-word transfer, A2-A0 001. Since port width bits, only first byte long word transferred. slave device latches byte acknowledges data transfer, indicating that port bits wide. When processor starts second cycle, SIZ1 SIZ0 specify that three bytes remain transferred with A2-A0 010. next bytes transferred during this cycle. processor then initiates third cycle, with SIZ1 SIZ0 indicating byte remaining transferred with A2-A0 100. port latches final byte, operation complete. Figure 5-10 shows associated transfer signal timing. Figure 5-11 shows equivalent operation data read cycle.
LONG-WORD OPERAND
DATA
WORD MEMORY SIZ1
MC68020/EC020 SIZ0
MEMORY CONTROL DSACK1 DSACK0
Figure 5-9. Misaligned Long-Word Operand Write Word Port Example
5-14
M68020 USER'S MANUAL
MOTOROLA
A31-A2
FC2-FC0
SIZ1
SIZ0
DSACK1
DSACK0
DBEN
D31-D24
D23-D16
D15-D8
BYTE WRITE WORD WRITE
BYTE WRITE
D7-D0
LONG-WORD OPERAND WRITE
MC68EC020, A23-A2. MC68EC020. This signal does apply Figure 5-10. Misaligned Long-Word Operand Write Word Port Timing
MOTOROLA
M68020 USER'S MANUAL
5-15
LONG-WORD OPERAND (REGISTER)
DATA
WORD MEMORY
MC68020/EC020 SIZ1 SIZ0
MEMORY CONTROL DSACK1 DSACK0
Figure 5-11. Misaligned Long-Word Operand Read from Word Port Example Figures 5-12 5-13 show word transfer (write) address word-organized memory. This example similar shown Figures 5-10 except that operand word sized transfer requires only cycles. Figure 5-14 shows equivalent operation data read cycle.
WORD OPERAND
DATA
WORD MEMORY SIZ1
MC68020/EC020 SIZ0
MEMORY CONTROL DSACK1 DSACK0
Figure 5-12. Misaligned Word Operand Write Word Port Example
5-16
M68020 USER'S MANUAL
MOTOROLA
*A31-A2
FC2-FC0
SIZ1
SIZ0
DSACK1
DSACK0
DBEN
D31-D24
D23-D16
D15-D8
D7-D0
WORD WRITE
BYTE WRITE
WORD OPERAND WRITE
MC68EC020, A23-A2. This signal does apply MC68EC020. Figure 5-13. Misaligned Word Operand Write Word Port Timing
MOTOROLA
M68020 USER'S MANUAL
5-17
WORD OPERAND (REGISTER)
DATA
WORD MEMORY SIZ1
MC68020/EC020 SIZ0
MEMORY CONTROL DSACK1 DSACK0
Figure 5-14. Misaligned Word Operand Read from Word Example Figures 5-15 5-16 show example long-word transfer (write) address long-word-organized memory. this example, long-word access attempted beginning least significant byte long-word-organized memory. Only byte transferred first cycle. second cycle then consists threebyte access long-word boundary. Since memory long word organized, further cycles necessary. Figure 5-17 shows equivalent operation data read cycle.
LONG-WORD OPERAND
DATA
LONG-WORD MEMORY SIZ1
MC68020/EC020 SIZ0
MEMORY CONTROL DSACK1 DSACK0
Figure 5-15. Misaligned Long-Word Operand Write Long-Word Port Example
5-18
M68020 USER'S MANUAL
MOTOROLA
*A31-A2
FC2-FC0
SIZ1
SIZ0
DSACK1
DSACK0
DBEN
D31-D24
D23-D16
D15-D8
D7-D0 BYTE WRITE
3-BYTE WRITE
LONG-WORD OPERAND WRITE
MC68EC020, A23-A2. This signal does apply MC68EC020. Figure 5-16. Misaligned Long-Word Operand Write Long-Word Port Timing
MOTOROLA M68020 USER'S MANUAL 5-19
LONG-WORD OPERAND (REGISTER)
DATA
LONG-WORD MEMORY SIZ1
MC68020/EC020 SIZ0
MEMORY CONTROL DSACK1 DSACK0
Figure 5-17. Misaligned Long-Word Operand Read from Long-Word Port Example
5.2.3 Effects Dynamic Sizing Operand Misalignment
combination operand size, operand alignment, port size determine number cycles required perform particular memory access. Table lists number cycles required different operand sizes different port sizes with possible alignment conditions read/write cycles. Table 5-6. Memory Alignment Port Size Influence Read/Write Cycles
Number Cycles (Data Port Size Bits:16 Bits:8 Bits) Operand Size Instruction Byte Operand Word Operand Long-Word Operand 1:2:4 1:1:1 1:1:2 1:2:4 1:1:1 1:2:2 2:3:4 1:1:1 1:1:2 2:2:4 1:1:1 2:2:2 2:3:4
*Instruction prefetches always words from long-word boundary
Table reveals that cycle throughput significantly affected port size alignment. MC68020/EC020 system designer programmer should aware account these effects, particularly time-critical applications.
5-20
M68020 USER'S MANUAL
MOTOROLA
Table demonstrates that processor always prefetches instructions reading long word from long-word address (A1, 00), regardless port size alignment. When required instruction begins odd-word boundary, processor attempts fetch entire bits loads both words into instruction cache, possible, although second required word. Even instruction access cached, entire bits latched into internal cache holding register from which instructions words subsequently referenced. Refer Section Instruction Execution Timing complete description cache holding register pipeline operation.
5.2.4 Address, Size, Data Relationships
data transfer examples show MC68020/EC020 drives data onto receives data from correct byte sections data bus. Table shows combinations SIZ1, SIZ0, signals that used generate byte enable signals each four sections data read write cycles addressed device requires them. port size also affects generation these enable signals shown table. four columns right correspond four byte enable signals. Letters refer port sizes: 8-bit ports, 16-bit ports, 32-bit ports. letters imply that byte enable signal should true that port size. dash implies that byte enable signal does apply. MC68020/EC020 always drives sections data because, beginning write cycle, controller does know port size. Table reveals that MC68020/EC020 transfers number bytes specified SIZ1, SIZ0 from specified address unless operand misaligned unless number bytes greater than port width. these cases, device transfers greatest number bytes possible port. example, size four 32-bit slave only receive three bytes current cycle. 8-bit slave only receive byte. table defines byte enables port sizes. Byte data strobes obtained combining enable signals with signal. Devices residing 8-bit ports data strobe itself since there only valid byte every transfer. These enable strobe signals select only bytes required write read cycles. other bytes selected, which prevents incorrect accesses sensitive areas such I/O.
MOTOROLA
M68020 USER'S MANUAL
5-21
Table 5-7. Data Byte Enable Signals Byte, Word, Long-Word Ports
Data Active Sections Byte (B), Word Long-Word Ports Transfer Size Byte SIZ1 SIZ0 D31-D24 D23-D16 D15-D8 D7-D0
Word
Bytes
Long Word
Figure 5-18 shows logic diagram method generating byte enable signals 32-bit ports from SIZ1, SIZ0, encodings signal.
5.2.5 Cache Interactions
organization requirements on-chip instruction cache affect interpretation DSACK1 DSACK0. Since MC68020/EC020 attempts load instructions into on-chip cache, operate differently when caching enabled. Specifically, read cycles that terminate normally, SIZ1, SIZ0 signals apply. cache also affect assertion operation read cycle. search cache processor begins when sequencer requires instruction. this time, controller also initiate external cycle case requested item resident instruction cache. internal cache occurs, external cycle aborts, asserted. MC68020, occupied with another read write cycle, controller asserts signal (and signal, appropriate). possible have asserted multiple consecutive clock cycles. Note that there minimum time specified from negation next assertion (refer Section Electrical Characteristics). Instruction prefetches occur every other clock that after aborted cycle instruction cache hit, controller asserts next clock, this second cycle data fetch. Note that, controller executing other cycles, these aborted cycles cache hits seen externally.
5-22
M68020 USER'S MANUAL
MOTOROLA
SIZ0
SIZ1
UPPER UPPER DATA (32-BIT PORT) UPPER MIDDLE DATA (32-BIT PORT) LOWER MIDDLE DATA (32-BIT PORT) LOWER LOWER DATA (32-BIT PORT) UPPER DATA (16-BIT PORT) LOWER DATA (16-BIT PORT)
Figure 5-18. Byte Enable Signal Generation 32-Bit Ports
MOTOROLA
M68020 USER'S MANUAL
5-23
5.2.6 Operation
MC68020/EC020 used asynchronous manner allowing external devices operate clock frequencies different from MC68020/EC020 clock. operation uses handshake lines (AS, DSACK0, DSACK1, BERR, HALT) control data transfers. signals start cycle, used condition valid data write cycle. Decoding SIZ1, SIZ0, provides byte enable signals that select active portion data bus. slave device (memory peripheral) then responds placing requested data correct portion data read cycle latching data write cycle asserting DSACK0/DSACK1 combination that corresponds port size terminate cycle. slave responds access invalid, external control logic asserts BERR abort BERR HALT retry cycle. DSACK1/DSACK0 asserted before data from slave device valid read cycle. length time that DSACK1/DSACK0 precede data given parameter #31, must asynchronous system ensure that valid data latched into processor. (Refer Section Electrical Characteristics timing parameters.) Note that maximum time specified from assertion assertion DSACK1/DSACK0. Although processor transfer data minimum three clock cycles when cycle terminated with DSACK1/DSACK0, processor inserts wait cycles clock period increments until DSACK1/DSACK0 recognized. BERR and/or HALT signals asserted after DSACK1/ DSACK0 asserted. BERR and/or HALT must asserted within time given (parameter #48), after DSACK1/DSACK0 asserted asynchronous system. this maximum delay time violated, processor exhibit erratic behavior.
5.2.7 Synchronous Operation with DSACK1/ DSACK0
Although cycles terminated with DSACK1/DSACK0 classified asynchronous, cycles terminated with DSACK1/DSACK0 also operate synchronously that signals interpreted relative clock edges. devices that these synchronous cycles must synchronize responses MC68020/EC020 clock. Since these devices terminate cycles with dynamic sizing capabilities MC68020/EC020 available. addition, minimum cycle time these synchronous cycles three clocks. support systems that system clock generate DSACK1/DSACK0 other asynchronous inputs, asynchronous input setup time (parameter #47A) asynchronous input hold time (parameter #47B) provided Section Electrical Characteristics. (Note: although misnomer, these "asynchronous" parameters setup hold times synchronous operation.) setup hold times assertion negation signal, such DSACK1/DSACK0, processor guaranteed recognize that signal level that specific falling edge system clock. assertion DSACK1/DSACK0 recognized particular falling edge clock, valid data latched into processor (for read cycle) next falling clock edge provided data meets data setup time (parameter #27). this case, parameter
5-24 M68020 USER'S MANUAL MOTOROLA
asynchronous operation ignored. timing parameters referred described Section Electrical Characteristics. system asserts DSACK1/DSACK0 required window around falling edge state obeys proper protocol maintaining DSACK1/DSACK0 (and/or BERR/HALT) until throughout clock edge that negates (with appropriate asynchronous input hold time specified parameter #47B), wait states inserted. cycle runs maximum speed three clocks cycle cycles terminated with DSACK1/DSACK0. ensure proper operation synchronous system when BERR BERR/HALT asserted after DSACK1/DSACK0, BERR (and HALT) must meet appropriate setup time (parameter #27A) prior falling clock edge clock cycle after DSACK1/DSACK0 recognized. This setup time critical, MC68020/EC020 exhibit erratic behavior violated. When operating synchronously, data-in setup (parameter #27) hold (parameter #30) times synchronous cycles used instead timing requirements data relative signal.
DATA TRANSFER CYCLES
transfer data between processor other devices involves following signals: Address (A31-A0 MC68020) (A23-A0 MC68EC020) Data (D31-D0) Control Signals address data buses both parallel, nonmultiplexed buses. master moves data issuing control signals, uses handshake protocol ensure correct movement data. cycles, master responsible de-skewing signals issues both start cycle. addition, master responsible de-skewing DSACK1/DSACK0, D31-D0, BERR, HALT, and, MC68020, DBEN from slave devices. following paragraphs define read, write, read-modify-write cycle operations. Each cycles defined succession states. These states apply operation different from processor states described Section Processing States. clock cycles used descriptions timing diagrams data transfer cycles independent clock frequency. operations described terms external states.
MOTOROLA
M68020 USER'S MANUAL
5-25
5.3.1 Read Cycle
During read cycle, processor receives data from memory, coprocessor, peripheral device. instruction specifies long-word operation, MC68020/EC020 attempts read four bytes once. word operation, attempts read bytes once byte operation, byte. some operations, processor requests three-byte transfer. processor properly positions each byte internally. section data from which each byte read depends operand size, A1-A0, port size. Refer 5.2.1 Dynamic Sizing 5.2.2 Misaligned Operands more information dynamic sizing misaligned operands. Figure 5-19 flowchart long-word read cycle. Figure 5-20 flowchart byte read cycle. Figures 5-21-5-23 read cycle timing diagrams terms clock periods. Figure 5-21 corresponds byte word read cycles from 32-bit port. Figure 5-22 corresponds long-word read cycle from 8-bit port. Figure 5-23 also applies long-word read cycle, from 32-bit ports.
PROCESSOR ADDRESS DEVICE EXTERNAL DEVICE
ASSERT ECS/OCS ONE-HALF CLOCK
READ DRIVE ADDRESS A31-A0 DRIVE FUNCTION CODE FC2-FC0 DRIVE SIZ1, SIZ0 (FOUR BYTES) ASSERT ASSERT ASSERT DBEN
PRESENT DATA DECODE ADDRESS PLACE DATA D31-D0 ASSERT DSACK1/DSACK0
ACQUIRE DATA LATCH DATA NEGATE NEGATE DBEN
TERMINATE CYCLE REMOVE DATA FROM D31-D0 NEGATE DSACK1/DSACK0
START NEXT CYCLE
step does apply Thisthe MC68EC020, A23-A0. MC68EC020.
Figure 5-19. Long-Word Read Cycle Flowchart
5-26
M68020 USER'S MANUAL
MOTOROLA
PROCESSOR ADDRESS DEVICE
EXTERNAL DEVICE
ASSERT ECS/OCS ONE-HALF CLOCK
READ DRIVE ADDRESS A31-A0 DRIVE FUNCTION CODE FC2-FC0 DRIVE SIZ1, SIZ0 (FOUR BYTES) ASSERT ASSERT ASSERT DBEN
PRESENT DATA DECODE ADDRESS PLACE DATA D31-D24 D23-D16 D15-D8 D7-D0 (BASED WIDTH) ASSERT DSACK1/DSACK0
ACQUIRE DATA LATCH DATA NEGATE NEGATE DBEN
TERMINATE CYCLE REMOVE DATA FROM D31-D0 NEGATE DSACK1/DSACK0
START NEXT CYCLE
This step does apply MC68EC020. MC68EC020, A23-A0. Figure 5-20. Byte Read Cycle Flowchart
MOTOROLA
M68020 USER'S MANUAL
5-27
*A31-A2
FC2-FC0
SIZ1 WORD SIZ0 BYTE
DSACK1
DSACK0
DBEN
D31-D24
D23-D16
D15-D8
D7-D0 WORD READ BYTE READ BYTE READ
Figure 5-21. Byte Word Read Cycles-32-Bit Port
5-28
M68020 USER'S MANUAL
MOTOROLA
*A31-A2
FC2-FC0
SIZ1 LONG WORD SIZ0 3-BYTE WORD BYTE
DSACK1
DSACK0
DBEN
D31-D24
D23-D16
D15-D8
D7-D0 BYTE READ BYTE READ BYTE READ BYTE READ
LONG-WORD OPERAND READ FROM 8-BIT PORT
MC68EC020, A23-A2. MC68EC020. This signal does apply Figure 5-22. Long-Word Read-8-Bit Port
MOTOROLA M68020 USER'S MANUAL 5-29
*A31-A2
FC2-FC0
SIZ1 LONG WORD SIZ0 WORD LONG WORD
DSACK1
DSACK0
DBEN
D31-D24
D23-D16
D15-D8
WORD READ WORD READ LONG-WORD READ FROM 32-BIT PORT
D7-D0
LONG-WORD OPERAND READ FROM 16-BIT PORT
MC68EC020, A23-A2. This signal does apply MC68EC020. Figure 5-23. Long-Word Read-16- 32-Bit Ports
5-30 M68020 USER'S MANUAL MOTOROLA
State MC68020-The read cycle starts state (S0). processor asserts ECS, indicating beginning external cycle. cycle first external cycle read operation, asserted simultaneously. During processor places valid address A31-A0 valid function codes FC2-FC0. function codes select address space cycle. processor drives high read cycle negates DBEN disable data buffers. SIZ0 SIZ1 become valid, indicating number bytes requested transferred. MC68EC020-The read cycle starts During processor places valid address A23-A0 valid function codes FC2-FC0. function codes select address space cycle. processor drives high read cycle. SIZ0 SIZ1 become valid, indicating number bytes requested transferred. State MC68020-One-half clock later state (S1), processor asserts indicating that address address valid. processor also asserts during addition, (and OCS, asserted) signal negated during MC68EC020-One-half clock later processor asserts indicating that address address valid. processor also asserts during State MC68020-During state (S2), processor asserts DBEN enable external data buffers. selected device uses R/W, SIZ1-SIZ0, A1-A0, place information data bus. bytes (D31-D24, D23-D16, D15-D8, D7-D0) selected SIZ1-SIZ0 A1-A0. Concurrently, selected device asserts DSACK1/DSACK0. MC68EC020-During selected device uses R/W, SIZ1-SIZ0, A1-A0, place information data bus. bytes (D31-D24, D23-D16, D15-D8, D7-D0) selected SIZ1-SIZ0 A1-A0. Concurrently, selected device asserts DSACK1/DSACK0. State MC68020/EC020-As long least DSACK1/DSACK0 signals recognized (meeting asynchronous input setup time requirement), data latched next falling edge clock, cycle terminates. DSACK1/DSACK0 recognized start state (S3), processor inserts wait states instead proceeding states ensure that wait states inserted, both DSACK1 must remain negated throughout asynchronous input setup hold times around wait states added, processor continues sample DSACK1/DSACK0 signals falling edges clock until assertion recognized.
MOTOROLA
M68020 USER'S MANUAL
5-31
State MC68020/EC020-At state (S4), processor latches incoming data. State MC68020-The processor negates DBEN during state (S5). holds address valid during provide address hold time memory systems. R/W, SIZ1- SIZ0, FC2-FC0 also remain valid throughout external device keeps data DSACK1/DSACK0 signals asserted until detects negation (whichever detects first). device must remove data negate DSACK1/DSACK0 within approximately clock period after sensing negation DSACK1/DSACK0 signals that remain asserted beyond this limit prematurely detected next cycle. MC68EC020-The processor negates during state holds address valid during provide address hold time memory systems. SIZ1, SIZ0, FC2-FC0 also remain valid throughout external device keeps data DSACK1/DSACK0 signals asserted until detects negation (whichever detects first). device must remove data negate DSACK1/DSACK0 within approximately clock period after sensing negation DSACK1/DSACK0 signals that remain asserted beyond this limit prematurely detected next cycle.
5-32
M68020 USER'S MANUAL
MOTOROLA
5.3.2 Write Cycle
During write cycle, processor transfers data memory peripheral device. Figure 5-24 flowchart write cycle operation long-word transfer. Figures 5-25- 5-28 write cycle timing diagrams terms clock periods. Figure 5-25 shows write cycles (between read cycles with idle time between) 32-bit port. Figure 5-26 shows byte word write cycles 32-bit port. Figure 5-27 shows longword write cycle 8-bit port. Figure 5-28 shows long-word write cycle 16-bit port.
PROCESSOR ADDRESS DEVICE EXTERNAL DEVICE
ASSERT ECS/OCS ONE-HALF CLOCK DRIVE ADDRESS A31-A0
DRIVE FUNCTION CODES FC2-FC0 DRIVE SIZ1, SIZ0 (FOUR BYTES) WRITE ASSERT ASSERT DBEN DRIVE DATA LINES D31-D0 ASSERT
ACCEPT DATA DECODE ADDRESS STORE DATA FROM D31-D0 ASSERT DSACK1/DSACK0
TERMINATE OUTPUT TRANSFER NEGATE REMOVE DATA FROM D31-D0 NEGATE DBEN
TERMINATE CYCLE NEGATE DSACK1/DSACK0
START NEXT CYCLE
This step does apply MC68EC020. MC68EC020, A23-A0. Figure 5-24. Write Cycle Flowchart
MOTOROLA
M68020 USER'S MANUAL
5-33
*A31-A2
FC2-FC0
SIZ1 LONG WORD SIZ0
DSACK1
DSACK0
DBEN
D31-D0 BYTE READ WRITE WRITE READ WITH WAIT STATES
MC68EC020, A23-A2. This signal does apply MC68EC020. Figure 5-25. Read-Write-Read Cycles-32-Bit Port
5-34
M68020 USER'S MANUAL
MOTOROLA
*A31-A2
FC2-FC0
SIZ1 WORD SIZ0 BYTE
DSACK1
DSACK0
DBEN
D31-D24
D23-D16
D15-D8
BYTE WRITE
D7-D0
WORD WRITE BYTE WRITE
MC68EC020, A23-A2. MC68EC020. This signal does apply Figure 5-26. Byte Word Write Cycles-32-Bit Port
MOTOROLA
M68020 USER'S MANUAL
5-35
*A31-A2
FC2-FC0
SIZ1 LONG WORD SIZ0 3-BYTE WORD BYTE
DSACK1
DSACK0
DBEN
D31-D24
D23-D16
D15-D8
D7-D0
BYTE WRITE
BYTE WRITE
BYTE WRITE
BYTE WRITE
LONG-WORD OPERAND WRITE 8-BIT PORT
MC68EC020, A23-A2. MC68EC020. This signal does apply Figure 5-27. Long-Word Operand Write-8-Bit Port
5-36 M68020 USER'S MANUAL MOTOROLA
*A31-A2
FC2-FC0
SIZ1 LONG WORD SIZ0 WORD LONG WORD
DSACK1
DSACK0
DBEN
D31-D24
D23-D16
D15-D8
D7-D0
WORD WRITE
WORD WRITE
LONG-WORD WRITE 32-BIT PORT
LONG-WORD OPERAND WRITE 16-BIT PORT
MC68EC020, A23-A2. This signal does apply MC68EC020. Figure 5-28. Long-Word Operand Write-16-Bit Port
MOTOROLA M68020 USER'S MANUAL 5-37
State MC68020-The write cycle starts processor negates ECS, indicating beginning external cycle. cycle first external cycle write operation, asserted simultaneously. During processor places valid address A31-A0 valid function codes FC2-FC0. function codes select address space cycle. processor drives write cycle. SIZ1- SIZ0 become valid, indicating number bytes transferred. MC68EC020-The write cycle starts During processor places valid address A23-A0 valid function codes FC2-FC0. function codes select address space cycle. processor drives write cycle. SIZ1, SIZ0 become valid, indicating number bytes transferred. State MC68020-One-half clock later processor asserts indicating that address address valid. processor also asserts DBEN during which enable external data buffers. addition, (and OCS, asserted) signal negated during MC68EC020-One-half clock later processor asserts indicating that address address valid. State MC68020/EC020-During processor places data written onto D31-D0. processor samples DSACK1/DSACK0. State MC68020/EC020-The processor asserts during indicating that data data stable. long least DSACK1/DSACK0 signals recognized (meeting asynchronous input setup time requirement), cycle terminates clock later. DSACK1/DSACK0 recognized start processor inserts wait states instead proceeding ensure that wait states inserted, both DSACK1 DSACK0 must remain negated throughou
Other recent searches
XRT75L04D - XRT75L04D XRT75L04D Datasheet
SN74ALVCH16952 - SN74ALVCH16952 SN74ALVCH16952 Datasheet
LVC374A - LVC374A LVC374A Datasheet
LTC660 - LTC660 LTC660 Datasheet
LTC1516 - LTC1516 LTC1516 Datasheet
LTC1775 - LTC1775 LTC1775 Datasheet
LTC1922 - LTC1922 LTC1922 Datasheet
ICS673-01 - ICS673-01 ICS673-01 Datasheet
ICS674-01 - ICS674-01 ICS674-01 Datasheet
CJ7908 - CJ7908 CJ7908 Datasheet
BR93L46-W - BR93L46-W BR93L46-W Datasheet
BR93L46F-W - BR93L46F-W BR93L46F-W Datasheet
BR93L46RF-W - BR93L46RF-W BR93L46RF-W Datasheet
BR93L46FJ-W - BR93L46FJ-W BR93L46FJ-W Datasheet
BR93L46RFJ-W - BR93L46RFJ-W BR93L46RFJ-W Datasheet
AN553 - AN553 AN553 Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
