WarpLink2.5 Quad high-speed, full-duplex, serializer/deserializer (SER

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

WarpLink2.5 Quad high-speed, full-duplex, serializer/deserializer (SER

Datasheet Thumbnail

Top Searches for this datasheet

MC92610 WarpLink2.5 Quad SERDES Transceiver
WarpLink2.5 Quad high-speed, full-duplex, serializer/deserializer (SERDES) data interface that used transmit data between chips across board, through backplane, through cabling. Four transceivers transmit receive coded data rate gigabit second (Gbps) through each 3.125 gigabaud link. rich feature makes easily adaptable many broadband applications. WarpLink Quad latest generation Motorola's WarpLink product line. Like predecessors, features very power 0.25 micron CMOS implementation that nominally consumes less than 1500mW with links operating full speed.
Four full-duplex differential data links Gbps data aggregate transfer speed Dual speed range: Gbps Gbps power: 1500mW, under typical conditions, with transceivers operating full speed Transceiver channels individually disabled IEEE 1149.1 JTAG support fullspeed Built Self Test, BIST, functions Data Interface Internal Fibre Channel 8B/10B encoder/decoder accessed through Byte Interface bypassed Ten-Bit Interface mode Double data rate (DDR), source synchronous, 8-bit 10-bit HSTL parallel data interfaces
XMIT_n_CLK XCVR_n_DISABLE XCVR_n_RSEL RECV_n[7:0] RECV_n_K RECV_n_9 RECV_n_IDEL RECV_n_ERR RECV_n_CLK
Transmit Interface Unit
Transmitter
XMIT_n[7:0] XMIT_n_K XMIT_n_IDEL_B
XLINK_n0_N 8B10B Decoder XLINK_n0_P XLINK_n1_N XLINK_n1_P RLINK_n1_P Receiver Receive Interface Unit 8B10B Decoder RLINK_n1_N RLINK_n0_P RLINK_n0_N RECV_EQ_EN XMIT_EQ_EN System Integration Unit JTAG BIST REF_CLK_P REF_CLK_N
Typical each channels (n=A,
CONFIG TEST System
MC92610 Quad SERDES Transciever Block Diagram
Technical pecifications
channels have: 8B/10B encoder/decoder that enabled bypassed Clock generation/recovery Independent 8-bit 10-bit system with parallel-to-serial, serial-to-parallel conversion Idle/control character generation/ detection Transceiver Links operate over media (100 differential) lengths meters FR-4 board/backplane, meters coax external loop filter components required Production in-system BIST test modes speed, circuit, with error counter In-system loopback BIST isolated from link inputs outputs IEEE 1149.1 JTAG boundary scan support Differential reference clock input with single-ended reference clock input option (156.25 max) Tolerates REF_CLK frequency offset excess Technology: High-performance 0.25µ CMOS Process, six-layer metal
Link Multiplex Mode enables operation links with single data rate (SDR), source synchronous, 16-bit 20-bit parallel data interfaces Selectable Idle character alignment mode enables transfers with automatic realignment unaligned data transfers Link-to-link synchronization supports aligned, 32-bit, word transfers. Synchronization mechanism tolerates 40-bit times link-to-link media delay skew Multi-chip link synchronization supports aligned multi-word transfers. four WarpLink devices combined provide 128-bit, fourword, synchronized transfers Each channel dedicated input clock (156.25 MHz) Received data clocked recovered clock reference clock frequency Link Interface Links drive media (100 differential), backplane cable
On-chip link termination external terminating resistors needed) On-chip coupling capacitors provide expanded common mode range Link inputs "hot-swap" compatible Selectable transmit receive equalization Repeater mode configures WarpLink Quad into four-link receivetransmit repeater Redundant transmitter link outputs receiver link inputs Redundant links selectable transceiver Broadcast mode enables transmit links
Typical Applications
High-speed data transfer applications high-bandwidth backplane chassisto-chassis networking High-end router systems Backbone switches Access switches Storage Area Network equipment High-speed Automatic Test Equipment
MC92610 Parametrics
Power Supply: Core Power Supply 1.8V 5Vdc HSTL Power Supply 1.5V 0Vdc 1.8V 5Vdc Link Power Supply 1.8V 5Vdc Power Dissipation: Package:
typical operation, <375mW channel maximum speed MAPBGA (19x19mm body size, 1.0mm ball pitch)
Contact Information
Motorola offers user's manuals, application notes, sample code full local support Smart Networks Platform processors. more informtion, visit: additional information this device please contact WarpLink Applications 480-814-2208 email R4028C@email.sps.mot.com other inquiries about Motorola products, please contact Motorola Customer Response Center 1-800-521-6274
MOTOROLA, Stylized Logo other trademarks indicated such herein trademarks Motorola, Inc. Reg. U.S. Pat. Off. PowerPC PowerPC 603e trademarks International Business Machines Corporation used Motorola, Inc. under license. 2001 Motorola, Inc. rights reserved. Printed U.S.A.
5/01
MPC92610FACT/D Rev.0

WarpLink2.5 Quad high-speed, full-duplex, serializer/deserializer (SER

Top Searches for this datasheet

Other recent searches