µPD784035(A), 784036(A) 16/8-BIT SINGLE-CHIP MICROCONTROLLER
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INTEGRATED CIRCUIT
µPD784035(A), 784036(A)
16/8-BIT SINGLE-CHIP MICROCONTROLLER
µPD784036(A) product µPD784038 sub-series 78K/IV series. stricter quality assurance program applies µPD784036(A) than µPD784036 (standard product). terms quality,
µPD784036(A) classified special grade.
µPD784036(A) contains various peripheral hardware such ROM, RAM, ports, 8-bit resolution converters, timers, serial interface, interrupt functions, well high-speed, high-performance CPU. addition, µPD78P4038(A) (one-time PROM EPROM product), which operated within same power supply voltage ranges masked-ROM products, development tools supported. specific functions other detailed information, consult following user's manual. This manual required reading design work. µPD784038, 784038Y Sub-Series User's Manual, Hardware U11316E 78K/IV Series User's Manual, Instruction U10905E
FEATURES
Higher reliability than µPD784036 (Refer Quality Grade Semiconductor Devices (Document number C11531E).) Minimum instruction execution time: MHz) Number ports: Timer/counters 16-bit timer/counter units 16-bit timer unit converter: 8-bit resolution channels converter: 8-bit resolution channels Standby function HALT/STOP/IDLE mode outputs: Serial interface: channels UART/IOE (3-wire serial I/O): channels (3-wire serial I/O, 2-wire serial I/O): channel Clock frequency division function Watchdog timer: channel Clock output function Selected from fCLK, fCLK/2, fCLK/4, fCLK/8, fCLK/16 Power supply voltage:
APPLICATIONS
Controllers automobile electronic control systems, detector circuit-breakers, various types safety equipment, etc.
This manual describes µPD784036(A) unless otherwise specified.
information this document subject change without notice.
Document U13010EJ1V0DS00 (1st edition) Date Published December 1997 Printed Japan
1997
µPD784035(A), 784036(A)
ORDERING INFORMATION
Part number Package 80-pin plastic 80-pin plastic Internal (bytes) Internal (bytes)
Remark code suffix.
QUALITY GRADE
Part number Package 80-pin plastic 80-pin plastic Quality grade Special Special
Remark code suffix.
Please refer "Quality Grades Semiconductor Devices" (Document C11531E) published Corporation know specification quality grade devices recommended applications.
µPD784035(A), 784036(A)
78K/IV SERIES PRODUCT DEVELOPMENT DIAGRAM
Under mass production Under development
supported
Multimaster supported
µPD784038Y
Standard models
µPD784225Y µPD784225
pins, added correction Multimaster supported
µPD784038
Enhanced internal memory capacity, compatible with µPD784026 Multimaster supported
µPD784026
Enhanced A/D, 16-bit timer, power management
µPD784216Y µPD784216
pins, enhanced internal memory capacity
µPD784218Y µPD784218
Enhanced internal memory capacity, added correction
µPD784054 µPD784046
ASSP models Equipped with 10-bit
PD784955
inverter control
PD784908
Equipped with IEBuscontroller
µPD784943
CD-ROM
Multimaster supported
PD784928Y PD784928
Enhanced function µPD784915
µPD784915
software servo control, equipped with analog circuit VCR, enhanced timer
µPD784035(A), 784036(A)
FUNCTIONS
Product Item Number basic instructions (mnemonics) General-purpose register Minimum instruction execution time Internal memory Memory space ports Total Input Input/output Additional function pinsNote bits registers banks, bits registers banks (memory mapping) ns/250 ns/500 ns/1 MHz) bytes bytes Program data: byte bytes
µPD784035(A)
µPD784036(A)
Pins with pull- resistor direct drive outputs Transistor direct drive bits bits Timer/counter bits) Timer register Capture register Compare register Timer register Capture register Capture/compare register Compare register Timer register Capture register Capture/compare register Compare register Timer register Compare register Pulse output capability Toggle output PWM/PPG output One-shot pulse output Pulse output capability Real-time output bits
Real-time output ports Timer/counter
Timer/counter (8/16 bits)
Timer/counter (8/16 bits)
Pulse output capability Toggle output PWM/PPG output
Timer (8/16 bits) outputs Serial interface converter converter Clock output Watchdog timer Standby Interrupt Hardware source Software source Nonmaskable Maskable
12-bit resolution channels UART/IOE (3-wire serial I/O) channels (incorporating baud rate generator) (3-wire serial I/O, 2-wire serial I/O): channel 8-bit resolution channels 8-bit resolution channels Selected from fCLK, fCLK/2, fCLK/4, fCLK/8, fCLK/16 (can used 1-bit output port) channel HALT/STOP/IDLE mode internal, external (sampling clock variable input: instruction, BRKCS instruction, operand error internal, external internal, external 4-level programmable priority operation statuses: vectored interrupt, macro service, context switching
Supply voltage Package
80-pin plastic
Note Additional function pins included pins.
µPD784035(A), 784036(A)
CONTENTS
DIFFERENCES BETWEEN µPD784038 SUB-SERIES SPECIAL PRODUCTS DIFFERENCES BETWEEN STANDARD SPECIAL PRODUCTS CONFIGURATION (TOP VIEW) BLOCK DIAGRAM LIST FUNCTIONS
Port Pins Non-Port Pins Circuits Pins Handling Unused Pins
ARCHITECTURE
Memory Space Registers 6.2.1 6.2.2 6.2.3 General-purpose registers Control registers Special function registers (SFRs)
PERIPHERAL HARDWARE FUNCTIONS
Ports Clock Generator Real-Time Output Port Timers/Counters Output (PWM0, PWM1) Converter Converter Serial Interface 7.8.1 7.8.2 Asynchronous serial interface/three-wire serial (UART/IOE) Synchronous serial interface (CSI)
Clock Output Function
7.10 Edge Detection Function 7.11 Watchdog Timer
INTERRUPT FUNCTION
Interrupt Source Vectored Interrupt Context Switching Macro Service Examples Macro Service Applications
µPD784035(A), 784036(A)
LOCAL INTERFACE
Memory Expansion Memory Space Programmable Wait Pseudo-Static Refresh Function Hold Function
STANDBY FUNCTION RESET FUNCTION INSTRUCTION ELECTRICAL CHARACTERISTICS PACKAGE DRAWINGS RECOMMENDED SOLDERING CONDITIONS APPENDIX DEVELOPMENT TOOLS APPENDIX RELATED DOCUMENTS
µPD784035(A), 784036(A)
DIFFERENCES BETWEEN µPD784038 SUB-SERIES SPECIAL PRODUCTS
only difference between µPD784031(A), µPD784035(A), µPD784036(A) their capacity internal memory. µPD78P4038(A) produced replacing masked µPD784031(A), µPD784035(A),
µPD784036(A) with 128K-byte one-time PROM EPROM. Table shows differences between these products.
Table 1-1. Differences between µPD784038 Sub-Series Special Products
Product Item Internal None bytes (masked ROM) bytes (masked ROM)
µPD784031(A)
µPD784035(A)
µPD784036(A)
µPD78P4038(A) (under develoment)
128K bytes (one-time PROM EPROM) bytes
Internal
bytes
DIFFERENCES BETWEEN STANDARD SPECIAL PRODUCTS
Table shows differences between standard special products. Table 2-1. Differences between Standard Special Products
Product Item Quality grade Package Special 80-pin plastic
µPD784035(A), µPD784036(A)
µPD784035, µPD784036, µPD784037, µPD784038
Standard 80-pin plastic 80-pin plastic 80-pin plastic TQFP (fine pitch,
µPD784035(A), 784036(A)
CONFIGURATION (TOP VIEW)
80-pin plastic
P25/INTP4/ASCK/SCK1
P31/ TxD/SO1
P23/INTP2/CI
P30/RxD/SI1
P22/INTP1
P24/INTP3
P26/INTP5
P21/INTP0
P77/ANI7
P76/ANI6
P32/SCK0/SCL P33/SO0/SDA P34/ P35/ P36/ P37/ RESET VDD1 VSS1 P67/REFRQ/HLDAK
P75/ANI5
P20/NMI
P27/SI0
AVREF3
AVREF2
AVREF1
ANO1
ANO0
AVDD
AVSS
P74/ANI4 P73/ANI3 P72/ANI2 P71/ANI1 P70/ANI0 VDD0 P14/TXD2/SO2 P13/RXD2/SI2 P12/ASCK2/SCK2 P11/PWM1 P10/PWM0 TESTNote VSS0 ASTB/CLKOUT P40/AD0 P41/AD1 P42/AD2
P66/ WAIT/HLDRQ
P63/A19
P62/A18
P61/A17
P60/A16
P57/A15
P56/A14
P55/A13
P54/A12
P53/A11
P52/A10
P51/A9
P50/A8
P47/AD7
P46/AD6
P45/AD5
P44/AD4
Note
Connect TEST VSS0 directly.
P43/AD3
P65/WR
P64/RD
µPD784035(A), 784036(A)
A8-A19 AD0-AD7 ANI0-ANI7 ANO0, ANO1 ASCK, ASCK2 ASTB AVDD AVREF1-AVREF3 AVSS CLKOUT HLDAK HLDRQ INTP0-INTP5 P00-P07 P10-P17 P20-P27 P30-P37 P40-P47 P50-P57 Address Address/data Analog input Analog output Asynchronous serial clock Address strobe Analog power supply Reference voltage Analog ground Clock input Clock output Hold acknowledge Hold request Interrupt from peripherals Non-maskable interrupt Port Port Port Port Port Port P60-P67 P70-P77 REFRQ RESET RxD, RxD2 SCK0-SCK2 SI0-SI2 SO0-SO2 TEST TO0-TO3 TxD, TxD2 VDD0, VDD1 VSS0, VSS1 WAIT Port Port Read strobe Refresh request Reset Receive data Serial clock Serial clock Serial data Serial input Serial output Test Timer output Transmit data Power supply Ground Wait Write strobe Crystal
PWM0, PWM1 Pulse width modulation output
µPD784035(A), 784036(A)
BLOCK DIAGRAM
UART/IOE2 INTP0-INTP5 Programmable interrupt controller Baud-rate generator UART/IOE1 INTP3 Timer/counter bits) Baud-rate generator
RxD/SI1 TxD/SO1 ASCK/SCK1 RxD2/SI2 TxD2/SO2 ASCK2/SCK2
SCK0/SCL INTP0 Timer/counter bits) core Clocked serial interface SO0/SDA Clock output ASTB/CLKOUT AD0-AD7 A8-A15 interface Timer bits) A16-A19 WAIT/HLDRQ REFRQ/HLDAK P00-P07
INTP1 INTP2/CI
Timer/counter bits)
P00-P03 Real-time output port P04-P07 PWM0 PWM1 ANO0 ANO1 AVREF2 AVREF3
Port
Port
P10-P17
Port Port
P20-P27 P30-P37 P40-P47 P50-P57 P60-P67 P70-P77 RESET TEST VDD0, VDD1 VSS0, VSS1
converter
Port Port
ANI0-ANI7 AVDD AVREF1 AVSS INTP5 Watchdog timer converter
Port Port
System control
Remark internal capacity differs each product.
µPD784035(A), 784036(A)
LIST FUNCTIONS
Port Pins (1/2)
P00-P07 Dual-function Port (P0): 8-bit port. Functions real-time output port bits Inputs outputs specified bit. pull-up resistors specified software pins input mode together. drive transistor. P15-P17 P34-P37 P40-P47 Input INTP0 INTP1 INTP2/CI INTP3 INTP4/ASCK/SCK1 INTP5 RxD/SI1 TxD/SO1 SCK0/SCL SO0/SDA TO0-TO3 AD0-AD7 PWM0 PWM1 ASCK2/SCK2 RxD2/SI2 TxD2/SO2 Port (P1): 8-bit port. Inputs outputs specified bit. pull-up resistors specified software pins input mode together. drive LED. Port (P2): 8-bit input-only port. does function general-purpose port (nonmaskable interrupt). However, input level checked interrupt service routine. pull-up resistors specified software pins units bits). P25/INTP4/ASCK/SCK1 functions SCK1 output CSIM1. Port (P3): 8-bit port. Inputs outputs specified bit. pull-up resistors specified software pins input mode together. Port (P4): 8-bit port. Inputs outputs specified bit. pull-up resistors specified software pins input mode together. drive LED. P50-P57 A8-A15 Port (P5): 8-bit port. Inputs outputs specified bit. pull-up resistors specified software pins input mode together. drive LED. Function
µPD784035(A), 784036(A)
Port Pins (2/2)
P60-P63 P70-P77
Dual-function A16-A19 WAIT/HLDRQ REFRQ/HLDAK Port (P6): 8-bit port.
Function
Inputs outputs specified bit. pull-up resistors specified software pins input mode together. Port (P7): 8-bit port. Inputs outputs specified bit.
ANI0-ANI7
µPD784035(A), 784036(A)
Non-Port Pins (1/2)
TO0-TO3 RXD2 TXD2 ASCK ASCK2 SCK0 SCK1 SCK2 INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 AD0-AD7 A8-A15 A16-A19 WAIT REFRQ HLDRQ HLDAK ASTB CLKOUT Output Output Output Output Input Output Input Output Output Output Input Output Input Input Output Output Input Input Dual-function P34-P37 P23/INTP2 P30/SI1 P13/SI2 P31/SO1 P14/SO2 P25/INTP4/SCK1 P12/SCK2 P33/SO0 P30/RXD P13/RXD2 P33/SDA P31/TXD P14/TXD2 P32/SCL P25/INTP4/ASCK P12/ASCK2 P32/SCK0 P23/CI P25/ASCK/SCK1 P40-P47 P50-P57 P60-P63 P66/HLDRQ P67/HLDAK P66/WAIT P67/REFRQ CLKOUT ASTB Timer output Input count clock timer/counter Serial data input (UART0) Serial data input (UART2) Serial data output (UART0) Serial data output (UART2) Baud rate clock input (UART0) Baud rate clock input (UART2) Serial data (2-wire serial I/O) Serial data input (3-wire serial I/O0) Serial data input (3-wire serial I/O1) Serial data input (3-wire serial I/O2) Serial data output (3-wire serial I/O0) Serial data output (3-wire serial I/O1) Serial data output (3-wire serial I/O2) Serial clock (3-wire serial I/O0) Serial clock (3-wire serial I/O1) Serial clock (3-wire serial I/O2) Serial clock (2-wire serial I/O) External interrupt reguest Input count clock timer/counter Capture/trigger signal CR11 CR12 Input count clock timer/counter Capture/trigger signal CR22 Input count clock timer/counter Capture/trigger signal CR21 Input count clock timer/counter Capture/trigger signal CR02 Input conversion start trigger converter Time multiplexing address/data (for connecting external memory) High-order address (for connecting external memory) High-order address during address expansion (for connecting external memory) Strobe signal output reading contents external memory Strobe signal output writing external memory Wait signal insertion Refresh pulse output external pseudo static memory Input hold request Output hold response Latch timing output time multiplexing address (A0-A7) (for connecting external memory) Clock output Function
µPD784035(A), 784036(A)
Non-Port Pins (2/2)
RESET ANI0-ANI7 ANO0, ANO1 AVREF1 AVREF2, AVREF3 AVDD AVSS VDD0Note VDD1Note VSS0Note VSS1Note TEST Input Input Input Output P70-P77 Dual-function Chip reset Crystal input system clock oscillation clock pulse also input pin.) Analog voltage inputs converter Analog voltage outputs converter Application converter reference voltage Application converter reference voltage Positive power supply converter Ground converter Positive power supply port part Positive power supply except port part Ground port part Ground except port part Directly connect VSS0. (The TEST test.) Function
Notes potential VDD0 must equal that VDD1 pin. potential VSS0 must equal that VSS1 pin.
µPD784035(A), 784036(A)
Circuits Pins Handling Unused Pins
Table describes types circuits pins handling unused pins. Figure configuration these various types circuits. Table 5-1. Types Circuits Pins Handling Unused Pins (1/2)
P00-P07 P10/PWM0 P11/PWM1 P12/ASCK2/SCK2 P13/RxD2/SI2 P14/TxD2/SO2 P15-P17 P20/NMI P21/INTP0 P22/INTP1 P23/INTP2/CI P24/INTP3 P25/INTP4/ASCK/SCK1
circuit type
Recommended connection method unused pins Input state Connect these pins VDD0. Output state: Leave open.
Input
Connect these pins VDD0 VSS0.
Connect these pins VDD0.
Input state Connect these pins VDD0. Output state: Leave open.
P26/INTP5 P27/SI0 P30/RxD/SI1 P31/TxD/SO1 P32/SCK0/SCL P33/SO0/SDA P34/TO0-P37/TO3 P40/AD0-P47/AD7 P50/A8-P57/A15 P60/A16-P63/A19 P64/RD P65/WR P66/WAIT/HLDRQ P67/REFRQ/HLDAK P70/ANI0-P77/ANI7
Input
Connect these pins VDD0.
Input state Connect these pins VDD0. Output state: Leave open.
10-B
20-A
Input state Connect these pins VDD0 VSS0. Output state: Leave open.
ANO0, ANO1 ASTB/CLKOUT
Output
Leave open.
µPD784035(A), 784036(A)
Table 5-1. Types Circuits Pins Handling Unused Pins (2/2)
RESET TEST AVREF1-AVREF3 AVSS AVDD
circuit type
Input
Recommended connection method unused pins Connect this VSS0 directly. Connect these pins VSS0.
Connect this VDD0.
Caution When mode dual-function unpredictable, connect VDD0 through resistor kilohms (particularly when voltage reset input becomes higher than that level input power-on when switched software). Remark Since type numbers consistent series, those numbers always serial each product. (Some circuits included.)
µPD784035(A), 784036(A)
Figure 5-1. Circuits Pins
Type
VDD0
Type
VDD0
Pull-up enable
VSS0
Type
Schmitt trigger input with hysteresis characteristics
Type Schmitt trigger input with hysteresis characteristics Type
VDD0 Pull-up enable Data
VDD0 Data
VDD0 IN/OUT
Output disable
VSS0
Output disable Input enable
VSS0
Push-pull output which output high impedance (both positive negative channels off.)
Type
VDD0 Pull-up enable Data
Type
VDD0 IN/OUT
Analog output voltage
Output disable
VSS0
Type 10-B VDD0
Type 20-A
Data
VDD0 IN/OUT
Pull-up enable VDD0 Data Open drain Output disable
Output disable VSS0
IN/OUT VSS0
Comparator AVREF AVSS (Threshold voltage) Input enable
µPD784035(A), 784036(A)
ARCHITECTURE
Memory Space
1M-byte memory space accessed. using LOCATION instruction, mode mapping internal data areas (special function registers internal RAM) selected. LOCATION instruction must always executed after reset, used only once. When LOCATION instruction executed Internal memory table below indicates internal data areas internal areas each product.
Product name Internal data area 0F700H-0FFFFH Internal area 00000H-0BFFFH 00000H-0F6FFH
µPD784035(A) µPD784036(A)
Caution following internal areas, existing same addresses internal data areas, cannot used when LOCATION instruction executed:
Product name
Unusable area 0F700H-0FFFFH bytes)
µPD784035(A) µPD784036(A)
External memory External memory accessed external memory expansion mode. When LOCATION instruction executed Internal memory table below lists internal data areas internal areas each product.
Product name Internal data area FF700H-FFFFFH Internal area 00000H-0BFFFH 00000H-0FFFFH
µPD784035(A) µPD784036(A)
External memory External memory accessed external memory expansion mode.
Figure 6-1. µPD784035(A) Memory
When LOCATION instruction executed
When LOCATION instruction executed
Special function registers (SFRs) Note (256 bytes)
External memory (960K bytes)Note General-purpose registers (128 bytes) Macro service control word area bytes) Data area (512 bytes) External memory bytes)Note Program/data area (48K bytes)
Note
Internal bytes)
Special function registers (SFRs)
Note
(256 bytes)
Internal bytes)
Program/data area bytes)
External memory (997 bytes)Note
µPD784035(A), 784036(A)
CALLF entry area bytes)
Note
Internal (48K bytes)
CALLT table area bytes) Vector table area bytes)
Internal (48K bytes)
Notes Accessed external memory expansion mode.
Base area, entry area based reset interrupt. Internal excluded case reset.
When LOCATION instruction executed External memory (960K bytes)Note FFDFH FFD0
Special function registers (SFRs)
Note
Figure 6-2. µPD784036(A) Memory
When LOCATION instruction executed
Special function registers (SFRs)
Note
(256 bytes)
General-purpose registers (128 bytes) Macro service control word area bytes) Data area (512 bytes) Internal bytes) Program/data area bytes)
Internal bytes)
(256 bytes)
External memory (980 bytes)Note
Note
Program/data areaNote Internal bytes)
Note
CALLF entry area bytes) CALLT table area bytes) Vector table area
µPD784035(A), 784036(A)
Internal (64K bytes)
Note
bytes)
Notes Accessed external memory expansion mode. This 2304-byte area used internal area only when LOCATION instruction executed. When LOCATION instruction executed bytes When LOCATION instruction executed: bytes Base area, entry area based reset interrupt. Internal excluded case reset.
µPD784035(A), 784036(A)
6.2.1 Registers General-purpose registers
general-purpose registers consists sixteen general-purpose 8-bit registers. 8-bit general-purpose registers combined form 16-bit general-purpose register. Moreover, four 16-bit general-purpose registers, when combined with 8-bit register address extension, used 24-bit address specification registers. Eight banks this register provided. user switch between banks software context switching function. General-purpose registers other than registers used address extension mapped onto internal RAM. Figure 6-3. General-Purpose Register Format
(R1) (RP0) (R3) (RP1) (RG4) (RP4)
(R0) (R2)
(RG5) (RP5) (R13) (R12) (RG6) (RP6) (R15) (R14) (RG7) (RP7) character strings enclosed parentheses represent absolute names. banks
Caution setting RP2, used registers, respectively. However, this function must used only when using programs 78K/III series.
µPD784035(A), 784036(A)
6.2.2 Control registers
Program counter (PC) This register 20-bit program counter. program counter automatically updated program execution. Figure 6-4. Format Program Counter (PC)
Program status word (PSW) This register holds state. program status word automatically updated program execution. Figure 6-5. Format Program Status Word (PSW)
PSWH PSWL RSSNote RBS2 RBS1 RBS0
Note This flag used maintain compatibility with 78K/III series. This flag must when programs 78K/III series being used. Stack pointer (SP) This register 24-bit pointer holding start address stack. high-order bits must Figure 6-6. Format Stack Pointer (SP)
µPD784035(A), 784036(A)
6.2.3 Special function registers (SFRs)
special function registers registers with special functions such mode registers control registers built-in peripheral hardware. special function registers mapped onto 256-byte space between 0FF00H 0FFFFHNote. Note Applicable when LOCATION instruction executed. FFF00H-FFFFFH when LOCATION instruction executed. Caution Never attempt access addresses this area where allocated. Otherwise,
µPD784036(A) placed deadlock state. deadlock state cleared only
reset. Table lists special function registers (SFRs). titles table columns explained below. Abbreviation Symbol used represent built-in SFR. abbreviations listed table reserved words assembler (RA78K4). compiler (CC78K4) allows abbreviations used variables with #pragma command. Indicates whether each allows read and/or write operations. Allows both read write operations. Allows read operations only. Allows write operations only.
Manipulatable bits Indicates maximum number bits that manipulated whenever manipulated. that supports 16-bit manipulation described sfrp operand. address specification, even-numbered address must specified. that supports 1-bit manipulation described manipulation instruction. When reset Indicates state each register when RESET applied.
µPD784035(A), 784036(A)
Table 6-1. Special Function Registers (SFRs) (1/4)
Manipulatable bits AddressNote 0FF00H 0FF01H 0FF02H 0FF03H 0FF04H 0FF05H 0FF06H 0FF07H 0FF0EH 0FF0FH 0FF10H 0FF12H 0FF14H 0FF15H 0FF16H 0FF17H 0FF18H 0FF19H 0FF1AH 0FF1BH 0FF1CH 0FF1DH 0FF20H 0FF21H 0FF23H 0FF24H 0FF25H 0FF26H 0FF27H 0FF2EH 0FF30H 0FF31H 0FF32H 0FF33H Port buffer register Compare register (timer/counter Capture/compare register (timer/counter Compare register (timer/counter Compare register (timer/counter Capture/compare register (timer/counter Capture/compare register (timer/counter Compare register (timer/counter Compare register (timer/counter Capture/compare register (timer/counter Capture/compare register (timer/counter Compare register (timer Compare register (timer Port mode register Port mode register Port mode register Port mode register Port mode register Port mode register Port mode register Real-time output port control register Capture/compare control register Timer output control register Capture/compare control register Capture/compare control register Special function register (SFR) name Port Port Port Port Port Port Port Port Abbreviation Port buffer register CR00 CR01 CR10 CR10W CR11 CR11W CR20 CR20W CR21 CR21W CR30 CR30W RTPC CRC0 CRC1 CRC2 bits bits Undefined Undefined When reset
Note Applicable when LOCATION instruction executed. When LOCATION instruction executed, F0000H added each address.
µPD784035(A), 784036(A)
Table 6-1. Special Function Registers (SFRs) (2/4)
Manipulatable bits AddressNote 0FF36H 0FF38H 0FF39H 0FF3AH 0FF3BH 0FF41H 0FF43H 0FF4EH 0FF50H 0FF51H 0FF52H 0FF53H 0FF54H 0FF55H 0FF56H 0FF57H 0FF5CH 0FF5DH 0FF5EH 0FF5FH 0FF60H 0FF61H 0FF62H 0FF68H 0FF6AH 0FF70H 0FF71H 0FF72H 0FF74H 0FF7DH 0FF80H 0FF81H 0FF82H Prescaler mode register Timer control register Prescaler mode register Timer control register conversion value setting register conversion value setting register converter mode register converter mode register conversion result register control register prescaler register modulo register modulo register One-shot pulse output control register control register Prescaler mode register serial clock Synchronous serial interface mode register Timer register Timer register Timer register PRM0 TMC0 PRM1 TMC1 DACS0 DACS1 ADCR PWMC PWPR PWM0 PWM1 OSPC IICC SPRM CSIM TM3W TM2W TM1W Special function register (SFR) name Capture register (timer/counter Capture register (timer/counter Capture register (timer/counter Capture register (timer/counter Capture register (timer/counter Port mode control register Port mode control register Register optional pull-up resistor Timer register Abbreviation CR02 CR12 CR12W CR22 CR22W PMC1 PMC3 RNote Undefined Undefined 0000H bits bits 0000H When reset
Notes Applicable when LOCATION instruction executed. When LOCATION instruction executed, F0000H added each address. Some registers cannot read. Refer µPD78038, µPD784038Y Sub-Series User's Manual, Hardware details.
µPD784035(A), 784036(A)
Table 6-1. Special Function Registers (SFRs) (3/4)
Manipulatable bits AddressNote 0FF84H 0FF85H 0FF86H 0FF88H 0FF89H 0FF8AH 0FF8BH 0FF8CH Special function register (SFR) name Synchronous serial interface mode register Synchronous serial interface mode register Serial shift register Asynchronous serial interface mode register Asynchronous serial interface mode register Asynchronous serial interface status register Asynchronous serial interface status register Serial receive buffer: UART0 Serial transmission shift register: UART0 Serial shift register: IOE1 0FF8DH Serial receive buffer: UART2 Serial transmission shift register: UART2 Serial shift register: IOE2 0FF90H 0FF91H 0FFA0H 0FFA1H 0FFA4H 0FFA8H 0FFAAH 0FFACH 0FFADH 0FFAEH 0FFC0H 0FFC2H 0FFC4H 0FFC5H 0FFC6H 0FFC7H 0FFC8H Baud rate generator control register Baud rate generator control register External interrupt mode register External interrupt mode register Sampling clock selection register In-service priority register Interrupt mode control register Interrupt mask register Interrupt mask register Interrupt mask register Standby control register Watchdog timer mode register Memory expansion mode register Hold mode register Clock output mode register Programmable wait control register Programmable wait control register Abbreviation CSIM1 CSIM2 ASIM ASIM2 ASIS ASIS2 SIO1 RXB2 TXS2 SIO2 BRGC BRGC2 INTM0 INTM1 SCS0 ISPR MK0L MK0H MK1L STBC HLDM CLOM PWC1 PWC2 Note Note
bits bits
When reset
Undefined
FFFFH
AAAAH
Notes Applicable when LOCATION instruction executed. When LOCATION instruction executed, F0000H added each address. write operation performed only with special instructions STBC, #byte WDM,#byte. Other instructions cannot perform write operation.
µPD784035(A), 784036(A)
Table 6-1. Special Function Registers (SFRs) (4/4)
Manipulatable bits AddressNote 0FFCCH 0FFCDH 0FFCFH 0FFD0H0FFDFH 0FFE0H 0FFE1H 0FFE2H 0FFE3H 0FFE4H 0FFE5H 0FFE6H 0FFE7H 0FFE8H 0FFE9H 0FFEAH 0FFEBH 0FFECH 0FFEDH 0FFEEH 0FFEFH Interrupt control register (INTP0) Interrupt control register (INTP1) Interrupt control register (INTP2) Interrupt control register (INTP3) Interrupt control register (INTC00) Interrupt control register (INTC01) Interrupt control register (INTC10) Interrupt control register (INTC11) Interrupt control register (INTC20) Interrupt control register (INTC21) Interrupt control register (INTC30) Interrupt control register (INTP4) Interrupt control register (INTP5) Interrupt control register (INTAD) Interrupt control register (INTSER) Interrupt control register (INTSR) Interrupt control register (INTCSI1) 0FFF0H 0FFF1H 0FFF2H 0FFF3H Interrupt control register (INTST) Interrupt control register (INTCSI) Interrupt control register (INTSER2) Interrupt control register (INTSR2) Interrupt control register (INTCSI2) 0FFF4H Interrupt control register (INTST2) PIC0 PIC1 PIC2 PIC3 CIC00 CIC01 CIC10 CIC11 CIC20 CIC21 CIC30 PIC4 PIC5 ADIC SERIC SRIC CSIIC1 STIC CSIIC SERIC2 SRIC2 CSIIC2 STIC2 Special function register (SFR) name Refresh mode register Refresh area specification register Oscillation settling time specification register External area Abbreviation OSTS bits bits When reset
Note Applicable when LOCATION instruction executed. When LOCATION instruction executed, F0000H added each address.
µPD784035(A), 784036(A)
PERIPHERAL HARDWARE FUNCTIONS
Ports
ports shown Figure provided enable application wide-ranging control. Table lists functions ports. inputs port port built-in pull-up resistor specified software. Figure 7-1. Port Configuration
Port Port
P20-P27
Port
Port Port Port Port Port
µPD784035(A), 784036(A)
Table 7-1. Port Functions
Port name Port
P00-P07
Function Bit-by-bit input/output setting supported Operable 4-bit real-time outputs (P00-P03, P04-P07) Capable driving transistors
Pull-up specification software Specified batch pins placed input mode.
Port
P10-P17
Bit-by-bit input/output setting supported Capable driving LEDs Input port Bit-by-bit input/output setting supported
Specified batch pins placed input mode. Specified bits (P22-P27) batch. Specified batch pins placed input mode. Specified batch pins placed input mode. Specified batch pins placed input mode. Specified batch pins placed input mode.
Port Port
P20-P27 P30-P37
Port
P40-P47
Bit-by-bit input/output setting supported Capable driving LEDs Bit-by-bit input/output setting supported Capable driving LEDs
Port
P50-P57
Port
P60-P67
Bit-by-bit input/output setting supported
Port
P70-P77
Bit-by-bit input/output setting supported
Clock Generator
circuit generating clock signal required operation provided. clock generator includes frequency divider; current consumption achieved operating lower internal frequency when high-speed operation necessary. Figure 7-2. Block Diagram Clock Generator
Oscillator
Selector
fCLK Peripheral circuits
fXX/2 UART/IOE INTP0 noise eliminator Oscillation settling timer
Remark Oscillator frequency external clock input fCLK Internal operating frequency
µPD784035(A), 784036(A)
Figure 7-3. Examples Using Oscillator Crystal/ceramic oscillation
PD784036(A)
VSS1
External clock When EXTC OSTS When EXTC OSTS
PD784036(A)
PD784036(A)
PD74HC04, etc.
Open
Caution When using clock generator, avoid problems caused influences such stray capacitance, wiring within area indicated dotted lines according following rules: Minimize wiring length. Wires must never cross other signal lines. Wires must never near line carrying large varying current. grounding point capacitor oscillator must always same potential VSS1. Never connect capacitor ground pattern carrying large current. Never extract signal from oscillator.
µPD784035(A), 784036(A)
Real-Time Output Port
real-time output port outputs data stored buffer, synchronized with timer/counter match interrupt external interrupt. Thus, pulse output that free jitter obtained. Therefore, real-time output port best suited applications (such open-loop control over stepping motors) where arbitrary pattern output arbitrary intervals. shown Figure 7-4, real-time output port built around port port buffer register (P0H, P0L). Figure 7-4. Block Diagram Real-Time Output Port
Internal
Real-time output port control register (RTPC) INTP0 (externally) INTC10 (from timer/counter INTC11 (from timer/counter
Buffer register
Output trigger control circuit
Output latch (P0)
µPD784035(A), 784036(A)
Timers/Counters
Three timer/counter units timer unit incorporated. Moreover, seven interrupt requests supported, allowing these units function seven timer/counter units. Table 7-2. Timer/Counter Operation
Name Item Count pulse width bits bits Operating mode Interval timer External event counter One-shot timer Function Timer output Toggle output PWM/PPG output One-shot pulse outputNote Real-time output Pulse width measurement Number interrupt requests input input inputs
Timer/counter
Timer/counter
Timer/counter
Timer
Note one-shot pulse output function makes level pulse output active software, makes level pulse output inactive hardware (interrupt request signal). Note that this function differs from one-shot timer function timer/counter
µPD784035(A), 784036(A)
Figure 7-5. Timer/Counter Block Diagram Timer/counter
Clear information
Software trigger
Selector
fxx/8
Prescaler
Timer register (TM0)
Compare register (CR00)
Pulse output control
Match Match
Compare register (CR01)
INTP3
Edge detection
Capture register (CR02)
INTP3
INTC00 INTC01
Timer/counter
Clear information
Selector
fxx/8
Prescaler Event input
Timer register (TM1/TM1W)
Match
Compare register (CR10/CR10W)
INTP0
Edge detection
Capture/compare register (CR11/CR11W)
Match
INTC10 real-time output port INTC11
INTP0
Capture register (CR12/CR12W)
Timer/counter
Clear information
Selector
fxx/8
Prescaler
Timer register (TM2/TM2W)
Pulse output control
Match
INTP2/CI
Edge detection
Compare register (CR20/CR20W)
INTP2
Capture/compare register (CR21/CR21W)
Match
INTP1
Edge detection
Capture register (CR22/CR22W)
INTC20 INTC21
INTP1
Timer
fxx/8 Prescaler
Timer register (TM3/TM3W)
Clear
Compare register (CR30/CR30W)
Match
INTC30
Remark OVF: Overflow flag
µPD784035(A), 784036(A)
Output (PWM0, PWM1)
channels (pulse width modulation) output circuitry with resolution bits repetition frequency 62.5 (fCLK MHz) incorporated. high active level selected output channels, independently each other. This output best suited motor speed control. Figure 7-6. Block Diagram Output Unit
Internal modulo register PWMn Reload control control register (PWMC)
fCLK
Prescaler
8-bit down-counter
Pulse control circuit 4-bit counter
Output control
PWMn (output pin)
1/256
Remark
µPD784035(A), 784036(A)
Converter
analog/digital (A/D) converter having multiplexed analog inputs (ANI0-ANI7) incorporated. successive approximation system used conversion. result conversion held 8-bit conversion result register (ADCR). Thus, speedy high-precision conversion achieved. (The conversion time about fCLK MHz.) conversion started following modes: Hardware start Conversion started means trigger input (INTP5). Software start Conversion started means setting converter mode register (ADM). After conversion started, following modes selected: Scan mode Multiple analog inputs selected sequentially obtain conversion data from pins. Select mode: single analog input selected times enable conversion data obtained continuously. used specify above modes, well termination conversion. When result conversion transferred ADCR, interrupt request (INTAD) generated. Using this feature, results conversion continuously transferred memory macro service. Figure 7-7. Block Diagram Converter
ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7
Input selector
Sample-and-hold circuit
Series resistor string AVREF1 Voltage comparator
Successive conversion register (SAR) Edge detector Conversion trigger INTAD
INTP5
Control circuit
selector AVSS
Trigger enable converter mode register (ADM) conversion result register (ADCR)
Internal
µPD784035(A), 784036(A)
Converter
digital/analog (D/A) converter channels voltage output type, having resolution bits, incorporated. R-2R resistor ladder system used conversion. writing value subject conversion 8-bit conversion value setting register (DACSn: resulting analog value output ANOn range output voltages determined voltages applied AVREF2 AVREF3 pins. Because high output impedance, current obtained from output pin. When load impedance low, insert buffer amplifier between load converter. impedance ANOn goes high while RESET signal low. DACSn after reset released. Figure 7-8. Block Diagram Converter
ANOn AVREF2
Selector
AVREF3
DACSn
DACEn
Internal
Remark
µPD784035(A), 784036(A)
Serial Interface
Three independent serial interface channels incorporated.
Asynchronous serial interface (UART)/three-wire serial (IOE) Synchronous serial interface (CSI)
Three-wire serial (IOE) Two-wire serial (IOE) communication with points external system local communication within system performed same time. (See Figure 7-9.) Figure 7-9. Example Serial Interfaces
UART Three-wire serial Two-wire serial
PD784036(A)
Master
[UART]
Slave [Three-wire serial I/O] Port Slave
RS-232-C driver/receiver
Port
SCK1 INTPm Port
Note
INTPn Port [Two-wire serial I/O]
Note
SCK0 Port
Note Handshake line
µPD784035(A), 784036(A)
7.8.1 Asynchronous serial interface/three-wire serial (UART/IOE)
serial interface channels available; each channel, asynchronous serial interface mode three-wire serial mode selected. Asynchronous serial interface mode this mode, 1-byte data transferred after start bit. baud rate generator incorporated enable communication wide range baud rates. Moreover, frequency clock signal applied ASCK divided define baud rate. With baud rate generator, baud rate conforming MIDI standard (31.25 kbps) obtained. Figure 7-10. Block Diagram Asynchronous Serial Interface Mode
Internal
Receive buffer
RXB, RXB2
RxD, RxD2
Receive shift register
Transmission shift register
TXS, TXS2
TxD, TxD2 INTSR, INTSR2 INTSER, INTSER2
Reception control parity check
Transmission control parity addition
INTST, INTST2
Baud rate generator
1/2m fXX/2 ASCK, ASCK2
Selector
1/2n+1 1/2m
Remark fXX: Oscillator frequency external clock input
µPD784035(A), 784036(A)
Three-wire serial mode this mode, master device makes serial clock active start transmission, then transfers 1-byte data phase with clock. This mode designed communication with device incorporating conventional synchronous serial interface. Basically, three lines used communication: serial clock line (SCK) serial data lines SO). general, handshake line required check state communication. Figure 7-11. Block Diagram Three-Wire Serial Mode
Internal
Direction control circuit
SIO1, SIO2 SI1, Shift register Output latch
SO1,
SCK1, SCK2
Serial clock counter
Interrupt signal generator
INTCSI1, INTCSI2
Serial clock control circuit
Remark fXX: Oscillator frequency external clock input
Selector
1/2n+1
fXX/2
µPD784035(A), 784036(A)
7.8.2 Synchronous serial interface (CSI)
With this interface, master device makes serial clock active start transmission, then transfers 1-byte data phase with clock. Figure 7-12. Block Diagram Synchronous Serial Interface
Internal
Direction control circuit
Reset
Selector
SO0/SDA
Shift register
Output latch
N-ch open-drain output enabled (when two-wire mode used) SCK0/SCL Serial clock counter Interrupt signal generator INTCSI
Prescaler
Selector
N-ch open-drain output enabled (when two-wire mode used) CLS0 CLS1
Selector
Serial clock control circuit
Timer output fXX/16
fXX/2
Remark fXX: Oscillator frequency external clock input
µPD784035(A), 784036(A)
Three-wire serial mode This mode designed communication with device incorporating conventional synchronous serial interface. Basically, three lines used communication: serial clock line (SCK0) serial data lines (SI0 SO0). general, handshake line required check state communication. Two-wire serial mode this mode, 8-bit data transferred using lines: serial clock line (SCL) serial data (SDA). general, handshake line required check communication state. Clock Output Function
frequency clock signal divided output point external system. Moreover, port used 1-bit port. ASTB also used CLKOUT pin, that when this function used, local interface cannot used. Figure 7-13. Block Diagram Clock Output Function
fCLK fCLK/2
Selector
fCLK/4 fCLK/8 fCLK/16
Output control
CLKOUT
Enable output
Output level
µPD784035(A), 784036(A)
7.10 Edge Detection Function
interrupt input pins (NMI, INTP0-INTP5) used apply only interrupt requests also trigger signals built-in circuits. these pins triggered edge (rising falling) input signal, function edge detection incorporated. Moreover, noise suppression function provided prevent erroneous edge detection caused noise. Table 7-3. Noise Suppression Method Interrupt Input Pins
INTP0-INTP3 INTP4, INTP5 Detectable edge Rising edge falling edge Rising edge falling edge, both edges Noise suppression method Analog delay Clock samplingNote Analog delay
Note INTP0 used sampling clock selection.
7.11 Watchdog Timer watchdog timer incorporated runaway detection. watchdog timer, cleared software within specified interval, generates nonmaskable interrupt. Furthermore, once watchdog timer operation enabled, cannot disabled software. user specify whether priority placed interrupt based watchdog timer interrupt based pin. Figure 7-14. Block Diagram Watchdog Timer
fCLK
Timer fCLK/221 fCLK/220
Selector
fCLK/219 fCLK/217
INTWDT
Clear signal
µPD784035(A), 784036(A)
INTERRUPT FUNCTION
Table lists interrupt request handling modes. These modes selected software. Table 8-1. Interrupt Request Handling Modes
Handling mode Vectored interrupt
Handled Software
Handling Branches handling routine execution (arbitrary handling). Automatically selects register bank, branches handling routine execution (arbitrary handling).
contents contents pushed popped from stack. contents saved read from fixed area register bank. Maintained
Context switching
Macro service
Firmware
Performs operations such memory-to-I/Odevice data transfer (fixed handling).
Interrupt Source
interrupt issued from interrupt sources listed Table 8-2: execution BRKCS instructions, operand error, other interrupt sources. Four levels interrupt handling priority set. Priority levels nest control during interrupt handling concurrently generate interrupt requests. Nested macro services, however, performed without suspension. When interrupt requests having same priority level generated, they handled according default priority (fixed). (See Table 8-2.)
µPD784035(A), 784036(A)
Table 8-2. Interrupt Sources
Type
Default priority Name instruction BRKCS instruction Operand error
Source Trigger Instruction execution
Internal/ external
Macro service
Software
When STBC,#byte, WDM,#byte, LOCATION instruction executed, exclusive byte operand byte does produce FFH. Detection edge input Watchdog timer overflow Detection edge input (TM1/TM1W capture trigger, TM1/TM1W event counter input) Detection edge input (TM2/TM2W capture trigger, TM2/TM2W event counter input) Detection edge input (TM2/TM2W capture trigger, TM2/TM2W event counter input) Detection edge input (TM0 capture trigger, event counter input) TM0-CR00 match signal issued TM0-CR01 match signal issued TM1-CR10 match signal issued 8-bit operation mode) TM1W-CR10W match signal issued 16-bit operation mode) TM1-CR11 match signal issued 8-bit operation mode) TM1W-CR11W match signal issued 16-bit operation mode) TM2-CR20 match signal issued 8-bit operation mode) TM2W-CR20W match signal issued 16-bit operation mode) TM2-CR21 match signal issued 8-bit operation mode) TM2W-CR21W match signal issued 16-bit operation mode) TM3-CR30 match signal issued 8-bit operation mode) TM3W-CR30W match signal issued 16-bit operation mode) Detection edge input Detection edge input converter processing completed (ADCR transfer) ASI0 reception error ASI0 reception completed CSI1 transfer completed Internal Enabled Enabled External Enabled Internal Enabled External Internal External Enabled
Nonmaskable
Maskable
(highest)
INTP0
INTP1
INTP2
INTP3
INTC00 INTC01 INTC10
INTC11
INTC20
INTC21
INTC30
INTP4 INTP5 INTAD INTSER INTSR INTCSI1
INTST INTCSI INTSER2 INTSR2 INTCSI2
ASI0 transmission completed CSI0 transfer completed ASI2 reception error ASI2 reception completed CSI2 transfer completed Enabled
(lowest)
INTST2
ASI2 transmission completed
Remark ASI: Asynchronous serial interface CSI: Synchronous serial interface
µPD784035(A), 784036(A)
Vectored Interrupt
When branch interrupt handling routine occurs, vector table address corresponding interrupt source used branch address. Interrupt handling consists following operations: When branch occurs Push status contents) stack.
When control returned status contents) from stack. return control from handling routine main routine, RETI instruction. branch destination addresses must within range FFFFH. Table 8-3. Vector Table Address
Interrupt source instruction Operand error INTP0 INTP1 INTP2 INTP3 INTC00 INTC01 INTC10 INTC11 INTC20 INTC21 INTC30 INTP4 INTP5 INTAD INTSER INTSR INTCSI1 INTST INTCSI INTSER2 INTSR2 INTCSI2 INTST2
Vector table address 003EH 003CH 0002H 0004H 0006H 0008H 000AH 000CH 000EH 0010H 0012H 0014H 0016H 0018H 001AH 001CH 001EH 0020H 0022H 0024H
0026H 0028H 002AH 002CH
002EH
µPD784035(A), 784036(A)
Context Switching
When interrupt request generated, when BRKCS instruction executed, appropriate register bank selected hardware. Then, branch vector address stored that register bank occurs. same time, contents current program counter (PC) program status word (PSW) stacked register bank. branch address must within range FFFFH. Figure 8-1. Context Switching Caused Interrupt Request
0000B Transfer PC19-16 PC15-0 Exchange Register bank 0-7) Save (Bits temporary register) Save Temporary register Save Switching between register banks (RBS0-RBS2 Register bank (0-7)
Macro Service
macro service function enables data transfer between memory special function registers (SFRs) without requiring intervention CPU. macro service controller accesses both memory SFRs within same transfer cycle directly transfer data without having perform data fetch. Since status neither saved restored, data fetch performed, high-speed data transfer possible. Figure 8-2. Macro Service
Read Memory Write
Macro service controller
Write Read
Internal
µPD784035(A), 784036(A)
Examples Macro Service Applications
Serial interface transmission
Transmission data storage buffer (memory) Data Data
Data Data
Internal
Transmission shift register
(SFR)
Transmission control
INTST
Each time macro service request (INTST) generated, next transmission data transferred from memory TXS. When data (last byte) been transferred (that once transmission data storage buffer becomes empty), vectored interrupt request (INTST) generated. Serial interface reception
Reception data storage buffer (memory) Data Data
Data Data
Internal
Reception buffer
(SFR)
Reception shift register
Reception control
INTSR
Each time macro service request (INTSR) generated, reception data transferred from memory. When data (last byte) been transferred memory (that once reception data storage buffer becomes full), vectored interrupt request (INTSR) generated.
µPD784035(A), 784036(A)
Real-time output port INTC10 INTC11 function output triggers real-time output ports. these triggers, macro service simultaneously next output pattern interval. Therefore, INTC10 INTC11 used independently control stepping motors. They also applied motor control.
Output pattern profile (memory) Pn-1 Output timing profile (memory) Tn-1
Internal
Internal
Match (SFR) INTC10 Output latch P00-P03 CR10 (SFR)
Each time macro service request (INTC10) generated, pattern timing data transferred buffer register (P0L) compare register (CR10), respectively. When contents timer register (TM1) CR10 match, another INTC10 generated, contents transferred output latch. When (last byte) transferred CR10, vectored interrupt request (INTC10) generated. INTC11, same operation that performed INTC10 performed.
µPD784035(A), 784036(A)
LOCAL INTERFACE
local interface enables connection external memory devices (memory-mapped I/O). supports 1M-byte memory space. (See Figure 9-1.) Figure 9-1. Example Local Interface
PD784036(A)
A16-A19
REFRQ
Decoder
Pseudo SRAM
PROM PD27C1001A
Kanji character generator µPD24C1000
AD0-AD7
Data Data
ASTB
Latch
Address A8-A15 Gate array expansion including Centronics interface circuit, etc.
Memory Expansion
adding external memory, program memory data memory expanded seven sizes between bytes approximately byte.
µPD784035(A), 784036(A)
Memory Space
1M-byte memory space divided into eight spaces, each having logical address. Each these spaces controlled using programmable wait pseudo-static refresh functions. Figure 9-2. Memory Space
FFFFFH
512K bytes
80000H 7FFFFH 256K bytes 40000H 3FFFFH 128K bytes 20000H 1FFFFH bytes 10000H 0FFFFH bytes 0C000H 0BFFFH bytes 08000H 07FFFH bytes 04000H 03FFFH bytes 00000H
µPD784035(A), 784036(A)
Programmable Wait
When memory space divided into eight spaces, wait state separately inserted each memory space while signal active. This prevents overall system efficiency from being degraded even when memory devices having different access times connected. addition, address wait function that extends ASTB signal active period provided assure longer address decode time. (This function entire space.) Pseudo-Static Refresh Function
Refresh performed follows: Pulse refresh cycle inserted where refresh pulse output REFRQ regular intervals. When memory space divided into eight, specified area being accessed, refresh pulses also output REFRQ memory being accessed. This prevent refresh cycle from suspending normal memory access. Power-down self-refresh standby mode, low-level signal output REFRQ maintain contents pseudo-static RAM. Hold Function
hold function provided facilitate connection devices such controller. Suppose that hold request signal (HLDRQ) received from external master. this case, upon completion cycle being performed reception, address bus, address/data bus, ASTB, pins placed high-impedance state, hold acknowledge signal (HLDAK) made active release external master. While hold function being used, external wait pseudo-static refresh functions disabled.
µPD784035(A), 784036(A)
STANDBY FUNCTION
standby function allows power consumption chip reduced. following standby modes supported: HALT mode operation clock stopped. occasionally inserting HALT mode during normal operation, overall average power consumption reduced. IDLE mode entire system stopped, with exception oscillator. This mode consumes only very little more power than STOP mode, normal program operation restored almost little time that required restore normal program operation from HALT mode. STOP mode oscillator stopped. operations chip stop, such that only leakage current flows. These modes selected software. macro service initiated HALT mode. Figure 10-1. Standby Mode Status Transition
Macro service request Program operation operation macro service Macro service
Wait oscillation settling
ttling tion Oscilla time
STOP (standby)
IDLE (standby)
Request masked interrupt
HALT (standby)
Notes INTP4 INTP5 applied when masked. Only when interrupt request masked Remark enabled only external input. watchdog timer cannot used release standby modes (STOP, HALT, IDLE mode).
µPD784035(A), 784036(A)
RESET FUNCTION
Applying low-level signal RESET initializes internal hardware (reset status). When RESET input makes low-to-high transition, following data loaded into program counter (PC): Eight low-order bits Four high-order bits Contents location address 0000H
Intermediate eight bits Contents location address 0001H
contents used branch destination address. Program execution starts from that address. Therefore, reset start performed from arbitrary address. contents each register software, required. RESET input circuit contains noise eliminator prevent malfunctions caused noise. This noise eliminator analog delay sampling circuit. Figure 11-1. Accepting Reset
Delay
Delay
Delay
Initialize
Execute instruction reset start address
RESET (input)
Internal reset signal
Start reset
reset
power-on reset, RESET signal must held active until oscillation settling time (approximately elapsed. Figure 11-2. Power-On Reset
Oscillation settling time
Delay
Initialize
Execute instruction reset start address
RESET (input)
Internal reset signal
reset
µPD784035(A), 784036(A)
INSTRUCTION
8-bit instructions (The instructions enclosed parentheses implemented combination operands, where described MOV, XCH, ADD, ADDC, SUB, SUBC, AND, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, SHR, SHL, ROR4, ROL4, DBNZ, PUSH, POP, MOVM, XCHM, CMPME, CMPMNE, CMPMNC, CMPMC, MOVBK, XCHBK, CMPBKE, CMPBKNE, CMPBKNC, CMPBKC, CHKL, CHKLA Table 12-1. Instructions Implemented 8-Bit Addressing
operand
#byte
saddr saddr'
!addr16 !!addr24
[saddrp] [%saddrg]
PSWL PSWH
[WHL+] [WHL-]
NoneNote
operand (MOV) ADDNote (MOV) (XCH) (MOV)Note (XCH)Note (XCH) (MOV) (XCH)
(MOV) (XCH) (ADD)Note RORNote MULU DIVUW
(ADD)Note (ADD)Note (ADD)Notes (ADD)Note ADDNote ADDNote ADDNote (MOV) (XCH) ADDNote ADDNote
(ADD)Note ADDNote
saddr
(MOV)Note
ADDNote
DBNZ PUSH CHKL CHKLA
ADDNote (ADD)Note ADDNote
ADDNote (ADD)Note ADDNote
!addr16 !!addr24 [saddrp] [%saddrg] mem3
(MOV) ADDNote ADDNote
ROR4 ROL4
PSWL PSWH STBC, [TDE+] [TDE-]
DBNZ (MOV) (ADD)Note MOVMNote MOVBKNote
Notes ADDC, SUB, SUBC, AND, XOR, same ADD. There second operand, second operand operand address. ROL, RORC, ROLC, SHR, same ROR. XCHM, CMPME, CMPMNE, CMPMNC, CMPMC same MOVM. XCHBK, CMPBKE, CMPBKNE, CMPBKNC, CMPBKC same MOVBK. When saddr saddr2 with this combination, instruction with short code exists.
µPD784035(A), 784036(A)
16-bit instructions (The instructions enclosed parentheses implemented combination operands, where described rp.) MOVW, XCHW, ADDW, SUBW, CMPW, MULUW, MULW, DIVUX, INCW, DECW, SHRW, SHLW, PUSH, POP, ADDWG, SUBWG, PUSHU, POPU, MOVTBLW, MACW, MACSW, SACW Table 12-2. Instructions Implemented 16-Bit Addressing
operand
#word
saddrp saddrp'
strp
!addr16 !!addr24
[saddrp] [%saddrg]
[WHL+]
byte
NoneNote
operand (MOVW) (MOVW) (MOVW) (XCHW) (MOVW)Note MOVW (MOVW) XCHW
MOVW XCHW
(MOVW) (XCHW)
ADDWNote (XCHW)
(XCHW)Note (XCHW)
(ADD)Note (ADDW)Note (ADDW)Notes (ADDW)Note MOVW (MOVW) MOVW XCHW MOVW XCHW MOVW XCHW MOVW SHRW SHLW MULWNote INCW DECW INCW DECW
ADDWNote (XCHW)
(ADDW)Note ADDWNote ADDWNote ADDWNote saddrp MOVW (MOVW)Note MOVW MOVW ADDWNote sfrp MOVW MOVW MOVW
ADDWNote (ADDW)Note ADDWNote XCHW
PUSH MOVTBLW
ADDWNote (ADDW)Note ADDWNote !addr16 !!addr24 [saddrp] [%saddrg] MOVW MOVW (MOVW) MOVW
PUSH
ADDWG SUBWG
post
PUSH PUSHU POPU
[TDE+] byte
(MOVW)
SACW MACW MACSW
Notes SUBW CMPW same ADDW. There second operand, second operand operand address. When saddrp saddrp2 with this combination, instruction with short code exists. MULUW DIVUX same MULW.
µPD784035(A), 784036(A)
24-bit instructions (The instructions enclosed parentheses implemented combination operands, where described rg.) MOVG, ADDG, SUBG, INCG, DECG, PUSH, Table 12-3. Instructions Implemented 24-Bit Addressing
operand operand
#imm24
saddrg
!!addr24
mem1
[%saddrg]
NoneNote
(MOVG) (ADDG) (SUBG)
(MOVG) (ADDG) (SUBG) (MOVG) (ADDG) (SUBG)
(MOVG) (ADDG) (SUBG) MOVG ADDG SUBG
(MOVG) ADDG SUBG MOVG
(MOVG)
MOVG
MOVG
MOVG
MOVG ADDG SUBG
MOVG
INCG DECG PUSH
saddrg !!addr24 mem1 [%saddrg] MOVG
(MOVG) (MOVG) MOVG MOVG MOVG
MOVG MOVG
INCG DECG
Note There second operand, second operand operand address.
µPD784035(A), 784036(A)
manipulation instructions MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BTCLR, BFSET Table 12-4. Manipulation Instructions Implemented Addressing
operand
saddr.bit sfr.bit A.bit X.bit PSWL.bit PSWH.bit mem2.bit
/saddr.bit /sfr.bit /A.bit /X.bit /PSWL.bit /PSWH.bit /mem2.bit /!addr16.bit AND1 /!!addr24.bit
NoneNote
operand
!addr16.bit !!addr24.bit MOV1 AND1 XOR1
NOT1 SET1 CLR1
saddr.bit sfr.bit A.bit X.bit PSWL.bit PSWH.bit mem2.bit !addr16.bit !!addr24.bit
MOV1
NOT1 SET1 CLR1 BTCLR BFSET
Note There second operand, second operand operand address.
µPD784035(A), 784036(A)
Call/return instructions branch instructions CALL, CALLF, CALLT, BRK, RET, RETI, RETB, RETCS, RETCSB, BRKCS, BNZ, BNE, BNC, BNL, BNV, BPO, BPE, BLT, BGE, BLE, BGT, BNH, BTCLR, BFSET, DBNZ Table 12-5. Call/Return Branch Instructions Implemented Addressing
Instruction address operand Basic instruction
$addr20 $!addr20
!addr16
!!addr20
[rp]
[rg]
!addr11
[addr5]
None
BCNote
CALL
CALL RETCS RETCSB
CALL
CALL
CALL
CALL
CALL
CALLF
CALLF
BRKCS
RETI RETB
Composite instruction BTCLR BFSET DBNZ
Note BNZ, BNE, BNC, BNL, BNV, BPO, BPE, BLT, BGE, BLE, BGT, BNH, same Other instructions ADJBA, ADJBS, CVTBW, LOCATION, SEL, SWRS
µPD784035(A), 784036(A)
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
Parameter Supply voltage Symbol AVDD AVSS Input voltage Output voltage Output current Total output pins Output high current Total output pins converter reference input voltage converter reference input voltage Operating ambient temperature Storage temperature AVREF1 Conditions Rating -0.5 +7.0 AVSS -0.5 +0.5 -0.5 -0.5 -100 -0.5 Unit
AVREF2 AVREF3 Tstg
-0.5 -0.5 +150
Caution Absolute maximum ratings rated values beyond which physical damage will caused product; rated value parameters above table exceeded, even momentarily, quality product deteriorate. Always product within rated values.
µPD784035(A), 784036(A)
OPERATING CONDITIONS Operating ambient temperature (TA) Power supply voltage clock cycle time Figure 13-1. Rise time fall time (tr, pins which specified)
Figure 13-1. Power Supply Voltage Clock Cycle Time
Clock cycle time tCYK [ns]
Guaranteed operating range 62.5
Power supply voltage
CAPACITANCE
Parameter Input capacitance Output capacitance capacitance Symbol pins other than measured pins Conditions MIN. TYP. MAX. Unit
µPD784035(A), 784036(A)
OSCILLATOR CHARACTERISTICS +4.5
Resonator Ceramic resonator crystal Recommended circuit Parameter Oscillator frequency (fXX) MIN. MAX. Unit
VSS1
External clock
input frequency (fX)
input rise fall times (tXR, tXF) input high-level lowlevel widths (tWXH, tWXL)
HCMOS inverter
Caution When using system clock generator, wires portion surrounded broken lines according following rules avoid effects such stray capacitance: Minimize wiring. Never cause wires cross other signal lines. Never cause wires near line carrying large varying current. Cause grounding point capacitor oscillator have same potential VSS1. Never connect capacitor ground pattern carrying large current. Never extract signal from oscillator.
µPD784035(A), 784036(A)
OSCILLATOR CHARACTERISTICS +2.7
Resonator Ceramic resonator crystal Recommended circuit Parameter Oscillator frequency (fXX) MIN. MAX. Unit
VSS1
External clock
input frequency (fX)
input rise fall times (tXR, tXF) input high-level lowlevel widths (tWXH, tWXL)
HCMOS inverter
Caution When using system clock generator, wires portion surrounded broken lines according following rules avoid effects such stray capacitance: Minimize wiring. Never cause wires cross other signal lines. Never cause wires near line carrying large varying current. Cause grounding point capacitor oscillator have same potential VSS1. Never connect capacitor ground pattern carrying large current. Never extract signal from oscillator.
µPD784035(A), 784036(A)
CHARACTERISTICS AVDD +2.7 AVSS (1/2)
Parameter Input voltage Symbol VIL1 Conditions pins other than those described Notes pins described Notes +5.0 pins described Notes pins other than those described Note pins described Note +5.0 pins described Notes +5.0 pins described Notes +5.0 pins described Note EXTC VIL2 EXTC VIH2 MIN. -0.3 TYP. MAX. 0.3VDD Unit
VIL2
-0.3
0.2VDD
VIL3
-0.3
+0.8
Input high voltage
VIH1
0.7VDD
VIH2 VIH3
0.8VDD
Output voltage
VOL1 VOL2
Output high voltage
VOH1 VOH2
input current
input high current
Notes RESET, P12/ASCK2/SCK2, P20/NMI, P21/INTP0, P22/INTP1, P23/INTP2/CI, P24/INTP3, P25/INTP4/ASCK/SCK1, P26/INTP5, P27/SI0, P32/SCK0/SCL, P33/SO0/SDA, TEST P40/AD0-P47/AD7, P50/A8-P57/A15 P60/A16-P63/A19, P64/RD, P65/WR, P66/WAIT/HLDRQ, P67/REFRQ/HLDAK P00-P07 P10-P17
µPD784035(A), 784036(A)
CHARACTERISTICS AVDD +2.7 AVSS (2/2)
Parameter Input leakage current Symbol Conditions pins other than when EXTC Operation mode +5.0 +2.7 IDD2 HALT mode +5.0 +2.7 IDD3 IDLE mode (EXTC +5.0 +2.7 Pull-up resistor MIN. TYP. MAX. Unit
Output leakage current supply current
IDD1
µPD784035(A), 784036(A)
CHARACTERISTICS AVDD +2.7 AVSS Read/write operation (1/2)
Parameter Address setup time Symbol tSAST Conditions +5.0 MIN. (0.5 (0.5 ASTB high-level width tWSTH +5.0 (0.5 (0.5 Address hold time ASTB) tHSTLA +5.0 0.5T 0.5T Address hold time Delay from address tHRA tDAR +5.0 0.5T Address float time tFRA +5.0 (2.5 (2.5 Delay from ASTB data input tDSTID +5.0 Delay from data input tDRID +5.0 (1.5 (1.5 Delay from ASTB Data hold time tDSTR tHRID After program read After data read Delay from ASTB low-level width tDRST tWRL +5.0 +5.0 0.5T 0.5T 0.5T +5.0 1.5T 1.5T 0.5T (1.5 (1.5 Address hold time Delay from address tHWA tDAW +5.0 0.5T Delay from ASTB data output tDSTOD +5.0 0.5T 0.5T Delay from data output Delay from ASTB tDWOD tDSTW 0.5T 0.5T MAX. Unit
Delay from address data input tDAID
Delay from address active tDRA
Remarks TCYK (system clock cycle time) (during address wait), otherwise, Number wait states
µPD784035(A), 784036(A)
Read/write operation (2/2)
Parameter Data setup time Symbol tSODW Conditions +5.0 MIN. (1.5 (1.5 Data hold time WR)Note tHWOD +5.0 0.5T 0.5T Delay from ASTB low-level width tDWST tWWL +5.0 0.5T (1.5 (1.5 MAX. Unit
Note hold time includes time during which VOH1 VOL1 held under load conditions Remarks TCYK (system clock cycle time) Number wait states
hold timing
Parameter Delay from HLDRQ float Symbol tFHQC +5.0 Conditions MIN. MAX. Delay from float HLDAK tDCFHA +5.0 Delay from HLDAK active tDHAC +5.0 Unit
Delay from HLDRQ HLDAK tDHQHHAH
Delay from HLDRQ HLDAK tDHQLHAL
Remarks TCYK (system clock cycle time) (during address wait), otherwise, Number wait states
µPD784035(A), 784036(A)
External wait timing
Parameter Symbol Conditions +5.0 MIN. MAX. Delay from ASTB WAIT input tDSTWT +5.0 1.5T 1.5T Hold time from ASTB WAIT tHSTWTH +5.0 (0.5 (0.5 Delay from ASTB WAIT tDSTWTH +5.0 (1.5 (1.5 Delay from WAIT input tDRWTL +5.0 Hold time from WAIT tHRWT +5.0 Delay from WAIT tDRWTH +5.0 Delay from WAIT data input tDWTID +5.0 0.5T 0.5T Delay from WAIT Delay from WAIT tDWTW tDWTR +5.0 0.5T 0.5T Hold time from WAIT tHWWT +5.0 Delay from WAIT tDWWTH +5.0 Unit
Delay from address WAIT input tDAWT
Delay from WAIT input tDWWTL
Remarks TCYK (system clock cycle time) (during address wait), otherwise, Number wait states
Refresh timing
Parameter Random read/write cycle time REFRQ low-level pulse width Symbol tWRFQL +5.0 Conditions MIN. 1.5T 1.5T Delay from ASTB REFRQ Delay from REFRQ Delay from REFRQ Delay from REFRQ ASTB REFRQ high-level pulse width tDSTRFQ tDRRFQ tDWRFQ tDRFQST tWRFQH +5.0 0.5T 1.5T 1.5T 0.5T 1.5T 1.5T MAX. Unit
Remark TCYK (system clock cycle time)
µPD784035(A), 784036(A)
SERIAL OPERATION +2.7 AVSS
Parameter Symbol Input Conditions External clock When SCK0 CMOS MIN. 10/fXX MAX. Unit
Serial clock cycle time (SCK0) tCYSK0
Output Serial clock low-level width (SCK0) tWSKL0 Input External clock When SCK0 CMOS
5/fXX
Output Serial clock high-level width (SCK0) tWSKH0 Input External clock When SCK0 CMOS
0.5T 5/fXX
Output setup time SCK0) hold time SCK0) output delay time SCK0) tSSSK0 tHSSK0 tDSBSK1 CMOS push-pull output (3-wire serial mode) Open-drain output (2-wire serial mode),
0.5T 5/fXX
tDSBSK2
Remarks values this table those when Serial clock cycle software. minimum value 16/fXX. Oscillator frequency
µPD784035(A), 784036(A)
IOE1, IOE2
Parameter Serial clock cycle time (SCK1, SCK2) Symbol tCYSK1 Input Conditions +5.0 MIN. Output Serial clock low-level width (SCK1, SCK2) tWSKL1 Input Internal, divided +5.0 Output Serial clock high-level width (SCK1, SCK2) tWSKH1 Input Internal, divided +5.0 0.5T Output Setup time SCK1, SCK2) Hold time SCK1, SCK2) tSSSK1 Internal, divided 0.5T MAX. Unit
tHSSK1
Output delay time tDSOSK SCK1, SCK2) Output hold time SCK1, SCK2) tHSOSK When data transferred
0.5tCYSK1
Remarks values this table those when Serial clock cycle software. minimum value 16/fXX. UART, UART2
Parameter ASCK clock input cycle time Symbol tCYASK Conditions +5.0 MIN. ASCK clock low-level width tWASKL +5.0 52.5 ASCK clock high-level width tWASKH +5.0 52.5 MAX. Unit
µPD784035(A), 784036(A)
CLOCK OUTPUT OPERATION
Parameter CLKOUT cycle time CLKOUT low-level width Symbol tCYCL tCLL +5.0 Conditions MIN. 0.5tCYCL 0.5tCYCL CLKOUT high-level width tCLH +5.0 0.5tCYCL 0.5tCYCL CLKOUT rise time tCLR +5.0 CLKOUT fall time tCLF +5.0 MAX. Unit
Remarks Divided frequency ratio software tCYK (system clock cycle time) OTHER OPERATIONS
Parameter low-level width high-level width INTP0 low-level width INTP0 high-level width Low-level width INTP1INTP3 High-level width INTP1INTP3 Low-level width INTP4 INTP5 Symbol tWNIL tWNIH tWIT0L tWIT0H tWIT1L Conditions MIN. 4tCYSMP 4tCYSMP 4tCYCPU MAX. Unit
tWIT1H
4tCYCPU
tWIT2L
High-level width INTP4 tWIT2H INTP5 RESET low-level width RESET high-level width tWRSL tWRSH
Remarks tCYSMP: Sampling clock software tCYCPU: operation clock software
µPD784035(A), 784036(A)
CONVERTER CHARACTERISTICS AVREF1 +2.7 AVSS
Parameter Resolution Total errorNote Linearity calibrationNote Quantization error Conversion time tCONV Sampling time tSAMP Analog input voltage Analog input impedance AVREF1 current AVDD supply current VIAN AIREF1 AIDD1 AIDD2 MHz, STOP mode, -0.3 AVREF1 Symbol Conditions MIN. ±1/2 TYP. MAX. Unit tCYK tCYK tCYK tCYK
Note Quantization error included. This parameter indicated ratio full-scale value. Remark tCYK: System clock cycle time
µPD784035(A), 784036(A)
CONVERTER CHARACTERISTICS AVDD +2.7 AVSS
Parameter Resolution Total error Load conditions: AVDD AVREF2 +2.7 AVREF3 AVDD +2.7 AVREF2 0.75VDD AVREF3 0.25VDD Load conditions: AVDD AVREF2 +2.7 AVREF3 AVDD +2.7 AVREF2 0.75VDD AVREF3 0.25VDD Settling time Output resistance Analog reference voltage AVREF2 AVREF3 Resistance AVREF2 AVREF3 Reference power supply input current RAIREF DACS0, Load conditions: DACS0, 0.75VDD 0.25VDD Symbol Conditions MIN. TYP. MAX. Unit
AIREF2 AIREF3
µPD784035(A), 784036(A)
DATA RETENTION CHARACTERISTICS
Parameter Data retention voltage Data retention current Symbol VDDDR IDDDR STOP mode VDDDR +2.7 VDDDR +2.5 rise time fall time hold time STOP mode setting) STOP clear signal input time Oscillation settling time tRVD tFVD tHVD Conditions MIN. TYP. MAX. Unit
tDREL tWAIT Crystal Ceramic resonator
0.9VDDDR 0.1VDDDR VDDDR
Input voltage Input high voltage
Specific pinsNote
Note RESET, P20/NMI, P21/INTP0, P22/INTP1, P23/INTP2/CI, P24/INTP3, P25/INTP4/ASCK/SCK1, P26/INTP5, P27/SI0, P32/SCK0/SCL, P33/SO0/SDA pins TIMING TEST POINTS
0.8VDD Test points 0.45 0.8VDD
µPD784035(A), 784036(A)
TIMING WAVEFORM Read operation
tWSTH ASTB tSAST tHSTLA A8-A19 tDSTID tDRST
tDAID AD0-AD7 tDSTR tDAR tWRL tFRA tDRID
tHRA
tHRID tDRA
Write operation
tWSTH ASTB tSAST tHSTLA A8-A19 tDSTOD tDWST
tHWA AD0-AD7 tDSTW tDAW tWWL tDWOD tSODW tHWOD
µPD784035(A), 784036(A)
HOLD TIMING
ADTB, A8-A19, AD0-AD7, tFHQC HLDRQ tDHQHHAH HLDAK tDHQLHAL tDCFHA tDHAC
EXTERNAL WAIT SIGNAL INPUT TIMING Read operation
ASTB tDSTWTH tHSTWTH
tDSTWT A8-A19
AD0-AD7 tDAWT tDRWTL WAIT tHRWT tDRWTH tDWTR tDWTID
Write operation
ASTB tDSTWTH tHSTWTH
tDSTWT A8-A19
AD0-AD7 tDAWT tDWWTL WAIT tHWWT tDWWTH tDWTW
µPD784035(A), 784036(A)
REFRESH TIMING WAVEFORM Random read/write cycle
ASTB
When refresh memory accessed read write same time
ASTB
tDSTRFQ tDRFQST tWRFQH
REFRQ tWRFQL
Refresh after read
ASTB tDRFQST tDRRFQ REFRQ tWRFQL
Refresh after write
ASTB tDRFQST tDWRFQ REFRQ tWRFQL
µPD784035(A), 784036(A)
SERIAL OPERATION
tWSKL0 tCYSK0 tDSBSK1 tHSBSK1 tSSSK0 tHSSK0 Input data tWSKH0
Output data
IOE1, IOE2
tWSKL1 tCYSK1 tDSOSK tHSOSK tSSSK1 tHSSK1 tWSKH1
Input data
Output data
UART, UART2
tWASKH tWASKL
ASCK, ASCK2 tCYASK
µPD784035(A), 784036(A)
CLOCK OUTPUT TIMING
tCLH tCLL
CLKOUT tCLR tCYCL tCLF
INTERRUPT REQUEST INPUT TIMING
tWNIH
tWNIL
tWIT0H
tWIT0L
INTP0
tWIT1H
tWIT1L
INTP1-INTP3
tWIT2H
tWIT2L
INTP4, INTP5
RESET INPUT TIMING
tWRSH tWRSL
RESET
µPD784035(A), 784036(A)
EXTERNAL CLOCK TIMING
tWXH tWXL
tCYX
DATA RETENTION CHARACTERISTICS
STOP mode setting
tHVD tFVD
VDDDR tRVD tDREL tWAIT
RESET
(Clearing falling edge)
(Clearing rising edge)
µPD784035(A), 784036(A)
PACKAGE DRAWINGS
PLASTIC (14x14)
detail lead
NOTE Each lead centerline located within 0.13 (0.005 inch) true position (T.P.) maximum material condition.
ITEM
MILLIMETERS 17.2±0.4 14.0±0.2 14.0±0.2 17.2±0.4 0.825 0.825 0.30±0.10 0.13 0.65 (T.P.) 1.6±0.2 0.8±0.2 0.15 +0.10 -0.05 0.10 2.7±0.1 0.1±0.1 5°±5° MAX.
INCHES 0.677±0.016 0.551 +0.009 -0.008 0.551 +0.009 -0.008 0.677±0.016 0.032 0.032 0.012 +0.004 -0.005 0.005 0.026 (T.P.) 0.063±0.008 0.031 +0.009 -0.008 +0.004 0.006 -0.003 0.004 0.106 +0.005 -0.004 0.004±0.004 5°±5° 0.119 MAX. S80GC-65-3B9-5
Remark shape material version same those corresponding mass-produced product.
µPD784035(A), 784036(A)
RECOMMENDED SOLDERING CONDITIONS
conditions listed below shall when soldering µPD784035(A) µPD784036(A). details recommended soldering conditions, refer document Semiconductor Device Mounting Technology Manual (C10535E). Please consult with sales offices case other soldering process used, case soldering done under different conditions. Table 15-1. Soldering Conditions Surface-Mount Devices
80-pin plastic 80-pin plastic
Soldering process Infrared reflow Soldering conditions Peak package's surface temperature: Reflow time: seconds less (210 more) Maximum allowable number reflow processes: Peak package's surface temperature: Reflow time: seconds less (200 more) Maximum allowable number reflow processes: Symbol IR35-00-3
VP15-00-3
Wave soldering
Solder temperature: less WS60-00-1 Flow time: seconds less Number flow processes: Preheating temperature max. (measured package surface) Terminal temperature: less Heat time: seconds less (for side device)
Partial heating method
Caution apply more different soldering methods chip (except partial heating method terminal sections).
µPD784035(A), 784036(A)
APPENDIX DEVELOPMENT TOOLS
following development tools available system development using µPD784036(A). also (5). Language processing software
RA78K4 CC78K4 DF784038 CC78K4-L Assembler package 78K/IV series models compiler package 78K/IV series models Device file µPD784038 sub-series models compiler library source file 78K/IV series models
PROM write tools
PG-1500 PA-78P4026GC PG-1500 controller PROM programmer Programmer adaptor, connects PG-1500 Control program PG-1500
Debugging tools When using in-circuit emulator IE-78K4-NS
IE-78K4-NSNote IE-70000-MC-PS-B IE-70000-98-IF-CNote IE-70000-CD-IFNote IE-70000-PC-IF-CNote IE-784038-NS-EM1Note NP-80GC EV-9200GC-80 ID78K4-NSNote SM78K4-NS DF784038 In-circuit emulator 78K/IV series models Power supply unit IE-78K4-NS Interface adapter when PC-9800 series computer (other than notebook) used host machine card interface cable when PC-9800 series notebook used host machine Interface adapter when PC/ATor compatible used host machine Emulation board evaluating µPD784038 sub-series models Emulation probe 80-pin plastic (GC-3B9 type) Socket mounting target system board made 80-pin plastic (GC-3B9 type) Integrated debugger IE-78K4-NS System simulator 78K/IV series models Device file µPD784038 sub-series models
Note Under development
µPD784035(A), 784036(A)
When using in-circuit emulator IE-784000-R
IE-784000-R IE-70000-98-IF-B IE-70000-98-IF-CNote IE-70000-98N-IF-B IE-70000-PC-IF-B IE-70000-PC-IF-CNote IE-78000-R-SV3 IE-784038-NS-EM1Note IE-784038-R-EM1Note IE-78400-R-EM IE-78K4-R-EX2Note In-circuit emulator 78K/IV series models Interface adapter when PC-9800 series computer (other than notebook) used host machine Interface adapter cable when PC-9800 series notebook used host machine Interface adapter when PC/AT compatible used host machine Interface adapter cable when used host machine Emulation board evaluating µPD784038 sub-series models Emulation board 78K/IV series models Conversion board pins IE-784038-NS-EM1 IE-784000-R. board needed when conventional product IE-784038-R-EM1 used. Emulation probe 80-pin plastic (GC-3B9 type) Socket mounting target system board made 80-pin plastic (GC-3B9 type) Integrated debugger IE-784000-R System simulator 78K/IV series models Device file µPD784038 sub-series models
EP-78230GC-R EV-9200GC-80 ID78K4 SM78K4 DF784038
Note Under development Real-time
RX78K/IV MX78K4 Real-time 78K/IV series models 78K/IV series models
µPD784035(A), 784036(A)
Notes when using development tools ID78K-NS, ID78K4, SM78K4 used combination with DF784038. CC78K RX78K/IV used combination with RA78K4 DF784038. NP-80GC product from Naito Densei Machida Seisakusho Co., Ltd. (044-822-3813). Consult sales representative purchasing. host machines operating systems corresponding each software shown below.
Host machine [OS]
PC-9800 Series [WindowsTM]
HP9000 Series 700[HP-UXTM]
PC/AT compatibles [Windows] SPARCstation[SunOSTM] NEWS(RISC) [NEWS-OSTM] Software RA78K4 CC78K4 PG-1500 controller ID78K4-NS ID78K4 SM78K4 RX78K/IV MX78K4
Note Note Note Note Note
Note Software under MS-DOS
µPD784035(A), 784036(A)
APPENDIX RELATED DOCUMENTS
Documents Related Devices
Document Document name Japanese English This manual Under creation created U11316E U10905E
µPD784035(A), 784036(A) Data Sheet µPD784031(A) Data Sheet µPD78P4038(A) Data Sheet µPD784038, 784038Y Sub-Series User's Manual, Hardware µPD784038 Sub-Series Special Function Registers
78K/IV Series User's Manual, Instruction 78K/IV Series Instruction Summary Sheet 78K/IV Series Instruction 78K/IV Series Application Note, Software Basic
U13010J U13009J created U11316J U11090J U10905J U10594J U10595J U10095J
Documents Related Development Tools (User's Manual)
Document Document name Japanese RA78K4 Assembler Package Operation Language RA78K Series Structured Assembler Preprocessor CC78K4 Compiler Operation Language CC78K Series Library Source File PG-1500 PROM Programmer PG-1500 Controller PC-9800 Series (MS-DOSTM) Base U11334J U11162J U11743J U11572J U11571J U12322J U11940J EEU-704 EEU-5008 Under creation U12903J created U11383J EEU-985 Reference External Parts User Open Interface Specifications Reference Reference Reference U10093J U10092J English U11334E U11162E U11743E U11572E U11571E U12322E U11940E EEU-1291 U10540E created EEU-1534 created U11383E EEU-1515 U10093E U10092E
PG-1500 Controller Series DOSTM) Base IE-78K4-NS IE-784000-R IE-784038-NS-EM1 IE-784038-R-EM1 EP-78230 SM78K4 System Simulator Windows Base SM78K Series System Simulator
ID78K4 Integrated Debugger ID78K4 Integrated Debugger Windows Base ID78K4 Integrated Debugger HP-UX, SunOS, NEW-OS Base
U12796J U10440J U11960J
U12796E U10440E U11960E
Caution above documents revised without notice. latest versions when design application systems.
µPD784035(A), 784036(A)
Documents Related Software Incorporated into Product (User's Manual)
Document Document name Japanese 78K/IV Series Real-Time Basic Installation Debugger 78K/IV Series MX78K4 Basic U10603J U10604J U10364J U11779J English U10603E U10604E
Other Documents
Document Document name Japanese PACKAGE MANUAL Semiconductor Mount Technology Manual Quality Grades Semiconductor Device Semiconductor Device Reliability/Quality Control System Guide Prevent Damage Semiconductor Devices Electrostatic Discharge (ESD) Semiconductor Device Quality Control/Reliability Handbook Guide Products Related Micro-Computer: Other Companies C10535J C11531J C10983J U11892J C12769J C11416J C10943X C10535E C11531E C10983E E11892E English
Caution above documents revised without notice. latest versions when design application systems.
µPD784035(A), 784036(A)
NOTES CMOS DEVICES
PRECAUTION AGAINST SEMICONDUCTORS
Note: Strong electric field, when exposed device, cause destruction gate oxide ultimately degrade device operation. Steps must taken stop generation static electricity much possible, quickly dissipate once, when occurred. Environmental control must adequate. When dry, humidifier should used. recommended avoid using insulators that easily build static electricity. Semiconductor devices must stored transported anti-static container, static shielding conductive material. test measurement tools including work bench floor should grounded. operator should grounded using wrist strap. Semiconductor devices must touched with bare hands. Similar precautions need taken boards with semiconductor devices
HANDLING UNUSED INPUT PINS CMOS
Note: connection CMOS device inputs cause malfunction. connection provided input pins, possible that internal input level generated noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar NMOS devices. Input levels CMOS devices must fixed high using pull-up pull-down circuitry. Each unused should connected with resistor, considered have possibility being output pin. handling related unused pins must judged device device related specifications governing devices.
STATUS BEFORE INITIALIZATION DEVICES
Note: Power-on does necessarily define initial status device. Production process does define initial operation status device. Immediately after power source turned devices with reset function have been initialized. Hence, power-on does guarantee out-pin levels, settings contents registers. Device initialized until reset signal received. Reset operation must executed immediately after power-on devices having reset function.
µPD784035(A), 784036(A)
IEBus trademark Corporation. MS-DOS Windows registered trademarks trademarks Microsoft Corporation United States and/or other countries. PC/AT, trademarks Corporation. HP9000 series HP-UX trademarks Hewlett-Packard Company. SPARCstation trademark SPARC International, Inc. SunOS trademark Microsystems, Inc. NEWS NEWS-OS trademarks SONY Corporation.
µPD784035(A), 784036(A)
Regional Information
Some information contained this document vary from country country. Before using product your application, pIease contact office your country obtain list authorized representatives distributors. They will verify:
Device availability Ordering information Product release schedule Availability related technical literature Development environment specifications (for example, specifications third-party tools components, host computers, power plugs, supply voltages, forth) Network requirements
addition, trademarks, registered trademarks, export restrictions, other legal issues also vary from country country.
Electronics Inc. (U.S.)
Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288
Electronics (Germany) GmbH
Benelux Office Eindhoven, Netherlands Tel: 040-2445845 Fax: 040-2444580
Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
Electronics Hong Kong Ltd. Electronics (France) S.A.
Velizy-Villacoublay, France Tel: 01-30-67 Fax: 01-30-67 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
Electronics (Germany) GmbH
Duesseldorf, Germany Tel: 0211-65 Fax: 0211-65
Electronics (France) S.A. Electronics (UK) Ltd.
Milton Keynes, Tel: 01908-691-133 Fax: 01908-670-290 Spain Office Madrid, Spain Tel: 01-504-2787 Fax: 01-504-2860
Electronics Singapore Pte. Ltd.
United Square, Singapore 1130 Tel: 253-8311 Fax: 250-3583
Electronics Taiwan Ltd. Electronics Italiana s.r.1.
Milano, Italy Tel: 02-66 Fax: 02-66
Electronics (Germany) GmbH
Scandinavia Office Taeby, Sweden Tel: 08-63 Fax: 08-63
Taipei, Taiwan Tel: 02-719-2377 Fax: 02-719-5951
Brasil S.A.
Cumbica-Guarulhos-SP, Brasil Tel: 011-6465-6810 Fax: 011-6465-6829
J97.
µPD784035(A), 784036(A)
Some related documents preliminary versions. Note that, however, what documents preliminary indicated this document.
export this product from Japan regulated Japanese government. export this product prohibited without governmental license, need which must judged customer. export re-export this product from country other than Japan also prohibited without license from that country. Please call sales representative.
part this document copied reproduced form means without prior written consent Corporation. Corporation assumes responsibility errors which appear this document. Corporation does assume liability infringement patents, copyrights other intellectual property rights third parties arising from device described herein other liability arising from such device. license, either express, implied otherwise, granted under patents, copyrights other intellectual property rights Corporation others. While Corporation been making continuous effort enhance reliability semiconductor devices, possibility defects cannot eliminated entirely. minimize risks damage injury persons property arising from defect semiconductor device, customers must incorporate sufficient safety measures design, such redundancy, fire-containment, anti-failure features. devices classified into following three quality grades: "Standard", "Special", "Specific". Specific quality grade applies only devices developed based customer designated "quality assurance program" specific application. recommended applications device depend quality grade, indicated below. Customers must check quality grade each device before using particular application. Standard: Computers, office equipment, communications equipment, test measurement equipment, audio visual equipment, home electronic appliances, machine tools, personal electronic equipment industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment medical equipment (not specifically designed life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems medical equipment life support, etc. quality grade devices "Standard" unless otherwise specified NEC's Data Sheets Data Books. customers intend devices applications other than those specified Standard quality grade, they should contact sales representative advance. Anti-radioactive design implemented this product.
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