8-BIT SINGLE-CHIP MICROCONTROLLER DESCRIPTION 78058 µPD78054

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

8-BIT SINGLE-CHIP MICROCONTROLLER DESCRIPTION 78058 µPD78054

Datasheet Thumbnail

Top Searches for this datasheet

INTEGRATED CIRCUIT
8-BIT SINGLE-CHIP MICROCONTROLLER
DESCRIPTION
78058 µPD78054 subseries products 78K/0 series. 8-bit resolution converter, 8-bit resolution converter, timer, serial interface, real-time output port interrupt functions. µPD78P054 78P058, one-time PROM EPROM products which operated same supply voltage mask product, various development tools also available. Details function description, etc, described following User's Manual. sure read when designing.
µPD78054, 78054Y Subseries User's Manual: U11747E
78K/0 Series User's Manual Instruction: U12326E
FEATURES Large on-chip
Items Product Name Program Memory (ROM) Kbytes Kbytes Kbytes Kbytes Kbytes Kbytes 1024 bytes Internal HighSpeed bytes 1024 bytes Data Memory Internal Internal Buffer Expanded bytes
Package 80-pin plastic 80-pin plastic TQFP (fine pitch)
µPD78052 µPD78053 µPD78054 µPD78055 µPD78056 µPD78058
External memory expansion space: bytes Minimum instruction execution time varied from high-speed (0.4 ultra-low-speed (122 ports: (N-ch open-drain 8-bit resolution converter channels 8-bit resolution converter channels Serial interface channels Timer: channels Supply voltage:
APPLICATIONS
Cellular phone, pager, printer, equipment, airconditioners, cameras, PPC, fuzzy home appliances, vending machine, etc.
information this document subject change without notice. Document U12327EJ4V0DS00 (4th edition) Date Published September 1997 Printed Japan
mark
shows major revised points.
1994
µPD78052, 78053, 78054, 78055, 78056, 78058
ORDERING INFORMATION
Part Number Package 80-pin plastic 80-pin plastic TQFP (fine pitch) 80-pin plastic 80-pin plastic TQFP (fine pitch) 80-pin plastic 80-pin plastic TQFP (fine pitch) 80-pin plastic 80-pin plastic TQFP (fine pitch) 80-pin plastic 80-pin plastic TQFP (fine pitch) 80-pin plastic 80-pin plastic TQFP (fine pitch)
Remark indicates code suffix.
µPD78052, 78053, 78054, 78055, 78056, 78058
78K/0 SERIES PRODUCT DEVELOPMENT
following shows 78K/0 Series products development. Subseries name shown inside frames.
Products mass production Products under development subseries products compatible with bus.
Control 100-pin 100-pin 100-pin 100-pin 80-pin 80-pin 80-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin 42/44-pin
µPD78075B µPD78078 PD78070A PD780058 PD78058F PD78054 PD780034 PD780024 PD78014H µPD78018F µPD78014 µPD780001 µPD78002 µPD78083
Inverter control
µPD78075BY µPD78078Y µPD78070AY µPD780018AY PD780058YNote PD78058FY PD78054Y PD780034Y µPD780024Y PD78018FY PD78014Y µPD78002Y
EMI-noise reduced version PD78078 timer added µPD78054 external interface enhanced ROM-less version µPD78078 Serial PD78078Y enhanched function limited Serial PD78054 enhanced EMI-noise reduced EMI-noise reduced version PD78054 UART converter were added PD78014 enchanced converter µPD780024 enchanced Serial PD78018F added EMI-noise reduced EMI-noise reduced version PD78018F Low-voltage (1.8 operation version PD78014, with larger selection capacities converter 16-bit timer were added µPD78002 converter added µPD78002 Basic subseries control On-chip UART, capable operating voltage (1.8
64-pin 64-pin 64-pin 78K/0 Series
PD780988 PD780964 PD780924
FIPdrive
Inverter control,timer, µPD780964 were enhanced. capacity increased converter µPD780924 enhanced On-chip inverter control circuit UART. EMI-noise reduced. PD78044F were enhanced, Display output total: PD78044H were enhanced, Display output total: N-ch open drain added µPD78044F, Display output total: Basic subseries driving FIP, Display output total:
100-pin 100-pin 80-pin 80-pin
µPD780208 PD780228 µPD78044H µPD78044F
drive
100-pin 100-pin 100-pin
PD780308 PD78064B µPD78064
µPD780308Y PD78064Y
PD78064 enhanced ROM, capacity increased EMI-noise reduced version µPD78064 Basic subseries driving LCDs, On-chip UART
IEBussupported 80-pin 80-pin
µPD78098B PD78098
Meter control
EMI-noise reduced version µPD78064 IEBus controller added PD78054
80-pin
µPD780973
On-chip controller/driver automobile meter drive
64-pin
PD78P0914
On-chip output, digital code decoder, Hsync counter
Note Under planning.
µPD78052, 78053, 78054, 78055, 78056, 78058
following lists main functional differences between subseries products.
Function Subseries Name Control Capacity Timer 8-bit 16-bit Watch 8-bit 10-bit 8-bit Serial Interface (UART MIN. External Value Expansion
µPD78075B µPD78078 µPD78070A µPD780058 µPD78058F µPD78054 µPD780034 µPD780024 µPD78014H µPD78018F µPD78014 µPD780001 µPD78002 µPD78083 µPD780988 µPD780964 µPD780924 µPD780208 µPD780228 µPD78044H µPD78044F µPD780308 µPD78064B µPD78064
(time division UART: (UART:
(UART: time division 3-wire:
Note Note (UART (UART (time division UART: 1ch) (UART (UART: (UART: (UART:
Inverter control
drive
drive
IEBus µPD78098B supported µPD78098 Meter control
µPD780973 µPD78P0914
Notes 16-bit timer: channels 10-bit timer: channel 10-bit timer: channel
µPD78052, 78053, 78054, 78055, 78056, 78058
OVERVIEW FUNCTION
Product Name Item Internal Memory High-speed Buffer Expanded Memory space General registers Minimum instruction execution time Kbytes bits registers bits registers banks) On-chip minimum instruction execution time cycle modification function 32.768-kHz operation) 16-bit operation Multiplication/division bits bits,16 bits bits) manipulation (set, reset, test, boolean operation) correction, etc. None
µPD78052
Kbytes bytes
µPD78053
Kbytes
µPD78054
Kbytes
µPD78055
Kbytes 1024 bytes
µPD78056
Kbytes
µPD78058
Kbytes
bytes 1024 bytes
When main system clock selected µs/0.8 µs/1.6 µs/3.2 µs/6.4 µs/12.8 5.0-MHz operation) When subsystem clock selected Instruction
ports
Total CMOS input CMOS N-ch open-drain 8-bit resolution channels 8-bit resolution channels
converter converter Serial interface
3-wire serial I/O/SBI/2-wire serial mode selectable: channel 3-wire serial mode (on-chip max. 32-byte automatic data transmit/receive function): channel 3-wire serial I/O/UART mode selectable channel 16-bit timer/event counter 8-bit timer/event counter Watch timer Watchdog timer channel channels channel channel
Timer
Timer output Clock output
(14-bit output 19.5 kHz, 39.1 kHz, 78.1 kHz, kHz, kHz, kHz, 1.25 MHz, MHz, main system clock 5.0-MHz operation) 32.768 subsystem clock 32.768-kHz operation) kHz, kHz, kHz, main system clock 5.0-MHz operation) Maskable Non-maskable Software Internal interrupt external interrupt Internal interrupt Internal external +85°C 80-pin plastic 80-pin plastic TQFP (fine pitch)
Buzzer output Vectored interrupt sources Test input Supply voltage Operating ambient temperature Package
µPD78052, 78053, 78054, 78055, 78056, 78058
CONTENTS
CONFIGURATION (Top View) BLOCK DIAGRAM
FUNCTIONS
Port Pins Other Pins Circuits Recommended Connection Unused Pins
MEMORY SPACE PERIPHERAL HARDWARE FUNCTION FEATURES
Ports Clock Generator Timer/Event Counter Clock Output Control Circuit Buzzer Output Control Circuit Converter Converter Serial Interfaces Real-Time Output Port Functions
INTERRUPT FUNCTIONS TEST FUNCTIONS
Interrupt Functions Test Functions
EXTERNAL DEVICE EXPANSION FUNCTIONS STANDBY FUNCTION RESET FUNCTION
INSTRUCTION ELECTRICAL SPECIFICATIONS CHARACTERISTIC CURVES (REFERENCE VALUE) PACKAGE DRAWINGS RECOMMENDED SOLDERING CONDITIONS APPENDIX DEVELOPMENT TOOLS APPENDIX RELATED DOCUMENTS
µPD78052, 78053, 78054, 78055, 78056, 78058
CONFIGURATION (Top View)
80-pin plastic
80-pin plastic TQFP (fine pitch)
P01/INTP1/TI01 P00/INTP0/TI00
P06/INTP6
P05/INTP5
P04/INTP4
P03/INTP3
P15/ANI5 P16/ANI6 P17/ANI7 AVSS P130/ANO0 P131/ANO1 AVREF1 P70/SI2/R P71/SO2/TXD P72/SCK2/ASCK P20/SI1 P21/SO1 P22/SCK1 P23/STB P24/BUSY P25/SI0/SB0 P26/SO0/SB1 P27/SCK0 P40/AD0 P41/AD1
P02/INTP2
P14/ANI4
P13/ANI3
P12/ANI2
P11/ANI1
P10/ANI0
XT1/P07
AVREF0
AVDD
RESET P127/RTP7 P126/RTP6 P125/RTP5 P124/RTP4 P123/RTP3 P122/RTP2 P121/RTP1 P120/RTP0 P36/BUZ P35/PCL P34/TI2 P33/TI1 P32/TO2 P31/TO1 P30/TO0 P67/ASTB P66/WAIT P65/WR
P56/A14
P42/AD2
P43/AD3
P44/AD4
P45/AD5
P46/AD6
P47/AD7
P52/A10
P53/A11
P54/A12
P55/A13
P57/A15
Cautions (Internally Connected) should connected directly VSS. AVDD should connected pin. AVSS should connected pin.
P64/RD
P50/A8
P51/A9
µPD78052, 78053, 78054, 78056, 78055, 78058
ANI0 ANI7 ANO0, ANO1 ASCK ASTB AVDD AVREF0, AVREF1 AVSS BUSY P120 P127
Address Address/Data Analog Input Analog Output Asynchronous Serial Clock Address Strobe Analog Power Supply Analog Reference Voltage Analog Ground Busy Buzzer Clock Internally Connected Port0 Port1 Port2 Port3 Port4 Port5 Port6 Port7 Port12
P130, P131 RESET RTP0 RTP7 SB0, SCK0 SCK2 TI00, TI01 TI1, WAIT XT1,
Port13 Programmable Clock Read Strobe Reset Real-Time Output Port Receive Data Serial Serial Clock Serial Input Serial Output Strobe Timer Input Timer Input Timer Output Transmit Data Power Supply Ground Wait Write Strobe Crystal (Main System Clock) Crystal (Subsystem Clock)
INTP0 INTP6 Interrupt from Peripherals
µPD78052, 78053, 78054, 78055, 78056, 78058
BLOCK DIAGRAM
TO0/P30 TI00/INTP0/P00 TI01/INTP1/P01 TO1/P31 TI1/P33
16-bit TIMER/ EVENT COUNTER
PORT0 P01-P06
8-bit TIMER/ EVENT COUNTER
PORT1
P10-P17
TO2/P32 TI2/P34
8-bit TIMER/ EVENT COUNTER
PORT2
P25-P27
WATCHDOG TIMER
PORT3
P30-P37
WATCH TIMER 78K/0 CORE
PORT4
P40-P47
SI0/SB0/P25 SO0/SB1/P26 SCK0/P27
SERIAL INTERFACE
PORT5
P50-P57
PORT6 SI1/P20 SO1/P21 SCK1/P22 STB/P23 BUSY/P24 PORT12 SI2/RxD/P70 SO2/TxD/P71 SCK2/ASCK/P72 ANI0/P10ANI7/P17 AVDD AVSS AVREF0 ANO0/P130, ANO1/P131 AVss AVREF1 INTP0/P00INTP6/P06 CONVERTER SERIAL INTERFACE SERIAL INTERFACE
P60-P67
PORT7
P70-P72
P120-P127
PORT13
P130, P131
REAL-TIME OUTPUT PORT
RTP0/P120RTP7/P127 AD0/P40AD7/P47 A8/P50A15/P57
CONVERTER
EXTERNAL ACCESS
RD/P64 WR/P65
INTERRUPT CONTROL
WAIT/P66 ASTB/P67 RESET XT1/P07
BUZ/P36
BUZZER OUTPUT CLOCK OUTPUT CONTROL
SYSTEM CONTROL
PCL/P35
Remark internal capacities differ depending product.
µPD78052, 78053, 78054, 78056, 78055, 78058
FUNCTIONS
Port Pins (1/2)
Input Input/ output Port 8-bit port Input only Input/output specified bit-wise. When used input port, pull-up resistor used software. Function After Reset Input Input DualFunction INTP0/TI00 INTP1/TI01 INTP2 INTP3 INTP4 INTP5 INTP6 Input Input/ output Input only Port 8-bit input/output port. Input/output specified bit-wise. When used input port, pull-up resistor used software.Note Port 8-bit input/output port. Input/output specified bit-wise. When used input port, pull-up resistor used software. Input Input ANI0 ANI7
Name
Note
Input/ output
Input
SCK1 BUSY SI0/SB0 SO0/SB1 SCK0
Input/ output
Port 8-bit input/output port. Input/output specified bit-wise. When used input port, pull-up resistor used software.
Input
Input/ output
Port 8-bit input/output port. Input/output specified 8-bit unit. When used input port, pull-up resistor used software. Test input flag (KRIF) falling edge detection.
Input
Notes When using P07/XT1 pins input port, (FRC) processor clock control register (PCC). On-chip feedback resistor subsystem clock oscillator should used. When using P10/ANI0 P17/ANI7 pins converter analog input pins, port input mode. pull-up resistor cancelled automatically.
µPD78052, 78053, 78054, 78055, 78056, 78058
Port Pins (2/2)
Input/ output Function Port 8-bit input/output port. driven directly. Input/output specified bit-wise. When used input port, pull-up resistor used software. Port 8-bit input/outport port. Input/output specified bit-wise. N-ch open-drain input/output port. On-chip pull-up resistor specified mask option. driven directly. When used input port, pull-up resistor used software. Input WAIT ASTB Input/ output Port 3-bit input/output port. Input/output specified bit-wise. When used input port, pull-up resistor used software. Port 8-bit input/output port. Input/output specified bit-wise. When used input port, pull-up resistor used software. Port 2-bit input/output port. Input/output specified bit-wise. When used input port, pull-up resistor used software. Input SI2/RxD SO2/TxD SCK2/ASCK Input RTP0 RTP7 After Reset Input DualFunction
Name
Input/ output
Input
P120 P127 Input/ output
P130, P131
Input/ output
Input
ANO0, ANO1
µPD78052, 78053, 78054, 78056, 78055, 78058
Other Pins (1/2)
Input Function External interrupt request input which effective edge (rising edge, falling edge, both rising edge falling edge) specified. After Reset Input DualFunction P00/TI00 P01/TI01 Input Serial interface serial data input. Input P25/SB0 P70/RxD Output Serial interface serial data output. Input P26/SB1 P71/TxD Input/ output Input/ output Serial interface serial data input/output. Input P25/SI0 P26/SO0 Serial interface serial clock input/ output Input P72/ASCK Output Input Input Output Input Input Serial interface automatic transmit/receive strobe output. Serial interface automatic transmit/receive busy input. Asynchronous serial interface serial data input. Asynchronous serial interface serial data output. Asynchronous serial interface serial clock input. External count clock input 16-bit timer (TM0) Capture trigger signal input capture register (CR00) External count clock input 8-bit timer (TM1) External count clock input 8-bit timer (TM2) Output 16-bit timer (TM0) output (dual-function 14-bit output) 8-bit timer (TM1) output 8-bit timer (TM2) output Output Output Clock output (for main system clock, subsystem clock trimming). Buzzer output. Real-time output port which data output synchronization with trigger. Low-order address/data external memory expansion. High-order address external memory expansion. External memory read operation strobe signal output. External memory write operation strobe signal output. Input Input Input Input Input Input Input Input Input Input Input Input Input P70/SI2 P71/SO2 P72/SCK2 P00/INTP0 P01/INTP1 P120 P127
Name INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTP6 SCK0 SCK1 SCK2 BUSY ASCK TI00 TI01
RTP0 RTP7 Output Input/ output Output Output
µPD78052, 78053, 78054, 78055, 78056, 78058
Other Pins (2/2)
Input Output Input Output Input Input Input Input Input Positive power supply. Ground potential. Internally connected. Connect directly VSS. Subsystem clock oscillation crystal connection. Function Wait insertion external memory access. Strobe output which latches address information output port access external memory. converter analog input. converter analog output. converter reference voltage input. converter reference voltage input. converter analog power supply. Connected Ground potential converter converter. Connected System reset input. Main system clock oscillation crystal connection. After Reset Input Input Input Input Input DualFunction P130, P131
Name WAIT ASTB ANI0 ANI7 ANO0, ANO1 AVREF0 AVREF1 AVDD AVSS RESET
µPD78052, 78053, 78054, 78056, 78055, 78058
Circuits Recommended Connection Unused Pins
input/output circuit type each recommended connection unused pins shown Table 3-1. input/output circuit configuration each type, refer Figure 3-1.
Table 3-1. Input/Output Circuit Type Each (1/2)
Name P00/INTP0/TI00 P01/INTP1/TI01 P02/INTP2 P03/INTP3 P04/INTP4 P05/INTP5 P06/INTP6 P07/XT1 P10/ANI0 P17/ANI7 P20/SI1 P21/SO1 P22/SCK1 P23/STB P24/BUSY P25/SI0/SB0 P26/SO0/SB1 P27/SCK0 P30/TO0 P31/TO1 P32/TO2 P33/TI1 P34/TI2 P35/PCL P36/BUZ P40/AD0 P47/AD7 P50/A8 P57/A15 P64/RD P65/WR P66/WAIT P67/ASTB
Input/output Circuit Type
Input Input/output
Recommended Connection when Used Connect Independently connect through resistor.
10-A
Input Input/output
Connect VDD. Independently connect through resistor.
13-B
Independently connect through resistor. Independently connect through resistor. Independently connect through resistor. Independently connect through resistor.
µPD78052, 78053, 78054, 78055, 78056, 78058
Table 3-1. Input/Output Circuit Type Each (2/2)
Name P70/SI2/RxD P71/SO2/TxD P72/SCK2/ASCK P120/RTP0 P127/RTP7 P130/ANO0 P131/ANO1 RESET AVREF0 AVREF1 AVDD AVSS
Input/output Circuit Type 12-A
Input/output
Recommended Connection when Used Independently connect through resistor.
Input/output Input/output Input Leave open. Connect Connect Independently connect through resistor.
Connect Connect directly.
µPD78052, 78053, 78054, 78056, 78055, 78058
Figure 3-1. Input/Output Circuits (1/2)
Type
Type
pull-up enable data P-ch
P-ch
IN/OUT Schmitt-Triggered Input with Hysteresis Characteristic output disable N-ch
Type pull-up enable data
Type 10-A
P-ch
pull-up enable data IN/OUT P-ch
P-ch
P-ch
IN/OUT open drain output disable N-ch
output disable
N-ch
input enable Type Type pull-up enable data
pull-up enable data P-ch
P-ch P-ch IN/OUT
P-ch
IN/OUT output disable N-ch
output disable Comparator
N-ch P-ch N-ch VREF (Threshold Voltage)
input enable
µPD78052, 78053, 78054, 78055, 78056, 78058
Figure 3-1. Input/Output Circuits (2/2)
Type 12-A pull-up enable data P-ch IN/OUT output disable input enable N-ch Type feed back cut-off P-ch
P-ch
P-ch Analog Output Voltage N-ch
Type 13-B Mask Option IN/OUT data output disable N-ch
P-ch
Middle-High Voltage Input Buffer
µPD78052, 78053, 78054, 78056, 78055, 78058
MEMORY SPACE
Figure shows memory map. Figure 4-1. Memory
FFFFH Special Function Registers (SFR) bits FF00H FEFFH FEE0H FEDFH
General Registers bits
7A7FH Prohibited F800H F7FFH
Internal High-Speed Note mmmmH mmmmH Prohibited Data Memory Space FAE0H FADFH Internal Buffer bits FAC0H FABFH Prohibited FA80H FA7FH
Internal Expanded 1024 bits F400H F3FFH Prohibited Note F000H nnnnH Program Area 1000H 0FFFH CALLF Entry Area 0800H 07FFH
Note
External Memory Program Memory Space nnnnH nnnnH 0080H 007FH
Program Area
CALLT Table Area 0040H 003FH Vector Table Area
Internal
Note
0000H
0000H
Notes µPD78058 only When external device expansion function used with µPD78058, internal capacity Kbytes less using memory size switching register (IMS). internal capacity internal high-speed capacity depend products (see next table).
µPD78052, 78053, 78054, 78055, 78056, 78058
Relevant Product Name
Internal Last Address nnnnH 3FFFH 5FFFH 7FFFH 9FFFH BFFFH EFFFH
Internal First Address mmmmH FD00H FB00H
µPD78052 µPD78053 µPD78054 µPD78055 µPD78056 µPD78058
µPD78052, 78053, 78054, 78055, 78056, 78058
PERIPHERAL HARDWARE FUNCTION FEATURES
Ports
following types ports available. CMOS input (P00, P07) CMOS input/output (P01 P06, port port P67, port port port N-channel open-drain input/output (P60 P63) Total
Table 5-1. Port Functions
Name Port Name P00, Port Port Port Port Dedicated input port pins Input/output port pins. Input/output specifiable bit-wise. When used input port pins, on-chip pull-up resistor used software. Input/output port pins. Input/output specifiable bit-wise. When used input port pins, on-chip pull-up resistor used software. Input/output port pins. Input/output specifiable bit-wise. When used input port pins, on-chip pull-up resistor used software. Input/output port pins. Input/output specifiable bit-wise. When used input port pins, on-chip pull-up resistor used software. Input/output port pins. Input/output specifiable 8-bit units. When used input port pins, on-chip pull-up resistor used software. Test flag (KRIF) falling edge detection. Input/output port pins. Input/output specifiable bit-wise. When used input port pins, on-chip pull-up resistor used software. direct drive capability. N-channel open-drain input/output port pins. Input/output specifiable bit-wise. On-chip pull-up resistor used mask option. direct drive capability. Input/output port pins. Input/output specifiable bit-wise. When used input port pins, on-chip pull-up resistor used software. Input/output port pins. Input/output specifiable bit-wise. When used input port pins, on-chip pull-up resistor used software. Input/output port pins. Input/output specifiable bit-wise. When used input port pins, on-chip pull-up resistor used software. Input/output port pins. Input/output specifiable bit-wise. When used input port pins, on-chip pull-up resistor used software. Function
Port
Port
Port Port Port P120 P127 P130, P131
µPD78052, 78053, 78054, 78055, 78056, 78058
Clock Generator
types generators, main system clock generator subsystem clock generator, avaibable. minimum instruction execution time also changed. µs/0.8 µs/1.6 µs/3.2 µs/6.4 µs/12.8 (main system clock: 5.0-MHz operation) (subsystem clock: 32.768-kHz operation) Figure 5-1. Clock Generator Block Diagram
XT1/P07 Subsystem Clock Oscillator
Watch Timer, Clock Output Function Prescaler
Main System Clock Oscillator Scaler STOP
Clock Peripheral Hardware
Selector
Prescaler Selector Standby Control Circuit
Wait Control Circuit
Clock (fCPU)
INTP0 Sampling Clock
Timer/Event Counter channel channels channel channel Table 5-2. Operation Timer/Event Counter
incorporate channels timer/event counter. 16-bit timer/event counter 8-bit timer/event counter Watch timer Watchdog timer
16-Bit Timer/Event Counter 8-Bit Timer/Event Counter Operation mode Interval timer External event counter Function Timer output output Pulse amplitude measurement Square wave output Ono-shot pulse output Interrupt source Test input output output inputs output output outputs outputs channel channel channels channels
Watch Timer
Watchdog Timer
channel
channel
input
µPD78052, 78053, 78054, 78055, 78056, 78058
Figure 5-2. 16-Bit Timer/Event Counter Block Diagram
Internal INTP1 TI01/P01/INTP1 Selector 16-Bit Capture/ Compare Register (CR00)
INTTM00
Match Watch Timer Output 2fXX fXX/2 fXX/2 TI00/P00/INTP0 Edge Detector Match Selector 16-Bit Timer Register (TM0) Clear
pulse Output Control Circuit
Output Control Circuit
TO0/P30
Selector INTTM01 INTP0
16-Bit Capture/ Compare Register (CR01)
Internal
Figure 5-3. 8-Bit Timer/Event Counter Block Diagram
Internal INTTM1 8-Bit Compare Register (CR10)
8-Bit Compare Register (CR20) Selector Match
Match fxx/2 fxx/29 fx/2 TI1/P33 Selector 8-Bit Timer Register (TM1) Selector
Clear
Output Control Circuit
TO2/P32 INTTM2
8-Bit Timer Register (TM2) Clear
fxx/2 fxx/29 fx/2 TI2/P34 Selector
Selector
Output Control Circuit Internal
TO1/P31
µPD78052, 78053, 78054, 78055, 78056, 78058
Figure 5-4. Watch Timer Block Diagram
Selector fXX/27 Selector Prescaler 5-Bit Counter Selector INTWT
Selector
INTTM3 16-Bit Timer/ Event Counter
Figure 5-5. Watchdog Timer Block Diagram
Prescaler Control Circuit
INTWDT Maskable Interrupt Request Selector 8-Bit Counter RESET INTWDT Non-Maskable Interrupt Request
µPD78052, 78053, 78054, 78055, 78056, 78058
Clock Output Control Circuit
clock with following frequency output clock output. 19.5 kHz/39.1 kHz/78.1 kHz/156 kHz/313 kHz/625 kHz/1.25 MHz/2.5 MHz/5.0 (main system clock: 5.0-MHz operation) 32.768 (subsystem clock: 32.768-kHz operation) Figure 5-6. Clock Output Control Circuit Configuration
fXX/2 fXX/2 fXX/2 fXX/2 fXX/2 fXX/2 fXX/2 Selector Synchronization Circuit Output Control Circuit PCL/P35
Buzzer Output Control Circuit
clock with following frequency output buzzer output. kHz/2.4 kHz/4.9 kHz/9.8 (main system clock: 5.0-MHz operation) Figure 5-7. Buzzer Output Control Circuit Block Diagram
fXX/29 fXX/210 fXX/211 Selector Output Control Circuit BUZ/P36
µPD78052, 78053, 78054, 78055, 78056, 78058
Converter
converter 8-bit resolution channels incorporated. following types conversion operation start-up methods available. Hardware start Software start Figure 5-8. Converter Block Diagram
Series Resistor String ANI0/P10 ANI1/P11 ANI2/P12 ANI3/P13 ANI4/P14 ANI5/P15 ANI6/P16 ANI7/P17 Succesive Approxmation Register (SAR) AVSS Selector Selector Sample Hold Circuit Voltage Comparator AVDD AVREF0
INTP3/P03
Edge Detector
Control Circuit
INTAD INTP3
Conversion Result Register (ADCR)
Internal
µPD78052, 78053, 78054, 78055, 78056, 78058
Converter
converter 8-bit resolution channels available. Conversion method R-2R resistor ladder method.
Figure 5-9. Converter Block Diagram
AVREF1
ANOn
Selector DACSn Write AVSS INTTMX
Conversion Value Register (DACSn)
DAMm Converter Mode Register
Internal
Serial Interfaces
channels clocked serial interface incorporated. Serifal interface channel Serifal interface channel Serifal interface channel Table 5-3. Types Functions Serial Interface
Function 3-wire serial made 3-wire serial mode with automatic transmit/receive function (serial interface) mode 2-wire serial mode 3-wire serial mode with automatic transmit/receive function Serial Interface Channel (MSB/LSB first switchable) (MSB first) (MSB first) Serial Interface Channel (MSB/LSB first switchable) (MSB/LSB first switchable) Serial Interface Channel (MSB/LSB first switchable) (Dedicated baud rate generator incorporated)
µPD78052, 78053, 78054, 78055, 78056, 78058
Figure 5-10. Serial Interface Channel Block Diagram
Internal
SI0/SB0/P25 Selector SO0/SB1/P26 Serial Shift Register (SIO0) Output Latch
Selector
Busy/Acknowledge Output Circuit Release/Command/ Acknowledge Detector Interrupt Request Signal Generator INTCSI0
SCK0/P27
Serial Clock Counter
fXX/2 fXX/2 Serial Clock Control Circuit Selector
Figure 5-11. Serial Interface Channel Block Diagram
Internal
Automatic Data Transmit/ Receive Address Pointer (ADTP)
Buffer
Automatic Data Transmit/Receive Interval Specification Register (ADTI) Match
SI1/P20
Serial Shift Register (SIO1)
SO1/P21 5-Bit Counter STB/P23 Handshake Control Circuit
BUSY/P24
SCK1/P22
Serial Counter
Interrupt Request Signal Generator
INTCSI1
fXX/2 fXX/2 Serial Clock Control Circuit Selector
µPD78052, 78053, 78054, 78055, 78056, 78058
Figure 5-12. Serial Interface Channel Block Diagram
Internal
Receive Buffer Register (RXB/SIO2)
Direction Control Circuit
Direction Control Circuit
Transmit Shift Register (TXS/SIO2)
RxD/SI2/P70 TxD/SO2/P71
Receive Shift Register (RXS)
Transmit Control Circuit
INTST
Receive Control Circuit
INTSER INTSR/INTCSI2 Output Control Circuit
ASCK/SCK2/P72
Baud Rate Generator
fXX/210
Real-Time Output Port Functions
Data previously real-time output buffer register transferred output latch hardware concurrently with timer interrupt external interrupt generation order output off-chip. This real-time output function. pins output off-chip called real-time output ports. using real-time output port, signal which jitter output. This most applicable control stepping motor, etc. Figure 5-13. Real-Time Output Port Block Diagram
Internal
INTP2 INTTM1 INTTM2
Output Trigger Control Circuit
Real-Time Output Real-Time Output Buffer Register Buffer Register Higher Bits Higher Bits (RTBL) (RTBH) Real-Time Output Port Mode Register (RTPM)
Output Latch
P127
P120
µPD78052, 78053, 78054, 78055, 78056, 78058
INTERRUPT FUNCTIONS TEST FUNCTIONS
Interrupt Functions Non-maskable Maskable Software following table shows interrupt source list. Table 6-1. Interrupt Source List (1/2)
Vector Table Address 0004H Basic Configuration Type Note External 0006H 0008H 000AH 000CH 000EH 0010H 0012H serial interface channel transfer serial interface channel transfer Generation serial interface channel UART receive error serial interface channel UART reception serial interface channel 3-wire transfer serial interface channel UART transmission 001CH Internal 0014H 0016H 0018H 001AH
There interrupt functions, sources three different kinds, shown below.
Interrupt Type Non-maskable Maskable
Default
Note
Interrupt Source Name INTWDT INTWDT INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTP6 INTCSI0 INTCSI1 INTSER INTSR INTCSI2 Trigger Watchdog timer overflow (watchdog timer mode selected) Watchdog timer overflow (interval timer mode selected) input edge detection
Internal/ External Internal
Priority
INTST
Notes default priority priority order when more maskable interrupt requests generated simultaneously. highest order lowest. Basic configuration types correspond Figure 6-1, respectively.
µPD78052, 78053, 78054, 78055, 78056, 78058
Table 6-1. Interrupt Source List (2/2)
Vector Table Address 001EH 0020H Basic Configuration Type Note
Interrupt Type Maskable
Default
Note
Interrupt Source Name INTTM3 INTTM00 Trigger Reference time interval signal from watch timer Generation match signal 16-bit timer register capture/compare register (CR00) Generation match signal 16-bit timer register capture/compare register (CR01) Generation match signal 8-bit timer/event counter Generation match signal 8-bit timer/event counter conversion converter instruction execution
Internal/ External Internal
Priority
INTTM01
0022H
Software
INTTM1 INTTM2 INTAD
0024H 0026H 0028H 003EH
Notes default priority priority order when more maskable interrupts generated simultaneously. highest order lowest. Basic configuration types correspond Figure 6-1, respectively.
µPD78052, 78053, 78054, 78055, 78056, 78058
Figure 6-1. Interrupt Function Basic Configuration(1/2) Internal non-maskable interrupt
Internal
Interrupt Request
Priority Control Circuit
Vector Table Address Generator Standby Release Signal
Internal maskable interrupt
Internal
Interrupt Request
Priority Control Circuit
Vector Table Address Generator Standby Release Signal
External maskable interrupt (INTP0)
Internal
Sampling Clock Select Register (SCS)
External Interrupt Mode Register (INTM0)
Interrupt Request
Sampling Clock
Edge Detector
Priority Control Circuit
Vector Table Address Generator Standby Release Signal
µPD78052, 78053, 78054, 78055, 78056, 78058
Figure 6-1. Interrupt Function Basic Configuration(2/2)
External maskable interrupt (except INTP0)
Internal
External Interrupt Mode Register (INTM0, INTM1)
Interrupt Request
Edge Detector
Priority Control Circuit
Vector Table Address Generator Standby Release Signal
Software interrupt
Internal
Interrupt Request
Priority Control Circuit
Vector Table Address Generator
Interrupt request flag Interrupt enable flag
In-service priority flag Interrupt mask flag Priority specification flag
µPD78052, 78053, 78054, 78055, 78056, 78058
Test Functions
There test functions shown Table 6-2. Table 6-2. Test Input Source List
Test Input Source Internal/External Name INTWT INTPT4 Watch timer overflow Port falling edge detection Trigger Internal External
Figure 6-2. Test Function Basic Configuration
Internal
Interrupt Request
Standby Release Signal
Test input flag
Test mask flag
µPD78052, 78053, 78054, 78055, 78056, 78058
EXTERNAL DEVICE EXPANSION FUNCTIONS
external device expansion functions connect external devices areas other than internal ROM, SFR. Ports used external device connection.
STANDBY FUNCTION
There following standby functions reduce system power consumption. HALT mode operating clock stopped. average consumption current reduced intermittent operation combination with normal operating mode. STOP mode main system clock oscillation stopped. whole operation main system clock stopped, that system operates withultra-low power consumption using only subsystem clock. Figure 8-1. Stand-by Function
Main System Clock Operation Interrupt Request STOP Instruction Interrupt Request
CSS=1 CSS=0 HALT Instruction
Subsystem Clock Operation Note HALT Instruction
Interrupt Request
STOP Mode (Main system clock oscillation stopped)
HALT Mode (Clock supply stopped, oscillation)
HALT Mode Note (Clock supply stopped, oscillation)
Note power consumption reduced stopping main system clock. When operating subsystem clock, (MCC) processor clock control register (PCC) stop main system clock. STOP instruction cannot used. Caution When main system clock stopped system operated subsystem clock, subsystem clock should switched again main system clock after oscillation stabilization time secured software.
RESET FUNCTION
There following reset methods. External reset input RESET Internal reset watchdog timer hung-up time detection
µPD78052, 78053, 78054, 78055, 78056, 78058
INSTRUCTION
8-bit instruction MOV, XCH, ADDC, SUB, SUBC, AND, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ
Second Operand First Operand #byte
Byte]
Note
saddr
!addr16
[DE]
[HL]
$addr16
None
ADDC SUBC
ADDC SUBC
ADDC SUBC
ADDC SUBC
ADDC SUBC
ADDC SUBC
RORC ROLC
ADDC SUBC
saddr ADDC SUBC !addr16
DBNZ
DBNZ
PUSH
[DE] [HL]
ROR4 ROL4
Byte]
MULU DIVUW
Note Except
µPD78052, 78053, 78054, 78055, 78056, 78058
16-bit instruction MOV, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW
Second instruction First instruction
#word ADDW SUBW CMPW MOVW MOVW MOVW MOVW
Note MOVW XCHW
sfrp MOVW
saddrp MOVW
!addr16 MOVW
MOVW
None
sfrp saddrp !addr16
MOVW Note MOVW MOVW MOVW MOVW
INCW, DECW PUSH,
Note Only when manipulation instruction MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BTCLR
Second instruction First instruction A.bit
A.bit
sfr.bit
saddr.bit
PSW.bit
[HL].bit
MOV1
$addr16 BTCLR BTCLR BTCLR BTCLR BTCLR
None SET1 CLR1 SET1 CLR1 SET1 CLR1 SET1 CLR1 SET1 CLR1
sfr.bit
MOV1
saddr.bit
MOV1
PSW.bit
MOV1
[HL].bit
MOV1
MOV1 AND1 XOR1
MOV1 AND1 XOR1
MOV1 AND1 XOR1
MOV1 AND1 XOR1
MOV1 AND1 XOR1
SET1 CLR1 NOT1
Call instruction/branch instruction CALL, CALLF, CALLT, BNC, BNZ, BTCLR, DBNZ
Second instruction First instruction Basic instruction Compound instruction
!addr16 CALL
!addr11 CALLF
[addr5] CALLT
$addr16 BTCLR DBNZ
µPD78052, 78053, 78054, 78055, 78056, 78058
Other instructions ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, HALT, STOP
µPD78052, 78053, 78054, 78055, 78056, 78058
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings 25°C)
Parameter Supply voltage Symbol AVDD AVREF0 AVREF1 AVSS Input voltage P07, P17,P20 P27, toP37, P47,P50 P57, P67, P72, P120 P127, P130, P131, XT2, RESET N-ch Open-drain Test Conditions Rating -0.3 +7.0 -0.3 -0.3 -0.3 -0.3 +0.3 -0.3 Unit
Output voltage Analog input voltage Output current high
-0.3 -0.3
Analog input
AVSS AVREF0 +150
P06, P37, P56, P57, P67, P120 P127 total P17, P27, P47, P55, P72, P130, P131 total
Output current
Note
Peak value r.m.s. value
total
Peak value r.m.s. value
P56, P57, total
Peak value r.m.s. value
P17, P27, P47, P72, P130, P131 total P06, P37, P67, P120 P127 total Operating ambient temperature Storage temperature Tstg
Peak value r.m.s. value Peak value r.m.s. value
Note r.m.s value should calculated follows: [r.m.s value] [Peak value] duty Caution Product quality suffer absolute maximum rating exceeded even single parameter even momentarily. That absolute maximuam ratings rated values which product verge suffering physical damage, therefore product must used under conditions which ensure that absolute maximum ratings exceeded.
µPD78052, 78053, 78054, 78055, 78056, 78058
Main System Clock Oscillation Circuit Characteristics +85°C,
Recommended Circuit
Resonator Ceramic resonator
Parameter
Oscillator frequency (fx)
Note
Test Conditions Oscillator voltage range After reaches oscillator voltage range MIN.
MIN.
TYP.
MAX.
Unit
Oscillation stabilization time
Note
Crystal resonator
Oscillator frequency (fx) Oscillation stabilization time
Note Note
External clock
input
frequency (fx) input
Note
PD74HCU04 high/low level width
(tXH tXL)
Notes Indicates only oscillation circuit characteristics. Refer Characteristics instruction execution time. Time required stabilize oscillation after reset STOP mode release. Cautions When using main system clock oscillator, wirinin area enclosed with broken line should carried follows avoid adverse effect from wiring capacitance. Wiring should short possible. Wiring should cross other signal lines. Wiring should placed close varying high current. potential oscillator capacitor ground should same VSS. ground wiring ground pattern which high current flows. fetch signal from oscillator. When main system clock stopped system operated subsystem clock, subsystem clock should switched again main system clock after oscillation stabilization time secured software.
µPD78052, 78053, 78054, 78055, 78056, 78058
Subsystem Clock Oscillation Circuit Characteristics +85°C,
Resonator Crystal resonator
Recommended Circuit
Parameter Oscillator frequency (fXT) Note
Test Conditions
MIN.
TYP. 32.768
MAX.
Unit
Oscillation stabilization time Note input frequency (fXT) Note input high/low level width (tXTH tXTL)
External clock
Notes Indicates only oscillation circuit characteristics. Refer Characteristics instruction execution time. Time required stabilize oscillation after reaches oscillator voltage range.
Cautions When using subsystem clock oscillator, wiring area enclosed with broken line should carried follows avoid adverse effect from wiring capacitance. Wiring should short possible. Wiring should cross other signal lines. Wiring should placed close varying high current. potential oscillator capacitor ground should same VSS. ground wiring ground pattern which high current flows. fetch signal from oscillator. subsystem clock oscillation circuit circuit with amplification level,more prone misoperation noise than main system clock.
µPD78052, 78053, 78054, 78055, 78056, 78058
Recommended Oscillation Circuit Constant µPD78052, 78053, 78054, 78055, 78056 Main system clock: ceramic resonator +85°C)
Manufacturer Product Name Frequency (MHz) Murata Mfg. Co., Ltd. Kyocera Corp. CSA5.00MG CST5.00MGW KBR-5.0MSA KBR-5.0MKS KBR-5.0MWS PBRC 5.00A Corp. CCR4.0MC3 CCR5.0MC3 5.00 5.00 5.00 5.00 5.00 5.00 4.00 5.00 Recommended Circuit consonant (pF) chip chip chip chip chip (pF) chip chip chip chip chip Oscillator Voltage range MIN. MAX. Capacitor chip Lead type Capacitor chip, lead type Capacitor chip, lead type Chip type Capacitor chip Capacitor chip Remarks
Main system clock: crystal resonator +70°C)
Recommended Circuit Constant (pF) Daishinku Corp. SMD-49 3.579545 (pF) Oscillator Voltage Range MIN. MAX.
Manufacturer
Product Name
Frequency (MHz)
Subsystem clock: crystal resonator +70°C)
Recommended Circuit Constant (pF) Daishinku Corp. DT-38 (1TA252E00) 32.768 (pF) Oscillator Voltage Range MIN. MAX.
Manufacturer
Product Name
Frequency (MHz)
Caution
oscillation circuit constants oscillation voltage range indicate conditions stable oscillation. However, they guarantee accuracy oscillation frequency. application circuit requires accuracy oscillation frequency, necessary oscillation frequency application circuit. this, necessary directly contact manufacturer resonator being used.
µPD78052, 78053, 78054, 78055, 78056, 78058
µPD78058 Main system clock: ceramic resonator +85°C)
Manufacturer Product Name Frequency (MHz) Kyocera Corp. PBRC4.19A PBRC4.19B KBR-4.19MSA KBR-4.19MKS PBRC4.91A PBRC4.91B KBR-4.91MSA KBR-4.91MKS 4.19 4.19 4.19 4.19 4.91 4.91 4.91 4.91 Recommended Circuit consonant (pF) chip chip chip chip (pF) chip chip chip chip Oscillator Voltage range MIN. MAX. Capacitor chip Capacitor chip Capacitor chip Capacitor chip Remarks
Caution
oscillation circuit constants oscillation voltage range indicate conditions stable oscillation. However, they guarantee accuracy oscillation frequency. application circuit requires accuracy oscillation frequency, necessary oscillation frequency application circuit. this, necessary directly contact manufacturer resonator being used.
Capacitance 25°C,
Parameter Input capacitance Input/output capacitance Symbol Test Conditions Measured pins retured Measured pins retured P06, P17, P27, P37, P47, P57, P67, P72, P120 P127, P130, P131 MIN. TYP. MAX. Unit
Remark characteristics dual-function pins same those port pins unless otherwise specified. Note P07, inverter input reverse phase pin.
µPD78052, 78053, 78054, 78055, 78056, 78058
Characteristics +85°C,
Parameter Input voltage, high Symbol VIH1 Test Conditions P17, P21, P23, P32, P37, P47, P57, P67, P71, P120 P127, P130, P131 P06, P20, P22, P27, P33, P34, P70, P72, RESET VIH3 (N-ch open-drain) VIH4 MIN. 0.85 VIH5 XT1/P07, TYP. 0.15 Unit
VIH2
VNote Input voltage, VIL1 P17, P21, P23, P32, P37, P47, P57, P67, P71, P120 P127, P130, P131 P06, P20, P22, P27, P33, P34, P70, P72, RESET VIL4 VIL5 XT1/P07, Output voltage, high Output voltage, VOL1 -1mA -100 P57, VNote
VIL2
VIL3
P06, P17, P27, P37, P47, P67, P72, P120 P127, P130, P131 VOL2 SB0, SB1, SCK0 open-drain, pulled-up
VOL3
Note using P07/X1 pins P07, input reverse phase pin. Remark characteristics dual-function port same unless specified otherwise.
µPD78052, 78053, 78054, 78055, 78056, 78058
Characteristics +85°C,
Parameter Input leakage current, high Symbol ILIH1 Test Conditions P06, P17, P27, P37, P47, P57, P67, P72, P120 P127, P130, P131, RESET XT1/P07, P06, P17, P27, P37, P47, P57, P67, P72, P120 P127, P130, P131, RESET XT1/P07, VOUT VOUT P06, P17, P27, P37, P47, P57, P67, P72, P120 P127, P130, P131 MIN. TYP. Unit
ILIH2 ILIH3 Input leakage current, ILIL1
ILIL2 ILIL3 Output leakage current, high Output leakage current, ILOH ILOL
Note
Mask option pull- resistor Software pullR2 resistor Note
Notes without on-chip pull-up resistor (specifiable mask option), low-level input leakage current -200 (MAX.) flows only during clocks wait) after instruction been executed read port (P6) port mode register (PM6). Outside period clocks following executing read-out instruction, current (MAX.). software pull-up resistor used only range Remark characteristics dual-function port same unless specified otherwise.
µPD78052, 78053, 78054, 78055, 78056, 78058
Characteristics +85°C,
Parameter Power supply current Note Symbol
IDD1
Test Conditions Crystal oscillation operating mode (fXX MHz)
Note
MIN.
Note Note Note Note Note
TYP. 0.35 0.65 0.05 0.05
1.05 19.5 1.95 12.5
Unit
Crystal oscillation operating mode (fXX MHz) Note IDD2 Crystal oscillation HALT mode (fXX MHz)
Note
Crystal oscillation HALT mode (fXX MHz) Note IDD3 32.768 Crystal oscillation operating mode Note
IDD4
32.768 Crystal oscillation HALT mode Note
IDD5
STOP mode When feedback resistor used STOP mode When feedback resistor unused
IDD6
Notes Operating high-speed mode (when processor clock control register (PCC) 00H). Operating low-speed mode (when 04H). Operation with main system clock fX/2 (when oscillation mode selection register (OSMS) 00H) Operation with main system clock (when OSMS 01H) This current flows AVDD pins. However, current flowing converter, converter, on-chip pull-up resistor included. When main system clock operation halted
µPD78052, 78053, 78054, 78055, 78056, 78058
Characteristics Basic operation +85°C,
Parameter Cycle time (Min. instruction execution time) Symbol Test Conditions Operating main system clock (fXX MHz)Note Operating main system clock (fXX MHz)Note Operating system clock TI00, TI01, TI1, input frequency TI00 input high/ level width TI01, TI1, input high/ low-level width Interrupt request input high/low -level width RESET level width MIN. 40Note tTIH, tTIL tTIH, tTIL 8/fsamNote tINTH, tINTL INTP0 INTP1 INTP6, 8/fsamNote tRSL TYP. MAX. Unit
Notes Main system clock fX/2 operation (when oscillation mode selection register (OSMS) 00H) Main system clock operation (when OSMS 01H) external clock. When crystal oscillation used, minimum value combination with bits (SCS0) (SCS1) sampling clock select register (SCS), selection fsam possible between fXX/2N, fXX/32, fXX/64 fXX/128 (when
µPD78052, 78053, 78054, 78055, 78056, 78058
fX/2 main system clock operation)
main system clock operation)
Cycle Time [µs]
Operation Guaranteed Range
Cycle Time [µs]
Operation Guaranteed Range
Supply Voltage
Supply Voltage
µPD78052, 78053, 78054, 78055, 78056, 78058
Read/write operation When PCC2 PCC0 000B +85°C,
Parameter ASTB high-level width Address setup time Address hold time Data input time from address Symbol tASTH tADS tADH tADD1 tADD2 Data input time from tRDD1 tRDD2 Read data hold time low-level width tRDH tRDL1 tRDL2 WAIT input time from tRDWT1 tRDWT2 WAIT input time from WAIT low-level width Write data setup time Write data hold time low-level width delay time from ASTB delay time from ASTB ASTB delay time from external fetch Address hold time from external fetch Write data output time from Write data output time from Address hold time from delay time from WAIT delay time from WAIT tRDWD tWRWD
tWRADH
Test Conditions
MIN. 0.85tCY 0.85tCY
MAX.
Unit
(2.85 2n)tCY 2n)tCY 2n)tCY (2.85 2n)tCY 2n)tCY (2.85 2n)tCY 0.85tCY 2tCY 2tCY (1.15 2n)tCY (2.85 2n)tCY (2.85 2n)tCY 0.85tCY 0.85tCY 1.15tCY 2n)tCY
tWRWT tWTL tWDS tWDH tWRL tASTRD tASTWR tRDAST
tRDADH
0.85tCY
1.15tCY
0.85tCY 1.15tCY 1.15tCY 1.15tCY 3.15tCY 3.15tCY
tWTRD tWTWR
Remarks MCS: Oscillation mode selection register (OSMS) PCC2 PCC0: Processor clock control register (PCC) bits TCY/4 indicates number waits.
µPD78052, 78053, 78054, 78055, 78056, 78058
When except PCC2 PCC0 000B +85°C,
Parameter ASTB high-level width Symbol tASTH Test Conditions MIN. Address setup time tADS Address hold time tADH 0.4tCY 0.37tCY Data input time from address tADD1 2n)tCY 2n)tCY tADD2 2n)tCY 2n)tCY Data input time from tRDD1 (1.4 2n)tCY (1.37 2n)tCY tRDD2 (2.4 2n)tCY (2.37 2n)tCY Read data hold time low-level width tRDH tRDL1 (1.4 2n)tCY (1.37 2n)tCY tRDL2 (2.4 2n)tCY (2.37 2n)tCY WAIT input time from tRDWT1 tRDWT2 2tCY 2tCY WAIT input time from tWRWT 2tCY 2tCY WAIT low-level width Write data setup time tWTL tWDS 2n)tCY (2.4 2n)tCY (2.37 2n)tCY Write data hold time low-level width tWDH tWRL (2.4 2n)tCY (2.37 2n)tCY delay time from ASTB tASTRD 0.4tCY 0.37tCY delay time from ASTB tASTWR 1.4tCY 1.37tCY 2n)tCY MAX. Unit
Remarks MCS: Oscillation mode selection register (OSMS) PCC2 PCC0: Processor clock control register (PCC) bits TCY/4 indicates number waits.
µPD78052, 78053, 78054, 78055, 78056, 78058
When except PCC2 PCC0 000B +85°C,
Parameter ASTB delay time from external fetch Address hold time from external fetch Write data output time from Symbol tRDAST tRDADH Test Conditions MIN. MAX. Unit
tRDWD
0.4tCY 0.37tCY
2.6tCY 2.63tCY 2.6tCY 2.63tCY
Write data output time from
tWRWD
Address hold time from
tWRADH
delay time from WAIT
tWTRD
0.6tCY 0.63tCY
delay time from WAIT
tWTWR
0.6tCY 0.63tCY
Remarks MCS: Oscillation mode selection register (OSMS) PCC2 PCC0: Processor clock control register (PCC) bits TCY/4 indicates number waits.
µPD78052, 78053, 78054, 78055, 78056, 78058
Serial interface +85°C, Serial interface channel 3-wire serial mode (SCK0. Internal clock output)
Symbol tKCY1 Test Conditions MIN. 1600 3200 SCK0 high/low-level width setup time SCK0) tKH1, tKL1 tKSI1
tKSO1
Parameter SCK0 cycle time
TYP.
MAX.
Unit
tKCY1/2 tKCY1/2
tSIK1
hold time (from SCK0) output delay time from SCK0
Note
Note load capacitance output line. (ii) 3-wire serial mode (SCK0. External clock input)
Parameter SCK0 cycle time Symbol tKCY2 Test Conditions MIN. 1600 3200 SCK0 high/low-level width tKH2, tKL2 1600 setup time SCK0) tSIK2 hold time (from SCK0) output delay time from SCK0 SCK0 rise, fall time tKSI2 TYP. MAX. Unit
tKSO2
Note
tR2,
When using external device expansion function When using external device expansion function
1000
Note load capacitance output line.
µPD78052, 78053, 78054, 78055, 78056, 78058
(iii) mode (SCK0. Internal clock output)
Parameter SCK0 cycle time Symbol tKCY3 Test Conditions MIN. 3200 SCK0 high/low-level width tKH3, tKL3 tKCY3/2 tKCY3/2 SB0, setup time SCK0) SB0, hold time (from SCK0) SB0, output delay time from SCK0 SB0, from SCK0 SCK0 from SB0, SB0, high-level width SB0, low-level width tKSO3 Note tKCY3 tKCY3 tKCY3 tKCY3 1000 tSIK3 tKSI3 tKCY3/2 TYP. MAX. Unit
tKSB tSBK tSBH tSBL
Note load resistors load capacitance SCK0, output line. (iv) mode (SCK0. External clock input)
Parameter SCK0 cycle time Symbol tKCY4 Test Conditions MIN. 3200 SCK0 high/low-level width tKH4, tKL4 1600 SB0, setup time SCK0) SB0, hold time (from SCK0) SB0, output delay time from SCK0 SB0, from SCK0 SCK0 from SB0, SB0, high-level width SB0, low-level width SCK0 rise, fall time tSIK4 tKSI4 tKSO4 Note tKCY4/2 tKCY4 tKCY4 tKCY4 tKCY4 When using external device expansion fanction When using external device expansion function 1000 1000 TYP. MAX. Unit
tKSB tSBK tSBH tSBL tR4,
Note load resistors load capacitance output line.
µPD78052, 78053, 78054, 78055, 78056, 78058
2-wire serial mode (SCK0. Internal clock output)
Parameter SCK0 cycle time Symbol tKCY5 SCK0 high-level width tKH5
Note
Test Conditions
MIN. 1600 3200
TYP.
MAX.
Unit
tKCY5/2 tKCY5/2
SCK0 low-level width
tKL5
tKCY5/2 tKCY5/2
SB0, setup time SCK0)
tSIK5
SB0, hold time (from SCK0) SB0, output delay time from SCK0
tKSI5
tKSO5
Note load resistors load capacitance SCK0, output line. (vi) 2-wire serial mode (SCK0. Internal clock input)
Parameter SCK0 cycle time Symbol tKCY6 Test Conditions MIN. 1600 3200 SCK0 high-level width tKH6 1300 SCK0 low-level width tKL6 1600 SB0, setup time SCK0) SB0, hold time (from SCK0) SB0, output delay time from SCK0 SCK0 rise, fall time tKSI6 tKCY6/2 tSIK6 TYP. MAX. Unit
tKSO6
Note
tR6,
When using external device expansion function When using external device expansion function
1000
Note load resistors load capacitance SCK0, output line.
µPD78052, 78053, 78054, 78055, 78056, 78058
Serial interface channel 3-wire serial mode (SCK1.Internal clock output)
Parameter SCK1 cycle time Symbol tKCY7 Test Conditions MIN. 1600 3200 SCK1 high/low-level width tKH7, tKL7 tSIK7 tKCY7/2 tKCY7/2 hold time (from SCK1) output delay time from SCK1 tKSI7 tKSO7 Note TYP. MAX. Unit
setup time SCK1)
Note load capacitance output line. (ii) 3-wire serial mode (SCK1.External clock input)
Parameter SCK1 cycle time Symbol tKCY8 Test Conditions MIN. 1600 3200 SCK1 high/low-level width tKH8, tKL8 1600 setup time SCK1) hold time (from SCK1) output delay time from SCK1 SCK1 rise, fall time tSIK8 tKIS8 tKSO8 tR8,
Note
TYP.
MAX.
Unit
1000
When using external device expansion function When using external device expansion function
Note load capacitance output line.
µPD78052, 78053, 78054, 78055, 78056, 78058
(iii) 3-wire serial mode with automatic transmit/receive function (SCK1.Internal clock output)
Parameter SCK1 cycle time Symbol tKCY9 Test Conditions MIN. 1600 3200 SCK1 high/low-level width tKH9, tKL9 tSIK9 tKCY9/2 tKCY9/2 hold time (from SCK1) output delay time from SCK1 from SCK1 Strobe signal high-level width tKSI9 tKSO9 tSBD tSBW 6.0V Note tKCY9/2 tKCY9 tKCY9 Busy signal setup time busy signal detection timing) Busy signal hold time (from busy signal detection timing) tBYS tBYH SCK1 from busy inactive tSPS 2tKCY9 tKCY9/2 tKCY9 tKCY9 TYP. MAX. Unit
setup time SCK1)
Note load capacitance output line. (iv) 3-wire serial mode with automatic transmit/receive function (SCK1.External clock input)
Parameter SCK1 cycle time Symbol tKCY10 Test Conditions MIN. 1600 3200 SCK1 high/low-level width tKH10, tKL10 1600 setup time SCK1) hold time (from SCK1) output delay time from SCK1 SCK1 rise, fall time tSIK10 tKIS10 tKSO10
Note
TYP.
MAX.
Unit
1000
tR10, tF10 When using external device expansion function When using external device expansion function
Note load capacitance output line.
µPD78052, 78053, 78054, 78055, 78056, 78058
Serial interface channel 3-wire serial mode (SCK2.Internal clock output)
Parameter SCK2 cycle time Symbol tKCY11 Test Conditions MIN. 1600 3200 SCK2 high/low-level width tKH11, tKL11 tSIK11 tKCY7/2 tKCY7/2 hold time (from SCK2) output delay time from SCK2 tKSI11 tKSO11 Note TYP. MAX. Unit
setup time SCK2)
Note load capacitance output line. (ii) UART mode (Dedicated baud rate generator output)
Parameter Transfer rate Symbol Test Conditions MIN. TYP. MAX. 78125 39063 19531 Unit
(iii) UART mode (External clock input)
Parameter ASCK cycle time Symbol tKCY12 Test Conditions MIN. 1600 3200 ASCK high-/low-level width tKH12, tKL12 1600 Transfer rate 39063 19531 9766 ASCK rise, fall time tR12, tF12 when using external device expansion function. 1000 TYP. MAX. Unit
µPD78052, 78053, 78054, 78055, 78056, 78058
Timing Test Point (Excluding Input)
Test Points
Clock Timing
1/fX
VIH4 (MIN.) VIL4 (MAX.)
Input
1/fXT
tXTL Input
tXTH VIH5 (MIN.) VIL5 (MAX.)
Timing
1/fTI tTIL TI00, TI01, TI0,
tTIH
µPD78052, 78053, 78054, 78055, 78056, 78058
Read/Write Operation External fetch wait)
Lower 8-Bit Address tADS tASTH ASTB
Upper 8-Bit Address tADD1 Hi-z Operation Code tRDD1 tRDADH tRDAST
tADH
tASTRD tRDL1 tRDH
External fetch (wait insertion)
Lower 8-Bit Address tADS tASTH ASTB
Upper 8-Bit Address
tADD1 Hi-z tRDD1 tADH tRDAST Operation Code tRDADH
tASTRD tRDL1 tRDH
WAIT tRDWT1 tWTL tWTRD
µPD78052, 78053, 78054, 78055, 78056, 78058
External data access wait)
Lower 8-Bit Address tADS tADH tASTH ASTB
Upper 8-Bit Address
tADD2 Hi-z tRDD2 tRDH Read Data Hi-z Write Data Hi-z
tASTRD tRDL2 tRDWD tWRWD tASTWR tWRL tWRADH tWDS tWDH
External data access (wait insertion)
Lower 8-Bit Address tADS tADH tASTH ASTB
Upper 8-Bit Address
tADD2 Hi-z tRDD2 tRDH Read Data Hi-z Write Data Hi-z
tASTRD tRDL2 tRDWD tWDWR tASTWR tWRL tWRADH tWDS tWDH
WAIT tRDWT2 tWTL tWTRD tWRWT tWTL tWTWR
µPD78052, 78053, 78054, 78055, 78056, 78058
Serial Transfer Timing 3-wire serial mode
tKCYm tKLm SCK0 SCK2 tSIKm tKSIm tKHm
tKSOm
Input Data
Output Data
mode (bus release signal transfer)
tKCY3, tKL3, SCK0 tKSB tSBL tSBH tSBK tSIK3, tKSI3, tKH3,
SB0, tKSO3,
mode (command signal transfer)
tKCY3,4
tKL3, SCK0
tKH3,
tSIK3, tKSB tSBK tKSI3,
SB0, tKSO3,
µPD78052, 78053, 78054, 78055, 78056, 78058
2-wire serial mode
tKCY5,
tKL5, SCK0 tSIK5, tKSO5, SB0,
tKH5,
tKSI5,
3-wire serial mode with automatic transmit/receive function
tSIK9,
tKSI9, tKH9,
tKSO9, SCK1
tR10
tF10
tKL9, tKCY9,
tSBD
tSBW
3-wire serial mode with automatic transmit/receive function (busy processing)
SCK1
Note
Note tBYS
10+n Note tBYH tSPS
BUSY (Active high)
Note signal actually driven here; shown such indicate timing.
µPD78052, 78053, 78054, 78055, 78056, 78058
UART mode (external clock input)
KCY12 KL12 tR12 KH12 tF12
ASCK
Converter Characteristics +85°C, AVDD AVSS
Parameter Resolution Overall errorNote AVREF0 AVDD AVREF0 Conversion time Sampling time Analog input voltage Reference voltage Resistance between AVREF0 AVSS tCONV tSAMP VIAN AVREF0 RAIREF0 19.1 12/fxx AVSS
Symbol
Test Conditions
MIN.
TYP.
MAX. ±0.6 ±1.4
Unit
AVREF0 AVDD
Note Overroll error excluding quantization error (±1/2 LSB). indicated ratio full-scale value. Remark Main system clock frequency fX/2) Main system clock oscillation frequency Converter Characteristics +85°C, AVSS
Parameter Resolution Overall error
Note Note Note
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
Settling time
Note
C=30pF
AVREF1 AVREF1 AVREF1
Output resistance Analog reference voltage AVREF1 current
AVREF1 IREF1
DACS0, DACS1
Note
Note
Notes denote converter output load resistance load capacitance, respectively. Value converter channel Remark DACS0 DACS1: conversion value setting register
µPD78052, 78053, 78054, 78055, 78056, 78058
Data Memory STOP Mode Supply Voltage Data Retention Characteristics +85°C)
Parameter Data retention power supply voltage Data retention power supply current Release signal time Oscillation stabiliation wait time Symbol VDDDR IDDDR VDDDR Subsystem clock stop feed-back resistor disconnected Release RESET Release interrupt request Note
Test Conditions
MIN.
TYP.
MAX.
Unit
tSREL tWAIT
Note combination with bits (OSTS0 OSTS2) oscillation stabilization time select register (OSTS) selection 212/fXX 214/fXX 217/fXX possible. Remark Main system clock frequency fX/2) Main system clock oscillatior frequency Data Retention Timing (STOP Mode Release RESET)
Internal Reset Operation HALT Mode STOP Mode Operating Mode
Data Retension Mode
STOP Instruction Execution RESET
VDDDR tSREL
tWAIT
Data Retention Timing (Standby Release Signal: STOP Mode Release Interrupt Request Signal)
HALT Mode STOP Mode Operating Mode
Data Retension Mode
STOP Instruction Execution Standby Release Signal (Interrupt Request)
VDDDR tSREL
tWAIT
µPD78052, 78053, 78054, 78055, 78056, 78058
Interrupt Request Input Timing
tINTL INTP0 INTP6
tINTH
RESET Input Timing
tRSL
RESET
µPD78052, 78053, 78054, 78055, 78056, 78058
CHARACTERISTIC CURVES (REFERENCE VALUE)
MHz) 25°C) 10.0 HALT osillation, osillation)
Supply Current (mA)
0.05
HALT stop, osillation)
0.01
0.005
0.001
Supply Voltage
µPD78052, 78053, 78054, 78055, 78056, 78058
MHz, MHz) 25°C) 10.0
HALT osillation, osillation)
Supply Current (mA)
0.05
HALT stop, osillation)
0.01
0.005
0.001
Supply Voltage
µPD78052, 78053, 78054, 78055, 78056, 78058
PACKAGE DRAWINGS
PLASTIC
detail lead
NOTE Each lead centerline located within 0.13 (0.005 inch) true position (T.P.) maximum material condition.
ITEM MILLIMETERS 17.20±0.20 14.00±0.20 14.00±0.20 17.20±0.20 0.825 0.825 0.32±0.06 0.13 0.65 (T.P.) 1.60±0.20 0.80±0.20 0.17 +0.03 -0.07 0.10 1.40±0.10 0.125±0.075 1.70 MAX. INCHES 0.677±0.008 0.551 +0.009 -0.008 0.551 +0.009 -0.008 0.677±0.008 0.032 0.032 0.013 +0.002 -0.003 0.005 0.026 (T.P.) 0.063±0.008 0.031 +0.009 -0.008 0.007 +0.001 -0.003 0.004 0.055±0.004 0.005±0.003 0.067 MAX. P80GC-65-8BT
Remark Dimensions materials product same those mass-production products.
µPD78052, 78053, 78054, 78055, 78056, 78058
PLASTIC TQFP (FINE PITCH)
detail lead
NOTE Each lead centerline located within 0.10 (0.004 inch) true position (T.P.) maximum material condition.
ITEM MILLIMETERS 14.0±0.2 12.0±0.2 12.0±0.2 14.0±0.2 1.25 1.25 0.22 +0.05 -0.04 0.10 (T.P.) 1.0±0.2 0.5±0.2 0.145 +0.055 -0.045 0.10 1.05 0.05±0.05 5°±5° 1.27 MAX. INCHES 0.551 +0.009 -0.008 0.472 +0.009 -0.008 0.472 +0.009 -0.008 0.551 +0.009 -0.008 0.049 0.049 0.009±0.002 0.004 0.020 (T.P.) 0.039 +0.009 -0.008 0.020 +0.008 -0.009 0.006±0.002 0.004 0.041 0.002±0.002 5°±5° 0.050 MAX. P80GK-50-BE9-4
Remark Dimensions materials product same those mass-production products.
µPD78052, 78053, 78054, 78055, 78056, 78058
RECOMMENDED SOLDERING CONDITIONS
This product should soldered mounted under conditions recommended table below. detail recommended soldering conditions, refer information document Semiconductor Device Mounting Technology Manual (C10535E). soldering methods conditions other than those recommended below, contact sales personnel. Table 14-1. Surface Mounting Type Soldering Conditions (1/2) 80-pin plastic
80-pin plastic 80-pin plastic 80-pin plastic 80-pin plastic 80-pin plastic
Soldering Method Infrared reflow Wave soldering Soldering Conditions Package peak temperature: 235°C, Duration: sec. max. 210°C above), Number times: Twice max. Package peak temperature: 215°C, Duration: sec. max. 200°C above), Number times: Twice max. Solder bath temperature: 260°C less, Duration: sec. max. Number times: Once Preparatory heating temepratuire: 120°C max. (package surface temperature) Time limit: daysNote (thereafter hours 125°C prebaking required) temperature: 300°C max. Duration: sec. max. (per device side) Recommended Condition Symbol IR35-100-2 VP15-100-2 WS60-100-1
Partial Heating
Caution
more than soldering method should avoided (except case partial heating).
µPD78052, 78053, 78054, 78055, 78056, 78058
Table 14-1. Surface Mounting Type Soldering Conditions (2/2) 80-pin plastic TQFP
80-pin plastic TQFP 80-pin plastic TQFP 80-pin plastic TQFP 80-pin plastic TQFP 80-pin plastic TQFP
Soldering Method Infrared reflow
Soldering Conditions Package peak temperature: 235°C, Duration: sec. max. 210°C above), Number times: Thrice max., Time limit: days Note (thereafter hours 125°C prebaking required) <Precautions> Baking cannot applied other than heat-resistant trays (magazine, taping, nonheat-resistant trays) when product wrapped. Package peak temperature: 215°C, Duration: sec. max. 200°C above), Number times: Thrice max., Time limit: days Note (thereafter hours 125°C prebaking required) <Precautions> Baking cannot applied other than heat-resistant trays (magazine, taping, nonheat-resistant trays) when product wrapped. temperature: 300°C max. Duration: sec. max. (per device side)
Recommended Condition Symbol IR35-107-3
VP15-107-3
Partial Heating
Note storage period after dry-pack decompression storage conditions max. 25°C, Caution more than soldering method should avoided (except case partial heating).
µPD78052, 78053, 78054, 78055, 78056, 78058
APPENDIX DEVELOPMENT TOOLS
following tools available development systems using µPD78054 subseries: Language Processing Software
RA78K/0Note CC78K/0
Note Note
Assembler package common 78K/0 series compiler package common 78K/0 series Device file µPD78054 subseries compiler library source file common 78K/0 series
DF78054
CC78K/0-LNote
PROM Writing Tools
PG-1500 PA-78P054GC PA-78P054GK PA-78P054KK-T PG-1500 ControllerNote PROM programmer Programmer adapter connectd PG-1500
Control program PG-1500
Debugging Tools
IE-78000-R IE-78000-R-A IE-78000-R-BK IE-780308-R-EM IE-78000-R-SV3 IE-78000-98-IF-B IE-78000-98N-IF IE-78000-98-IF-B EP-78230GC-R EP-78054GK-R EV-9200GC-80 TGK-080SBW In-circuit emulator common 78K/0 series In-circuit emulator common 78K/0 series (for integrated debugger) Break board common 78K/0 series Emulation board evaluating µPD780308 subseries Interface adapter cable when using host machine (for IE-78000-R-A) Interface adapter when using PC-9800 series (except notebook computers) host machine (for IE-78000-R-A) Interface adapter cable when using PC-9800 series notebook computers host machine (for IE-78000-R-A) Interface adapter when using IBM/PC ATand compatibles host machine (for IE-78000-R-A) Emulation probe common µPD78234 subseries Emulation probe µPD78054 subseries Socket mounted target system created 80-pin plastic (GC-8BT type) Adapter mounted target system created 80-pin plastic TQFP (GK-BE9 Type). This product from TOKYO ELETECH CORPORATION (TEL (03) 5295-1661) When purchasing this product, please consult with sales offices. System simulator common 78K/0 series Integrated debugger IE-78000-R-A Screen debugger IE-78000-R Device file µPD78054 subseries
SM78K0Note ID78K0
Note
SD78K/0Note DF78054
Note
Real-time
RX78K/0Note MX78K0
Note
Real-time 78K/0 series 78K/0 series
µPD78052, 78053, 78054, 78055, 78056, 78058
Fuzzy Inference Development Support System
FE9000Note 1/FE9200Note FT9080Note 1/FT9085Note FI78K0Note FD78K0Note Fuzzy knowledge data creation tool Translator Fuzzy inference module Fuzzy inference debugger
Notes PC-9800 series (MS-DOS based PC/AT compatibles DOSTM/IBM DOSTM/MS-DOS) based HP9000 series 300(HP-UXTM) based HP9000 series based PC-9800 series (MS-DOS WindowsTM) based PC/AT compatible DOS/IBM DOS/MS-DOS Windows) based NEWS(NEWS-OSTM) based Remarks Please refer 78K/0 Series Selection Guide (U11126E) information third party development tools. RA78K/0, CC78K/0, SM78K0, ID78K0, SD78K/0, RX78K/0 used combination with DF78054.
(HP-UX) based, SPARCstation
(Sun based, EWS4800 series (EWS-UX/V)
µPD78052, 78053, 78054, 78055, 78056, 78058
APPENDIX RELATED DOCUMENTS
Documents Related Devices
Document Name Document English Japanese U11747J U12327J U12346J IC-8884 U12326J U10904J U10903J U10102J U10182J IEA-718
µPD78054 78054Y subseries user's manual µPD78052, 78053, 78054, 78055, 78056, 78058 data sheet µPD78P054 Data Sheet µPD78P058 Data Sheet
78K/0 series user's manual instruction 78K/0 series instruction 78K/0 series instruction list
U11747E This document IC-3216 U10417E U12326E U10182E IEA-1289
µPD78054 subseries special function register table
78K/0 series application note Fundamental (III) Floating-point operation program volume
Development Tool Documents (User's Manual)
Document Name RA78K series assembler package Operation Language RA78K series structured assembler preprocessor RA78K0 assembler package Operation Assembly language Structured assembly language CC78K series compiler Operation Language CC78K0 compiler Operation Language CC78K/0 compiler application note CC78K series library source file PG-1500 PROM programmer PG-1500 controller PC-9800 series (MS-DOS) based PG-1500 controller series DOS) based IE-78000-R IE-78000-R-A IE-78000-R-BK IE-780308-R-EM EP-78230 EP-78054GK-R Programming know-how Document English EEU-1399 EEU-1404 EEU-1402 U11802E U11801E U11789E EEU-1280 EEU-1284 U11517E U11518E EEA-1208 U11940E EEU-1291 U10540E U11376E U10057E EEU-1427 U11362E EEU-1515 EEU-1468 Japanese EEU-809 EEU-815 U12323J U11802J U11801J U11789J EEU-656 EEU-655 U11517J U11518J EEA-618 U12322J U11940J EEU-704 EEU-5008 U11376J U10057J EEU-867 U11362J EEU-985 EEU-932
Caution
documents listed above subject change without notice. sure latest documents designing your system.
µPD78052, 78053, 78054, 78055, 78056, 78058
Document Name SM78K0 system simulator Windows based SM78K series system simulator Reference External components user-open interface specification Reference Reference Guide
Document English U10181E U10092E Japanese U10181J U10092J
ID78K0 integrated debugger based ID78K0 integrated debugger based ID78K0 integrated debugger Windows based
U11539E U11649E U10539E U11279E
U11151J U11539J U11649J EEU-852 U10952J EEU-5024 U11279J
SD78K/0 screen debugger PC-9800 series (MS-DOS) based Introduction Reference SD78K/0 screen debugger PC/AT DOS) based Introduction Reference
Documents Related Embedded Software (User's Manual)
Document Name 78K/0 series real-time Fundamental Installation 78K/0 series MX78K0 Fuzzy knowledge data creation tool 78K/0, 78K/II, 87AD series fuzzy inference development suppport system translator 78K/0 series fuzzy inference development support system fuzzy inference module 78K/0 series fuzzy inference development support system fuzzy inference debugger Fundamental Document English U11537E U11536E U12257E EEU-1438 EEU-1444 EEU-1441 EEU-1458 Japanese U11537J U11536J U12257J EEU-829 EEU-862 EEU-858 EEU-921
Other Related Documents
Document Name package manual Semiconductor device mounting technology manual Quality grade semiconductor devices semiconductor device reliability/quality control system Guide Prevent Damage Semiconductor Devices Electrostatic Discharge (ESD) Semiconductor device quality guarantee guide Product guide related microcomputer other manufacturers Document English Japanese C10943X C10535E C11531E C10983E C11892E MEI-1202 C10535J C11531J C10983J C11892J C11893J U11416J
Caution
documents listed above subject change without notice. sure latest documents designing your system.
µPD78052, 78053, 78054, 78055, 78056, 78058
[MEMO]
µPD78052, 78053, 78054, 78055, 78056, 78058
NOTES CMOS DEVICES
PRECAUTION AGAINST SEMICONDUCTORS
Note: Strong electric field, when exposed device, cause destruction gate oxide ultimately degrade device operation. Steps must taken stop generation static electricity much possible, quickly dissipate once, when occurred. Environmental control must adequate. When dry, humidifier should used. recommended avoid using insulators that easily build static electricity. Semiconductor devices must stored transported anti-static container, static shielding conductive material. test measurement tools including work bench floor should grounded. operator should grounded using wrist strap. Semiconductor devices must touched with bare hands. Similar precautions need taken boards with semiconductor devices
HANDLING UNUSED INPUT PINS CMOS
Note: connection CMOS device inputs cause malfunction. connection provided input pins, possible that internal input level generated noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar NMOS devices. Input levels CMOS devices must fixed high using pull-up pull-down circuitry. Each unused should connected with resistor, considered have possibility being output pin. handling related unused pins must judged device device related specifications governing devices.
STATUS BEFORE INITIALIZATION DEVICES
Note: Power-on does necessarily define initial status device. Production process does define initial operation status device. Immediately after power source turned devices with reset function have been initialized. Hence, power-on does guarantee out-pin levels, settings contents registers. Device initialized until reset signal received. Reset operation must executed immediately after power-on devices having reset function.
µPD78052, 78053, 78054, 78055, 78056, 78058
Regional Information
Some information contained this document vary from country country. Before using product your application, please contact office your country obtain list authorized representatives distributors. They will verify: Device availability Ordering information Product release schedule Availability related technical literature Development environment specifications (for example, specifications third-party tools components, host computers, power plugs, supply voltages, forth) Network requirements addition, trademarks, registered trademarks, export restrictions, other legal issues also vary from country country.
Electronics Inc. (U.S.)
Santa Clara, California Tel: 800-366-9782 Fax: 800-729-9288
Electronics (Germany) GmbH
Benelux Office Eindhoven, Netherlands Tel: 040-2445845 Fax: 040-2444580
Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
Electronics (Germany) GmbH
Duesseldorf, Germany Tel: 0211-65 Fax: 0211-65
Electronics Hong Kong Ltd. Electronics (France) S.A.
Velizy-Villacoublay, France Tel: 01-30-67 Fax: 01-30-67 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
Electronics (UK) Ltd.
Milton Keynes, Tel: 01908-691-133 Fax: 01908-670-290
Electronics (France) S.A.
Spain Office Madrid, Spain Tel: 01-504-2787 Fax: 01-504-2860
Electronics Singapore Pte. Ltd.
United Square, Singapore 1130 Tel: 253-8311 Fax: 250-3583
Electronics Italiana s.r.1.
Milano, Italy Tel: 02-66 Fax: 02-66
Electronics Taiwan Ltd. Electronics (Germany) GmbH
Scandinavia Office Taeby, Sweden Tel: 08-63 Fax: 08-63 Taipei, Taiwan Tel: 02-719-2377 Fax: 02-719-5951
Brasil S.A.
Paulo-SP, Brasil Tel: 011-889-1680 Fax: 011-889-1689
J96.
µPD78052, 78053, 78054,78055,78056, 78058
trademark Corporation. IEBus trademark Corporation. MS-DOS Windows either registered trademarks trademarks Microsoft Corporation United States and/or other countries. DOS, PC/AT, trademarks International Business Machines Corporation. HP9000 series 300, HP9000 series 700, HP-UX trademarks Hewlett-Packard Company. SPARCstation trademark SPARC International, Inc. SunOS trademark Microsystems, Inc. NEWS NEWS-OS trademarks Sony corporation.
export this product from Japan regulated Japanese government. export this product prohibited without governmental license, need which must judged customer. export re-export this product from country other than Japan also prohibited without license from that country. Please call sales representative.
part this document copied reproduced form means without prior written consent Corporation. Corporation assumes responsibility errors which appear this document. Corporation does assume liability infringement patents, copyrights other intellectual property rights third parties arising from device described herein other liability arising from such device. license, either express, implied otherwise, granted under patents, copyrights other intellectual property rights Corporation others. While Corporation been making continuous effort enhance reliability semiconductor devices, possibility defects cannot eliminated entirely. minimize risks damage injury persons property arising from defect semiconductor device, customers must incorporate sufficient safety measures design, such redundancy, fire-containment, anti-failure features. devices classified into following three quality grades: "Standard", "Special", "Specific". Specific quality grade applies only devices developed based customer designated "quality assurance program" specific application. recommended applications device depend quality grade, indicated below. Customers must check quality grade each device before using particular application. Standard: Computers, office equipment, communications equipment, test measurement equipment, audio visual equipment, home electronic appliances, machine tools, personal electronic equipment industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment medical equipment (not specifically designed life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems medical equipment life support, etc. quality grade devices "Standard" unless otherwise specified NEC's Data Sheets Data Books. customers intend devices applications other than those specified Standard quality grade, they should contact sales representative advance. Anti-radioactive design implemented this product.
96.5

8-BIT SINGLE-CHIP MICROCONTROLLER DESCRIPTION 78058 µPD78054

Top Searches for this datasheet

Other recent searches