Ultra Power/Voltage CMOS SRAM 512K DESCRIPTION BS62UV4000
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Ultra Power/Voltage CMOS SRAM 512K
DESCRIPTION
BS62UV4000
Wide operation voltage 2.0V 3.6V Ultra power consumption 2.2V C-grade: 15mA (Max.) operating current -grade: 20mA (Max.) operating current 0.2uA (Typ.) CMOS standby current 3.0V C-grade: 20mA (Max.) operating current -grade: 25mA (Max.) operating current 0.25uA (Typ.) CMOS standby current High speed access time 120ns (Max.) 150ns (Max.) Automatic power down when chip deselected Three state outputs compatible Fully static operation Data retention supply voltage 1.5V Easy expansion with options
BS62UV4000 high performance, ultra power CMOS Static Random Access Memory organized 524,288 words bits operates from wide range 2.0V 3.6V supply voltage. Advanced CMOS technology circuit techniques provide both high speed power features with typical CMOS standby current 0.2uA@2.2V/25oC maximum access time 120ns. Easy memory expansion provided active chip enable (CE), active output enable (OE) three-state output drivers. BS62UV4000 automatic power down feature, reducing power consumption significantly when chip deselected. BS62UV4000 available JEDEC standard PDIP, TSOP, TSOP STSOP.
PRODUCT FAMILY
PRODUCT FAMILY
BS62UV4000TC BS62UV4000STC BS62UV4000SC BS62UV4000EC BS62UV4000PC BS62UV4000TI BS62UV4000STI BS62UV4000SI BS62UV4000EI BS62UV4000PI
OPERATING TEMPERATURE
RANGE
SPEED
POWER DISSIPATION
CCSB1
STANDBY
=3.0V
Operating
Vcc=2.0~3.6V 2.2V
2.2V =3.0V
TYPE TSOP STSOP TSOP2 PDIP TSOP STSOP TSOP2 PDIP
2.0V 3.6V
1.2uA
1.5uA
15mA
20mA
2.0V 3.6V
20mA
25mA
CONFIGURATIONS
BLOCK DIAGRAM
BS62UV4000SC BS62UV4000SI BS62UV4000EC BS62UV4000EI BS62UV4000PC BS62UV4000PI
Address Input Buffer
Decoder
2048
Memory Array 2048 2048
2048 Data Input Buffer Column Write Driver Sense Column Decoder Control Address Input Buffer
BS62UV4000TC BS62UV4000STC BS62UV4000TI BS62UV4000STI
Data Output Buffer
Brilliance Semiconductor Inc. reserves right modify document contents without notice.
R0201-BS62UV4000
Revision April 2002
DESCRIPTIONS
BS62UV4000
Function
These address inputs select 524,288 8-bit words active LOW. Chip enables must active when data read from write device. chip enable active, device deselected standby power mode. pins will high impedance state when device deselected.
Name
A0-A18 Address Input Chip Enable Input
Write Enable Input
write enable input active controls read write operations. With chip selected, when HIGH LOW, output data will present pins; when LOW, data present pins will written into selected memory location.
Output Enable Input
output enable input active LOW. output enable active while chip selected write enable inactive, data will present pins they will enabled. pins will high impedance state when inactive.
DQ0-DQ7 Data Input/Output Ports
These bi-directional ports used read data from write data into RAM. Power Supply Ground
TRUTH TABLE
MODE selected Output Disabled Read Write OPERATION High High DOUT CURRENT ICCSB, ICCSB1
ABSOLUTE MAXIMUM RATINGS(1)
SYMBOL VTERM TBIAS TSTG IOUT PARAMETER
Terminal Voltage Respect with
OPERATING RANGE
UNITS
RATING
-0.5 Vcc+0.5 +125 +150
RANGE
Commercial Industrial
AMBIENT TEMPERATURE
2.0V 3.6V 2.0V 3.6V
Temperature Under Bias Storage Temperature Power Dissipation Output Current
CAPACITANCE 25oC, MHz)
SYMBOL
Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability.
PARAMETER Input Capacitance Input/Output Capacitance
CONDITIONS
MAX.
UNIT
VIN=0V VI/O=0V
This parameter guaranteed 100% tested.
R0201-BS62UV4000
Revision April 2002
ELECTRICAL CHARACTERISTICS 70oC
PARAMETER NAME
BS62UV4000
TEST CONDITIONS
PARAMETER
Guaranteed Input Voltage(2) Guaranteed Input High Voltage(2) Input Leakage Current Output Leakage Current Output Voltage Output High Voltage Operating Power Supply Current Standby Current-TTL
MIN. TYP.
-0.5
MAX.
Vcc+0.2
UNITS
Max, Max, VI/O
-Vcc
Max, Min, -0.5mA VIL, 0mA, Fmax(3)
-1.6
ICCSB
VIH, Vcc-0.2V, 0.2V 0.2V
-0.2 0.25
ICCSB1
Standby Current-CMOS
Typical characteristics 25oC. These absolute values with respect device ground overshoots system tester notice included. Fmax 1/tRC
DATA RETENTION CHARACTERISTICS 70oC
SYMBOL
PARAMETER
Data Retention
TEST CONDITIONS
0.2V 0.2V 0.2V 0.2V 0.2V 0.2V
MIN.
TYP.
MAX.
UNITS
ICCDR tCDR
Data Retention Current Chip Deselect Data Retention Time Operation Recovery Time
-(2)
Retention Waveform
1.5V, 25OC Read Cycle Time
DATA RETENTION WAVEFORM
Controlled
Data Retention Mode
1.5V
0.2V
R0201-BS62UV4000
Revision April 2002
TEST CONDITIONS
Input Pulse Levels Input Rise Fall Times Input Output Timing Reference Level Vcc/0 1V/ns 0.5Vcc
WAVEFORM INPUTS
BS62UV4000
SWITCHING WAVEFORMS
OUTPUTS MUST STEADY WILL CHANGE FROM WILL CHANGE FROM CHANGE STATE UNKNOWN CENTER LINE HIGH IMPEDANCE "OFF "STATE
MUST STEADY CHANGE FROM
1333
TEST LOADS WAVEFORMS
OUTPUT
100PF
INCLUDING SCOPE
1333
OUTPUT
CHANGE FROM CARE: CHANGE PERMITTED DOES APPLY
2000
INCLUDING SCOPE
2000
FIGURE
THEVENIN EQUIVALENT
FIGURE
OUTPUT
1.2V
INPUT PULSES
1V/ns
FIGURE
ELECTRICAL CHARACTERISTICS
READ CYCLE
JEDEC PARAMETER NAME PARAMETER NAME DESCRIPTION
Read Cycle Time Address Access Time Chip Select Access Time Output Enable Output Valid Chip Select Output Output Enable Output Chip Deselect Output High Output Disable Output High Output Disable Output Address Change BS62UV4000-12 MIN. TYP. MAX. BS62UV4000-15 MIN. TYP. MAX.
UNIT
AVAX AVQV ELQV GLQV ELQX GLQX EHQZ GHQZ AXOX
-120
-150
R0201-BS62UV4000
Revision April 2002
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1
(1,2,4)
BS62UV4000
ADDRESS
READ CYCLE2
(1,3,4)
READ CYCLE3
(1,4)
ADDRESS
(1,5)
NOTES: high read Cycle. Device continuously selected when VIL. Address valid prior coincident with transition low. Transition measured 500mV from steady state with shown Figure parameter guaranteed 100% tested.
R0201-BS62UV4000
Revision April 2002
ELECTRICAL CHARACTERISTICS
WRITE CYCLE
JEDEC PARAMETER NAME PARAMETER NAME DESCRIPTION
Write Cycle Time Chip Select Write Address Time Address Valid Write Write Pulse Width Write Recovery Time Write Output High Data Write Time Overlap Data Hold from Write Time Output Disable Output High Write Output Active BS62UV4000-12 MIN. TYP. MAX.
BS62UV4000
BS62UV4000-15 MIN. TYP. MAX.
UNIT
AVAX E1LWH AVWL AVWH WLWH WHAX WLOZ DVWH WHDX GHOZ WHQX
SWITCHING WAVEFORMS (WRITE CYCLE)
WRITE CYCLE1
ADDRESS
(11)
(4,10)
R0201-BS62UV4000
Revision April 2002
WRITE CYCLE2 (1,6)
BS62UV4000
ADDRESS
(11)
(4,10)
(8,9)
NOTES: must high during address transitions. internal write time memory defined overlap low. signals must active initiate write signal terminate write going inactive. data input setup hold timing should referenced second transition edge signal that terminates write. measured from earlier going high write cycle. During this period, pins output state that input signals opposite phase outputs must applied. transition occurs simultaneously with transitions after transition, output remain high impedance state. continuously DOUT same phase write data this write cycle. DOUT read data next address. during this period, pins output state. Then data input signals opposite phase outputs must applied them. Transition measured 500mV from steady state with shown Figure parameter guaranteed 100% tested. measured from later going write.
R0201-BS62UV4000
Revision April 2002
ORDERING INFORMATION
BS62UV4000
BS62UV4000
SPEED 120ns 150ns GRADE +0oC +70oC -40oC +85oC PACKAGE TSOP Small TSOP TSOP PDIP
PACKAGE DIMENSIONS
WITH PLATING
BASE METAL
SECTION
R0201-BS62UV4000
Revision April 2002
BS62UV4000
TSOP2
TSOP
R0201-BS62UV4000
Revision April 2002
PACKAGE DIMENSIONS (continued)
BS62UV4000
STSOP
PDIP
R0201-BS62UV4000
Revision April 2002
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