BS62LV1024 Easy expansion with CE2, CE1, options BS62LV1024 high

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BS62LV1024 Easy expansion with CE2, CE1, options BS62LV1024 high

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Very Power/Voltage CMOS SRAM 128K
BS62LV1024
Easy expansion with CE2, CE1, options BS62LV1024 high performance, very power CMOS Static Random Access Memory organized 131,072 words bits operates from wide range 2.4V 5.5V supply voltage. Advanced CMOS technology circuit techniques provide both high speed power features with typical CMOS standby current 0.02uA maximum access time 70ns operation. Easy memory expansion provided active chip enable (CE1), active HIGH chip enable (CE2), active output enable (OE) three-state output drivers. BS62LV1024 automatic power down feature, reducing power consumption significantly when chip deselected. BS62LV1024 available JEDEC standard 450mil Plastic SOP, 300mil Plastic 600mil Plastic DIP, 8mmx13.4mm STSOP, 8mmx13.4mm Reverse STSOP 8mmx20mm TSOP.
SPEED cc=3V
Wide operation voltage 2.4V 5.5V Very power consumption 3.0V C-grade 20mA (Max.) operating current grade 25mA (Max.) operating current 0.02uA (Typ.) CMOS standby current 5.0V C-grade 35mA (Max.) operating current grade 40mA (Max.) operating current 0.4uA (Typ.) CMOS standby current High speed access time 70ns (Max.) 3.0V Automatic power down when chip deselected Three state outputs compatible Fully static operation Data retention supply voltage 1.5V
PRODUCT FAMILY
PRODUCT RANGE
cc=5V cc=3V
TYPE
cc=5V
cc=3V
CONFIGURATIONS
BLOCK DIAGRAM
Brilliance Semiconductor Inc. reserves right modify document contents without notice.
R0201-BS62LV1024
BS62LV1024SC BS62LV1024SI BS62LV1024PC BS62LV1024PI BS62LV1024JC BS62LV1024JI
BS62LV1024TC BS62LV1024STC BS62LV1024TI BS62LV1024STI
Address Input Buffer
Decoder
1024
Memory Array 1024 1024
1024 Data Input Buffer Column Write Driver Sense Column Decoder Control Address Input Buffer
BS62LV1024RC BS62LV1024RI
Data Output Buffer
Revision Feb. 2003
DESCRIPTIONS
BS62LV1024
Function
These address inputs select 131,072 8-bit words active active HIGH. Both chip enables must active when data read from write device. either chip enable active, device deselected standby power mode. pins will high impedance state when device deselected. write enable input active controls read write operations. With chip selected, when HIGH LOW, output data will present pins; when LOW, data present pins will written into selected memory location. output enable input active LOW. output enable active while chip selected write enable inactive, data will present pins they will enabled. pins will high impedance state when inactive. These bi-directional ports used read data from write data into RAM. Power Supply Ground
Name
A0-A16 Address Input Chip Enable Input Chip Enable Input
Write Enable Input
Output Enable Input
DQ0-DQ7 Data Input/Output Ports
TRUTH TABLE
MODE OPERATION CURRENT
selected (Power Down) Output Disabled Read Write
High High
CCSB, CCSB1
ABSOLUTE MAXIMUM RATINGS(1)
SYMBOL TERM BIAS PARAMETER
Terminal Voltage with Respect Temperature Under Bias Storage Temperature Power Dissipation Output Current
OPERATING RANGE
UNITS
RATING
-0.5 Vcc+0.5 +150
RANGE
Commercial Industrial
AMBIENT TEMPERATURE
2.4V 5.5V 2.4V 5.5V
CAPACITANCE 25oC, MHz)
SYMBOL
Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability.
PARAMETER Input Capacitance Input/Output Capacitance
CONDITIONS
MAX.
UNIT
VIN=0V VI/O=0V
This parameter guaranteed 100% tested.
R0201-BS62LV1024
Revision Feb. 2003
ELECTRICAL CHARACTERISTICS 70oC
PARAMETER NAME
ICCSB ICCSB1
BS62LV1024
TEST CONDITIONS
Vcc=3.0V Vcc=5.0V Vcc=3.0V Vcc=5.0V
PARAMETER
Guaranteed Input Voltage Guaranteed Input High Voltage(2) Input Leakage Current Output Leakage Current Output Voltage Output High Voltage Operating Power Supply Current Standby Current-TTL Standby Current-CMOS
MIN. TYP. MAX.
-0.5 -Vcc=3.0V Vcc=5.0V Vcc=3.0V Vcc=5.0V Vcc=3.0V Vcc=5.0V Vcc=3.0V Vcc=5.0V Vcc=3.0V Vcc=5.0V
UNITS
-0.02
Vcc+0.2
Max, Max, CE1= VIH, CE2= VIL, VIH, VI/O Max, Min, -1mA VIL, VIH, 0mA, Fmax(3) VIH, VIL, CE1Vcc-0.2V, CE20.2V, VINVcc-0.2V VIN0.2V
-2.4
Typical characteristics 25oC. These absolute values with respect device ground overshoots system tester notice included. Fmax 1/tRC
DATA RETENTION CHARACTERISTICS 70oC
SYMBOL
ICCDR tCDR
PARAMETER
Data Retention Data Retention Current Chip Deselect Data Retention Time Operation Recovery Time
TEST CONDITIONS
0.2V, 0.2V, 0.2V 0.2V 0.2V, 0.2V, 0.2V 0.2V Retention Waveform
MIN.
TYP.
-0.02
MAX.
-0.3
UNITS
1.5V, 25OC Read Cycle Time
DATA RETENTION WAVEFORM Controlled
Data Retention Mode 1.5V
0.2V
DATA RETENTION WAVEFORM Controlled
Data Retention Mode
1.5V
0.2V
R0201-BS62LV1024
Revision Feb. 2003
TEST CONDITIONS
Input Pulse Levels Input Rise Fall Times Input Output Timing Reference Level Vcc/0V 1V/ns 0.5Vcc
WAVEFORM INPUTS
BS62LV1024
SWITCHING WAVEFORMS
OUTPUTS MUST STEADY WILL CHANGE FROM WILL CHANGE FROM CHANGE STATE UNKNOWN CENTER LINE HIGH IMPEDANCE "OFF "STATE
MUST STEADY CHANGE FROM CHANGE FROM CARE: CHANGE PERMITTED DOES APPLY
TEST LOADS WAVEFORMS
3.3V OUTPUT
100PF
INCLUDING SCOPE
1269
3.3V OUTPUT
1269
1404
INCLUDING SCOPE
1404
FIGURE
THEVENIN EQUIVALENT INPUT PULSES
FIGURE
OUTPUT
1.73V
FIGURE
ELECTRICAL CHARACTERISTICS 70oC, Vcc=3.0V
READ CYCLE
JEDEC PARAMETER NAME PARAMETER NAME Read Cycle Time Address Access Time Chip Select Access Time Chip Select Access Time Output Enable Output Valid Chip Select Output Chip Select Output Output Enable Output Chip Deselect Output High Chip Deselect Output High Output Disable Output High Output Disable Address Change (CE1) (CE2) (CE1) (CE2) (CE1) (CE2) BS62LV1024-70 MIN. TYP. MAX.
UNIT
tAVAX tAVQV E1LQV E2HOV tGLQV E1LQX E2HOX tGLQX E1HQZ tE2HQZ tGHQZ tAXOX
ACS1 ACS2 CLZ1 CLZ2 CHZ1 CHZ2
R0201-BS62LV1024
Revision Feb. 2003
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1
(1,2,4)
BS62LV1024
ADDRESS
READ CYCLE2
(1,3,4)
ACS1
ACS2
CHZ1,
CHZ2
(1,4)
READ CYCLE3
ADDRESS
CLZ1
ACS1
(1,5) CHZ1
CLZ2
ACS2
(2,5)
CHZ2
NOTES: high read Cycle. Device continuously selected when CE2= VIH. Address valid prior coincident with transition and/or transition high. Transition measured 500mV from steady state with shown Figure parameter guaranteed 100% tested.
R0201-BS62LV1024
Revision Feb. 2003
ELECTRICAL CHARACTERISTICS 70oC, Vcc=3.0V
WRITE CYCLE
JEDEC PARAMETER NAME PARAMETER NAME Write Cycle Time Chip Select Write Address Time Address Valid Write Write Pulse Width Write Recovery Time Write Recovery Time Write Output High Data Write Time Overlap Data Hold from Write Time Output Disable Output High Write Output Active (CE1 (CE2)
BS62LV1024
BS62LV1024-70 MIN. TYP. MAX.
UNIT
tAVAX tE1LWH tAVWL tAVWH tWLWH tWHAX tE2LAX tWLOZ tDVWH tWHDX tGHOZ tWHQX
tWR1 tWR2 tWHZ tOHZ
SWITCHING WAVEFORMS (WRITE CYCLE)
WRITE CYCLE1
ADDRESS
(11)
(11)
(4,10)
Revision Feb. 2003
R0201-BS62LV1024
WRITE CYCLE2 (1,6)
BS62LV1024
ADDRESS
(11)
(11)
(4,10)
(8,9)
NOTES: must high during address transitions. internal write time memory defined overlap active low. signals must active initiate write signal terminate write going inactive. data input setup hold timing should referenced second transition edge signal that terminates write. measured from earlier going high going write cycle. During this period, pins output state that input signals opposite phase outputs must applied. transition high transition occurs simultaneously with transitions after transition, output remain high impedance state. continuously DOUT same phase write data this write cycle. DOUT read data next address. high during this period, pins output state. Then data input signals opposite phase outputs must applied them. Transition measured 500mV from steady state with shown Figure parameter guaranteed 100% tested. measured from later going going high write.
R0201-BS62LV1024
Revision Feb. 2003
ORDERING INFORMATION
BS62LV1024
BS62LV1024
SPEED 70ns GRADE +0oC +70oC -40oC +85oC PACKAGE PDIP TSOP (8x20mm) Small TSOP (8x13.4mm) Reverse Small TSOP (8x13.4mm)
PACKAGE DIMENSIONS
WITH PLATING
BASE METAL
SECTION
R0201-BS62LV1024
Revision Feb. 2003
PACKAGE DIMENSIONS (continued)
BS62LV1024
STSOP (Normal Type)
STSOP 32(Reversed Type)
R0201-BS62LV1024-SP
Revision Feb. 2003
PACKAGE DIMENSIONS (continued)
BS62LV1024
PDIP
R0201-BS62LV1024-SP
Revision Feb. 2003
PACKAGE DIMENSIONS (continued)
BS62LV1024
TSOP
R0201-BS62LV1024
Revision Feb. 2003

BS62LV1024 Easy expansion with CE2, CE1, options BS62LV1024 high

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