µPD78P058Y 8-BIT SINGLE-CHIP MICROCONTROLLER DESCRIPTION

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µPD78P058Y 8-BIT SINGLE-CHIP MICROCONTROLLER DESCRIPTION

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INTEGRATED CIRCUIT
µPD78P058Y
8-BIT SINGLE-CHIP MICROCONTROLLER
DESCRIPTION
µPD78P058Y member µPD78054Y subseries 78K/0 series products, which on-chip mask µPD78058Y replaced with one-time programmable one-time PROM EPROM. Because this device programmed users, ideally suited applications involving evaluation systems development stages, small-scale production many different products, rapid development timeto-market product. Caution reliability µPD78P058YKK-T guaranteed when used mass-production applications. Please this device only experimentally evaluation during trial manufacture. Details given following User's Manuals. sure read them before starting design.
µPD78054, 78054Y Subseries User's Manual U11747E
Series User's Manual-Instruction U12326E
FEATURES
compatible with mask versions (except pin) Internal PROM: KbytesNote µPD78P058YKK-T: Reprogrammable (ideal system evaluation) µPD78P058YGC: Programmable once only (ideal small-lot production) Internal high-speed 1024 bytesNote Internal expansion 1024 bytesNote Buffer bytes Operable same supply voltage range mask versions (VDD QTOPmicrocontrollers compatible Notes Internal PROM internal high-speed capacities changed memory size switching register (IMS). Internal expansion capacity changed internal expansion size switching register (IXS). Remarks QTOP Microcontroller general name microcontrollers with on-chip one-time PROM that totally supported write service (from write marking, screening testing.) differences between PROM version mask version, refer DIFFERENCES BETWEEN µPD78P058Y MASK VERSIONS. this document, "PROM" used parts common one-time PROM EPROM versions.
information this document subject change without notice. Document U10907EJ2V0DS00 (2nd edition) Date Published December 1997 Printed Japan
mark
shows major revised points.
1996
µPD78P058Y
ORDERING INFORMATION
Part Number Package 80-pin plastic 80-pin ceramic WQFN Internal One-time PROM EPROM Quality Grade Standard applicable
µPD78P058YGC-8BT µPD78P058YKK-T
Please refer "Quality Grades Semiconductor Devices" (Document C11531E) published Corporation know specification quality grade devices recommended applications.
µPD78P058Y
78K/0 SERIES DEVELOPMENT
following shows products organized according usage. names parallelograms subseries names.
Products mass production Products under development subseries products compatible with bus. Control 100-pin 100-pin 100-pin 100-pin 80-pin 80-pin 80-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin 42/44-pin
PD78075B PD78078 PD78070A PD780058 PD78058F µPD78054 µPD780034 PD780024 PD78014H µPD78018F µPD78014 PD780001 µPD78002 PD78083
Inverter control
EMI-noise reduced version µPD78078
µPD78078Y PD78070AY PD780018AY PD780058YNote PD78058FY PD78054Y µPD780034Y PD780024Y µPD78018FY PD78014Y PD78002Y
timer added PD78054 external interface enhanced ROM-less version µPD78078 Serial PD78078Y enhanced function limited. Serial PD78054 enhanced EMI-noise reduced. EMI-noise reduced version PD78054 UART converter were enhanced PD78014 enhanced converter PD780024 enhanced Serial PD78018F added EMI-noise reduced. EMI-noise reduced version µPD78018F Low-voltage (1.8 operation version µPD78014, with larger selection capacities converter 16-bit timer were added µPD78002 converter added µPD78002 Basic subseries control On-chip UART, capable operating voltage (1.8
64-pin 64-pin 64-pin
µPD780988 µPD780964 µPD780924
FIPdrive
Inverter control, timer, µPD780964 were enhanced. ROM, capacity increased. converter PD780924 enhanced On-chip inverter control circuit UART. EMI-noise reduced.
100-pin 100-pin 78K/0 Series 80-pin 80-pin
PD780208 PD780228 PD78044H µPD78044F
drive
PD78044F were enhanced, Display output total: PD78044H were enhanced, Display output total: N-ch open drain added µPD78044F, Display output total: Basic subseries driving FIP, Display output total:
100-pin 100-pin 100-pin
PD780308 µPD78064B µPD78064
µPD780308Y PD78064Y
µPD78064 enhanced, ROM, capacity increased EMI-noise reduced version PD78064 Basic subseries driving LCDs, on-chip UART
IEBussupported 80-pin 80-pin
PD78098B PD78098
Meter control
EMI-noise reduced version µPD78098 IEBus controller added µPD78054
80-pin
PD780973
On-chip automobile meter driving controller/driver
Note
Under planning
µPD78P058Y
following lists main functional differences between subseries products.
Function Subseries Name Control Capacity K-60 K-60 Serial Interface 3-wire/2-wire/I2C 3-wire with automatic transmit/receive function 3-wire/UART 3-wire with automatic transmit/receive function Time division 3-wire (multi-master compatible) 3-wire/2-wire/I2C 3-wire with automatic transmit/receive function 3-wire/time division UART 3-wire/2-wire/I2C 3-wire with automatic transmit/receive function 3-wire/UART UART 3-wire (multi-master compatible) MIN. Value
µPD78078Y µPD78070AY µPD780018AY
µPD780058Y
K-60
µPD78058FY µPD78054Y µPD780034Y µPD780024Y µPD78018FY µPD78014Y µPD78002Y
drive
K-60 K-60 K-32
K-60
3-wire/2-wire/I2C 3-wire with automatic transmit/receive function 3-wire/2-wire/SBI/I2C 3-wire with automatic transmit/receive function 3-wire/2-wire/SBI/I2C 3-wire/2-wire/I2C 3-wire/time division UART 3-wire
K-32
K-16 K-60
µPD780308Y
µPD78064Y
K-32
3-wire/2-wire/I2C 3-wire/UART
Remark functions other than serial interface common subseries without suffix.
µPD78P058Y
FUNCTION DESCRIPTION
Item Internal memory PROM High-speed RAM: Expansion Buffer Kbytes bits registers bits registers banks) Minimum instruction execution time variable. When main system clock selected When subsystem clock selected Instruction µs/0.8 µs/1.6 µs/3.2 µs/6.4 µs/12.8 MHz) 32.768 kHz) 16-bit operation Multiply/divide (8-bit 8-bit, 16-bit 8-bit) manipulation (set, reset, test, Boolean operation) adjust, etc. Function KbytesNote
1024 bytesNote 1024 bytesNote bytes
Memory space General-purpose register Minimum instruction execution time
Total CMOS input CMOS input/output N-ch open-drain input/output converter converter Serial interface 8-bit resolution 8-bit resolution
3-wire serial I/O/2-wire serial I/O/I2C mode selectable 3-wire serial mode (with on-chip max. 32-byte automatic transmit/receive function) 3-wire serial I/O/UART mode selectable 16-bit timer/event counter 8-bit timer/event counter Watch timer Watchdog timer
Timer
Timer output Clock output
pins (14-bit output: pin) 19.5 kHz, 39.1 kHz, 78.1 kHz, kHz, kHz, kHz, 1.25 MHz, MHz, with main system clock) 32.768 32.768 with subsystem clock) kHz, kHz, with main system clock) Maskable Non-maskable Software Internal: external: Internal: Internal: external: 80-pin plastic 80-pin ceramic WQFN
Buzzer output
Vectored interrupt sources Test inputs Supply voltage
Operating ambient temperature Packages
Notes Internal PROM/internal high-speed capacity changed memory size switching register (IMS). Internal expansion capacity changed internal expansion size switching register (IXS).
µPD78P058Y
CONFIGURATIONS (TOP VIEW) Normal Operating Mode 80-pin plastic
µPD78P058YGC-8BT
80-pin ceramic WQFN
P01/INTP1/TI01
µPD78P058YKK-T
P06/INTP6 P05/INTP5 P04/INTP4 P03/INTP3 P02/INTP2 P14/ANI4 P13/ANI3 P12/ANI2 P11/ANI1 P10/ANI0
P15/ANI5 P16/ANI6 P17/ANI7 AVSS P130/ANO0 P131/ANO1 AVREF1 P70/SI2/RXD P71/SO2/TXD P72/SCK2/ASCK P20/SI1 P21/SO1 P22/SCK1 P23/STB P24/BUSY P25/SI0/SB0/SDA0 P26/SO0/SB1/SDA1 P27/SCK0/SCL P40/AD0 P41/AD1
P00/INTP0/TI00
XT1/P07
AVREF
AVDD
RESET P127/RTP7 P126/RTP6 P125/RTP5 P124/RTP4 P123/RTP3 P122/RTP2 P121/RTP1 P120/RTP0 P36/BUZ P35/PCL P34/TI2 P33/TI1 P32/TO2 P31/TO1 P30/TO0 P67/ASTB P66/WAIT P65/WR
P56/A14
P57/A15
P42/AD2
P43/AD3
P44/AD4
P45/AD5
P46/AD6
P47/AD7
P50/A8
P51/A9
P52/A10
P53/A11
P54/A12
P55/A13
Cautions Connect directly. Connect AVDD VDD. Connect AVSS VSS.
P64/RD
µPD78P058Y
A8-A15 AD0-AD7 ANI0-ANI7 ANO0-ANO7 ASCK ASTB AVDD AVSS BUSY INTP0-INTP6 P00-P07 P10-P17 P20-P27 P30-P37 P40-P47 P50-P57 P60-P67 P70-P72 P120-P127 P130, P131 Address Address/Data Analog Input Analog Output Asynchronous Serial Clock Address Strobe Analog Power Supply Analog Ground Busy Buzzer Clock Interrupt from Peripherals Port0 Port1 Port2 Port3 Port4 Port5 Port6 Port7 Port12 Port13 Programmable Clock RESET RTP0-RTP7 SB0, SCK0, SCK1 SDA0, SDA1 SI0, SO0, TI1, TI00, TI01 TO0-TO2 WAIT XT1, Reset Read Strobe Real-Time Output Port Receive Data Serial Serial Clock Serial Clock Serial Data Serial Input Serial Output Strobe Timer Input Timer Input Timer Output Transmit Data Power Supply Programming Power Supply Ground Wait Write Strobe Crystal (Main System Clock) Crystal (Subsystem Clock)
AVREF0, AVREF1 Analog Reference Voltage
µPD78P058Y
PROM Programming Mode 80-pin plastic
µPD78P058YGC-8BT
80-pin ceramic WQFN
µPD78P058YKK-T
Open Open
RESET
Cautions A0-A16 D0-D7
Open
Individually connect pull-down resistor. Connect GND. connection RESET Reset Power Supply Programming Power Supply Ground
RESET level.
Address Chip Enable Data Output Enable Program
µPD78P058Y
BLOCK DIAGRAM
TO0/P30 TI00/INTP0/P00 TI01/INTP1/P01 TO1/P31 TI1/P33 TO2/P32 TI2/P34
16-bit TIMER/ EVENT COUNTER
PORT0
8-bit TIMER/ EVENT COUNTER
PORT1
8-bit TIMER/ EVENT COUNTER
PORT2
WATCHDOG TIMER
PORT3
WATCH TIMER
PORT4
SI0/SB0/SDA0/P25 SO0/SB1/SDA1/P26 SCK0/SCLP27 SI1/P20 SO1/P21 SCK1/P22 STB/P23 BUSY/P24 SI2/RxD/P70 SO2/TxD/P71 SCK2/ASCK/P72 ANI0/P10 ANI7/P17 AVDD AVSS AVREF0 ANO0/P130 ANO1/P131 AVSS AVREF1 SERIAL INTERFACE SERIAL INTERFACE
78K/0 CORE
PROM Bytes
PORT5
PORT6
PORT7 2048 Bytes PORT12
P120 P127
SERIAL INTERFACE PORT13 P130, P131
CONVERTER
REAL-TIME OUTPUT PORT
RTP0/P120 RTP7/P127 AD0/P40 AD7/P47 A8/P50 A15/P57 RD/P64 WR/P65 WAIT/P66 ASTB/P67 RESET XT1/P07
CONVERTER EXTERNAL ACCESS INTERRUPT CONTROL
INTP0/P00 INTP6/P06
BUZ/P36
BUZZER OUTPUT SYSTEM CONTROL
PCL/P35
CLOCK OUTPUT CONTROL
µPD78P058Y
CONTENTS
DIFFERENCES BETWEEN µPD78P058Y MASK VERSIONS FUNCTIONS
PINS NORMAL OPERATING MODE PINS PROM PROGRAMMING MODE INPUT/OUTPUT CIRCUITS RECOMMENDED CONNECTION UNUSED PINS
MEMORY SIZE SWITCHING REGISTER (IMS) INTERNAL EXPANSION SIZE SWITCHING REGISTER (IXS) PROM PROGRAMMING
OPERATING MODES PROM WRITE PROCEDURE PROM READ PROCEDURE
ERASURE (µPD78P058YKK-T ONLY) ERASURE WINDOW OPAQUE FILM (µPD78P058YKK-T ONLY) SCREENING ONE-TIME PROM VERSIONS ELECTRICAL SPECIFICATIONS CHARACTERISTIC CURVES PACKAGE DRAWINGS RECOMMENDED SOLDERING CONDITIONS APPENDIX DEVELOPMENT TOOLS APPENDIX RELATED DOCUMENTS
µPD78P058Y
DIFFERENCES BETWEEN µPD78P058Y MASK VERSIONS
µPD78P058Y single-chip microcontroller with on-chip one-time writable PROM with on-chip EPROM which program write, erasure, rewrite capability. possible make functions except PROM specification, mask option pins, same those mask versions setting memory size switching register (IMS) internal expansion size switching register (IXS). Differences between PROM version (µPD78P058Y) mask versions (µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y) shown Table 1-1. Table 1-1. Differences between µPD78P058Y Mask Versions
Item Internal structure Internal capacity
µPD78P058Y
One-time PROM/EPROM Kbytes
Mask Versions Mask
µPD78052Y µPD78053Y µPD78054Y µPD78055Y µPD78056Y µPD78058Y
Kbytes Kbytes Kbytes Kbytes Kbytes Kbytes
Internal high-speed capacity
1024 bytes
µPD78052Y bytes Other than µPD78052Y 1024 bytes µPD78058Y 1024 bytes Other than µPD78058Y None
Internal expansion capacity
1024 bytes YesNote
Changing internal internal expansion capacities memory size switching register (IMS) Changing internal expansion capacity internal expansion size switching register (IXS) P60-P63 mask option with pull-up resistor Electrical specifications, recommended soldering conditions
YesNote
None Provided None
Provided None Provided
Refer data sheet separately available
Notes internal PROM capacity becomes Kbytes, internal high-speed capacity becomes 1024 bytes RESET input. internal expansion capacity becomes 1024 bytes RESET input. Caution PROM mask versions differ from each other terms noise immunity noise radiation. When replacing PROM version with mask version course experimental production mass production, perform thorough evaluation with version (not version) mask version. Remark internal expansion size switching register (IXS) provided µPD78058Y µPD78P058Y only.
µPD78P058Y
FUNCTIONS
PINS NORMAL OPERATING MODE
Port Pins (1/2)
Name P07Note1 Input Input/output Port 8-bit input/output port. Input/output specifiable bit-wise. When used input port, possible on-chip pull-up resistor software.Note Input/output Port 8-bit input/output port. Input/output specifiable bit-wise. When used input port, possible on-chip pull-up resistor software. Input Input/output Port 8-bit input/output port. Input/output specifiable bit-wise. When used input port, possible on-chip pull-up resistor software. Input SCK1 BUSY SI0/SB0/SDA0 SO0/SB1/SDA1 SCK0/SCL Input only. Input Input Input/Output Input Input/output Port 8-bit input/output port. Function Input only. Input/output specifiable bit-wise. When used input port, possible on-chip pull-up resistor software. After Reset Alternate Function Input Input INTP0/TI00 INTP1/TI01 INTP2 INTP3 INTP4 INTP5 INTP6 ANI0 ANI7
Notes When using P07/XT1 pins input ports, processor clock control register (PCC) (FRC) feedback resistor subsystem clock). When using P10/ANI0 P17/ANI7 pins analog inputs converter, port input mode. Their pull-up resistor automatically disabled.
µPD78P058Y
Port Pins (2/2)
Name Input/Output Input/output Port 8-bit input/output port. Input/output specifiable 8-bit unit. When used input port, possible on-chip pull-up resistor software. test input flag (KRIF) falling edge detection. Input/output Port 8-bit input/output port. possible directly drive LEDs. Input/output specifiable bit-wise. When used input port, possible on-chip pull-up resistor software. Input/output Port 3-bit input/output port. Input/output specifiable bit-wise. When used input port, possible on-chip pull-up resistor software. P120 P127 Input/output Port 8-bit input/output port. Input/output specifiable bit-wise. When used input port, possible on-chip pull-up resistor software. P130, P131 Input/output Port 2-bit input/output port. Input/output specifiable bit-wise. When used input port, possible on-chip pull-up resistor software. Input ANO0, ANO1 Input RTP0 RTP7 SCK2/ASCK SO2/TXD Input Input/output Port 8-bit input/output port. Input/output specifiable bit-wise. When used input port, possible on-chip pull-up resistor software. Input WAIT ASTB SI2/RXD N-ch open-drain input/output port. possible directly drive LEDs. Input Input Function After Reset Alternate Function Input
µPD78P058Y
Non-Port Pins (1/2)
Name INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTP6 SDA0 SDA1 SCK0 SCK1 SCK2 BUSY ASCK TI00 TI01 Output Output Input Input Output Input Input Automatic transmit/receive strobe output serial interface Automatic transmit/receive busy input serial interface Serial data input asynchronous serial interface Serial data output asynchronous serial interface Serial clock input asynchronous serial interface External count clock input 16-bit timer (TM0) Capture trigger signal input capture register (CR00) External count clock input 8-bit timer (TM1) External count clock input 8-bit timer (TM2) 16-bit timer (TM0) output (Can also used 14-bit output.) RTP0 RTP7 Output Output Output 8-bit timer (TM1) output 8-bit timer (TM2) output Clock output (for trimming main system clock subsystem clock) Buzzer output Real-time output port which outputs data synchronization with trigger. Low-order address/data when expanding memory outside. Input Input Input P120 P127 Input Input Input Input Input Input Input Input/output Serial clock input/output serial interface Input Input/output Serial data input/output serial interface Input Output Serial data output serial interface Input Input Serial data input serial interface Input Input/Output Input Function External interrupt request inputs, which effective edges (rising edge, falling edge, both rising falling edges) specified. After Reset Alternate Function Input P00/TI00 P01/TI01 P25/SB0/SDA0 P70/RXD P26/SB1/SDA1 P71/TXD P25/SI0/SDA0 P26/SO0/SDA1 P25/SI0/SB0 P26/SO0/SB1 P27/SCL P72/ASCK P27/SCK0 P70/SI2 P71/SO2 P72/SCK2 P00/INTP0 P01/INTP1
Input/output
Input
µPD78P058Y
Non-Port Pins (2/2)
Input/Output Output Output Function After Reset Alternate Function Input
Name WAIT ASTB
High-order address when expanding memory outside. Input Strobe signal output external memory read operation Strobe signal output external memory write operation Input
Input Output
Wait insertion when accessing external memory
Strobe output externally latches address information which Input output ports accessing external memory.
ANI0 ANI7
Input
Analog input converter Analog output converter Reference voltage input converter Reference voltage input converter Analog power supply converter. Connect VDD. Ground potential converter. Connect VSS. System reset input Main system clock oscillation crystal connection
Input Input
P130, P131
ANO0, ANO1 Output AVREF0 AVREF1 AVDD AVSS RESET Input Input Input Input Input
Subsystem clock oscillation crystal connection
Input
Positive power supply High-voltage applied during program write/verify. Connect directly normal operating mode.
Ground potential
PINS PROM PROGRAMMING MODE
Input/Output Input PROM programming mode setting When +12.5 applied low-level signal applied RESET pin, this chip PROM programming mode. Function
Name RESET
Input Input Input/output Input Input Input
PROM programming mode setting high-voltage applied during program write/verification Address Data PROM enable input/program pulse input Read strobe input PROM Program/program inhibit input PROM programing mode. Positive power supply Ground potential
µPD78P058Y
INPUT/OUTPUT CIRCUITS RECOMMENDED CONNECTION UNUSED PINS
Types input/output circuits pins recommeded connection unused pins shown Table 2-1. configuration each type input/output circuit, Figure 2-1. Table 2-1. Input/Output Circuits (1/2)
Name Input/Output Circuit Type Input/Output Recommended Connecting Method when Unused
P00/INTP0/TI00 P01/INTP1/TI01 P02/INTP2 P03/INTP3 P04/INTP4 P05/INTP5 P06/INTP6 P07/XT1 P10/ANI0 P17/ANI7 P20/SI1 P21/SO1 P22/SCK1 P23/STB P24/BUSY P25/SI0/SB0/SDA0 P26/SO0/SB1/SDA1 P27/SCK0/SCL P30/TO0 P31/TO1 P32/TO2 P33/TI1 P34/TI2 P35/PCL P36/BUZ P40/AD0 P47/AD7
Input Input/output
Connect VSS. Independently connect through resistor.
10-A
Input Input/output
Connect VDD. Independently connect through resistor.
Independently connect through resistor.
µPD78P058Y
Table 2-1. Input/Output Circuits (2/2)
Name Input/Output Circuit Type 13-D Input/Output Recommended Connecting Method when Unused
P50/A8 P57/A15 P64/RD P65/WR P66/WAIT P67/ASTB P70/SI2/RxD P71/SO2/TxD P72/SCK2/ASCK P120/RTP0 P127/RTP7 P130/ANO0, P131/ANO1 RESET AVREF0 AVREF1 AVDD AVSS
Input/output
Independently connect through resistor. Independently connect through resistor. Independently connect VSS.
12-A Input Leave open. Connect VSS. Connect VDD. Independently connect through resistor.
Connect VSS. Directly connect VSS.
µPD78P058Y
Figure 2-1. Input/Output Circuits (1/2)
Type
Type
pullup enable
P-ch
data
P-ch
output disable
N-ch
Schmitt-Triggered Input with Hysteresis Characteristic
Type
Type 10-A
pullup enable data P-ch
P-ch
pullup enable data
P-ch
P-ch N-ch
output disable
N-ch
open drain output disable
input enable
Type
Type
pullup enable data P-ch P-ch
pullup enable data P-ch
P-ch
output disable N-ch
output disable Comparator
N-ch P-ch
N-ch VREF (Threshold Voltage)
input enable
µPD78P058Y
Figure 2-1. Input/Output Circuits (2/2)
Type 12-A
Type
pullup enable data P-ch
P-ch
feedback cut-off P-ch
IN/OUT output disable input enable Analog Output Voltage N-ch
P-ch N-ch
Type 13-D
IN/OUT data output disable N-ch
P-ch
Medium Voltage Input Buffer
µPD78P058Y
MEMORY SIZE SWITCHING REGISTER (IMS)
This register disable part internal memories software. setting this memory size switching register (IMS), possible same memory mapping that mask version having different internal memory capacities (ROM, RAM). 8-bit memory manipulation instruction. will result RESET input. Figure 3-1. Memory Size Switching Register Format
Symbol Address FFF0H After Reset
RAM2 RAM1 RAM0
ROM3 ROM2 ROM1 ROM0
ROM3 ROM2 ROM1 ROM0
Selection Internal Capacity bytes bytes bytes bytes bytes bytesNote bytes Setting prohibited
Other than above
RAM2 RAM1 RAM0
Selection Internal High-Speed Capacity bytes 1024 bytes Setting prohibited
Other than above
Note
internal capacity less than bytes when external device expansion function used.
Table shows setting values which makes memory mapping same that various mask products. Table 3-1. Memory Size Switching Register Setting Values
Target Mask Version Setting Value
µPD78052Y µPD78053Y µPD78054Y µPD78055Y µPD78056Y µPD78058Y
µPD78P058Y
INTERNAL EXPANSION SIZE SWITCHING REGISTER (IXS)
This register internal expansion capacity software. setting this internal expansion size switching register (IXS), possible same memory mapping that mask version having different internal expansion capacity. 8-bit memory manipulation instruction. will result RESET input. Figure 4-1. Internal Expansion Size Switching Register Format
Symbol
Address FFF4H
After Reset
IXRAM3 IXRAM2 IXRAM1 IXRAM0
IXRAM3 IXRAM2 IXRAM1 IXRAM0
Selection Internal Expansion Capacity byte 1024 bytes Setting prohibited
Other than above
Table shows setting values which makes memory mapping same that various mask versions. Table 4-1. Internal Expansion Size Switching Register Setting Values
Target Mask Version
Setting Value
µPD78052Y µPD78053Y µPD78054Y µPD78055Y µPD78056Y µPD78058Y
Remark
Even PD78P058Y program that includes "MOV IXS, #0CH" implemented PD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, operation will affected.
µPD78P058Y
PROM PROGRAMMING
µPD78P058Y on-chip 60K-byte PROM program memory. programming, PROM programming mode RESET pins. connecting unused pins, refer CONFIGURATIONS (TOP VIEW) PROM Programming Mode. Caution Program writing should performed address range 0000H EFFFH (the last address, EFFFH, should specified). Writing cannot performed with PROM programmer that cannot specify write addresses. OPERATING MODES
When +12.5 applied level signal applied RESET pin, PROM programming mode set. This mode will become operating mode shown Table when pins shown. Further, when read mode set, possible read contents PROM. Table 5-1. Operating Modes PROM Programming
Operating Mode Page data latch Page write Byte write Program verify Program inhibit
RESET
+12.5
+6.5
Data input High-impedance Data input Data output High-impedance
Read Output disable Standby
Data output High-impedance High-impedance
Remark
µPD78P058Y
Read mode Read mode set. Output disable mode Data output becomes high-impedance, output disable mode, set. Therefore, allows data read from device controlling pin, multiple µPD78P058Ys connected data bus. Standby mode Standby mode set. this mode, data outputs become high-impedance irrespective status. Page data latch mode Page data latch mode beginning page write mode. this mode, page 4-byte data latched internal address/data latch circuit. Page write mode After page bytes addresses data latched page data latch mode, page write executed applying program pulse (active low) with Then, program verification performed, set. programming performed one-time program pulse, write verification operations should executed repeatedly. Byte write mode Byte write executed when program pulse (active low) applied with Then, program verification performed set. programming performed one-time program pulse, write verification operations should executed repeatedly. Program verify mode Program verify mode set. this mode, check write operation performed correctly, after write. Program inhibit mode Program inhibit mode used when pin, pin, pins multiple µPD78P058Ys connected parallel write performed those devices. When write operation performed, page write mode byte write mode described above used. this time, write performed device which driven high.
µPD78P058Y
PROM WRITE PROCEDURE Figure 5-1. Page Program Mode Flowchart
Start Address 12.5
Latch Address Address Latch Address Address Latch Address Address Address Address Latch
X=X+1 program pulse
Verify bytes Pass Address Pass
Fail
Verify bytes Pass writing
Fail
Defective product
Remark
Start address Program last address
µPD78P058Y
Figure 5-2. Page Program Mode Timing
Page Data Latch Page Program Program Verify
A2-A16
Hi-Z D0-D7 Data Input Data Output
µPD78P058Y
Figure 5-3. Byte Program Mode Flowchart
Start Address 12.5
X=X+1 program pulse Address Address Fail Verify Pass Address Pass Fail
Verify bytes Pass writing
Defective product
Remark
Start address Program last address
µPD78P058Y
Figure 5-4. Byte Program Mode Timing
Program
Program Verify
A0-A16
D0-D7
Data Input
Hi-Z
Data Output
Cautions
should applied before removed after VPP. must exceed +13.5 including overshoot. Reliability adversely affected removal/reinsertion performed while +12.5 being applied VPP.
µPD78P058Y
PROM READ PROCEDURE
contents PROM readable external data according read procedure shown below. RESET level, supply pin, connect other unused pins shown CONFIGURATION (TOP VIEW) PROM Programming Mode. Supply pins. Input address read data into pins. Read mode Output data pins. timings above steps shown Figure 5-5. Figure 5-5. PROM Read Timings
A0-A16
Address Input
(Input)
(Input)
D0-D7
Hi-Z
Data Output
Hi-Z
µPD78P058Y
ERASURE (µPD78P058YKK-T ONLY)
µPD78P058YKK-T capable erasing (all contents FFH) data written program memory rewriting. When erasing data, irradiate light having wavelength less than about window package. Normally, ultraviolet rays 254-nm wavelength should used. Volume irradiation required completely erase data follows: intensity erasing time more Erasing time More than min. (When lamp 12,000 µW/cm2 used. However, longer time needed because deterioration performance lamp, contamination erasing window, etc.) When erasing data, lamp within from erasing window. Further, filter provided lamp, remove filter during erasure process.
ERASURE WINDOW OPAQUE FILM (µPD78P058YKK-T ONLY)
protect from unintentional erasure other than EPROM erasure lamp light, protect internal circuits other than EPROM from malfunction light coming through window, mask window with attached opaque film except when EPROM erasure performed.
SCREENING ONE-TIME PROM VERSIONS
one-time PROM version (µPD78P058YGC-8BT) tested completely before shipped, because structure. recommended perform screening verify PROM after writing necessary data performing high-temperature storage under condition below.
Storage Temperature Storage Time hours
present, charged one-time PROM after-programming marking, screening, verify service QTOP Microcontroller. details, contact your sales representative.
µPD78P058Y
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Parameter Supply voltage Symbol AVDD AVREF0 AVREF1 AVSS Input voltage P00-P07, P10-P17, P20-P27, P30-P37, P40-47, P50-P57, P64-P67, P70-P72, P120-P127, P130, P131, XT2, RESET Output voltage Analog input voltage Output current, high P10-P17 Total P01-P06, P30-P37, P56, P57, P60-P67, P120-P127 Total P10-P17, P20-P27, P40-P47, P50-P55, P70-P72, P130, P131 Output current, IOLNote Peak value r.m.s. Total P50-P55 Peak value r.m.s. Total P56, P57, P60-P63 Peak value r.m.s. Total P10-P17, P20-P27, P40-P47, P70-P72, P130, P131 Total P01-P06, P30-P37, P64-P67, P120-P127 Operating ambient temperature Storage temperature Peak value r.m.s. Peak value r.m.s Analog input pins P60-P63 N-ch open drain PROM programming mode -0.3 -0.3 +13.5 -0.3 AVSS AVREF0 Test Conditions Rating -0.3 +7.0 -0.3 +13.5 -0.3 -0.3 -0.3 -0.3 +0.3 -0.3 Unit
Tstg
+150
Note Caution
r.m.s. should calculated follows: [r.m.s.] [peak value] Duty Product quality suffer absolute maximum rating exceeded even single parameter, even momentarily. other words, absolute maximum ratings rated values which product verge suffering physical damage, therefore product must used under conditions which ensure that absolute maximum ratings exceeded.
Remark
Unless otherwise specified, alternate function characteristics same port characteristics.
µPD78P058Y
MAIN SYSTEM CLOCK OSCILLATOR CHARACTERISTICS
Resonator Ceramic resonator Recommended Circuit
Parameter Oscillation frequency (fX)Note
Test Conditions Oscillation voltage range
MIN. TYP. MAX. Unit
Oscillation stabilization timeNote
After reached MIN. oscillation voltage range
Crystal resonator
Oscillation frequency (fX)Note
Oscillation stabilization timeNote
External clock
input frequency (fX)Note
input high-/low-level
PD74HCU04
width (tXH/tXL)
Notes
Only oscillation characteristics shown. characteristics instruction execution times. This time required oscillation stabilize after reset STOP mode release.
Cautions When main system clock oscillator used, following should noted concerning wiring area figure enclosed broken lines prevent influence wiring capacitance, etc. wiring should kept short possible. other signal lines should crossed. Keep away from lines carrying high fluctuating current. oscillator capacitor grounding point should always same potential VSS. connect ground pattern carrying high current. signal should taken from oscillator. When main system clock stopped device operating subsystem clock, wait until oscillation stabilization time been secured program before switching back main system clock.
µPD78P058Y
SUBSYSTEM CLOCK OSILLATOR CHARACTERISTICS
Resonator Ceramic resonator Recommended Circuit
Parameter Oscillation frequency (fX)Note
Test Conditions
MIN. TYP. MAX. Unit 32.768
Oscillation stabilization timeNote
External clock
input frequency (fXT)Note
PD74HCU04
input high-/low-level width (tXTH/tXTL)
Notes
Only oscillation characteristics shown. characteristics instruction execution times. This time required oscillation stabilize after reached MIN. oscillation voltage range.
Cautions When subsystem clock oscillator used, following should noted concerning wiring area figure enclosed broken lines prevent influence wiring capacitance, etc. wiring should kept short possible. other signal lines should crossed. Keep away from lines carrying high fluctuating current. oscillator capacitor grounding point should always same potential VSS. connect ground pattern carrying high current. signal should taken from oscillator. subsystem clock oscillator low-amplitude circuit order achieve consumption current, more prone misoperation noise than main system clock oscillator. Particular care therefore required with wiring method when subsystem clock used.
µPD78P058Y
RECOMMENDED OSCILLATOR CONSTANT MAIN SYSTEM CLOCK: CERAMIC RESONATOR +80°C)
Manufacturer Part Number Frequency (MHz) Recommended Circuit Constant (pF) Kyocera Corp. KBR-4.19MKS 4.19 Built-in (pF) Built-in Oscillator Voltage Range MIN. MAX.
MAIN SYSTEM CLOCK: CERAMIC RESONATOR +85°C)
Manufacturer Part Number Frequency (MHz) Recommended Circuit Constant (pF) Murata Mfg. Co., Ltd. CST5.00MGW CSA5.00MG Built-in (pF) Built-in Oscillator Voltage Range MIN. MAX.
Caution oscillation circuit constants oscillation voltage range indicate conditions stable oscillation guarantee accuracy oscillation frequency. application circuit requires accuracy oscillation frequency, necessary oscillation frequency resonator application circuit. this, necessary directly contact manufacturer resonator being used. CAPACITANCE
Parameter Input capacitance Input/output capacitance Symbol Test Conditions MHz, unmeasured pins returned MHz. Unmeasured pins returned P01-P06, P10-P17, P20-P27, P30-P37, P40- P47, P50-P57, P64-P67, P70-P72, P120-P127, P130, P131 P60-P63 MIN. TYP. MAX. Unit
Remark Unless specified otherwise, alternate function characteristics same port characteristics.
µPD78P058Y
Characteristics +85°C,
Parameter Input voltage, high Symbol VIH1 Test Conditions P10-P17, P21, P23, P30-P32, P35-P37, P40-P47, P50-P57, P64-P67, P71, P120-P127, P130, P131 P00-P06, P20, P22, P24-P27, P33, P34, P70, P72, RESET P60-P63 (N-ch open drain) MIN. TYP. MAX. Unit
VIH2
0.85
VIH3
VIH4
-0.5 -0.2
VIH5
XT1/P07,
VNote
Input voltage,
VIL1
P10-P17, P21, P23, P30-P32, P35-P37, P40-P47, P50-P57, P64-P67, P71, P120-P127, P130, P131 P00-P06, P20, P22, P24-P27, P33, P34, P70, P72, RESET P60-P63
VIL2
0.15
VIL3
VIL4
VIL5
XT1/P07,
VNote
VDD-1.0 VDD-0.5
Output voltage, high Output voltage,
VOH1
-100
VOL1
P50-P57, P60-P63
P01-P06, P10-P17, P20-P27, P30-P37, P40-P47, P64-P67, P70-P72, P120-P127, P130, P131 VOL2 SB0, SB1, SCK0
N-ch open drain, with pull-up resistor
VOL3
Note
When using XT1/P07 P07, inverse phase should input using inverter.
Remark Unless specified otherwise, alternate function characteristics same port characteristics.
µPD78P058Y
CHARACTERISTICS
Parameter Input leakage current, high Symbol ILIH1 Test Conditions P00-P06, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67, P70-P72, P120-P127, P130, P131, RESET XT1/P07, P60-63 P00-P06, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P64-P67, P70-P72, P120-P127, P130, P131, RESET XT1/P07, P60-P63 VOUT MIN. TYP. MAX. Unit
ILIH2 ILIH3 Input leakage current, ILIL1
ILIL2 ILIL3 Output leakage current, high Output leakage current, Software pull-up resistorNote ILOH1
-3Note
ILOL1
VOUT
P01-P06, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P64-P67, P70-P72, P120-P127, P130, P131
Notes
P63, low-level input leak current -200 (MAX.) flows only during clocks (no-wait time) after instruction been executed read port (P6) port mode register (PM6). Outside period clocks following executing read-out instruction, current (MAX.).
software pull-up resistor only used range
Remark Unless specified otherwise, alternate function characteristics same port characteristics.
µPD78P058Y
CHARACTERISTICS
Parameter Supply currentNote Symbol IDD1 Test Conditions crystal oscillation operating mode (fXX MHz)Note 5.0V±10%Note 3.0V±10%Note 2.2V±10%Note 5.0V±10%Note 3.0V±10%Note MIN. TYP. 0.65 0.05 0.05 MAX. 27.0 1.95 12.5 Unit
crystal oscillation operating mode (fXX IDD2 MHz)Note
crystal oscillation HALT mode (fXX MHz)Note
5.0V±10% 3.0V±10% 2.2V±10% 5.0V±10% 3.0V±10% 5.0V±10% 3.0V±10% 2.2V±10% 5.0V±10% 3.0V±10% 2.2V±10% 5.0V±10% 3.0V±10% 2.2V±10% 5.0V±10% 3.0V±10% 2.2V±10%
crystal oscillation HALT mode (fXX IDD3 32.768 crystal oscillation operating modeNote IDD4 32.768 crystal oscillation HALT modeNote IDD5 STOP mode Feedback resistor used IDD6 STOP mode Feedback resistor used MHz)Note
Notes
Current flowing AVDD pins. However, current flowing converter, converter, onchip pull-up resistors included. Main system clock: fX/2 operation (when oscillation mode selection register (OSMS) 00H). Main system clock: operation (when OSMS 01H). When main system clock stopped. High-speed mode operation (when processor clock control register (PCC) 00H). Low-speed mode operation (when 04H).
µPD78P058Y
CHARACTERISTICS Basic Operation
Parameter Cycle time (minimum instruction execution time) Symbol Test Conditions Operating main system clock (fXX MHz)Note MIN. 40Note
Note
TYP.
MAX.
Unit
Operating main system clock (fXX MHz)Note
Operating subsystem clock TI00 input high/low level width tTH00, tTIL00
2/fsam+0.1
Note
2/fsam+0.2
Note
2/fsam+0.5 TI01 input high/low level width TI1, input frequency TI1, TI2, input high-/low-level width Interrupt request input high-/lowlevel width tTH01, tTIL01 tTI1 tTIH1, tTIL1 tINTH tINTL INTP0 2/fsam+0.1 2/fsam+0.2
Note Note Note
2/fsam+0.5 INTP1-INTP6, KR0-KR7 RESET low-level width tRSL
Notes
Main system clock: fX/2 operation (when oscillation mode selection register (OSMS) 00H). Main system clock: operation (when OSMS 01H). value when external clock used. When using crystal resonator, (MIN.). fsam selected fXX/2N, fXX/32, fXX/64, fXX/128 bits (SCS0 SCS1) sampling clock selection register (SCS)
µPD78P058Y
(Main System Clock, fX/2) (Main System Clock,
Cycle Time
Guaranteed Operation Range
Cycle Time
Guaranteed Operation Range
Supply Voltage
Supply Voltage
µPD78P058Y
Read/Write Operations When PCC2 PCC0 000B
Parameter ASTB high-level width Address setup time Address hold time Data input time from address Symbol tASTH tADS tADH tADD1 tADD2 Data input time from tRDD1 tRDD2 Read data hold time low-level width tRDH tRDL1 tRDL2 WAIT input time from tRDWT1 tRDWT2 WAIT input time from WAIT low-level width Write data setup time Write data hold time low-level width delay time from ASTB delay time from ASTB ASTBdelay time from external fetch Address hold time from external fetch Write data output time from Write data output time from Address hold time from delay time from WAIT delay time from WAIT tWRWT tWTL tWDS tWDH tWRL1 tASTRD tASTWR tRDAST tRDADH tRDWD tWRWD tWRADH tWTRD tWTWR (1.15 2n)tCY (2.85 2n)tCY (2.85 2n)tCY 0.85tCY 0.85tCY 0.85tCY 0.85tCY 1.15tCY 1.15tCY 1.15tCY 3.15tCY 3.15tCY 1.15tCY 1.15tCY 2n)tCY (2.85 2n)tCY 0.85tCY 2tCY 2tCY 2n)tCY Test Conditions MIN. 0.85tCY 0.85tCY (2.85 2n)tCY 2n)tCY 2n)tCY (2.85 2n)tCY MAX. Unit
Remarks
MCS: oscillation mode selection register (OSMS) PCC2 PCC0: processor clock control register (PCC) TCY/4 indicates number waits.
µPD78P058Y
Except when PCC2 PCC0 000B (1/2)
Parameter ASTB high-level width Symbol tASTH Test Conditions 6.0V MIN. Address setup time tADS 6.0V Address hold time tADH 6.0V 0.4tCY 0.37tCY Data input time from address tADD1 6.0V 2n)tCY 2n)tCY tADD2 6.0V 2n)tCY 2n)tCY Data input time from tRDD1 6.0V (1.4 2n)tCY (1.37 2n)tCY tRDD2 6.0V (2.4 2n)tCY (2.37 2n)tCY Read data hold time low-level width tRDH tRDL1 6.0V (1.4 2n)tCY (1.37 2n)tCY tRDL2 6.0V (2.4 2n)tCY (2.37 2n)tCY WAIT input time from tRDWT1 6.0V tRDWT2 6.0V 2tCY 2tCY WAIT input time from tWRWT 6.0V 2tCY 2tCY WAIT low-level width Write data setup time tWTL tWDS 6.0V 2n)tCY (2.4 2n)tCY (2.37 2n)tCY Write data hold time low-level width tWDH tWRL1 6.0V (2.4 2n)tCY (2.37 2n)tCY 2n)tCY MAX. Unit
Remarks
MCS: oscillation mode selection register (OSMS) PCC2 PCC0: processor clock control register (PCC) TCY/4 indicates number waits.
µPD78P058Y
Except when PCC2 PCC0 000B (2/2)
Parameter delay time from ASTB Symbol tASTRD Test Conditions 6.0V MIN. 0.4tCY 0.37tCY delay time from ASTB tASTWR 6.0V 1.4tCY 1.37tCY ASTB delay time from external fetch Address hold time from external fetch Write data output time from tRDAST tRDADH tRDWD 6.0V 0.4tCY 0.37tCY Write data output time from tWRWD 6.0V Address hold time from tWRADH 6.0V delay time from WAIT tWTRD 6.0V 0.6tCY 0.63tCY delay time from WAIT tWTWR 6.0V 0.6tCY 0.63tCY 2.6tCY 2.63tCY 2.6tCY 2.63tCY MAX. Unit
Remarks
MCS: oscillation mode selection register (OSMS) PCC2 PCC0: processor clock control register (PCC) TCY/4 indicates number waits.
µPD78P058Y
Serial Interface Serial interface channel 3-wire serial mode (SCK0 internal clock output)
Parameter SCK0 cycle time Symbol tKCY1 Test Conditions MIN. 1600 3200 SCK0 high-/low-level width tKH1, tKL1 tSIK1 (tKCY1/2)-50 (tKCY1/2)-100 hold time (from SCK0) output delay time from SCK0 tKSI1 tKSO1 100pFNote TYP. MAX. Unit
setup time SCK0)
Note output line load capacitance. (ii) 3-wire serial mode (SCK0 external clock input)
Parameter SCK0 cycle time Symbol tKCY2 Test Conditions MIN. 1600 3200 SCK0 high-/low-level width tKH2, tKL2 1600 setup time SCK0) hold time (from SCK0) output delay time from SCK0 SCK0 rise, fall time tSIK2 tKSI2 tKSO2 tR2, pFNote When using external device expansion function When using external device expansion function TYP. MAX. Unit
1000
Note output line load capacitance.
µPD78P058Y
(iii) 2-wire serial mode (SCK0 internal clock output)
Parameter SCK0 cycle time Symbol tKCY3 Test Conditions pFNote MIN. 1600 3200 (tKCY3/2)-160 (tKCY3/2)-190 SCK0 low-level width tKL3 (tKCY3/2)-50 (tKCY3/2)-100 SB0, setup time SCK0) tSIK3 <4.5 SB0, hold time (from SCK0) SB0, output delay time from SCK0 tKSI3 tKSO3 TYP. MAX. Unit
SCK0 high-level width
tKH3
Note
SCK0, output line load resistance load capacitance. (iv) 2-wire serial mode (SCK0 external clock input)
Parameter Symbol tKCY4 Test Conditions MIN. 1600 3200 TYP. MAX. Unit
SCK0 cycle time
SCK0 high-level width
tKH4
1300
SCK0 low-level width
tKL4
1600
SB0, setup time SCK0) SB0, hold time (from SCK0) SB0, output delay time from SCK0 SCK0 rise, fall time
tSIK4 tKSI4 tKSO4 pFNote
tKCY4/2
tR4,
When using external device expansion function When using external device expansion function
1000
Note
output line load resistance load capacitance.
µPD78P058Y
mode (SCL internal clock output)
Parameter cycle time Symbol tKCY5 Test Conditions pFNote MIN. tKCY5-160 tKCY5-190 low-level width tKL5 tKCY5-50 tKCY5-100 SDA0, SDA1 setup time SCL) tSIK5 SDA0, SDA1 hold time (from SCL) SD0, output delay time from SDA0, SDA1 from SDA0, SDA1 from from SDA0, SDA1 SDA0, SDA1 high-level width tKSB tKSI5 tKSO5 TYP. MAX. Unit
high-level width
tKH5
tSBK tSBH
Note
SCL, SDA0 SDA1 output line load resistance load capacitance. (vi) mode (SCL external clock input)
Parameter Symbol tKCY6 tKH6, tKL6 Test Conditions MIN. 1000 TYP. MAX. Unit
cycle time high-/low-level width
SDA0, SDA1 setup time SCL) SDA0, SDA1 hold time (from SCL) SD0, output delay time from SDA0, SDA1 from SDA0, SDA1 from from SDA0, SDA1 SDA0, SDA1 high-level width rise, fall time
tSIK6 tKSI6 tKSO5 pFNote tKSB
tSBK tSBH tR6, When using external device expansion function When using external device expansion function
1000
Note
SDA0 SDA1 output line load resistance load capacitance.
µPD78P058Y
Serial interface channel 3-wire serial mode (SCK1.internal clock output)
Parameter SCK1 cycle time Symbol tKCY7 Test Conditions MIN. 1600 3200 SCK1 high-/low-level width tKH7, tKL7 tSIK7 (tKCY7/2)-50 (tKCY7/2)-100 hold time SCK1) output delay time from SCK1 tKSI7 tKSO7 pFNote TYP. MAX. Unit
setup time SCK1)
Note
output line load capacitance. (ii) 3-wire serial mode (SCK1.external clock output)
Parameter Symbol tKCY8 Test Conditions MIN. 1600 3200 TYP. MAX. Unit
SCK1 cycle time
SCK1 high-/low-level width
tKH8, tKL8
1600
setup time SCK1) hold time SCK1) output delay time from SCK1 SCK1 rise, fall time
tSIK8 tKSI8 tKSO8 tR8, pFNote When using external device expansion function When using external device expansion function
1000
Note
output line load capacitance.
µPD78P058Y
(iii) Automatic transmit/receive function 3-wire serial mode (SCK1 internal clock output)
Parameter SCK1 cycle time Symbol tKCY9 Test Conditions MIN. 1600 3200 SCK1 high-/low-level width tKH9, tKL9 tSIK9 (tKCY9/2)-50 (tKCY9/2)-100 hold time (from SCK1) output delay time from SCK1 from SCK1 Strobe signal high-level width tKSI9 tKSO9 tSBD tSBW pFNote (tKCY9/2)-100 tKCY9-30 tKCY9-60 Busy signal setup time busy signal detection timing) Busy signal hold time (from busy signal detection timing) tBYH SCK1 from busy inactivation tSPS 2tKCY9 tBYS tKCY9/2+100 tKCY9+30 tKCY9+60 TYP. MAX. Unit
setup time SCK1)
Note
output line load capacitance. (iv) Automatic transmit/receive function 3-wire serial mode (SCK1 external clock input)
Parameter Symbol tKCY10 Test Conditions MIN. 1600 3200 TYP. MAX. Unit
SCK1 cycle time
SCK1 high-/low-level width
tKH10, tKL10
1600
setup time SCK1) hold time (from SCK1) output delay time from SCK1 SCK1 rise, fall time
tSIK10 tKSI10 tKSO10 tR10, tF10 pFNote When using external device expansion function When using external device expansion function
1000
Note
output line load capacitance.
µPD78P058Y
Serial interface channel 3-wire serial mode (SCK2.internal clock output)
Parameter SCK2 cycle time Symbol tKCY11 Test Conditions MIN. 1600 3200 SCK2 high-/low-level width tKH11, tKL11 tSIK11 (tKCY11/2)-50 (tKCY11/2)-100 hold time SCK2) output delay time from SCK2 tKSI11 tKSO11 pFNote TYP. MAX. Unit
setup time SCK2)
Note
output line load capacitance. (ii) UART mode (Dedicated baud rate generator output)
Parameter Symbol Test Conditions MIN. TYP. MAX. 78125 39063 19531 Unit
Transfer rate
(iii) UART mode (External clock input)
Parameter ASCK cycle time Symbol tKCY12 Test Conditions MIN. 1600 3200 ASCK high-/low-level width tKH12, tKL12 1600 Transfer rate 39063 19531 9766 rise, fall time tR12, tF12 when using external device expansion function 1000 TYP. MAX. Unit
µPD78P058Y
Timing Test Point (Excluding Input)
Test Points
Clock Timing
1/fX
Input
VIH4 (MIN.) VIL4 (MAX.)
1/fXT tXTL tXTH
Input
VIH5 (MIN.) VIL5 (MAX.)
Timing
tTIL00, tTIL01
tTIH00, tTIH01
TI00, TI01
1/fTI1 tTIL1 tTIH1
TI1,
µPD78P058Y
Read/Write Operations External fetch wait):
A8-A15
High-Order 8-Bit Address tADD1
AD0-AD7 tADS tASTH ASTB
Low-Order 8-Bit Address
Hi-Z
Operation Code tRDD1 tRDADH tRDAST
tADH
tASTRD tRDL1 tRDH
External fetch (wait insertion):
A8-A15
High-Order 8-Bit Address
ADD1 AD0-AD7 ASTH ASTB
Low-Order 8-Bit Address
Hi-Z RDD1
Operation Code tRDADH tRDAST
ASTRD WAIT RDL1
RDWT1
WTRD
µPD78P058Y
External data access wait):
A8-A15
Low-Order 8-Bit Address
High-Order 8-Bit Address tADD2 Hi-Z Hi-Z Hi-Z
AD0-AD7 tADS tASTH ASTB
Read Data tRDD2 tRDH
Write Data
tADH
tASTRD
tRDL2
tRDWD tWRWD
tWDS
tWDH tWRADH
tASTWR tWRL1
External data access (wait insertion):
A8-A15 tADD2 AD0-AD7 tADS tASTH ASTB tASTRD tADH tRDD2
Low-Order 8-Bit Address
High-Order 8-Bit Address Hi-Z Hi-Z Hi-Z Write Data
Read Data
tRDH
tRDL2
tRDWD tWRWD
tWDS
tWDH
tASTWR WAIT tRDWT2 tWTL tWTRD tWRWT tWTL tWTWR tWRL1 tWRADH
µPD78P058Y
Serial Transfer Timing 3-wire serial mode:
tKCYm
tKLm SCK0-SCK2 tSIKm tKSIm
tKHm
SI0-SI2 tKSOm
Input Data
SO0-SO2
Output Data
Remark
2-wire serial mode:
tKCY3, tKL3, SCK0 tSIK3, tKSO3, SB0, tKSI3, tKH3,
mode:
tKL5, tKSI5, tKH5, tSIK5, tKSO5,
tKCY5, tKSB tSBK tKSB
SDA0, SDA1 tSBH tSBK
µPD78P058Y
Automatic transmit/receive function 3-wire serial mode:
SIK9, KSO9,
KSI9, KH9,
SCK1 KL9, KCY9,
Automatic transmit/receive function 3-wire serial mode (busy processing):
SCK1
9Note
10Note
10+n Note
BUSY (Active high)
Note
signal actually here, represented this show timing.
UART mode (external Clock Input):
tKCY12 tKL12 ASCK tKH12
µPD78P058Y
Converter Characteristics AVDD AVSS
Parameter Resolution Total errorNote tCONV tSAMP VIAN AVREF0 RAIREF0 AVREF0 AVDD 19.1 12/fXX AVSS AVREF0 AVDD Symbol Test Conditions MIN. TYP. MAX. Unit
Conversion time Sampling time Analog input voltage Reference voltage AVREF0-AVSS resistance
Note
Excluding quantization error (±1/2 LSB). Shown percentage full scale value.
Remark Main system clock frequency fX/2) Main system clock oscillatior frequency Converter Characteristics AVSS
Parameter Resolution Total error MNote MNote MNote pFNote AVREF1 AVREF1 AVREF1 Output resistor Analog reference voltage AVREF1 AVSS resistance AVREF1 RAIREF1 DACS0, DACS1
Note
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
Settling time
Note
Notes
converter output load resistance load capacitance. Value converter channel.
Remark DACS0, DACS1: conversion value setting register
µPD78P058Y
DATA MEMORY STOP MODE SUPPLY VOLTAGE DATA RETENTION CHARACTERISTICS
Parameter Data retention supply voltage Data retention supply current Symbol VDDDR IDDDR VDDDR Subsystem clock stopped, feedback resister disconnected Release RESET Release interrupt request 217/fx Note Test Conditions MIN. TYP. MAX. Unit
Release signal setup time Oscillation stabilization wait time
tSREL tWAIT
Note
212/fXX, 214/fXX through 217fXX selected bits (OSTS0 OSTS2) oscillation stabilization time selection register (OSTS).
Remark Main system clock frequency fx/2) Main system clock oscillatior frequency Data Retention Timing (STOP mode release RESET)
Internal Reset Operation HALT Mode STOP Mode Operating Mode
Data Retention Mode
STOP Instruction Execution RESET
VDDDR tSREL
tWAIT
Data Retention Timing (STOP mode release standby release signal: interrupt request signal)
HALT Mode STOP Mode Operating Mode
Data Retention Mode
STOP Instruction Execution Standby Release Signal (Interrupt Request)
VDDDR tSREL
tWAIT
µPD78P058Y
Interrupt Request Input Timing
INTL INTP0-INTP6
INTH
RESET Input Timing
RESET
µPD78P058Y
PROM PROGRAMMING CHARACTERISTICS Characteristics PROM Write Mode 0.25 12.5
Parameter Input voltage, high Input voltage, Output voltage, high Output voltage, Input leakage current supply voltage supply voltage supply current supply current Symbol SymbolNote 12.2 6.25 12.5 Test Conditions MIN. 12.8 6.75 TYP. MAX. Unit
PROM Read Mode
Parameter Input voltage, high Input voltage, Output voltage, high Symbol SymbolNote VOH1 VOH2 Output voltage, Input leakage current Output leakage current supply voltage supply voltage supply current supply current VOH1 VOH2 ICCA1 VIL, -100 VOUT VDD, Test Conditions MIN. TYP. MAX. Unit
Note
Correspond symbols µPD27C1001A.
µPD78P058Y
Characteristics PROM Write Mode Page program mode 0.25 12.5
Parameter Address setup time setup time setup time Input data setup time Address hold time (from Symbol SymbolNote tOES tCES tAHL tAHV Input data hold time (from Data output float delay time from setup time setup time Program pulse width Valid data delay time from pulse width during data latching setup time hold time hold time tVPS tVDS tPGMS tCEH tOEH tOES tCES tAHL tAHV tVPS tVCS tPGMS tCEH tOEH Test Conditions MIN. 0.095 0.105 TYP. MAX. Unit
Byte program mode 0.25 12.5
Parameter Address setup time PGM) setup time setup time PGM) Input data setup time PGM) Address hold time (from Input data hold time (from PGM) Data output float delay time from setup time PGM) setup time PGM) Program pulse width Valid data delay time from hold time Symbol SymbolNote tOES tCES tVPS tVDS tOEH tOES tCES tVPS tVCS Test Conditions MIN. 0.095 0.105 TYP. MAX. Unit
Note
Correspond symbols µPD27C1001A.
µPD78P058Y
PROM Read Mode
Parameter Data output delay time from address Data output delay time from Data output delay time from Data output float delay time from Data hold time from address Symbol SymbolNote tACC tACC Test Conditions MIN. TYP. MAX. Unit
Note
Correspond symbols µPD27C1001A.
PROM Programming Mode Setting
Parameter PROM programming mode setup time Symbol tSMA Test Conditions MIN. TYP. MAX. Unit
µPD78P058Y
PROM Write Mode Timing (page program mode)
Page Data Latch
Page Program
Program Verify
A2-A16 D0-D7 Hi-Z Hi-Z tPGMS Data Output Hi-Z tAHL tAHV
tVPS tVDS
Data Input
tCES tOES tCEH
tOEH
µPD78P058Y
PROM Write Mode Timing (byte program mode)
Program Program Verify
A0-A16 D0-D7 Hi-Z tVDS tCES tOES tOEH tVPS Page Data Input Data Latch Hi-Z Data Output Hi-Z
Cautions shonld applied before VPP, removed after VPP. shonld exceed +13.5 including overshoot. Disconnection during application +12.5 have adverse effect reliability. PROM Read Mode Timing
A0-A16
Effective Address
tACC
Note
Note
Note
Data Output Hi-Z
D0-D7
Hi-Z
Notes want read within tACC range, make input delay time from fall maximum tACC tOE. time from when either first reaches VIH.
µPD78P058Y
PROM Programming Mode Setting Timing
RESET
tSMA
A0-A16
Effective Address
µPD78P058Y
CHARACTERISTIC CURVES (for reference only)
MHz, MHz)
10.0
25°C)
HALT(X1 Oscillation, Oscillation)
Supply Current [mA]
0.05
HALT(X1 Stop, Oscillation)
0.01
0.005
0.001
Supply Voltage
µPD78P058Y
MHz)
10.0
HALT(X1 Oscillation, Oscillation)
Supply Current [mA]
0.05
HALT(X1 Stop, Oscillation)
0.01
0.005
0.001
Supply Voltage
µPD78P058Y
PACKAGE DRAWINGS
PLASTIC
detail lead
NOTE Each lead centerline located within 0.13 (0.005 inch) true position (T.P.) maximum material condition.
ITEM MILLIMETERS 17.20±0.20 14.00±0.20 14.00±0.20 17.20±0.20 0.825 0.825 0.32±0.06 0.13 0.65 (T.P.) 1.60±0.20 0.80±0.20 0.17 +0.03 -0.07 0.10 1.40±0.10 0.125±0.075 1.70 MAX. INCHES 0.677±0.008 0.551 +0.009 -0.008 0.551 +0.009 -0.008 0.677±0.008 0.032 0.032 0.013 +0.002 -0.003 0.005 0.026 (T.P.) 0.063±0.008 0.031 +0.009 -0.008 0.007 +0.001 -0.003 0.004 0.055±0.004 0.005±0.003 0.067 MAX. P80GC-65-8BT
Remark package dimensions materials version(s) same those mass production product.
µPD78P058Y
CERAMIC WQFN
X80KW-65A-1 NOTE Each lead centerline located within 0.06 (0.003 inch) true position (T.P.) maximum material condition. ITEM MILLIMETERS 14.0 13.6 13.6 14.0 1.84 MAX. 0.45 0.10 0.06 0.65 (T.P.) 0.15 0.825 0.825 0.75 0.15 0.10 INCHES 0.551 0.008 0.535 0.535 0.551 0.008 0.072 0.142 MAX. 0.018+0.004 -0.005 0.003 0.024 (T.P.) 0.039+0.007 -0.006 0.012 0.032 0.032 0.079 0.354 0.083 0.030+0.006 -0.007 0.004
µPD78P058Y
RECOMMENDED SOLDERING CONDITIONS
These products should soldered mounted under conditions recommended below. details recommended soldering conditions, refer information document Semiconductor Device Mounting Technology Manual (C10535E). soldering methods conditions other than those recommended, please contact your sales representative. Table 12-1. Surface Mount Type Soldering Conditions
µPD78P058YGC-8BT: 80-Pin Plastic
Soldering Method(s) Soldering Conditions Package peak temperature: Time: secs. max. (210 min.), Number times: twice max., Number days: 7Note (after that, prebaking hours necessary) <Precaution> Products other than heat-resistance trays (such those packaged magazine, taping, non-heat-resistance tray) cannot baked while they their package. Package peak temperature: Time: secs. max. (200 min.), Number times: twice max., Number days: 7Note (after that, prebaking hours necessary) <Precaution> Products other than heat-resistance trays (such those packaged magazine, taping, non-heat-resistance tray) cannot baked while they their package. Wave soldering Solder bath temperature: max., Time: secs. max., Number times: once, Preheating temperature: max. (package surface temperature), Number days: Note (after that, prebaking hours necessary) <Precaution> Products other than heat-resistance trays (such those packaged magazine, taping, non-heat-resistance tray) cannot baked while they their package. temperature: max., Time: secs. max. (per device side) WS60-107-1 Recommended Conditions Symbol IR35-107-2
Infrared reflow
VP15-107-2
Partial heating
Note
storage period after dry-pack decapsulation, storage conditions max.
Caution more than soldering method should avoided (except case partial heating).
µPD78P058Y
APPENDIX DEVELOPMENT TOOLS
following development tools available system development using µPD78P058Y. Also refer Notes using development tools. Language Processing Software
RA78K/0 CC78K/0 DF78054 CC78K/0-L 78K/0 series common assembler package 78K/0 series common compiler package
µPD78054 subseries device file
78K/0 series common compiler library source file
PROM Writing Tools
PG-1500 PA-78P054GC PA-78P054KK-T PG-1500 controller PROM programmer Programmer adapters connected PG-1500
PG-1500 control program
Debugging Tools When in-circuit emulator IE-78K0-NS used
IE-78K0-NSNote IE-70000-MC-PS-B IE-70000-98-IF-CNote IE-70000-CD-IFNote IE-70000-PC-IF-CNote IE-780308-NS-EM1Note NP-80GC EV-9200GC-80 ID78K0-NSNote SM78K0 DF78054 In-circuit emulator common 78K/0 series Power supply unit IE-78K0-NS Interface adapter used when PC-9800 series (except notebook type) used host machine card interface cable used when notebook type PC-9800 series used host machine Interface adapter used when PC/ATor compatible machine used host machine Emulation board common µPD780308 subseries Emulation probe 80-pin plastic (GC-8BT type) Socket mounted target system board made 80-pin plastic (GC-8BT type) Integrated debugger IE-78K0-NS 78K/0 series common system simulator
µPD78054 subseries device file
Note
Under development
µPD78P058Y
When in-circuit emulator IE-78001-R-A
IE-78001-R-ANote IE-70000-98-IF-B IE-70000-98-IF-CNote IE-70000-PC-IF-B IE-70000-PC-IF-CNote IE-78000-R-SV3 IE-780308-NS-EM1Note IE-780308-R-EM IE-78K0-R-EX1Note NP-78230GC-R EV-9200GC-80 ID78K0 SM78K0 DF78054 Emulation probe conversion board necessary when using IE-780308-NS-EM1 IE-78001-R-A Emulation probe 80-pin plastic (GC-8BT type) Socket mounted board target system created 80-pin plastic (GC-8BT type) Integrated debugger IE-78001-R-A System simulator common 78K/0 series Device file common µPD78054 subseries In-circuit emulator common 78K/0 series Interface adapter used when PC-9800 series (except notebook type) used host machine
Interface adapter used when PC/AT compatible machine used host machine
Interface adapter cable used when used host machine Emulation board common µPD780308 subseries
Note
Under development
Real-Time
RX78K/0 MX78K0 78K/0 series real-time 78K/0 series
µPD78P058Y
Notes using development tools ID78K0-NS, ID78K0, SM78K0 combination with DF78054. CC78K/0 RX78K/0 combination with RA78K/0 DF78054. NP-80GC product Naito Densei Machida Mfg. Co., Ltd. (TEL (044) 822-3813). Consult your distributor when purchasing these products. development tools made third parties, refer 78K/0 Series Selection Guide (U11126E). host machine corresponding each software package follows:
Host Machine [OS] PC-9800 series PC/AT Compatible Machines [Japanese/English Windows]
Note Note Note
[WindowsTM] HP9000 series 700[HP-UXTM] SPARCstation[SunOSTM] NEWS (RISC)[NEWS-OSTM]
Software RA78K/0 CC78K/0 PG-1500 controller ID78K0-NS ID78K0 SM78K0 RX78K/0 MX78K0
Note Note
Note
This software based DOS.
µPD78P058Y
CONVERSION SOCKET (EV-9200GC-80) DRAWING RECOMMENDED BOARD MOUNTING PATTERN Figure A-1. EV-9200GC-80 Drawing (for reference only)
EV-9200GC-80
No.1 index
EV-9200GC-80-G1E ITEM MILLIMETERS 18.0 14.4 14.4 18.0 16.0 18.7 16.0 18.7 0.35 INCHES 0.709 0.567 0.567 0.709 0.079 0.031 0.236 0.63 0.736 0.236 0.63 0.736 0.323 0.315 0.098 0.079 0.014
0.091 0.059
µPD78P058Y
Figure A-2. EV-9200GC-80 Recommended Board Mounting Pattern (for reference only)
EV-9200GC-80-P1E ITEM Caution MILLIMETERS 19.7 15.0 0.65±0.02 19=12.35±0.05 INCHES 0.776 0.591 0.026+0.001 -0.002 0.748=0.486+0.003 -0.002 0.591 0.776 0.236+0.003 -0.002 0.236+0.003 -0.002 0.014+0.001 -0.001
0.65±0.02 19=12.35±0.05 0.026+0.001 0.748=0.486 +0.003 -0.002 -0.002 15.0 19.7 0.05 0.05 0.35 0.02
2.36 0.03 1.57 0.03
0.093+0.001 -0.002 0.091 0.062+0.001 -0.002
Dimensions mount EV-9200 that target device (QFP) different some parts. recommended mount dimensions QFP, refer "SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL" (C10535E).
µPD78P058Y
APPENDIX RELATED DOCUMENTS
Device Related Documents
Document Name Document Japanese English U10906E This document U11747E U12326E U10182E
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y Data Sheet µPD78P058Y Data Sheet µPD78054, 78054Y Subseries User's Manual
78K/0 Series User's Manual (Instruction) 78K/0 Series Instruction 78K/0 Series Instruction Table
U10906J U10907J U11747J U12326J U10904J U10903J U10087J U10182J
µPD78054Y Subseries Special Function Register Table
78K/0 Series Application Note Basic (III)
Development Tool Related Documents (User's Manual) (1/2)
Document Name Document Japanese RA78K0 Assembler Package Operation Assembly language Structured assembly language RA78K Series Structured Assembler Preprocessor CC78K0 Compiler Operation Language CC78K/0 Compiler Application Note CC78K Series Library Source File PG-1500 PROM Programmer PG-1500 Controller PC-9800 Series (MS-DOSTM) Based PG-1500 Controller Series DOSTM) Based IE-78K0-NS IE-78001-R-A IE-780308-NS-EM1 IE-780308-R-EM EP-78230 Programming know-how U11802J U11801J U11789J U12323J U11517J U11518J EEA-618 U12322J U11940J EEU-704 EEU-5008 Planned Planned Planned U11362J EEU-985 English U11802E U11801E U11789E EEU-1402 U11517E U11518E EEA-1208 U12322E U11940E EEU-1291 U10540E Planned Planned Planned U11362E EEU-1515
Caution above related documents subject change without notice. design purpose, etc., sure latest documents.
µPD78P058Y
Development Tool Related Documents (User's Manual) (2/2)
Document Name Document Japanese SM78K0 System Sumilator Windows Based SM78K Series System Simulator Reference External part user open interface specifications Reference Reference Reference Guide U10181J U10092J English U10181E U10092E
ID78K0-NS Integrated Debugger ID78K0 Integrated Debugger Based ID78K0 Integrated Debugger Based ID78K0 Integrated Debugger Windows Based
U12900J U11151J U11539J U11649J
Planned U11539E U11649E
Embedded Software Related Documents (User's Manual)
Document Name Document Japanese 78K/0 Series Real-Time Fundamentals Installation 78K/0 Series MX78K0 Fundamental U11537J U11536J U12257J English U11537E U11536E U12257E
Other Related Documents
Document Name Document Japanese Package Manual Semiconductor Device Mounting Technology Manual Quality Grades Semiconductor Devices Semiconductor Device Reliability Quality Control Guide Prevent Damage Semiconductor Devices Electrostatic Discharge (ESD) Semiconductor Quality/Reliability Handbook Microcomputer-Related Product Guide (Products Other Manufacturers) C10943X C10535J C11531J C10983J C11892J C12769J U11416J C10535E C11531E C10983E C11892E English
Caution above related documents subject change without notice. design purpose, etc., sure latest documents.
µPD78P058Y
NOTES CMOS DEVICES
PRECAUTION AGAINST SEMICONDUCTORS
Note: Strong electric field, when exposed device, cause destruction gate oxide ultimately degrade device operation. Steps must taken stop generation static electricity much possible, quickly dissipate once, when occurred. Environmental control must adequate. When dry, humidifier should used. recommended avoid using insulators that easily build static electricity. Semiconductor devices must stored transported anti-static container, static shielding conductive material. test measurement tools including work bench floor should grounded. operator should grounded using wrist strap. Semiconductor devices must touched with bare hands. Similar precautions need taken boards with semiconductor devices
HANDLING UNUSED INPUT PINS CMOS
Note: connection CMOS device inputs cause malfunction. connection provided input pins, possible that internal input level generated noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar NMOS devices. Input levels CMOS devices must fixed high using pull-up pull-down circuitry. Each unused should connected with resistor, considered have possibility being output pin. handling related unused pins must judged device device related specifications governing devices.
STATUS BEFORE INITIALIZATION DEVICES
Note: Power-on does necessarily define initial status device. Production process does define initial operation status device. Immediately after power source turned devices with reset function have been initialized. Hence, power-on does guarantee out-pin levels, settings contents registers. Device initialized until reset signal received. Reset operation must executed immediately after power-on devices having reset function.
µPD78P058Y
Regional Information
Some information contained this document vary from country country. Before using product your application, please contact office your country obtain list authorized representatives distributors. They will verify: Device availability Ordering information Product release schedule Availability related technical literature Development environment specifications (for example, specifications third-party tools components, host computers, power plugs, supply voltages, forth) Network requirements addition, trademarks, registered trademarks, export restrictions, other legal issues also vary from country country.
Electronics Inc. (U.S.)
Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288
Electronics (Germany) GmbH
Benelux Office Eindhoven, Netherlands Tel: 040-2445845 Fax: 040-2444580
Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
Electronics Hong Kong Ltd. Electronics (France) S.A.
Velizy-Villacoublay, France Tel: 01-30-67 Fax: 01-30-67 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
Electronics (Germany) GmbH
Duesseldorf, Germany Tel: 0211-65 Fax: 0211-65
Electronics (France) S.A. Electronics (UK) Ltd.
Milton Keynes, Tel: 01908-691-133 Fax: 01908-670-290 Spain Office Madrid, Spain Tel: 01-504-2787 Fax: 01-504-2860
Electronics Singapore Pte. Ltd.
United Square, Singapore 1130 Tel: 253-8311 Fax: 250-3583
Electronics Taiwan Ltd. Electronics Italiana s.r.1.
Milano, Italy Tel: 02-66 Fax: 02-66
Electronics (Germany) GmbH
Scandinavia Office Taeby, Sweden Tel: 08-63 Fax: 08-63
Taipei, Taiwan Tel: 02-719-2377 Fax: 02-719-5951
Brasil S.A.
Cumbica-Guarulhos-SP, Brasil Tel: 011-6465-6810 Fax: 011-6465-6829
J97.
µPD78P058Y
Purchase components conveys license under Philips Patent Rights these components system, provided that system conforms Standard Specification defined Philips.
export these products from Japan regulated Japanese government. export some these products prohibited without governmental license. export re-export some these products from country other than Japan also prohibited without license from that country. Please call sales representative. License needed µPD78P058YKK-T customer must judge need license µPD78P058YGC-8BT
FIP, IEBus QTOP trademarks Corporation. MS-DOS Windows either registered trademarks trademarks Microsoft Corporation United States and/or other countries. PC/AT trademarks Corporation. HP9000 series HP-UX trademarks Hewlett-Packard Company. SPARCstation trademark SPARC International, Inc. SunOS trademark Microsystems, Inc. NEWS NEWS-OS trademarks Sony Corporation. part this document copied reproduced form means without prior written consent Corporation. Corporation assumes responsibility errors which appear this document. Corporation does assume liability infringement patents, copyrights other intellectual property rights third parties arising from device described herein other liability arising from such device. license, either express, implied otherwise, granted under patents, copyrights other intellectual property rights Corporation others. While Corporation been making continuous effort enhance reliability semiconductor devices, possibility defects cannot eliminated entirely. minimize risks damage injury persons property arising from defect semiconductor device, customers must incorporate sufficient safety measures design, such redundancy, fire-containment, anti-failure features. devices classified into following three quality grades: "Standard", "Special", "Specific". Specific quality grade applies only devices developed based customer designated "quality assurance program" specific application. recommended applications device depend quality grade, indicated below. Customers must check quality grade each device before using particular application. Standard: Computers, office equipment, communications equipment, test measurement equipment, audio visual equipment, home electronic appliances, machine tools, personal electronic equipment industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment medical equipment (not specifically designed life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems medical equipment life support, etc. quality grade devices "Standard" unless otherwise specified NEC's Data Sheets Data Books. customers intend devices applications other than those specified Standard quality grade, they should contact sales representative advance. Anti-radioactive design implemented this product.
96.5

µPD78P058Y 8-BIT SINGLE-CHIP MICROCONTROLLER DESCRIPTION

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