µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y 8-BIT SINGLE-CH

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y 8-BIT SINGLE-CH

Datasheet Thumbnail

Top Searches for this datasheet

INTEGRATED CIRCUIT
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
8-BIT SINGLE-CHIP MICROCONTROLLER
DESCRIPTION
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y versions control function µPD78052, 78053, 78054, 78055, 78056, 78058, suitable application products. Various peripheral hardware such 8-bit resolution converter, timer, serial interface, real-time output port interrupt functions incorporated. 78P058Y, one-time PROM EPROM version which operated same supply voltage mask version, various development tools also available. Detailed function descriptions, etc., provided following User's Manual. sure read when designing.
µPD78054, 78054Y Subseries User's Manual U11747E
78K/0 Series User's Manual Instructions U12326E
FEATURES
Internal high-capacity External memory expansion space Kbytes
Item Part number Program memory (ROM) Kbytes Kbytes Kbytes Kbytes Kbytes Kbytes 1024 bytes Internal High-Speed bytes 1024 bytes Data memory Internal Buffer bytes Internal Expanded
µPD78052Y µPD78053Y µPD78054Y µPD78055Y µPD78056Y µPD78058Y
Minimum instruction execution time varied from high-speed (0.4 ultra-low-speed (122 ports (N-ch open-drain 8-bit resolution converter: channels 8-bit resolution converter: channels Serial interface channels (I2C mode channel) Timer channels Supply voltage
APPLICATIONS
Cellular phones, pagers, printers, equipment, airconditioners, cameras, PPC, fuzzy home applicances, vending machines, etc.
information this document subject change without notice. Document U10906EJ2V0DS00 (2nd edition) Date Published September 1997 Printed Japan
mark
shows major revised points.
1993 1996
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
ORDERING INFORMATION
Part Number µPD78052YGC-xxx-8BT µPD78053YGC-xxx-8BT µPD78054YGC-xxx-8BT µPD78055YGC-xxx-8BT µPD78056YGC-xxx-8BT µPD78058YGC-xxx-8BT Remark Package 80-pin plastic 80-pin plastic 80-pin plastic 80-pin plastic 80-pin plastic 80-pin plastic
indicates code suffix.
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
78K/0 SERIES DEVELOPMENT
following shows 78K/0 Series products development. Subseries names shown inside frames.
Under mass production Under development Controller 100-pin 100-pin 100-pin 100-pin 80-pin 80-pin 80-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin 42/44-pin
PD780058 PD78058F PD78054 µPD780034 PD780024 PD78014H PD78018F µPD78014 µPD780001 PD78002 PD78083 PD78002Y PD78018FY µPD78014Y PD78075B PD78078 PD78070A PD78075BY PD78078Y PD78070AY µPD780018AY µPD780058Y
Note
subseries provide interface function noise reduced version PD78078 Added timer enhanced external interface PD78054 Subseries ROM-less versions µPD78078 Enhanced serial PD78078Y with limited number functions Enhanced serial µPD78054, noise reduced version noise reduced version µPD78054 Added UART, PD78014 enhanced ports Enhanced PD780024 Enhanced serial PD78018F, noise reduced version noise reduced version µPD78018F voltage (1.8 operation version PD78014, enhanced variation Added 16-bit timer/event PD78002 Added µPD78002 Basic subseries controller On-chip UART, operatable low-voltage (1.8
µPD78058FY PD78054Y µPD780034Y PD780024Y
Inverter controller 64-pin 64-pin 64-pin
PD780988 PD780964 PD780924
Enhanced inverter control, timer, µPD78064. Expanded RAM. Enhanced PD780924 On-chip inverter control circuit UART, noise reduced version
driver 78K/0 Series 100-pin 100-pin 80-pin 80-pin
PD780208 PD780228 PD78044H PD78044F
Enhanced ports, controller/driver µPD78044F, Total display outputs: Enhanced ports, controller/driver PD78044H, Total display outputs: Added N-ch open-drain input/output PD78044F, Total display outputs: Basic subseries drive, Total display outputs:
driver 100-pin 100-pin 100-pin
PD780308 µPD78064B PD78064 PD78064Y PD780308Y
Enhanced µPD78064 expanded noise reduced version µPD78064 Basic subseries driving, on-chip UART
IEBus supported 80-pin 80-pin
µPD78098B PD78098
noise reduced version µPD78098 Added IEBus controller µPD78054
Meter controller 80-pin
PD780973
Automobile meter drive controller/driver incorporated
64-pin
µPD78P0914
Incorporated output, digital code decorder, Hsync counter
Note Under planning
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
major functional differences among subseries shown below.
Function Subseries Name Control Capacity Serial Interface 3-wire/2-wire/I2C With automatic transmit/receive function, 3-wire 3-wire/UART With automatic transmit/receive function, 3-wire Time division 3-wire (multi master supported) 3-wire/2-wire/I2C With automatic transmit/receive function, 3-wire 3-wire/Time division UART 3-wire/2-wire/I2C With automatic transmit/receive function, 3-wire 3-wire/UART UART 3-wire (multi master supported) 3-wire/2-wire/I With automatic transmit/receive function, 3-wire 3-wire/2-wire/SBI/I2C With automatic transmit/receive function, 3-wire 3-wire/2-wire/SBI/I2C 3-wire/2-wire/I 3-wire/Time division UART 3-wire 3-wire/2-wire/I2C 3-wire/UART
MIN. Value
µPD78075BY µPD78078Y µPD78070AY
µPD780018AY
µPD780058Y
µPD78058FY µPD78054Y
µPD780034Y µPD780024Y µPD78018FY µPD78014Y µPD78002Y
driver
µPD780308Y
µPD78064Y
Remark functions other than serial interface same those Subseries products without suffix
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
OVERVIEW FUNCTION
Product Name Item Internal Memory High-speed Buffer Expanded Memory space General registers Minimum instruction execution time Kbytes bits registers bits registers banks) On-chip minimum instruction execution time cycle modification function 32.768-kHz operation) 16-bit operation Multiplication/division bits bits,16 bits bits) manipulation (set, reset, test, boolean operation) adjustment, etc. None
µPD78052Y
Kbytes bytes
µPD78053Y
Kbytes
µPD78054Y
Kbytes
µPD78055Y
Kbytes 1024 bytes
µPD78056Y
Kbytes
µPD78058Y
Kbytes
bytes 1024 bytes
When main system clock selected µs/0.8 µs/1.6 µs/3.2 µs/6.4 µs/12.8 5.0-MHz operation) When subsystem clock selected Instruction
ports
Total CMOS input CMOS N-ch open-drain 8-bit resolution channels 8-bit resolution channels
converter converter Serial interface
3-wire serial I/O/2-wire serial mode/I2C mode selectable: channel 3-wire serial mode (on-chip max. 32-byte automatic data transmit/receive function): channel 3-wire serial I/O/UART mode selectable channel 16-bit timer/event counter 8-bit timer/event counter Watch timer Watchdog timer channel channels channel channel
Timer
Timer output Clock output
(14-bit output 19.5 kHz, 39.1 kHz, 78.1 kHz, kHz, kHz, kHz, 1.25 MHz, MHz, 5.0-MHz operation with main system clock) 32.768 32.768-kHz operation with subsystem clock) kHz, kHz, kHz, 5.0-MHz operation with main system clock) Maskable Non-maskable Software Internal interrupt external interrupt Internal interrupt Internal external +85°C 80-pin plastic
Buzzer output Vectored interrupt sources Test input Supply voltage Operating ambient temperature Package
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
CONTENTS
CONFIGURATION (TOP VIEW) BLOCK DIAGRAM FUNCTIONS Port Pins
Non-port Pins Circuits Recommended Connection Unused Pins
MEMORY SPACE PERIPHERAL HARDWARE FUNCTION FEATURES Ports Clock Generator Timer/Event Counter Clock Output Control Circuit Buzzer Output Control Circuit Converter Converter Serial Interfaces Real-Time Output Port Functions
INTERRUPT FUNCTIONS TEST FUNCTIONS Interrupt Functions Test Functions
EXTERNAL DEVICE EXPANSION FUNCTIONS STANDBY FUNCTION RESET FUNCTION
INSTRUCTION ELECTRICAL SPECIFICATIONS CHARACTERISTIC CURVES (REFERENCE VALUE) PACKAGE DRAWING RECOMMENDED SOLDERING CONDITIONS APPENDIX DEVELOPMENT TOOLS APPENDIX RELATED DOCUMENTS
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
CONFIGURATION (TOP VIEW)
80-pin plastic
µPD78052YGC-xxx-8BT µPD78053YGC-xxx-8BT µPD78054YGC-xxx-8BT µPD78055YGC-xxx-8BT µPD78056YGC-xxx-8BT µPD78058YGC-xxx-8BT
P01/INTP1/TI01 P00/INTP0/TI00 P06/INTP6 P05/INTP5 P04/INTP4 P03/INTP3 P02/INTP2
P14/ANI4
P13/ANI3
P12/ANI2
P11/ANI1
P10/ANI0
XT1/P07
AVREF0
AVDD
P15/ANI5 P16/ANI6 P17/ANI7 AVSS P130/ANO0 P131/ANO1 AVREF1 P70/SI2/RxD P71/SO2/TxD P72/SCK2/ASCK P20/SI1 P21/SO1 P22/SCK1 P23/STB P24/BUSY P25/SI0/SB0/SDA0 P26/SO0/SB1/SDA1 P27/SCK0/SCL P40/AD0 P41/AD1
RESET P127/RTP7 P126/RTP6 P125/RTP5 P124/RTP4 P123/RTP3 P122/RTP2 P121/RTP1 P120/RTP0 P36/BUZ P35/PCL P34/TI2 P33/TI1 P32/TO2 P31/TO1 P30/TO0 P67/ASTB P66/WAIT P65/WR
P56/A14
P57/A15
P52/A10
P53/A11
P54/A12
P42/AD2
P43/AD3
P44/AD4
P45/AD5
P46/AD6
Cautions (Internally Connected) should connected directly VSS. AVDD should connected pin. AVSS should connected pin.
P47/AD7
P55/A13
P64/RD
P50/A8
P51/A9
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
ANI0 ANI7 ANO0, ANO1 ASCK ASTB AVDD AVREF0, AVREF1 AVSS BUSY P120 P127 P130, P131 Address Address/Data Analog Input Analog Output Asynchronous Serial Clock Address Strobe Analog Power Supply Analog Reference Voltage Analog Ground Busy Buzzer Clock Internally Connected Port0 Port1 Port2 Port3 Port4 Port5 Port6 Port7 Port12 Port13 RESET RTP0 RTP7 SB0, SCK0 SCK2 SDA0, SDA1 TI00, TI01 TI1, WAIT XT1, Programmable Clock Read Strobe Reset Real-Time Output Port Receive Data Serial Serial Clock Serial Clock Serial Data Serial Input Serial Output Strobe Timer Input Timer Input Timer Output Transmit Data Power Supply Ground Wait Write Strobe Crystal (Main System Clock) Crystal (Subsystem Clock)
INTP0 INTP6 Interrupt from Peripherals
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
BLOCK DIAGRAM
TO0/P30 TI00/INTP0/P00 TI01/INTP1/P01 16-bit TIMER/ EVENT COUNTER
PORT0
TO1/P31 TI1/P33 TO2/P32 TI2/P34
PORT1 8-bit TIMER/ EVENT COUNTER PORT2
8-bit TIMER/ EVENT COUNTER
PORT3 WATCHDOG TIMER
WATCH TIMER
PORT4
SI0/SB0/SDA0/P25 SO0/SB1/SDA1/P26 SCK0/SCL/P27 SERIAL INTERFACE 78K/0 CORE SI1/P20 SO1/P21 SCK1/P22 STB/P23 BUSY/P24 SI2/RxD/P70 SO2/TxD/P71 SCK2/ASCK/P72 ANI0/P10 ANI7/P17 AVDD AVSS AVREF0 CONVERTER SERIAL INTERFACE SERIAL INTERFACE
PORT5
PORT6
PORT7
PORT12
P120 P127
PORT13
P130, P131
REAL-TIME OUTPUT PORT
RTP0/P120 RTP7/P127
ANO0/P130, ANO1/P131 AVSS AVREF1
CONVERTER
EXTERNAL ACCESS
AD0/P40AD7/P47 A8/P50 A15/P57 RD/P64 WR/P65 WAIT/P66
INTP0/P00 INTP6/P06
INTERRUPT CONTROL
ASTB/P67
BUZ/P36
RESET BUZZER OUTPUT SYSTEM CONTROL XT1/P07
PCL/P35
CLOCK OUTPUT CONTROL
Remark internal capacity depends product.
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
FUNCTIONS
Port Pins (1/2)
After Reset Input Input Alternate Function INTP0/TI00 INTP1/TI01 INTP2 INTP3 INTP4 INTP5 INTP6 Input Input/ output Input only Port 8-bit input/output port. Input/output specified bit-wise. When used input port, on-chip pull-up resistor used software.Note Port 8-bit input/output port. Input/output specified bit-wise. When used input port, on-chip pull-up resistor used software. Input Input ANI0 ANI7
Name
Note
Input Input/ output Port 8-bit port Input only
Function
Input/output specified bit-wise. When used input port, on-chip pull-up resistor used software.
Input/ output
Input
SCK1 BUSY SI0/SB0/SDA0 SO0/SB1/SDA1 SCK0/SCL
Input/ output
Port 8-bit input/output port. Input/output specified bit-wise. When used input port, on-chip pull-up resistor used software.
Input
Input/ output
Port 8-bit input/output port. Input/output specified 8-bit unit. When used input port, on-chip pull-up resistor used software. Test input flag (KRIF) falling edge detection.
Input
Notes When using P07/XT1 pins input port, (FRC) processor clock control register (PCC). On-chip feedback resistor subsystem clock oscillator should used. When using P10/ANI0 P17/ANI7 pins converter analog input pins, port input mode. pull-up resistor disabled automatically.
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
Port Pins (2/2)
Name
Input/ output
Function Port 8-bit input/output port. driven directly. Input/output specified bit-wise. When used input port, on-chip pull-up resistor used software. Port 8-bit input/outport port. Input/output specified bit-wise. N-ch open-drain input/output port. On-chip pull-up resistor specified mask option. driven directly. When used input port, on-chip pull-up resistor used software.
After Reset Input
Alternate Function
Input/ output
Input
Input
WAIT ASTB
Input/ output
Port 3-bit input/output port. Input/output specified bit-wise. When used input port, on-chip pull-up resistor used software. Port 8-bit input/output port. Input/output specified bit-wise. When used input port, on-chip pull-up resistor used software. Port 2-bit input/output port. Input/output specified bit-wise. When used input port, on-chip pull-up resistor used software.
Input
SI2/RxD SO2/TxD SCK2/ASCK
P120 P127 Input/ output
Input
RTP0 RTP7
P130, P131
Input/ output
Input
ANO0, ANO1
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
Non-port Pins (1/2)
Input Function External interrupt request input which effective edge (rising edge, falling edge, both rising edge falling edge) specified. After Reset Input Alternate Function P00/TI00 P01/TI01 Input Serial interface serial data input. Input P25/SB0/SDA0 P70/RxD Output Serial interface serial data output. Input P26/SB1/SDA1 P71/TxD Input/ output Serial interface serial data input/output. Input P25/SI0/SDA0 P26/SO0/SDA1 P25/SI0/SB0 P26/SO0/SB1 Input/ output Serial interface serial clock input/ output Input P27/SCL P72/ASCK P27/SCK0 Output Input Input Output Input Input Serial interface automatic transmit/receive strobe output. Serial interface automatic transmit/receive busy input. Asynchronous serial interface serial data input. Asynchronous serial interface serial data output. Asynchronous serial interface serial clock input. External count clock input 16-bit timer (TM0) Capture trigger signal input capture register (CR00) External count clock input 8-bit timer (TM1) External count clock input 8-bit timer (TM2) Output 16-bit timer (TM0) output (dual-function 14-bit output) 8-bit timer (TM1) output 8-bit timer (TM2) output Output Output Clock output (for main system clock, subsystem clock trimming). Buzzer output. Real-time output port which data output synchronization with trigger. Low-order address/data external memory expansion. High-order address external memory expansion. External memory read operation strobe signal output. External memory write operation strobe signal output. Input Input Input Input Input Input Input Input Input Input Input Input Input P70/SI2 P71/SO2 P72/SCK2 P00/INTP0 P01/INTP1 P120 P127
Name INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTP6 SDA0 SDA1 SCK0 SCK1 SCK2 BUSY ASCK TI00 TI01
RTP0 RTP7 Output Input/ output Output Output
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
Non-port Pins (2/2)
Input Output Input Output Input Input Input Input Input Positive power supply. Ground potential. Internally connected. Connect directly VSS. Subsystem clock oscillation crystal connection. Function Wait insertion external memory access. Strobe output which latches address information output port port access external memory. converter analog input. converter analog output. converter reference voltage input. converter reference voltage input. converter analog power supply. Connect Ground potential converter converter. Connect System reset input. Main system clock oscillation crystal connection. After Reset Input Input Input Input Input DualFunction P130, P131
Name WAIT ASTB ANI0 ANI7 ANO0, ANO1 AVREF0 AVREF1 AVDD AVSS RESET
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
Circuits Recommended Connection Unused Pins
input/output circuit type each recommended connection unused pins shown Table 3-1. input/output circuit configuration each type, Figure 3-1.
Table 3-1. Input/Output Circuit Type Each (1/2)
Name P00/INTP0/TI00 P01/INTP1/TI01 P02/INTP2 P03/INTP3 P04/INTP4 P05/INTP5 P06/INTP6 P07/XT1 P10/ANI0 P17/ANI7 P20/SI1 P21/SO1 P22/SCK1 P23/STB P24/BUSY P25/SI0/SB0/SDA0 P26/SO0/SB1/SDA1 P27/SCK0/SCL P30/TO0 P31/TO1 P32/TO2 P33/TI1 P34/TI2 P35/PCL P36/BUZ P40/AD0 P47/AD7 P50/A8 P57/A15 P64/RD P65/WR P66/WAIT P67/ASTB
Input/output Circuit Type
Input Input/output
Recommended Connection when Used Connect Independently connect through resistor.
10-A
Input Input/output
Connect VDD. Independently connect through resistor.
13-B
Independently connect through resistor. Independently connect through resistor. Independently connect through resistor. Independently connect through resistor.
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
Table 3-1. Input/Output Circuit Type Each (2/2)
Name P70/SI2/RxD P71/SO2/TxD P72/SCK2/ASCK P120/RTP0 P127/RTP7 P130/ANO0 P131/ANO1 RESET AVREF0 AVREF1 AVDD AVSS
Input/output Circuit Type 12-A
Input/output
Recommended Connection when Used Independently connect through resistor.
Independently connect through resistor. Input Leave open. Connect Connect
Connect Connect directly VSS.
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
Figure 3-1. Input/Output Circuits (1/2)
Type
Type
pull-up enable data P-ch
P-ch
IN/OUT Schmitt-Triggered Input with Hysteresis Characteristic output disable N-ch
Type pull-up enable data
Type 10-A
P-ch
pul-lup enable data IN/OUT P-ch
P-ch
P-ch
IN/OUT open drain output disable N-ch
output disable
N-ch
input enable Type Type pull-up enable data P-ch P-ch IN/OUT IN/OUT output disable N-ch output disable Comparator N-ch P-ch N-ch VREF (Threshold Voltage) input enable
pull-up enable data P-ch
P-ch
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
Figure 3-1. Input/Output Circuits (2/2)
Type 12-A pull-up enable data
Type feed back cut-off P-ch
P-ch
P-ch IN/OUT
output disable input enable
N-ch
P-ch Analog Output Voltage N-ch
Type 13-B Mask Option IN/OUT data output disable N-ch
P-ch
Middle-High Voltage Input Buffer
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
MEMORY SPACE
Figure shows memory map. Figure 4-1. Memory
FFFFH Special Function Registers (SFR) bits FF00H FEFFH FEE0H FEDFH
General Registers bits
7A7FH Prohibited F800H F7FFH
Internal High-Speed Note3 mmmmH mmmmH Prohibited Data Memory Space FAE0H FADFH Buffer bits FAC0H FABFH Prohibited FA80H FA7FH
Internal Expanded 1024 bits F400H F3FFH Prohibited Note2 F000H nnnnH Program Area 1000H 0FFFH CALLF Entry Area 0800H 07FFH
Note1
External Memory Program Memory Space nnnnH nnnnH 0080H 007FH
Program Area
CALLT Table Area 0040H 003FH Vector Table Area
Internal
Note3
0000H
0000H
Notes Provided µPD78058Y only When external device expansion function used with µPD78058Y, internal capacity Kbytes less using internal memory size switching register (IMS). internal capacity internal high-speed capacity depend products (see next table).
Internal Last Address nnnnH 3FFFH 5FFFH 7FFFH 9FFFH BFFFH EFFFH Internal High-Speed First Address mmmmH FD00H FB00H
Relevant Product Name
µPD78052Y µPD78053Y µPD78054Y µPD78055Y µPD78056Y µPD78058Y
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
PERIPHERAL HARDWARE FUNCTION FEATURES
Ports CMOS input (P00, P07) CMOS input/output (P01 P06, port port P67, port port port N-channel open-drain input/output (P60 P63) Total
following types ports available.
Table 5-1. Port Functions
Name Port Name P00, Port Port Port Port Dedicated input port pins Input/output port pins. Input/output specifiable bit-wise. When used input port pins, on-chip pull-up resistor used software. Input/output port pins. Input/output specifiable bit-wise. When used input port pins, on-chip pull-up resistor used software. Input/output port pins. Input/output specifiable bit-wise. When used input port pins, on-chip pull-up resistor used software. Input/output port pins. Input/output specifiable bit-wise. When used input port pins, on-chip pull-up resistor used software. Input/output port pins. Input/output specifiable 8-bit units. When used input port pins, on-chip pull-up resistor used software. Test input flag (KRIF) falling edge detection. Input/output port pins. Input/output specifiable bit-wise. When used input port pins, on-chip pull-up resistor used software. direct drive capability. N-channel open-drain input/output port pins. Input/output specifiable bit-wise. On-chip pull-up resistor used mask option. direct drive capability. Input/output port pins. Input/output specifiable bit-wise. When used input port pins, on-chip pull-up resistor used software. Input/output port pins. Input/output specifiable bit-wise. When used input port pins, on-chip pull-up resistor used software. Input/output port pins. Input/output specifiable bit-wise. When used input port pins, on-chip pull-up resistor used software. Input/output port pins. Input/output specifiable bit-wise. When used input port pins, on-chip pull-up resistor used software. Function
Port
Port
Port Port Port P120 P127 P130, P131
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
Clock Generator
types generators, main system clock generator subsystem clock generator, avaibable. minimum instruction execution time also changed. µs/0.8 µs/1.6 µs/3.2 µs/6.4 µs/12.8 (@5.0-MHz operation with main system clock) (@32.768-kHz operation with subsystem clock) Figure 5-1. Clock Generator Block Diagram
XT1/P07 Subsystem Clock Oscillator
Watch Timer, Clock Output Function Prescaler
Main System Clock Oscillator Scaler STOP
Clock Peripheral Hardware
Selector
Prescaler Selector Standby Control Circuit
Wait Control Circuit
Clock (fCPU)
INTP0 Sampling Clock
Timer/Event Counter 16-bit timer/event counter channel 8-bit timer/event counter channels Watch timer Watchdog timer channel channel Table 5-2. Operation Timer/Event Counter
16-Bit Timer/Event Counter 8-Bit Timer/Event Counter Watch Timer Watchdog Timer
timer/event counter channels incorporated.
Operation mode Interval timer External event counter Function Timer output output Pulse amplitude measurement Square wave output One-shot pulse output Interrupt source Test input output output inputs output output outputs input outputs channel channel channels channels channel channel
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
Figure 5-2. 16-Bit Timer/Event Counter Block Diagram
Internal INTP1 TI01/P01/INTP1 Selector 16-Bit Capture/ Compare Register (CR00)
INTTM00
Match Watch Timer Output 2fXX fXX/2 fXX/2
pulse Output Control Circuit
Output Control Circuit
TO0/P30
Selector
16-Bit Timer Register (TM0) Clear Selector INTTM01 INTP0 16-Bit Capture/ Compare Register (CR01)
TI00/P00/INTP0
Edge Detector
Match
Internal
Figure 5-3. 8-Bit Timer/Event Counter Block Diagram
Internal INTTM1 8-Bit Compare Register (CR10)
8-Bit Compare Register (CR20) Selector Match
Match fxx/2 fxx/29 fxx/211 TI1/P33 Selector 8-Bit Timer Register (TM1) Selector Clear 8-Bit Timer Register (TM2) Clear Selector Selector
Output Control Circuit
TO2/P32 INTTM2
fxx/2 fxx/29 fxx/211 TI2/P34
Output Control Circuit Internal
TO1/P31
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
Figure 5-4. Watch Timer Block Diagram
fXX/2 Selector Selector Prescaler 5-Bit Counter Selector INTWT
Selector
INTTM3 16-Bit Timer/ Event Counter
Figure 5-5. Watchdog Timer Block Diagram
Prescaler Control Circuit
INTWDT Maskable Interrupt Request Selector 8-Bit Counter RESET INTWDT Non-Maskable Interrupt Request
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
Clock Output Control Circuit 19.5 kHz/39.1 kHz/78.1 kHz/156 kHz/313 kHz/625 kHz/1.25 MHz/2.5 MHz/5.0 (@5.0-MHz operation with main system clock) 32.768 (@32.768-kHz operation with subsystem clock) Figure 5-6. Clock Output Control Circuit Block Diagram
clock with following frequencies output clock output.
fXX/2 fXX/22 fXX/23 fXX/24 fXX/25 fXX/26 fXX/27 Selector Synchronization Circuit Output Control Circuit PCL/P35
Buzzer Output Control Circuit kHz/2.4 kHz/4.9 kHz/9.8 (@5.0-MHz operation with main system clock) Figure 5-7. Buzzer Output Control Circuit Block Diagram
clock with following frequencies output buzzer output.
fXX/29 fXX/210 fXX/211 Selector Output Control Circuit BUZ/P36
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
Converter
converter 8-bit resolution channels incorporated. following conversion operation start-up methods available. Hardware start Software start Figure 5-8. Converter Block Diagram
Series Resistor String ANI0/P10 ANI1/P11 ANI2/P12 ANI3/P13 ANI4/P14 ANI5/P15 ANI6/P16 ANI7/P17 Successive Approximation Register (SAR) AVSS Selector Selector Sample Hold Circuit Voltage Comparator AVDD AVREF0
INTP3/P03
Edge Detection Circuit
Control Circuit
INTAD INTP3
Conversion Result Register (ADCR)
Internal
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
Converter
converter 8-bit resolution channels available. Conversion method R-2R resistor ladder method. Figure 5-9. Converter Block Diagram
AVREF1 ANOn
Selector DACSn Write AVSS INTTMX
Conversion Value Register (DACSn)
DAMm Converter Mode Register
Internal
Serial Interfaces Serial interface channel Serial interface channel Serial interface channel Table 5-3. Types Functions Serial Interface
Function 3-wire serial made 3-wire serial mode with automatic transmit/receive function 2-wire serial mode mode Asynchronous serial interface (UART) mode Serial Interface Channel (MSB/LSB first switchable) (MSB first) (MSB first) Serial Interface Channel (MSB/LSB first switchable) (MSB/LSB first switchable) Serial Interface Channel (MSB/LSB first switchable) (Dedicated baud rate generator incorporated)
channels clocked serial interface incorporated.
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
Figure 5-10. Serial Interface Channel Block Diagram
Internal
SI0/SB0/SDA0/P25 Selector SO0/SB1/SDA1/P26 Serial Shift Register (SIO0) Output Latch
Selector
Stop Condition/Start Condition/Acknowledge Detection Circuit Serial Clock Counter
Acknowledge Output Circuit
SCK0/SCL/P27
Interrupt Request Signal Generator
INTCSI0
fXX/2 fXX/28 Serial Clock Control Circuit Selector
Figure 5-11. Serial Interface Channel Block Diagram
Internal
Automatic Data Transmit/ Receive Address Pointer (ADTP)
Buffer
Automatic Data Transmit/Receive Interval Specification Register (ADTI) Match
SI1/P20
Serial Shift Register (SIO1)
SO1/P21 5-Bit Counter STB/P23 Handshake Control Circuit
BUSY/P24
SCK1/P22
Serial Clock Counter
Interrupt Request Signal Generator
INTCSI1
fXX/2 fXX/2 Serial Clock Control Circuit Selector
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
Figure 5-12. Serial Interface Channel Block Diagram
Internal
Receive Buffer Register (RXB/SIO2)
Direction Control Circuit
Direction Control Circuit
Transmit Shift Register (TXS/SIO2)
RxD/SI2/P70 TXD/SO2/P71
Receive Shift Register (RXS)
Transmit Control Circuit
INTST
Receive Control Circuit
INTSER INTSR/INTCSI2 Output Control Circuit
ASCK/SCK2/P72
Baud Rate Generator
fXX/210
Real-time Output Port Functions
Data previously real-time output buffer register transferred output latch hardware concurrently with timer interrupt external interrupt generation order output off-chip. This real-time output function. Pins used output data off-chip called real-time output ports. using real-time output port, signal which jitter output. This most applicable control stepping motors, etc. Figure 5-13. Real-Time Output Port Block Diagram
Internal
INTP2 INTTM1 INTTM2
Output Trigger Control Circuit
Real-Time Output Real-Time Output Buffer Register Buffer Register Higher Bits Lower Bits (RTBH) (RTBL) Real-Time Output Port Mode Register (RTPM)
Output Latch
P127
P120
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
INTERRUPT FUNCTIONS TEST FUNCTIONS
Interrupt Functions Non-maskable interrupt: Maskable interrupts: Software interrupt: following table shows interrupt source list. Table 6-1. Interrupt Source List (1/2)
Interrupt Source Name INTWDT INTWDT INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTP6 INTCSI0 INTCSI1 INTSER INTSR INTCSI2 INTST serial interface channel transfer serial interface channel transfer Generation serial interface channel UART receive error serial interface channel UART reception serial interface channel 3-wire transfer serial interface channel UART transmission 001CH Internal Trigger Watchdog timer overflow (watchdog timer mode selected) Watchdog timer overflow (interval timer mode selected) input edge detection External 0006H 0008H 000AH 000CH 000EH 0010H 0012H 0014H 0016H 0018H 001AH Vector Table Address 0004H Basic Configuration TypeNote
There interrupt functions, sources three different types, shown below.
Interrupt Type Non-maskable Maskable
DefaultNote Priority
Internal/ External Internal
Notes default priority priority order when more maskable interrupt requests generated simultaneously. highest order lowest. Basic configuration types correspond Figure 6-1, respectively.
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
Table 6-1. Interrupt Source List (2/2)
Interrupt Source Name INTTM3 INTTM00 Trigger Reference time interval signal from watch timer Generation match signal 16-bit timer register capture/compare register (CR00) Generation match signal 16-bit timer register capture/compare register (CR01) Generation match signal 8-bit timer/event counter Generation match signal 8-bit timer/event counter conversion converter instruction execution Vector Table Address 001EH 0020H Basic Configuration TypeNote
Interrupt Type Maskable
DefaultNote Priority
Internal/ External Internal
INTTM01
0022H
Software
INTTM1 INTTM2 INTAD
0024H 0026H 0028H 003EH
Notes default priority priority order when more maskable interrupts generated simultaneously. highest order lowest. Basic configuration types correspond Figure 6-1, respectively.
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
Figure 6-1. Interrupt Function Basic Configuration(1/2) Internal non-maskable interrupt
Internal
Interrupt Request
Priority Control Circuit
Vector Table Address Generator Standby Release Signal
Internal maskable interrupt
Internal
Interrupt Request
Priority Control Circuit
Vector Table Address Generator Standby Release Signal
External maskable interrupt (INTP0)
Internal
Sampling Clock Select Register (SCS)
External Interrupt Mode Register (INTM0)
Interrupt Request
Sampling Clock
Edge Detection Circuit
Priority Control Circuit
Vector Table Address Generator Standby Release Signal
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
Figure 6-1. Interrupt Function Basic Configuration(2/2) External maskable interrupt (except INTP0)
Internal
External Interrupt Mode Register (INTM0 INTM1)
Interrupt Request
Edge Detection Circuit
Priority Control Circuit
Vector Table Address Generator Standby Release Signal
Software interrupt
Internal
Interrupt Request
Priority Control Circuit
Vector Table Address Generator
Interrupt request flag Interrupt enable flag In-service priority flag Interrupt mask flag Priority specification flag
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
Test Functions There test functions shown Table 6-2. Table 6-2. Test Input Source List
Test Input Source Internal/External Name INTWT INTPT4 Watch timer overflow Port falling edge detection Trigger Internal External
Figure 6-2. Test Function Basic Configuration
Internal
Test Input
Standby Release Signal
Test input flag Test mask flag
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
EXTERNAL DEVICE EXPANSION FUNCTIONS
external device expansion functions connect external devices areas other than internal ROM, RAM, SFR. Ports used external device connection.
STANDBY FUNCTION
There following standby functions reduce system current consumption. HALT mode operating clock stopped. average current consumption reduced intermittent operation combination with normal operating mode. STOP mode main system clock oscillation stopped. whole operation main system clock stopped, that system operates with ultra-low current consumption using only subsystem clock. Figure 8-1. Standby Function
Main System Clock Operation Interrupt Request STOP Instruction Interrupt Request
CSS=1 CSS=0 HALT Instruction
Subsystem Clock Operation Note HALT Instruction
Interrupt Request
STOP Mode (Main system clock oscillation stopped)
HALT Mode (Clock supply stopped, oscillation)
HALT Mode Note (Clock supply stopped, oscillation)
Note current consumption reduced stopping main system clock. When operating subsystem clock, (MCC) processor clock control register (PCC) stop main system clock. STOP instruction cannot used. Caution When main system clock stopped system operated subsystem clock, subsystem clock should switched again main system clock after oscillation stabilization time secured program.
RESET FUNCTION
There following reset methods. External reset input RESET Internal reset watchdog time runaway time detection
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
INSTRUCTION
8-bit instructions MOV, XCH, ADDC, SUB, SUBC, AND, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ
Second Operand First Operand #byte
Byte]
Note
saddr
!addr16
[DE]
[HL]
$addr16
None
ADDC SUBC
ADDC SUBC
ADDC SUBC
ADDC SUBC
ADDC SUBC
ADDC SUBC
RORC ROLC
ADDC SUBC
saddr ADDC SUBC !addr16
DBNZ
DBNZ
PUSH
[DE] [HL]
ROR4 ROL4
Byte]
MULU DIVUW
Note Except
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
16-bit instructions MOV, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW
Second Operand First Operand #word ADDW SUBW CMPW MOVW MOVW Note Note MOVW XCHW sfrp MOVW saddrp MOVW !addr16 MOVW MOVW None
INCW DECW PUSH
sfrp saddrp !addr16
MOVW MOVW MOVW
MOVW MOVW MOVW MOVW
Note Only when manipulate instructions MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BTCLR
Second Operand First Operand A.bit A.bit sfr.bit saddr.bit PSW.bit [HL].bit MOV1 $addr16 BTCLR BTCLR BTCLR BTCLR BTCLR None SET1 CLR1 SET1 CLR1 SET1 CLR1 SET1 CLR1 SET1 CLR1
sfr.bit
MOV1
saddr.bit
MOV1
PSW.bit
MOV1
[HL].bit
MOV1
MOV1 AND1 XOR1
MOV1 AND1 XOR1
MOV1 AND1 XOR1
MOV1 AND1 XOR1
MOV1 AND1 XOR1
SET1 CLR1 NOT1
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
Call instruction/branch instructions CALL, CALLF, CALLT, BNC, BNZ, BTCLR, DBNZ
Second Operand First Operand Basic instruction
!addr16 CALL
!addr11 CALLF
[addr5] CALLT
$addr16 BTCLR DBNZ
Compound instruction
Other instructions ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, HALT, STOP
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings 25°C)
Parameter Supply voltage Symbol AVDD AVREF0 AVREF1 AVSS Input voltage P07, P17, P27, P37, P47, P57, P67, P72, P120 P127, P130, P131, XT2, RESET N-ch Open-drain Test Conditions Rating -0.3 +7.0 -0.3 -0.3 -0.3 -0.3 +0.3 -0.3 Unit
Output voltage Analog input voltage Output current high
-0.3 -0.3
Analog input
AVSS AVREF0 +150
P06, P37, P56, P57, P67, P120 P127 total P17, P27, P47, P55, P72, P130, P131 total
Output current
Note
Peak value r.m.s. value
total
Peak value r.m.s. value
P56, P57, total
Peak value r.m.s. value
P17, P27, P47, P72, P130, P131 total P06, P37, P67, P120 P127 total Operating ambient temperature Storage temperature Tstg
Peak value r.m.s. value Peak value r.m.s. value
Note r.m.s. should calculated follows: [r.m.s.] [Peak value] duty Caution parameters exceed absolute maximum ratings, even momentarily, device reliability impaired. absolute maximum ratings values that physically damage product. sure product within ratings. Remark characteristics dual-function pins port pins same unless otherwise specified.
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
Main System Clock Oscillation Circuit Characteristics +85°C,
Resonator Ceramic resonator
Recommended Circuit
Parameter
Oscillator frequency (fx)
Note
Test Conditions Oscillator voltage range After reaches oscillation voltage range MIN.
MIN.
TYP.
MAX.
Unit
Oscillation stabilization time
Note
Crystal resonator
Oscillator frequency (fx) Oscillation stabilization time
Note Note
External clock
input
frequency (fx) input
Note
µPD74HCU04
high/low level width (tXH tXL)
Notes Indicates only oscillation circuit characteristics. Refer Characteristics" instruction execution time. Time required stabilize oscillation after reset STOP mode release. Cautions When using main system clock oscillator, wiring area enclosed with broken line should carried follows avoid adverse effects from wiring capacitance. Wiring should short possible. Wiring should cross other signal lines. Wiring should placed close varying high current. potential oscillator capacitor ground should same VSS. ground wiring ground pattern which high current flows. fetch signal from oscillator. When main system clock stopped system operated subsystem clock, subsystem clock should switched again main system clock after oscillation stabilization time secured program.
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
Subsystem Clock Oscillation Circuit Characteristics +85°C,
Resonator Crystal resonator
Recommended Circuit
Parameter Oscillator frequency (fXT) Note
Test Conditions
MIN.
TYP. 32.768
MAX.
Unit
Oscillation Note stabilization time input frequency (fXT) Note input high/low level width (tXTH tXTL)
External clock
Notes Indicates only oscillation circuit characteristics. Refer Characteristics instruction execution time. Time required stabilize oscillation after reaches MIN. oscillation voltage range. Cautions When using subsystem clock oscillator, wiring area enclosed with broken line should carried follows avoid adverse effect from wiring capacitance. Wiring should short possible. Wiring should cross other signal lines. Wiring should placed close varying high current. potential oscillator capacitor ground should same VSS. ground wiring ground pattern which high current flows. fetch signal from oscillator. subsystem clock oscillation circuit circuit with amplification level, more prone misoperation noise than main system clock. When using subsystem clock, special attention wiring described above.
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
Recommended Oscillator Constant µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y Main System Clock: Ceramic Resonator +85°C)
Frequency (MHz) Murata Mfg. Co., Ltd. Kyocera Corp. CSA5.00MG CST5.00MGW KBR-5.0MSA KBR-5.0MKS KBR-5.0MWS PBRC 5.00A Corp. CCR4.0MC3 CCR5.0MC3 5.00 5.00 5.00 5.00 5.00 5.00 4.00 5.00 Recommended Circuit consonant (pF) On-chip On-chip On-chip On-chip On-chip (pF) On-chip On-chip On-chip On-chip On-chip Oscillator Voltage range MIN. MAX. Capacitor chip Lead type Capacitor chip, lead type Capacitor chip, lead type Chip type Capacitor chip Capacitor chip
Manufacturer
Product Name
Remarks
Main System Clock: Crystal Resonator +70°C)
Recommended Circuit Constant (pF) Daishinku Corp. SMD-49 3.579545 (pF) Oscillator Voltage Range MIN. MAX.
Manufacturer
Product Name
Frequency (MHz)
Subsystem Clock: Crystal Resonator +70°C)
Recommended Circuit Constant (pF) Daishinku Corp. DT-38 (1TA252E00) 32.768 (pF) Oscillator Voltage Range MIN. MAX.
Manufacturer
Product Name
Frequency (MHz)
Caution
oscillation circuit constants oscillation voltage range indicate conditions stable oscillation. However, they guarantee accuracy oscillation frequency. application circuit requires accuracy oscillation frequency, necessary oscillation frequency application circuit. this, necessary directly contact manufacturer resonator being used.
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
µPD78058Y Main System Clock: Ceramic Resonator +85°C)
Manufacturer Product Name Frequency (MHz) Kyocera Corp. PBRC4.19A PBRC4.19B KBR-4.19MSA KBR-4.19MKS PBRC4.91A PBRC4.91B KBR-4.91MSA KBR-4.91MKS 4.19 4.19 4.19 4.19 4.91 4.91 4.91 4.91 Recommended Circuit consonant (pF) On-chip On-chip On-chip On-chip (pF) On-chip On-chip On-chip On-chip Oscillator Voltage range MIN. MAX. Capacitor chip Capacitor chip Capacitor chip Capacitor chip Remarks
Caution
oscillation circuit constants oscillation voltage range indicate conditions stable oscillation. However, they guarantee accuracy oscillation frequency. application circuit requires accuracy oscillation frequency, necessary oscillation frequency application circuit. this, necessary directly contact manufacturer resonator being used.
Capacitance 25°C,
Parameter Input capacitance Input/output capacitance Symbol Test Conditions Measured pins retured Measured pins retured P06, P17, P27, P37, P47, P57, P67, P72, P120 P127, P130, P131 MIN. TYP. MAX. Unit
Remark characteristics dual-function pins port pins same unless otherwise specified.
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
Characteristics +85°C,
Parameter Input voltage, high Symbol VIH1 Test Conditions P17, P21, P23, P32, P37, P47, P57, P67, P71, P120 P127, P130, P131 P06, P20, P22, P27, P33, P34, P70, P72, RESET VIH3 (N-ch open-drain) VIH4 Input voltage, VIL1 VNote MIN. 0.85 VIH5 XT1/P07, VIL4 Output voltage, high Output voltage, VOL1 -100 P57, VNote VIL5 XT1/P07, TYP. 0.15 Unit
VIH2
P17, P21, P23, P32, P37, P47, P57, P67, P71, P120 P127, P130, P131 P06, P20, P22, P27, P33, P34, P70, P72, RESET
VIL2
VIL3
P06, P17, P27, P37, P47, P67, P72, P120 P127, P130, P131 VOL2 SB0, SB1, SCK0 open-drain, pulled-up
VOL3
Note P07/XT1 P07, input reverse phase pin. Remark characteristics dual-function pins port pins same unless otherwise specified.
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
Characteristics +85°C,
Parameter Input leakage current, high Symbol ILIH1 Test Conditions P06, P17, P27, P37, P47, P57, P67, P72, P120 P127, P130, P131, RESET XT1/P07, P06, P17, P27, P37, P47, P57, P67, P72, P120 P127, P130, P131, RESET XT1/P07, VOUT VOUT P06, P17, P27, P37, P47, P57, P67, P72, P120 P127, P130, P131 MIN. TYP. Unit
ILIH2 ILIH3 Input leakage current, ILIL1
ILIL2 ILIL3 Output leakage current, high Output leakage current, Mask option pull-up resistor Software pull-up resistor Note ILOH ILOL
Note
Notes pull-up resistor connected (specified with mask option), -200 (MAX.) low-level input leak current flows only during 1.5-clock interval wait interval) during which read instruction executed port (P6) port mode register (PM6). leak current (MAX.) times other than 1.5-clock interval during which read instruction executed. software pull-up resistor used only range Remark characteristics dual-function pins port pins same unless otherwise specified.
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
Characteristics +85°C,
Parameter Power supply current Note Symbol
IDD1
Test Conditions Crystal oscillation operating mode (fXX MHz) Note Crystal oscillation operating mode (fXX MHz) Note
Note Note Note Note Note
MIN.
TYP. 0.35 0.65 0.05 0.05
1.05 19.5 1.95 12.5
Unit
IDD2
Crystal oscillation HALT mode (fXX MHz) Note Crystal oscillation HALT mode (fXX MHz)
Note
IDD3
32.768 Crystal oscillation operating mode Note
IDD4
32.768 Crystal oscillation HALT mode Note
IDD5
STOP mode When feedback resistor used
IDD6
STOP mode When feedback resistor unused
Notes on-chip pull-up resistor, AVREF0, AVREF1, AVDD current, port current included. Operation with main system clock fX/2 (when oscillation mode selection register (OSMS) 00H) Operation with main system clock (when OSMS 01H) When main system clock operation halted. Operating high-speed mode (when processor clock control register (PCC) 00H.) Operating low-speed mode (when 04H)
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
Characteristics Basic Operation +85°C,
Parameter Cycle time (Min. instruction execution time) Symbol Test Conditions Operating main system clock (fXX MHz)Note Operating main system clock (fXX MHz)Note Operating system clock TI00 input high-/low-level width tTIH00, tTIL00 MIN. 40Note 2/fsam 0.1Note4 2/fsam 0.2Note4 2/fsam TI01 input high-/low-level width TI1, input frequency TI1, input high-/low-level width Interrupt request input high-/ low-level width tTIH01, tTIL01 fTI1 tTIH1, tTIL1 tINTH, tINTL INTP0 2/fsam 2/fsam
Note4 Note4 Note4
TYP.
MAX.
Unit
2/fsam Note4 INTP1 INTP6,
RESET level width
tRSL
Notes Main system clock fX/2 operation (when oscillation mode selection register (OSMS) 00H) Main system clock operation (when OSMS 01H) external clock. When crystal resonator used, minimum value combination with bits (SCS0) (SCS1) sampling clock selection register, fsam selectable between fXX/2N, fXX/32, fXX/64, fXX/128 (when
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
fX/2 main system clock operation) main system clock operation)
Cycle Time [µs]
Cycle Time [µs]
Operation Guaranteed Range
Operation Guaranteed Range
Supply Voltage
Supply Voltage
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
Read/write Operation When PCC2 PCC0 000B +85°C,
Parameter ASTB high-level width Address setup time Address hold time Data input time from address Symbol tASTH tADS tADH tADD1 tADD2 Data input time from tRDD1 tRDD2 Read data hold time low-level width tRDH tRDL1 tRDL2 WAIT input time from tRDWT1 tRDWT2 WAIT input time from WAIT low-level width Write data setup time Write data hold time low-level width delay time from ASTB delay time from ASTB ASTB delay time from external fetch Address hold time from external fetch Write data output time from Write data output time from Address hold time from delay time from WAIT delay time from WAIT tRDWD tRDWD tWRADH tWTRD tWTWR 0.85tCY 1.15tCY 1.15tCY 1.15tCY 3.15tCY 3.15tCY tWRWT tWTL tWDS tWDH tWRL tASTRD tASTWR tRDAST (1.15 2n)tCY (2.85 2n)tCY (2.85 2n)tCY 0.85tCY 0.85tCY 1.15tCY 2n)tCY (2.85 2n)tCY 0.85tCY 2tCY 2tCY 2n)tCY Test Conditions MIN. 0.85tCY 0.85tCY (2.85 2n)tCY 2n)tCY 2n)tCY (2.85 2n)tCY MAX. Unit
tRDADH
0.85tCY
1.15tCY
Remarks MCS: Oscillation mode selection register (OSMS) PCC2 PCC0: Processor clock control register (PCC) TCY/4 indicates number waits.
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
Except when PCC2 PCC0 000B +85°C, (1/2)
Parameter ASTB high-level width Symbol tASTH Test Conditions MIN. Address setup time tADS Address hold time tADH 0.4tCY 0.37tCY Data input time from address tADD1 2n)tCY 2n)tCY tADD2 2n)tCY 2n)tCY Data input time from tRDD1 (1.4 2n)tCY (1.37 2n)tCY tRDD2 (2.4 2n)tCY (2.37 2n)tCY Read data hold time low-level width tRDH tRDL1 (1.4 2n)tCY (1.37 2n)tCY tRDL2 (2.4 2n)tCY (2.37 2n)tCY WAIT input time from tRDWT1 tRDWT2 2tCY 2tCY WAIT input time from tWRWT 2tCY 2tCY WAIT low-level width Write data setup time tWTL tWDS 2n)tCY (2.4 2n)tCY (2.37 2n)tCY Write data hold time low-level width tWDH tWRL (2.4 2n)tCY (2.37 2n)tCY delay time from ASTB tASTRD 0.4tCY 0.37tCY delay time from ASTB tASTWR 1.4tCY 1.37tCY 2n)tCY MAX. Unit
Remarks MCS: Oscillation mode selection register (OSMS) PCC2 PCC0: Processor clock control register (PCC) TCY/4 indicates number waits.
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
Except when PCC2 PCC0 000B +85°C, (1/2)
Parameter ASTB delay time from external fetch Address hold time from external fetch Write data output time from Symbol tRDAST tRDADH tRDWD Test Conditions MIN. 0.4tCY 0.37tCY Write data output time from tWRWD Address hold time from tWRADH delay time from WAIT tWTRD 0.6tCY 0.63tCY delay time from WAIT tWTWR 0.6tCY 0.63tCY 2.6tCY 2.63tCY 2.6tCY 2.63tCY MAX. Unit
Remarks MCS: Oscillation mode selection register (OSMS) PCC2 PCC0: Processor clock control register (PCC) TCY/4 indicates number waits.
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
Serial Interface +85°C, Serial interface channel 3-wire serial mode (SCK0. Internal clock output)
Parameter SCK0 cycle time Symbol tKCY1 Test Conditions MIN. 1600 3200 SCK0 high-/low-level width setup time SCK0) tKH1, tKL1 tKCY1/2 tKCY1/2 tSIK1 hold time (from SCK0) output delay time from SCK0 tKSI1 tKSO1 Note TYP. MAX. Unit
Note load capacitance SCK0, output line. (ii) 3-wire serial mode (SCK0. External clock input)
Parameter SCK0 cycle time Symbol tKCY2 Test Conditions MIN. 1600 3200 SCK0 high-/low-level width tKH2, tKL2 1600 setup time SCK0) hold time (from SCK0) output delay time from SCK0 SCK0 rise, fall time tKSO2 tR2, Note When using external device expansion function When using external device expansion function 1000 tSIK2 tKSI2 TYP. MAX. Unit
Note load capacitance output line.
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
(iii) 2-wire serial mode (SCK0. Internal clock output)
Parameter SCK0 cycle time Symbol tKCY3 Note SCK0 high-level width tKH3 Test Conditions MIN. 1600 3200 tKCY3/2 tKCY3/2 SCK0 low-level width tKL3 tKCY3/2 tKCY3/2 SB0, setup time SCK0) tSIK3 SB0, hold time (from SCK0) SB0, output delay time from SCK0 tKSI3 tKSO3 TYP. MAX. Unit
Note load resistance load capacitance SCK0, SB0, output line. (iv) 2-wire serial mode (SCK0. External clock input)
Parameter SCK0 cycle time Symbol tKCY4 Test Conditions MIN. 1600 3200 SCK0 high-level width tKH4 1300 SCK0 low-level width tKL4 1600 SB0, setup time SCK0) SB0, hold time (from SCK0) SB0, output delay time from SCK0 SCK0 rise, fall time tSIK4 tKSI4 tKSO4 tR4,
Note
TYP.
MAX.
Unit
tKCY4/2 1000
When using external device expansion function When using external device expansion function
Note load resistance load capacitance SCK0, SB0, output line.
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
mode (SCL.Internal clock output)
Parameter cycle time Symbol tKCY5 100pF high-level width tKH5
Note
Test Conditions
MIN.
TYP.
MAX.
Unit
tKCY5 tKCY5
low-level width
tKL5
tKCY5 tKCY5
SDA0, SDA1 setup time tSIK5 SCL) SDA0, SDA1 hold time SCL) SDA0, SDA1 output delay time from tKSO5 tKSI5
SCLSDA0, SDA1 tKSB SCLSDA0, SDA1 SDA0, SDA1SCL SDA0, SDA1 high-level width tSBK tSBH
Note load resistance load capacitance SCK0, SB0, output line. (vi) mode (SCL.External clock input)
Parameter cycle time Symbol tKCY6 Test Conditions MIN. 1000
Note
TYP.
MAX.
Unit
high-/low-level width tKH6, tKL6 SDA0, SDA1 setup time tSIK6 SCL) SDA0, SDA1 hold time SCL) SDA0, SDA1 output delay time tKSI6 tKSO6
SCLSDA0, SDA1 tKSB SCLSDA0, SDA1 SDA0, SDA1 SDA0, SDA1 high-level width rise, fall time tSBK tSBH tR6, When using external device expansion function When using external device expansion function
1000
Note load resistance load capacitance SDA0, SDA1 output line.
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
Serial interface channel 3-wire serial mode (SCK1. Internal clock output)
Parameter SCK1 cycle time Symbol tKCY7 Test Conditions 1600 3200 SCK1 high-/low-level width setup time SCK1) tKH7, tKL7 tKCY7/2 tKCY7/2 tSIK7 hold time (from SCK1) output delay time from SCK1 tKSI7 tKSO7
Note
MIN.
TYP.
MAX.
Unit
Note load capacitance SCK1 output lines. (ii) 3-wire serial mode (SCK1. External clock input)
Parameter SCK1 cycle time Symbol tKCY8 Test Conditions tKH8, tKL8 MIN. 1600 3200 SCK1 high-/low-level width 1600 setup time SCK1) hold time (from SCK1) output delay time from SCK1 SCK1 rise, fall time tSIK8 tKSI8 tKSO8 tR8,
Note
TYP.
MAX.
Unit
1000
When using external device expansion function When using external device expansion function
Note load capacitance output line.
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
(iii) 3-wire serial mode with automatic transmit/receive function (SCK1.Internal clock output)
Parameter SCK1 cycle time Symbol tKCY9 Test Conditions MIN. 1600 3200 SCK1 high-/low-level width tKH9, tKL9 setup time SCK1) tSIK9 tKCY9/2 tKCY9/2 hold time (from SCK1) output delay time from SCK1 from SCK1 Strobe signal high-level width tKSI9 tKSO9 tSBD tSBW 6.0V Note tKCY9/2 tKCY9 tKCY9 Busy signal setup time busy signal detection timing) Busy signal hold time (from busy signal detection timing) tBYS tBYH SCK1 from busy inactive tSPS 2tKCY9 tKCY9/2 tKCY9 tKCY9 TYP. MAX. Unit
Note load capacitance SCK1, output line. (iv) 3-wire serial mode with automatic transmit/receive function (SCK1.External clock input)
Parameter SCK1 cycle time Symbol tKCY10 Test Conditions MIN. 1600 3200 SCK1 high-/low-level width tKH10, tKL10 1600 setup time SCK1) hold time (from SCK1) output delay time from SCK1 SCK1 rise, fall time tSIK10 tKIS10 tKSO10 tR10, tF10
Note
TYP.
MAX.
Unit
1000
When using external device expansion function When using external device expansion function
Note load capacitance output line.
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
Serial interface channel 3-wire serial mode (SCK2. Internal clock output)
Symbol tKCY11 Test Conditions MIN. 1600 3200 SCK2 high-/low-level width setup time SCK2) tKH11, tKL11 tSIK11 tKCY11/2 tKCY11/2 hold time SCK2) output delay time from SCK2 tKSI11 tKSO11
Note
Parameter SCK2 cycle time
TYP.
MAX.
Unit
Note load capacitance SCK2, output line. (ii) UART mode (Dedicated baud rate generator output)
Parameter Transfer rate Symbol Test Conditions MIN. TYP. MAX. 78125 39063 19531 Unit
(iii) UART mode (External clock input)
Parameter ASCK cycle time Symbol tKCY12 Test Conditions MIN. 1600 3200 ASCK high-/low-level width tKH12, tKL12 1600 Transfer rate 39063 19531 9766 ASCK rise, fall time tR12, tF12 when using external device expansion function. 1000 TYP. MAX. Unit
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
Timing Test Point (Excluding Input)
Test Points
Clock Timing
1/fX
VIH4 (MIN.) VIL4 (MAX.)
Input
1/fXT
tXTL Input
tXTH VIH5 (MIN.) VIL5 (MAX.)
Timing
tTIL00, tTIL01 tTIH00, tTIH01
TI00, TI01
1/fTI1 tTIL1 tTIH1
TI1,
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
Read/Write Operation External Fetch Wait)
Lower 8-Bit Address tADS tASTH ASTB
Higher 8-Bit Address tADD1 Hi-z Operation Code tRDD1 tRDADH tRDAST
tADH
tASTRD tRDL1 tRDH
External Fetch (Wait Insertion)
Lower 8-Bit Address tADS tASTH ASTB
Higher 8-Bit Address
tADD1 Hi-z tRDD1 tADH tRDAST Operation Code tRDADH
tASTRD tRDL1 tRDH
WAIT tRDWT1 tWTL tWTRD
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
External Data Access Wait)
Lower 8-Bit Address tADS tADH tASTH ASTB
Higher 8-Bit Address
tADD2 Hi-z tRDD2 tRDH Read Data Hi-z Write Data Hi-z
tASTRD tRDL2 tRDWD tWDWR tASTWR tWRL tWRADH tWDS tWDH
External Data Access (Wait Insertion)
Lower 8-Bit Address tADS tADH tASTH ASTB
Higher 8-Bit Address
tADD2 Hi-z tRDD2 tRDH Read Data Hi-z Write Data Hi-z
tASTRD tRDL2 tRDWD tWDWR tASTWR tWRL tWRADH tWDS tWDH
WAIT tRDWT2 tWTL tWTRD tWRWT tWTL tWTWR
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
Serial Transfer Timing 3-wire Serial Mode
tKCYm tKLm SCK0 SCK2 tKHm
tSIKm
tKSIm
Input Data
tKSOm
Output Data
2-wire Serial Mode
tKCY3, tKL3, SCK0 tSIK3, tKH3,
tKSO3,
tKSI3,
SB0,
Mode:
tKL5, SDA0, SDA1 tSBH tSBK
tKCY5,
tKSI5,
tKH5,
tSIK5, tKSO5,
tKSB tSBK
tKSB
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
3-wire Serial Mode with Automatic Transmit/Receive Function
tSIK9, tKSO9,
tKSI9, tKH9,
tF10 SCK1 tR10 tKL9, tKCY9, tSBD tSBW
3-wire Serial Mode with Automatic Transmit/Receive Function (Busy processing)
SCK1
Note
Note tBYS
10+n Note tBYH tSPS
BUSY (Active high)
Note signal actually driven here; shown such indicate timing.
UART Mode (External Clock Input)
KCY12 KL12 tR12 KH12 tF12
ASCK
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
Converter Characteristics +85°C, AVDD AVSS
Parameter Resolution Overall error Note AVREF0 AVDD AVREF0 Conversion time Sampling time Analog input voltage Reference voltage Resistance between AVREF0 AVSS tCONV tSAMP VIAN AVREF0 RAIREF0 19.1 12/fxx AVSS
Symbol
Test Conditions
MIN.
TYP.
MAX. ±0.6 ±1.4
Unit
AVREF0 AVDD
Note Overall error excluding quantization error (±1/2 LSB). indicated ratio full-scale value. Main system clock frequency fX/2) Main system clock oscillation frequency
Converter Characteristics +85°C, AVSS
Parameter Resolution Overall error
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
Note1 Note1
Note1 Settling time C=30pF
Note1
AVREF1 AVREF1 AVREF1
Output resistance Analog reference voltage AVREF1 current
AVREF1 IREF1
DACS0, DACS1 Note
Note2
Notes denote converter output load resistance load capacitance, respectively. Value converter channel DACS0, DACS1: conversion value setting register.
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
Data Memory Stop Mode Supply Voltage Data Retention Characteristics +85°C)
Parameter Data retention power supply voltage Data retention power supply current Release signal time Oscillation stabiliation wait time IDDDR VDDDR Subsystem clock stop feedback resistor disconnected Release RESET Release interrupt request 217/fx Note Symbol VDDDR Test Conditions MIN. TYP. MAX. Unit
tSREL tWAIT
Note
combination with bits (OSTS0 OSTS2) oscillation stabilization time selection register (OSTS), selection 212/fXX 214/fXX 217/fXX possible.
Main system clock frequency fX/2) Main system clock oscillation frequency
Data Retention Timing (STOP Mode Release RESET)
Internal Reset Operation HALT Mode
STOP Mode
Operating Mode
Data Retention Mode
STOP Instruction Execution
VDDDR tSREL
RESET
tWAIT
Data Retention Timing (Standby Release Signal: STOP Mode Release Interrupt Request Signal)
HALT Mode STOP Mode Operating Mode
Data Retention Mode
STOP Instruction Execution Standby Release Signal (Interrupt Request)
VDDDR tSREL
tWAIT
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
Interrupt Request Input Timing
tINTL INTP0 INTP6
tINTH
RESET Input Timing
tRSL
RESET
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
CHARACTERISTIC CURVES (REFERENCE VALUE)
MHz) 25°C) 10.0 HALT oscillation, oscillation)
Supply Current (mA)
0.05
HALT stop, oscillation)
0.01
0.005
0.001
Supply Voltage
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
MHz, MHz) 25°C) 10.0
HALT oscillation, oscillation)
Supply Current (mA)
0.05
HALT Stop, oscillation)
0.01
0.005
0.001
Supply Voltage
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
PACKAGE DRAWING
PLASTIC
detail lead
NOTE Each lead centerline located within 0.13 (0.005 inch) true position (T.P.) maximum material condition.
ITEM MILLIMETERS 17.20±0.20 14.00±0.20 14.00±0.20 17.20±0.20 0.825 0.825 0.32±0.06 0.13 0.65 (T.P.) 1.60±0.20 0.80±0.20 0.17 +0.03 -0.07 0.10 1.40±0.10 0.125±0.075 1.70 MAX. INCHES 0.677±0.008 0.551 +0.009 -0.008 0.551 +0.009 -0.008 0.677±0.008 0.032 0.032 0.013 +0.002 -0.003 0.005 0.026 (T.P.) 0.063±0.008 0.031 +0.009 -0.008 0.007 +0.001 -0.003 0.004 0.055±0.004 0.005±0.003 0.067 MAX. P80GC-65-8BT
Remark Dimensions materials product same those mass-production products.
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
RECOMMENDED SOLDERING CONDITIONS
This product should soldered mounted under conditions recommended table below. detailed description recommended soldering conditions, refer information document Semiconductor Device Mounting Technology Manual (C10535E). soldering methods conditions other than those recommended below, contact sales representative. Table 14-1. Surface Mounting Type Soldering Conditions
µPD78052YGC-xxx-8BT 80-pin plastic µPD78053YGC-xxx-8BT 80-pin plastic µPD78054YGC-xxx-8BT 80-pin plastic µPD78055YGC-xxx-8BT 80-pin plastic µPD78056YGC-xxx-8BT 80-pin plastic µPD78058YGC-xxx-8BT 80-pin plastic
Soldering Method Infrared reflow Wave soldering Partial heating Soldering Conditions Package peak temperature: Duration: sec. max. 210°C above), Number times: Twice max. Package peak temperature: Duration: sec. max. 200°C above), Number times: Twice max. Solder bath temperature 260°C max., Duration sec. max., Number times: once, Preheating temperature 120°C max. (package surface temperature) temperature: 300°C max. Duration: sec. max. (per row) Recommended Condition Symbol IR35-00-2 VP15-00-2 WS60-00-1
Caution
Avoid much possible combining more soldering methods (except partial heating method).
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
APPENDIX DEVELOPMENT TOOLS
following development tools available system development using µPD78054Y subseries. Language Processing Software
RA78K/0 Notes CC78K/0 DF78054
Notes Notes
78K/0 series common assembler package 78K/0 series common compiler package Device file common µPD78054 subseries 78K/0 series common compiler library source file
CC78K/0-L Notes
PROM Writing Tools
PG-1500 PA-78P054GC PA-78P054KK-T PG-1500 controller Notes PROM programmer Programmer adapters connected PG-1500 PG-1500 control program
Debugging Tools
IE-78000-R IE-78000-R-A IE-78000-R-BK IE-780308-R-EM IE-78000-R-SV3 IE-78000-98-IF-B IE-78000-98N-IF IE-78000-PC-IF-B EP-78230GC-R EV-9200GC-80 SM78K0 ID78K0
Notes
In-circuit emulator common 78K/0 series In-circuit emulator common 78K/0 series (for integrated debugger) Break board common 78K/0 series Emulation board common µPD780308 subseries Interface adapter cable when using host machine (for IE-78000-R-A) Interface adapter when using PC-9800 series (except notebook computers) host machine (for IE-78000-R-A) Interface adapter cable when using PC-9800 series notebook computers host machine (for IE-78000-R-A) Interface adapter when using IBM/PC ATand compatibles host machine (for IE-78000-R-A) Emulation probe common µPD78234 subseries Socket mounted target system board manufactured 80-pin plastic (GC-8BT type) System simulator common 78K/0 series Integrated debugger IE-78000-R-A Screen debugger IE-78000-R Device file common µPD78054 subseries
Notes
SD78K/0 Notes DF78054
Notes
Notes PC-9800 series (MS-DOSTM) based PC/AT compatible computer DOSTM/IBM DOSTM/MS-DOS) based HP9000 series 300(HP-UXTM) based HP9000 series 700(HP-UX) based, SPARCstation(Sun OSTM) based, EWS4800 series (EWS-UX/ based PC-9800 series (MS-DOS WindowsTM) based PC/AT compatible computer DOS/IBM DOS/MS-DOS Windows) based NEWS(NEWS-OSTM) based
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
Real-Time
RX78K/0 Notes MX78K0 Notes Real-time 78K/0 series 78K/0 series
Fuzzy Inference Development Support System
FE9000 FT9080 FI78K0
Note Note
FE9200
Note Note
Fuzzy knowledge data creation tool Translator Fuzzy inference module Fussy inference debugger
FT9085
Notes Notes
FD78K0
Notes PC-9800 series (MS-DOS) based PC/AT compatible computers DOS/IBM DOS/MS-DOS) based HP9000 series (HP-UX) based HP9000 series (HP-UX) based, SPARCstation (Sun based, EWS4800 series (EWS-UX/V) based PC/AT compatible computers DOS/IBM DOS/MS-DOS Windows) based
Remarks third party development tools, 78K/0 Series Selection Guide (U11126E). RA78K/0, CC78K/0, SM78K0, ID78K0, SD78K/0, RX78K/0 used combination with DF78054.
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
APPENDIX RELATED DOCUMENTS
Device Related Documents
Document (English) This document U10907E IEU-1356 U12326E Basics (III) U10182E Document (Japanese) U10906J U10907J U11747J U12326J U10904J U10903J U10087J U10182J
Document Name
µPD78052Y,78053Y, 78054Y, 78055Y, 78056Y, 78058Y Data Sheet µPD78P058Y Data Sheet µPD78054 µPD78054Y Subseries User's Manual
78K/0 Series User's Manual Instructions 78K/0 Series Instruction 78K/0 Series Instruction Table
µPD78054Y Special Function Register Table
78K/0 Series Application Note
Development Tool Related Documents (User's Manual)
Document Name RA78K Series Assembler Package Operation Language RA78K Series Structured Assembler Preprocessor CC78K0 Assembler Package Operation Assembly Language Structured Assembly Language CC78K Series Compiler CC78K0 Compiler Operation Language Operation Language CC78K/0 Compiler Application Note CC78K Series Library Source File PG-1500 PROM Programmer PG-1500 Controller PC-9800 Series (MS-DOS) Based PG-1500 Controller Series DOS) Based IE-78000-R IE-78000-R-A IE-78000-R-BK IE-780308-R-EM EP-78230 SM78K0 System Simulator WIndows based SM78K Series System Simulator SD78K/0 Screen Debugger PC-9800 Series (MS-DOS) Based SD78K/0 Screen Debugger PC/AT DOS) Based ID78K0 Integrated Debugger based ID78K0 Integrated Debugger based ID78K0 Integrated Debugger Windows based Reference External Part User Open Interface Specifications Introduction Reference Introduction Reference Reference Reference Guide Programming Know-How Document (English) EEU-1399 EEU-1404 EEU-1402 U11802E U11801E U11789E EEU-1280 EEU-1284 U11517E U11518E EEA-1208 U12322E U11940E EEU-1291 U10540E U11376E U10057E EEU-1427 U11362E EEU-1515 U10181E U10092E U10539E U11279E U11539E U11649E Document (Japanese) EEU-809 EEU-815 U12323J U11802J U11801J U11789J EEU-656 EEU-655 U11517J U11518J EEA-618 U12322J U11940J EEU-704 EEU-5008 U11376J U10057J EEU-867 U11362J EEU-985 U10181J U10092J EEU-852 U10952J EEU-5024 U11279J U11151J U11539J U11649J
Caution
above documents subject change without notice. design purpose, etc., sure latest document.
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
Embedded Software Documents (User's Manual)
Document Name 78K/0 Series Real Time MX78K0: 78K/0 Series Fuzzy Knowledge Data Creation Tools 78K/0, 78K/II, 87AD Series Fuzzy Inference Development Support System Translator 78K/0 Series Fuzzy Inference Development Support System Fuzzy Inference Module 78K/0 Series Fuzzy Inference Development Support System Fuzzy Inference Debugger Basics Installation Basic Document (English) U11537E U11536E U12257E EEU-1438 EEU-1444 EEU-1441 EEU-1458 Document (Japanese) U11537J U11536J U12257J EEU-829 EEU-862 EEU-858 EEU-921
Other Documents
Document Name Package Manual Semiconductor Device Mounting Technology Manual Quality Grades Semiconductor Device Semiconductor Device Reliability/Quality Control System Guide Prevent Damage Semiconductor Devices Electrostatic Discharge (ESD) Guide Quality Assurance Semiconductor Devices Microcomputer-related Product Guide, Third Party Products C10535E C11531E C10983E C11892E MEI-1202 Document (English) Document (Japanese)
C10943X C10535J C11531J C10983J C11892J C11893J U11416J
Caution
above related documents subject change without notice. design purpose, etc., sure latest documents.
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
NOTES CMOS DEVICES
PRECAUTION AGAINST SEMICONDUCTORS
Note: Strong electric field, when exposed device, cause destruction gate oxide ultimately degrade device operation. Steps must taken stop generation static electricity much possible, quickly dissipate once, when occurred. Environmental control must adequate. When dry, humidifier should used. recommended avoid using insulators that easily build static electricity. Semiconductor devices must stored transported anti-static container, static shielding conductive material. test measurement tools including work bench floor should grounded. operator should grounded using wrist strap. Semiconductor devices must touched with bare hands. Similar precautions need taken boards with semiconductor devices
HANDLING UNUSED INPUT PINS CMOS
Note: connection CMOS device inputs cause malfunction. connection provided input pins, possible that internal input level generated noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar NMOS devices. Input levels CMOS devices must fixed high using pull-up pull-down circuitry. Each unused should connected with resistor, considered have possibility being output pin. handling related unused pins must judged device device related specifications governing devices.
STATUS BEFORE INITIALIZATION DEVICES
Note: Power-on does necessarily define initial status device. Production process does define initial operation status device. Immediately after power source turned devices with reset function have been initialized. Hence, power-on does guarantee out-pin levels, settings contents registers. Device initialized until reset signal received. Reset operation must executed immediately after power-on devices having reset function.
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
Regional Information
Some information contained this document vary from country country. Before using product your application, please contact office your country obtain list authorized representatives distributors. They will verify: Device availability Ordering information Product release schedule Availability related technical literature Development environment specifications (for example, specifications third-party tools components, host computers, power plugs, supply voltages, forth) Network requirements addition, trademarks, registered trademarks, export restrictions, other legal issues also vary from country country.
Electronics Inc. (U.S.)
Santa Clara, California Tel: 800-366-9782 Fax: 800-729-9288
Electronics (Germany) GmbH
Benelux Office Eindhoven, Netherlands Tel: 040-2445845 Fax: 040-2444580
Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
Electronics (Germany) GmbH
Duesseldorf, Germany Tel: 0211-65 Fax: 0211-65
Electronics Hong Kong Ltd. Electronics (France) S.A.
Velizy-Villacoublay, France Tel: 01-30-67 Fax: 01-30-67 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
Electronics (UK) Ltd.
Milton Keynes, Tel: 01908-691-133 Fax: 01908-670-290
Electronics (France) S.A.
Spain Office Madrid, Spain Tel: 01-504-2787 Fax: 01-504-2860
Electronics Singapore Pte. Ltd.
United Square, Singapore 1130 Tel: 253-8311 Fax: 250-3583
Electronics Italiana s.r.1.
Milano, Italy Tel: 02-66 Fax: 02-66
Electronics Taiwan Ltd. Electronics (Germany) GmbH
Scandinavia Office Taeby, Sweden Tel: 08-63 Fax: 08-63 Taipei, Taiwan Tel: 02-719-2377 Fax: 02-719-5951
Brasil S.A.
Paulo-SP, Brasil Tel: 011-889-1680 Fax: 011-889-1689
J96.
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
CAUTION
Purchase components conveys license under Philips Patent Rights these components system, provided that system conforms Standard Specification defined Philips.
IEBus trademarks Corporation. MS-DOS Windows either registered trademarks trademarks Microsoft Corporation United States and/or other countries. DOS, PC/AT, trademarks International Business Machines Corporation. HP9000 series 300, HP9000 series 700, HP-UX trademarks Hewlett-Packard Company. SPARCstation trademark SPARC International, Inc. SunOS trademark Microsystems, Inc. NEWS NEWS-OS trademarks SONY Corporation.
export this product from Japan regulated Japanese government. export this product prohibited without governmental licence, need which must judged customer. export reexport this product from country other than Japan also prohibited without licence from country. Please call sales representative.
part this document copied reproduced form means without prior written consent Corporation. Corporation assumes responsibility errors which appear this document. Corporation does assume liability infringement patents, copyrights other intellectual property rights third parties arising from device described herein other liability arising from such device. license, either express, implied otherwise, granted under patents, copyrights other intellectual property rights Corporation others. While Corporation been making continuous effort enhance reliability semiconductor devices, possibility defects cannot eliminated entirely. minimize risks damage injury persons property arising from defect semiconductor device, customers must incorporate sufficient safety measures design, such redundancy, fire-containment, anti-failure features. devices classified into following three quality grades: "Standard", "Special", "Specific". Specific quality grade applies only devices developed based customer designated "quality assurance program" specific application. recommended applications device depend quality grade, indicated below. Customers must check quality grade each device before using particular application. Standard: Computers, office equipment, communications equipment, test measurement equipment, audio visual equipment, home electronic appliances, machine tools, personal electronic equipment industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment medical equipment (not specifically designed life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems medical equipment life support, etc. quality grade devices "Standard" unless otherwise specified NEC's Data Sheets Data Books. customers intend devices applications other than those specified Standard quality grade, they should contact sales representative advance. Anti-radioactive design implemented this product.
96.5

µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y 8-BIT SINGLE-CH

Top Searches for this datasheet

Other recent searches