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G522-0291-00
MPCBUSIF/AD 3/97 REV.
PowerPC Microprocessor Family:
Interface 32-Bit Microprocessors
Motorola Inc. 1997. rights reserved. Portions hereof International Business Machines Corp. 1991-1997. rights reserved. This document contains information product under development Motorola IBM. Motorola reserve right change discontinue this product without notice. Information this document provided solely enable system software implementers PowerPC microprocessors. There express implied copyright patent licenses granted hereunder Motorola design, modify design fabricate circuits based information this document. PowerPC microprocessor embodies intellectual property Motorola IBM. However, neither Motorola assumes responsibility liability aspects performance, operation, other attributes microprocessor marketed other party third party. Neither Motorola considered agent representative other, neither assumed, created, granted hereby right authority other, third party, assume create express implied obligations behalf. Information such errata sheets data sheets, well sales terms conditions such prices, schedules, support, product vary between parties selling product. Accordingly, customers wishing learn more information about products marketed given party should contact that party. Both Motorola reserve right modify this document and/or products described herein without further notice. NOTHING THIS DOCUMENT, ERRATA SHEETS, DATA SHEETS, OTHER SUPPORTING DOCUMENTATION, SHALL INTERPRETED CONVEYANCE MOTOROLA EXPRESS WARRANTY KIND IMPLIED WARRANTY, REPRESENTATION, GUARANTEE REGARDING MERCHANTABILITY FITNESS PRODUCTS PARTICULAR PURPOSE. Neither Motorola assumes liability obligation damages kind arising application these materials. warranty other obligations products described herein shall undertaken solely marketing party customer, under separate sale agreement between marketing party customer. absence such agreement, liability assumed Motorola, IBM, marketing party damages, actual otherwise. "Typical" parameters vary different applications. operating parameters, including "Typicals," must validated each customer application customer's technical experts. Neither Motorola convey license under their respective intellectual property rights rights others. Neither Motorola makes claim, warranty, representation, express implied, that products described this document designed, intended, authorized components systems intended surgical implant into body, other applications intended support sustain life, other application which failure product could create situation where personal injury death occur. Should customer purchase products such unintended unauthorized application, customer shall indemnify hold Motorola their respective officers, employees, subsidiaries, affiliates, distributors harmless against claims, costs, damages, expenses, reasonable attorney's fees arising directly indirectly, claim personal injury death associated with such unintended unauthorized use, even such claim alleges that Motorola negligent regarding design manufacture part. Motorola registered trademarks Motorola, Inc. Motorola, Inc. Equal Opportunity/Affirmative Action Employer.
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Overview Signal Descriptions Memory Access Protocol Memory Coherency System Status Signals Additional Configurations Direct-Store Interface System Considerations Processor Summary Processor Clocking Overview Processor Upgrade Suggestions Considerations PowerPC Processor Coherency Action Tables Glossary Terms Abbreviations Index
Overview Signal Descriptions Memory Access Protocol Memory Coherency System Status Signals Additional Configurations Direct-Store Interface System Considerations Processor Summary Processor Clocking Overview Processor Upgrade Suggestions Considerations PowerPC Processor Coherency Action Tables Glossary Terms Abbreviations Index
CONTENTS
Paragraph Number Title Page Number
About This Document
Audience Organization. Suggested Reading. xvii Conventions Acronyms Abbreviations Chapter
Overview
PowerPC Microprocessor Interface PowerPC System Block Diagram Processor Features Interface Signals Chapter
Signal Descriptions
2.1.1 2.1.2 2.1.3 2.1.4 2.2.1 2.2.2 2.2.3 2.2.4 2.3.1 2.3.2 2.3.3 2.3.4 2.3.5 Address Arbitration Signals. Request (BR)-Output Grant (BG)-Input Address Busy (ABB)-Output Address Busy (ABB)-Input. Address Transfer Start Signals. Transfer Start (TS)-Output Transfer Start (TS)-Input. Extended Address Transfer Start (XATS)-Output (Direct-Store). Extended Address Transfer Start (XATS)-Input (Direct-Store) Address Transfer Signals Address (A[0-31])-Output (Memory Operations). Address (A[0-31])-Input (Memory Operations) Address (A[0-31])-Output (Direct-Store Operations). Address (A[0-31])-Input (Direct-Store Operations) Address Parity (AP[0-3])-Output
Contents
CONTENTS
Paragraph Number 2.3.6 2.3.7 2.4.1 2.4.2 2.4.3 2.4.4 2.4.5 2.4.6 2.4.7 2.4.8 2.4.9 2.4.10 2.4.11 2.4.12 2.4.13 2.5.1 2.5.2 2.5.3 2.5.4 2.5.5 2.6.1 2.6.2 2.6.3 2.6.4 2.7.1 2.7.2 2.7.3 2.7.4 2.7.5 2.7.6 2.8.1 2.8.2 2.8.3 2.9.1 2.9.2 2.9.3 2.9.4 Title Page Number
Address Parity (AP[0-3])-Input .2-7 Address Parity Error (APE)-Output .2-8 Address Transfer Attribute Signals .2-8 Transfer Type (TT[0-4])-Output .2-8 Transfer Type (TT[0-4])-Input.2-9 Transfer Burst (TBST)-Output.2-10 Transfer Burst (TBST)-Input .2-10 Transfer Size (TSIZ[0-2])-Output.2-10 Transfer Size (TSIZ[0-2])-Input .2-11 Transfer Code (TCn)-Output .2-11 Cache Inhibit (CI)-Output .2-15 Write-Through (WT)-Output.2-16 Global (GBL)-Output .2-16 Global (GBL)-Input .2-16 Cache Element (CSEn)-Output.2-17 High-Priority Snoop Request (HP_SNP_REQ)-601 Only .2-17 Address Transfer Termination Signals .2-17 Address Acknowledge (AACK)-Input.2-17 Address Retry (ARTRY)-Output.2-18 Address Retry (ARTRY)-Input .2-19 Shared (SHD)-Output.2-19 Shared (SHD)-Input .2-19 Data Arbitration Signals.2-20 Data Grant (DBG)-Input.2-20 Data Write Only (DBWO)-Input .2-21 Data Busy (DBB)-Output .2-21 Data Busy (DBB)-Input .2-22 Data Transfer Signals .2-22 Data (DH[0-31], DL[0-31])-Output .2-22 Data (DH[0-31], DL[0-31])-Input.2-23 Data Parity (DP[0-7])-Output .2-23 Data Parity (DP[0-7])-Input.2-24 Data Parity Error (DPE)-Output.2-24 Data Disable (DBDIS)-Input .2-24 Data Transfer Termination Signals.2-25 Transfer Acknowledge (TA)-Input.2-25 Data Retry (DRTRY)-Input .2-25 Transfer Error Acknowledge (TEA)-Input.2-26 System Status Signals.2-27 Interrupt (INT)-Input.2-27 System Management Interrupt (SMI)-Input .2-27 Machine Check Interrupt (MCP)-Input.2-28 Checkstop Input (CKSTP_IN)-Input .2-28
PowerPC Microprocessor Family: Interface 32-Bit Microprocessors
CONTENTS
Paragraph Number 2.9.5 2.9.6 2.9.7 2.10 2.10.1 2.10.2 2.10.3 2.10.4 2.11 2.11.1 2.11.2 2.11.3 2.11.4 2.11.5 2.11.6 2.11.7 2.11.7.1 2.11.7.2 2.11.7.3 2.12 Title Page Number
Checkstop Output (CKSTP_OUT)-Output.2-28 Hard Reset (HRESET)-Input .2-29 Soft Reset (SRESET)-Input.2-29 Processor State Signals.2-29 Reservation (RSRV)-Output.2-29 External Cache Intervention (L2_INT)-Input .2-30 Time Base Enable (TBEN)-Input.2-30 TLBI Synchronization (TLBISYNC)-Input .2-30 Power Management Signals .2-31 Quiescent Request (QUIESC_REQ)-Output.2-31 System Quiesced (SYS_QUIESC)-Input .2-31 Resume (RESUME)-Input.2-31 Quiescent Request (QREQ)-Output.2-32 Quiescent Acknowledge (QACK)-Input .2-32 Halted (HALTED)-Output .2-32 (RUN)-Input.2-32 Going from Normal Doze State (604e).2-33 Going from Doze State.2-33 Going from Doze State.2-34 Summary Signal Differences .2-34 Chapter
Memory Access Protocol
3.1.1 3.1.2 3.2.1 3.2.2 3.2.2.1 3.2.2.2 3.2.2.2.1 3.2.2.2.2 3.2.2.3 3.2.2.4 3.2.2.4.1 3.2.3 3.3.1 3.3.1.1 Protocol .3-2 Arbitration Signals .3-4 Address Pipelining Split-Bus Transactions.3-5 Address Tenure .3-6 Address Arbitration.3-6 Address Transfer .3-8 Address Parity.3-9 Address Transfer Attribute Signals.3-9 Transfer Type (TT[0-4]) Signals.3-9 Transfer Size (TSIZ[0-2]) Signals.3-9 Burst Ordering during Data Transfers .3-10 Effect Alignment Data Transfers.3-10 Alignment External Control Instructions.3-17 Address Transfer Termination .3-17 Data Tenure.3-19 Data Arbitration .3-19 Effect ARTRY Assertion Data Transfer Arbitration PowerPC Processor .3-20
Contents
CONTENTS
Paragraph Number 3.3.1.2 3.3.2 3.3.3 3.3.4 3.3.4.1 3.3.4.2 Title Page Number Using Signal .3-21 Data Write Only .3-22 Data Transfer .3-22 Data Transfer Termination .3-23 Normal Single-Beat Termination .3-24 Data Transfer Termination Error .3-26 Timing Examples.3-28 Chapter
Memory Coherency
4.1.1 4.1.2 4.1.3 4.1.4 4.1.5 4.5.1 4.5.2 4.5.3 4.6.1 4.6.2 4.6.2.1 4.7.1 4.7.2 4.7.3 4.7.4 4.7.5 4.7.6 4.7.7 4.7.8 4.7.9 4.7.10 4.7.11 4.7.12 4.7.13 Overview Cache Implementations .4-1 PowerPC Processor Cache Organization.4-2 PowerPC Processor Cache Organization.4-3 PowerPC 603e Processor Cache Enhancements .4-3 PowerPC Processor Cache Organization.4-4 PowerPC 604e Processor Cache Enhancements .4-5 Cache Coherency Overview .4-5 Memory Coherency-MESI Protocol .4-6 Coherency Timing .4-9 Coherency Protocol .4-9 PowerPC Processor lwarx/stwcx. Implementation.4-11 Cache Element Signals.4-11 Address Retry Sources .4-11 Memory Coherency Actions-PowerPC Processor-Initiated Operations.4-12 Cache Control Instructions .4-12 Invalidate Entry Instruction Processing .4-14 TLBIE Operation .4-14 Descriptions Transactions Snoop Responses .4-14 General Comments Snooping.4-14 Clean Block .4-15 Flush Block.4-15 Write with Flush, Write with Flush Atomic.4-15 Kill Block .4-15 Write with Kill.4-16 Read, Read Atomic.4-16 Read with Intent Modify (RWITM).4-16 Invalidate.4-16 SYNC .4-17 TLBSYNC.4-17 EIEIO.4-17 ICBI .4-18
PowerPC Microprocessor Family: Interface 32-Bit Microprocessors
CONTENTS
Paragraph Number 4.7.14 4.7.15 4.10 Title Page Number
Read with Intent Cache (RWNITC).4-18 XFERDATA .4-18 External Settings.4-19 Direct-Memory Access Memory Coherency.4-19 Overview Implementation Differences.4-19 Chapter
System Status Signals
5.2.1 5.2.1.1 5.2.2 5.2.2.1 5.2.2.2 5.2.2.3 5.2.2.4 5.3.1 5.3.2 5.3.2.1 5.3.2.2 5.3.2.2.1 5.3.2.3 5.3.2.4 5.3.2.5 5.3.2.5.1 5.3.2.5.2 5.4.1 5.4.2 Overview .5-1 Resets .5-2 Hard Reset Power-On Reset.5-3 Hard Reset Settings .5-3 Soft Reset .5-5 System Reset Exception (0x00100) .5-5 Soft Reset PowerPC Microprocessor .5-6 Soft Reset PowerPC Microprocessor .5-7 Soft Reset PowerPC Microprocessor .5-7 Machine Check Checkstops .5-7 Checkstop State (MSR[ME] 0).5-7 Machine Check Exception (0x00200).5-8 Machine Check Exception (0x00200)- PowerPC Processor .5-9 Checkstop State (MSR[ME] 0)-PowerPC Processor .5-10 Checkstop Sources Enables Register-HID0 .5-10 Machine Check Exception-PowerPC Processor.5-12 Checkstop State (MSR[ME] 0)-PowerPC Processor .5-13 Machine Check Exception-PowerPC Processor.5-13 Machine Check Exception Enabled (MSR[ME] .5-14 Checkstop State (MSR[ME] 0).5-14 External Interrupt Exception (0x00500) .5-14 External Interrupt-PowerPC Processor.5-15 External Interrupt-PowerPC Processor.5-16 System Management Interrupt Exception (0x01400) .5-16 Chapter
Additional Configurations
6.1.1 6.2.1 No-DRTRY Mode (603 604e).6-1 No-DRTRY Mode PowerPC 604e Processor .6-2 Data Streaming Mode (604).6-3 Data Valid Window Data Streaming Mode .6-3
Contents
CONTENTS
Paragraph Number 6.2.2 6.2.3 Title Page Number
Data Valid Window Data Streaming Mode.6-3 Design Practices Data Streaming Mode .6-4 32-Bit Data Mode (603) .6-4 Reduced-Pinout Mode (603) .6-6 Chapter
Direct-Store Interface
7.1.1 7.1.2 7.1.3 Direct-Store Transaction Protocol Details.7-2 Packet .7-3 Packet .7-4 Reply Operations.7-4 Direct-Store Operations.7-6 Store Operations .7-7 Load Operations .7-7 Direct-Store Operation Timing.7-8 Memory-Forced Direct-Store Interface (PowerPC Processor Only).7-9 Chapter
System Considerations
8.7.1 8.8.1 8.8.1.1 8.8.1.2 8.8.1.3 8.8.1.4 8.8.1.5 8.8.1.6 8.8.2 8.8.2.1 8.8.2.2 Arbitration .8-1 Using Data Write-Only Mechanism.8-1 AACK Generation .8-4 SYNC TLBSYNC System Design.8-4 Pull-Up Resistors.8-5 Features Improved Performance.8-5 IEEE 1149.1-Compliant Interface .8-5 IEEE 1149.1 Interface Description.8-5 lwarx/stwcx. Considerations.8-6 Coherency Participation .8-6 Noncacheable Reservations.8-6 Cacheable Reservations.8-7 Read Snooping Requirements .8-7 Write-Back Reservation-Canceling Snoops .8-7 Write-Through Reservation-Canceling Snoops .8-8 Noncanceling Operations .8-8 Filtering Options Reservations .8-8 Minimal Reservation Support .8-8 Improved Reservation Snooping .8-9
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PowerPC Microprocessor Family: Interface 32-Bit Microprocessors
CONTENTS
Paragraph Number 8.8.2.3 8.8.2.4 Title Page Number
lwarx/stwcx. Address-Only Operation.8-10 Software Implications .8-10 Appendix
Processor Summary
Appendix
Processor Clocking Overview
PowerPC Microprocessor Clocking PowerPC PowerPC Microprocessor Clocking Appendix
Processor Upgrade Suggestions
PowerPC Processor Upgrade PowerPC Processor Upgrade PowerPC Processor Upgrade Appendix
Considerations PowerPC Processor
D.2.1 D.2.2 D.2.3 D.3.1 D.3.2 D.3.3 D.4.1 D.4.2 D.4.3 D.5.1 D.5.2 D.5.3 Unfiltered Snooping Keeping Copy Tags Requirements Saving State Information. Operations Required Processor Operations. Forwarding System Operations Processor Maintaining State Tags Requirements Saving State Information. Operations Required Processor Operations. Forwarding System Operations Processor Simple Inclusion Requirements Saving State Information. Operations Required Processor Operations. Forwarding System Operations Processor Marked Inclusion Requirements Saving State Information. Operations Required Processor Operations. Forwarding System Operations Processor
Contents
CONTENTS
Paragraph Number Title Appendix Page Number
Coherency Action Tables
E.10 E.11 E.12 E.13 E.14 E.15 E.16 E.17 E.18 E.19 E.20 E.21 E.22 E.23 E.24 E.25 E.26 E.27 E.28 E.29 E.30 E.31 Load Operations Store Operations LWARX Operations STWCX Operations. E-11 DCBT Operations E-17 DCBTST Operations E-20 DCBZ Operations E-21 DCBST Operations. E-23 DCBF Operations E-27 DCBI Operations E-31 ICBI Operations. E-34 SYNC Operations E-36 EIEIO Operations E-37 TLBIE Operations E-37 TLBSYNC Operations E-37 Snoop-Kill Operations. E-38 Snoop-Read Operations. E-39 Snoop-Read-Atomic Operations. E-40 Snoop-RWIOperations E-41 Snoop-RWITM-Atomic Operations E-41 Snoop-Flush Operations E-42 Snoop-Clean Operations. E-42 Snoop-Write-with-Flush Operations E-43 Snoop-Write-with-Kill Operations E-44 Snoop-Write-with-Flush-Atomic Operations E-45 Snoop-TLB-Invalidate Operations E-46 Snoop-SYNC Operations E-46 Snoop-EIEIO Operations. E-46 Snoop-TLBSYNC Operations. E-47 Snoop-ICBI Operations E-47 Snoop-RWNITC Operations E-48
Glossary Terms Abbreviations Index
PowerPC Microprocessor Family: Interface 32-Bit Microprocessors
ILLUSTRATIONS
Figure Number Title Page Number
3-10 3-11 3-12 3-13 3-14 3-15 3-16 3-17 3-18 3-19
Illustrations
Typical System Diagram with Processor Bus. Processor Signals Timing Diagram Legend. Overlapping Tenures Processor Single-Beat Transfer Address Arbitration Showing Qualified Grant. Address Arbitration Showing Parking. Address Transfer. Snooped Address Cycle with ARTRY 3-18 Data Arbitration 3-19 Qualified Generation Following ARTRY 3-21 Normal Single-Beat Read Termination 3-24 Normal Single-Beat Write Termination. 3-24 Normal Burst Transaction. 3-25 Termination with DRTRY. 3-25 Read Burst with Wait States DRTRY 3-26 Fastest Single-Beat Reads. 3-28 Fastest Single-Beat Writes. 3-29 Single-Beat Reads Showing Data-Delay Controls 3-30 Single-Beat Writes Showing Data Delay Controls. 3-31 Burst Transfers with Data Delay Controls. 3-32 Transfer Error Acknowledge (TEA) 3-33 PowerPC Processor Cache Organization PowerPC Processor Cache Organization PowerPC Processor Cache Organization PowerPC 604e Processor Cache Organization MESI States MESI Cache Coherency Protocol (601/604)-State Diagram (WIM 001). Cache Coherency Protocol (603)-State Diagram (WIM 001) 4-10 Effective Address Bits Address. 4-17 HID0-Checkstop Sources Enables Register (601) 5-10 Data Transfer Data Streaming Mode 32-Bit Data Transfer (Eight-Beat Burst) 32-Bit Data Transfer (Two-Beat Burst with DRTRY) Direct-Store Interface Protocol Tenures Direct-Store Operation-Packet Direct-Store Operation-Packet
ILLUSTRATIONS
Figure Number Page Number Reply Operation. Direct-Store Interface Load Access Example. Direct-Store Interface Store Access Example. Data Write Only Transaction. PowerPC Processor Clocking .B-1 PowerPC PowerPC Processor Clock Generation.B-2 PowerPC PowerPC Processor Upgrade Option.C-2 Cache Controller Organization. Title
PowerPC Microprocessor Family: Interface 32-Bit Microprocessors
TABLES
Table Number Title Page Number
5-10
Tables
Acronyms Abbreviated Terms. Signal Groupings Reference Signals. Transfer Encoding PowerPC 601, 603, Processors. Data Transfer Size. 2-11 Transfer Code Signal Encoding PowerPC Processor. 2-12 Transfer Code Signal Encoding PowerPC Processor. 2-12 Transfer Code Signal Encoding PowerPC Processor. 2-13 Data Lane Assignments 2-23 DP[0-7] Signal Assignments. 2-23 Processor Signal Differences. 2-34 Number Arbitration Signals Processor Read Burst Ordering. 3-10 Aligned Data Transfers 64-Bit Data 3-11 Aligned Data Transfers 32-Bit Data 3-12 Misaligned Data Transfers PowerPC Processor. 3-13 Misaligned Data Transfers PowerPC 603/ Processors. 3-14 Misaligned Data Transfers 32-Bit Mode. 3-16 MESI State Definitions CSE[0-1] Signals. 4-11 Memory Coherency Actions Load Operations 4-12 Memory Coherency Actions Store Operations 4-12 PowerPC Processor Operations Initiated Cache Control Instructions 4-13 PowerPC Operations Initiated Cache Control Instructions 4-13 Differences Implementation Operations 4-20 Resets, Interrupts, Their Sources Processor Signal Differences. Hard Reset Settings. PowerPC 604e Processor Modes Configurable during HRESET. System Reset Exception-Register Settings Machine Check Exception-Register Settings. HID0-Checkstop Sources Enables Register (601) 5-11 Machine Check Enable Bits. 5-13 External Interrupt-Register Settings. 5-15 System Management Interrupt-Register Settings. 5-16
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TABLES
Table Number E-10 E-11 E-12 E-13 E-14 E-15 E-16 E-17 E-18 E-19 E-20 E-21 E-22 E-23 E-24 E-25 E-26 E-27 E-28 E-29 E-30 E-31 E-32 Title Page Number
Address Bits Packet Address Bits Reply Operations. Direct-Store Operations Extended Address Transfer Code Definitions IEEE Interface Signal Descriptions Transfer Type Settings lwarx/stwcx. Address-Only Operation 8-10 Memory Coherency Behavior Summary Operations Required Processor Operations Guide Abbreviations .E-1 Coherency Actions-Load Operations .E-2 Coherency Actions-Store Operations.E-5 Coherency Actions-LWARX Operations.E-8 Coherency Actions-STWCX Operations .E-11 Coherency Actions-DCBT Operations.E-17 Coherency Actions-DCBTST Operations.E-20 Coherency Actions-DCBZ Operations.E-22 Coherency Actions-DCBST Operations .E-23 Coherency Actions-DCBF Operations.E-27 Coherency Action-DCBI Operations .E-31 Coherency Actions-ICBI Operations .E-34 Coherency Actions-SYNC Operations.E-36 Coherency Actions-EIEIO Operations.E-37 Coherency Actions-TLBIE Operations.E-37 Coherency Actions-TLBSYNC Operations .E-37 Coherency Actions-Snoop-Kill Operations .E-38 Coherency Actions-Snoop-Read Operations .E-39 Coherency Actions-Snoop-Read Atomic Operations .E-40 Coherency Coherency Actions-Snoop-RWIAtomic Operations.E-41 Coherency Actions-Snoop-Flush Operations.E-42 Coherency Actions-Snoop-Clean.E-42 Coherency Actions-Snoop-Write-with-Flush Operations.E-43 Coherency Actions-Snoop-Write-with-Kill Operations.E-44 Coherency Operations.E-45 Coherency Actions-Snoop-TLB-Invalidate Operations.E-46 Coherency Actions-Snoop-SYNC Operations .E-46 Coherency Actions-Snoop-EIEIO Operations .E-46 Coherency Actions-Snoop-TLBSYNC Operations .E-47 Coherency Actions-Snoop-ICBI Operations.E-47 Coherency Actions-Snoop-RWNITC Operations.E-48
PowerPC Microprocessor Family: Interface 32-Bit Microprocessors
About This Document
primary objective this document provide detailed functional description interface, implemented PowerPC 601TM, PowerPC 603TM, PowerPC 604family PowerPCmicroprocessors. This document intended help system chip developers providing centralized reference source identify interface presented family PowerPC microprocessors. This document should used conjunction with individual microprocessors' user's manuals, hardware specifications, PowerPC Microprocessor Family: Programming Environments (referred Programming Environments Manual). communication channel first generation PowerPC microprocessors. This description documents current operations system implementation information following PowerPC processors: PowerPC processor. first PowerPC processor designed desktop, server, workstation implementations designed support implementation multiprocessing systems. PowerPC processors. References include PowerPC 603eprocessors unless otherwise specified. family processors optimized implementation low-power systems, includes support power management, provides less support multiprocessing than either families processors. PowerPC processors. References include PowerPC 604eprocessors unless specified otherwise. family processors designed implementation desktop, workstation, server systems provides extensive support both multiprocessing power management.
Although this book used general guide PowerPC 602processor, some other 32-bit PowerPC processors, does include descriptions operations unique that processor. these processors support 32-bit addressing, provide separate address data buses. provide 64-bit data buses, some allow option configuring data work optional 32-bit mode.
About This Document
allows processors access otherwise communicate with other resources that share bus, including system memory, secondary caches, devices, arbiters, other devices. large, implementation consistent among 601, 603, 604; however, because PowerPC architecture supports broad range system implementations, each processor offers unique features. Primary goals this book provide reader with understanding operations basic signals that common required processors well familiarity with those signals that common parts required basic operation that maximize performance system implementation. this understanding, this document focuses following relationships among current microprocessors: General characteristics Common characteristics Differences between current implementations
This document specifically describes communication signals protocols used 601, 603, 604, does describe power, test, clock signals. that information, refer particular microprocessor user's manual. this document, terms `601', `603', `603e' `604', `604e', `60x bus' used abbreviations `PowerPC microprocessor', `PowerPC microprocessor', PowerPC 603e microprocessor', `PowerPC microprocessor', PowerPC 604e microprocessor', `PowerPC microprocessor interface', respectively. terms `processor interface' `interface' analogous with bus. locate published errata updates this document, refer world-wide http://www.mot.com/powerpc/
Audience
This document intended system processor hardware developers developing products that incorporate interface with microprocessors. also benefit software developers work with products that these microprocessors.
Organization
Following summary brief description major sections this manual: Chapter "Overview," useful readers wanting general understanding features functions PowerPC processor interface. defines various operational subsets these features functions. Chapter "Signal Descriptions," describes each processor input output signal gives timing considerations.
PowerPC Microprocessor Family: Interface 32-Bit Microprocessors
Chapter "Memory Access Protocol," describes operation processor interface memory operations. Chapter "Memory Coherency," describes features protocols maintaining coherency uniprocessor multiprocessor systems. Chapter "System Status Signals," describes operation interrupt, checkstop, reset signals. also includes brief overview asynchronous exceptions, with particular attention given differences processors implement those exceptions. Chapter "Additional Configurations," describes some alternate modes available bus. Chapter "Direct-Store Interface, describes optional direct-store interface synchronous I/O. Chapter "System Considerations," gives useful information designing systems that processor bus. Appendix "Processor Summary," summarizes processor objectives table comparing processor behavior. Appendix "Processor Clocking Overview," describes clocking 601, 603, 604. Appendix "Processor Upgrade Suggestions," describes considerations systems designed allow processor upgrade. Appendix Considerations PowerPC Processor," gives useful information those implementing cache system with 604. Appendix "Coherency Action Tables," provides comprehensive table coherency actions that generated response various operations different contexts such settings, cache state, states.
Suggested Reading
This section lists additional reading that provides background information this manual well general information about PowerPC architecture.
General Information
following documentation provides useful information about PowerPC architecture computer architecture general: following books available from Morgan-Kaufmann Publishers, Pine Street, Sixth Floor, Francisco, 94104; Tel. (800) 745-7323 (U.S.A.), (415) 392-2665 (International); internet address: mkp@mkp.com. PowerPC Architecture: Specification Family RISC Processors, Second Edition, International Business Machines, Inc. Updates architecture specification accessible world-wide
About This Document xvii
PowerPC Microprocessor Common Hardware Reference Platform: System Architecture, Apple Computer, Inc., International Business Machines, Inc., Motorola, Inc. Macintosh Technology Common Hardware Reference Platform, Apple Computer, Inc. Computer Architecture: Quantitative Approach, Second Edition, John Hennessy David Patterson Inside Macintosh: PowerPC System Software, Addison-Wesley Publishing Company, Jacob Way, Reading, 01867; Tel. (800) 282-2732 (U.S.A.), (800) 637-0029 (Canada), (716) 871-6555 (International) PowerPC Programming Intel Programmers, McClanahan; Books Worldwide, Inc., East Hillsdale Boulevard, Suite 400, Foster City, 94404; Tel. (800) 434-3422 (U.S.A.), (415) 655-3022 (International)
PowerPC Documentation
PowerPC documentation organized following types documents: User's manuals-These books provide details about individual PowerPC implementations intended used conjunction with Programming Environments Manual. These include following: PowerPC 601RISC Microprocessor User's Manual: MPC601UM/AD (Motorola order 52G7484/(MPR601UMU-02) (IBM order PowerPC 602RISC Microprocessor User's Manual: MPC602UM/AD (Motorola order MPR602UM-01 (IBM order PowerPC 603eRISC Microprocessor User's Manual with Supplement PowerPC Microprocessor: MPC603EUM/AD (Motorola order MPR603EUM-01 (IBM order PowerPC 604RISC Microprocessor User's Manual: MPC604UM/AD (Motorola order MPR604UMU-01 (IBM order Programming environments manuals-These books provide information about resources defined PowerPC architecture that common PowerPC processors. There versions, that describes functionality combined 64-bit architecture models that describes only 32-bit model. PowerPC Microprocessor Family: Programming Environments, MPCFPE/AD (Motorola order G522-0290-00 (IBM order PowerPC Microprocessor Family: Programming Environments 32-Bit Microprocessors, Rev. MPCFPE32B/AD (Motorola order Implementation Variances Relative Rev. Programming Environments Manual available world-wide http://www.mot.com/powerpc/
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PowerPC Microprocessor Family: Interface 32-Bit Microprocessors
Addenda/errata user's manuals-Because some processors have follow-on parts addendum provided that describes additional features changes functionality follow-on part. These addenda intended with corresponding user's manuals. These include following: Addendum PowerPC 603e RISC Microprocessor User's Manual: PowerPC 603e Microprocessor Supplement User's Manual Errata: MPC603EUMAD/AD (Motorola order SA14-2034-00 (IBM order Addendum PowerPC RISC Microprocessor User's Manual: PowerPC 604eMicroprocessor Supplement User's Manual Errata: MPC604UMAD/AD (Motorola order SA14-2056-01 (IBM order Hardware specifications-Hardware specifications provide specific data regarding timing, signal behavior, thermal characteristics, well other design considerations each PowerPC implementation. These include following: PowerPC RISC Microprocessor Hardware Specifications: MPC601EC/D (Motorola order MPR601HSU-03 (IBM order PowerPC RISC Microprocessor Hardware Specifications: MPC602EC/D (Motorola order SC229897-00 (IBM order PowerPC RISC Microprocessor Hardware Specifications: MPC603EC/D (Motorola order G522-0289-00 (IBM order PowerPC 603e RISC Microprocessor Family: PID6-603e Hardware Specifications: MPC603EEC/D (Motorola order G522-0268-00 (IBM order PowerPC 603e RISC Microprocessor Family: PID7V-603e Hardware Specifications: MPC603E7VEC/D (Motorola order G522-0267-00 (IBM order PowerPC RISC Microprocessor Hardware Specifications: MPC604EC/D (Motorola order MPR604HSU-02 (IBM order PowerPC 604e RISC Microprocessor Family: PID9V-604e Hardware Specifications: MPC604E9VEC/D (Motorola order SA14-2054-00 (IBM order
Technical Summaries-Each PowerPC implementation technical summary that provides overview features. This document roughly equivalent overview (Chapter implementation's user's manual. Technical summaries available 601, 602, 603, 603e, 604, 604e well following: PowerPC 620RISC Microprocessor Technical Summary: MPC620/D (Motorola order SA14-2069-01 (IBM order
About This Document
PowerPC Microprocessor Family: Programmer's Reference Guide concise reference that includes register summary, memory control model, exception vectors, PowerPC instruction set. MPCPRG/D (Motorola order MPRPPCPRG-01 (IBM order PowerPC Microprocessor Family: Programmer's Pocket Reference Guide: This foldout card provides overview PowerPC registers, instructions, exceptions 32-bit implementations. MPCPRGREF/D (Motorola order SA14-2093-00 (IBM order Application notes-These short documents contain useful information about specific design issues useful programmers engineers working with PowerPC processors. Documentation support chips-These include following: MPC105 Bridge/Memory Controller User's Manual: MPC105UM/AD (Motorola order MPC106 Bridge/Memory Controller User's Manual: MPC106UM/AD (Motorola order
Additional literature PowerPC implementations being released processors become available. current list PowerPC documentation, refer world-wide http://www.mot.com/powerpc/
Conventions
This document uses following notational conventions: ACTIVE_HIGH ACTIVE_LOW Names signals that active high shown uppercase text without overbar. over signal name indicates that signal active low-for example, ARTRY (address retry) (transfer start). Active-low signals referred asserted (active) when they negated when they high. Signals that active low, such AP[0-3] (address parity signals) TT[0-4] (transfer type signals) referred asserted when they high negated when they low. This prefix used distinguish signals coming from system from processor that otherwise have same name. Instruction mnemonics shown lowercase bold. Address-only operations that named instructions that generate them identified uppercase letters, example, ICBI, SYNC, TLBSYNC, EIEIO operations. Italics indicate variable command parameters, example, bcctrx Prefix denote hexadecimal number Prefix denote binary number
PowerPC Microprocessor Family: Interface 32-Bit Microprocessors
SYS- SYS-) mnemonics OPERATIONS
italics
rA|0 frA, frB, REG[FIELD]
Instruction syntax used identify source contents specified value Instruction syntax used identify destination Instruction syntax used identify source Instruction syntax used identify destination Abbreviations acronyms registers shown uppercase text. Specific bits, fields, ranges appear brackets. example, MSR[LE] refers little-endian mode enable machine state register. certain contexts, such signal encoding, this indicates don't care. Used express undefined numerical value.
Acronyms Abbreviations
Table contains acronyms abbreviations that used this document.
Table Acronyms Abbreviated Terms
Term BIST BUID DABR DBAT DSISR DTLB Arithmetic logic unit Address space register Block address translation Built-in self test interface unit unit Common on-chip processor Condition register Count register Data address breakpoint register Data address register Data Decrementer (register) Register used determining source exception Data translation look-aside buffer Effective address External access register Error checking correction Meaning
About This Document
Table Acronyms Abbreviated Terms (Continued)
Term FIFO FPSCR HIDn IABR IBAT IEEE ITLB JTAG MESI MMCRn No-op PMCn Extended transfer protocol Exclusive state (includes shared, exclusive unmodified, First-in, first-out Floating-point register Floating-point status control register Floating-point unit General-purpose register Hardware implementation-dependent register Instruction address breakpoint register Instruction Institute Electrical Electronics Engineers Instruction translation look-aside buffer Joint Test Action Group Secondary cache Link register lwarx reservation Least recently used Least-significant byte Least-significant coherency protocol Monitor mode control register Memory management unit Most-significant byte Most-significant Machine state register number operation Operating environment architecture Processor identification Phase-locked loop Performance monitor control (register) Performance monitor interrupt Meaning
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PowerPC Microprocessor Family: Interface 32-Bit Microprocessors
Table Acronyms Abbreviated Terms (Continued)
Term PTEG RISC RWIRWITMA SBRA SDR1 SPRGn SRR0 SRR1 UISA WWFA XATC Page table entry Page table entry group Processor version register Read atomic Reduced instruction computing/computer Register transfer language Read with intent modify Read with intent modify atomic Single-beat read Single-beat read atomic Single-beat write Register that specifies page table base address virtual-to-physical address translation Segment lookaside buffer Special-purpose register Registers available general purposes Segment register (Machine status) save/restore register (Machine status) save/restore register Test access port controller Time base register Translation lookaside buffer User instruction architecture Virtual environment architecture Write with flush Write with flush atomic Write with kill Extended address transfer code Register used indicating conditions such carries overflows integer operations Meaning
About This Document
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PowerPC Microprocessor Family: Interface 32-Bit Microprocessors
Chapter Overview
This chapter gives overview interface common microprocessors. describes operation features this interface, lists microprocessor signals, shows differences between three microprocessors number signals, defines various operational subsets signals, particular identifies those that required system. This description documents current operations system implementation information following PowerPCprocessors: PowerPC 601processor. first PowerPC processor designed desktop, server, workstation implementations designed support implementation multiprocessing systems. PowerPC 603processors. References include PowerPC 603eprocessors unless otherwise specified. family processors optimized implementation low-power systems, includes support power management, provides less support multiprocessing than either families processors. PowerPC 604processors. References include PowerPC 604eprocessors unless otherwise specified. family processors designed implementation desktop, workstation, server systems provides extensive support both multiprocessing power management.
Although this book used general guide PowerPC 602processor, does include descriptions specific operations that unique that processor.
PowerPC Microprocessor Interface
601, 603, support range systems, including low-power notebook machines, low-cost desktop personal computers, high-performance workstations, multiprocessor server systems. meet those needs, interface these processors defined with minimum functions 32-bit 64-bit data modes, well optional performance function enhancement signals modes.
Chapter Overview
definition based Motorola 88110 definition. This interface runs synchronous system clock. Inputs sampled outputs driven from rising edge system clock. This processor provides transfer protocols: basic transfer protocol used access normal memory segments. This protocol supports transfer number 64-bit continuous bytes within aligned double word address 32-bit address range. also supports burst transfers multiple-beat transfers that transfer bits data during each beat. Direct-store operations (elsewhere referred extended transfer protocol, ETP) slightly different protocol accessing direct-store segments defined PowerPC architecture. This protocol provides extended address, support split transactions, positive reply each transaction. synchronous nature this protocol limits performance compared basic protocol, provides enhanced error recovery. This functionality considered optional PowerPC architecture supported PowerPC processors, example second generation processors family.
PowerPC architecture includes following: address space shared processing elements system weakly-ordered memory model that allows processors improve performance reordering loads stores explicit cache management translation lookaside buffer (TLB) management instructions that broadcast processor allow software control caches single- multiple-processor environment Instructions synchronizing operations between different processors
Each processor separate address data bus. basic transfer protocol, these separate buses used implement coupled address data tenures typical lowend personal computers, they used implement advanced features such address pipelining, which allows transaction begin before current transaction finished, split-bus transactions, which allows address data have separate masters same time. processor supports full write-back cache coherency, snooping, transaction retry, snoop copy-back operations, although should noted that each processor implement such features that some processors implement such features more sophisticated manner. defines signals that support access from multiple masters, including other processors devices, with arbitration provided system implementation.
PowerPC Microprocessor Family: Interface 32-Bit Microprocessors
PowerPC System Block Diagram
Figure shows processor typical system design. provides communications layer between more PowerPC processors, memory controller, system-provided arbiter, bridge expansion system I/O, optionally high-speed adaptor such graphics adaptor. processor component have external cache. This supports cache implementations that in-line lookaside that write-through write-back.
Processor Cache Processor Cache Memory Controller
Memory
Processor
Graphics Adaptor
System Arbiter
Bridge Expansion
System
Figure 1-1. Typical System Diagram with Processor
Processor Features
processor provides high performance adaptability various system environments. Features this include following: operation greater than with 601, 603, Maintenance coherency external cache Support split transactions Support pipelined transactions Support address-only transactions used primarily cache control Support multiprocessor configurations Optional performance enhancements
Note that processors family support available features.
Chapter Overview
Interface Signals
Figure shows PowerPC processor view signals. Signals that part basic shown solid lines. Those that optional provide enhanced functions performance shown dashed lines.
DBWO DH[0-31], DL[0-31] DP[0-7] DBDIS DRTRY CKSTP_IN CKSTP_OUT HRESET SRESET RSRV L2_INT TBEN TLBISYNC (Processor Specific) (Processor Specific)
Address Arbitration
XATS A[0-31]
Data Arbitration
Address Transfer Start
Data Transfer
Address Transfer
AP[0-3] TT[0-4] TBST TSIZ[0-2]
Data Transfer Termination
Address Transfer Attribute
CSEn HP_SNP_REQ AACK ARTRY
System Status
Address Transfer Termination
Processor State
Power Management
Figure 1-2. Processor Signals
PowerPC Microprocessor Family: Interface 32-Bit Microprocessors
signal groupings Figure described Table 1-1.
Table 1-1. Signal Groupings
Signal Group Address arbitration Address transfer start Address transfer Address transfer attribute Address transfer termination Data arbitration Data transfer Data transfer termination System status Processor state Power management Functionality Used arbitrate address Indicate that master begun transaction address Used transfer address ensure integrity transfer Provide information about type transfer Indicate address phase need repeat address phase Used arbitrate data mastership Used transfer data ensure integrity transfer Indicate data transfer that data phase should repeated Indicate interrupts system resets Used manage processor state Provide means processor system cooperate power management operations. specific signals each processor identified Table 1-2.
evolution processors target market processors dictated that some these signals supported some processors, have different counts, operate differently some processors. Those differences described Section 2.12, "Summary Signal Differences." Table briefly describes each signal function provides reference detailed description signal state meanings timing considerations Chapter "Signal Descriptions."
Table 1-2. Reference Signals
Application Signal Function Basic Opt. Address Arbitration Signals request (BR) grant (BG) Address busy (ABB) Requests mastership Indicates ownership properly qualified 2.1.1 2.1.2 2.1.3 2.1.4 Section
Indicates whether address busy
Address Transfer Start Signals Transfer start (TS) Extended transfer start (XATS) Indicates that master begun transaction memory Indicates that master begun transaction direct-store address 2.2.1 2.2.2 2.2.3 2.2.4
Chapter Overview
Table 1-2. Reference Signals (Continued)
Application Signal Function Basic Opt. Address Transfer Signals Address (A[0-31]) Address parity (AP[0-3]) Address parity error (APE) Indicates real address transaction Gives parity each address byte Indicates detection address parity error Address Transfer Attribute Signals Transfer type (TT[0-4]) Transfer burst (TBST) Transfer size (TSIZ[0-2]) Transfer code (TCn) Cache inhibit (CI) Write-through (WT) Global (GBL) Cache element (CSEn]) High-priority snoop request (HP_SNP_REQ) Indicates type transfer progress Indicates that burst transfer progress Indicates size bytes transfer progress Gives information about transaction external cache operations Indicates whether transfer cached Indicates whether transaction write-through Indicates that transaction global that data coherence required Represents cache replacement element current transaction only: Used indicate when reserved position write queue needed push operation resulting from snoop Address Transfer Termination Signals Address acknowledgment (AACK) Address retry (ARTRY) Shared (SHD) Indicates that address portion transaction complete 2.5.1 2.5.2 2.5.3 2.5.4 2.5.5 2.4.1 2.4.2 2.4.3 2.4.4 2.4.5 2.4.6 2.4.7 2.4.8 2.4.9 2.4.10 2.4.11 2.4.12 2.4.13 2.3.1- 2.3.4 2.3.5 2.3.6 2.3.7 Section
Asserted when address tenure must retried output, indicates master shared cache block. input, indicates incoming cache block should marked shared Data Arbitration Signals
Data grant (DBG) Data write only (DBWO)
Indicates master may, with proper qualification, assume ownership data Indicates outstanding write precede pipeline read
2.6.1 2.6.2
PowerPC Microprocessor Family: Interface 32-Bit Microprocessors
Table 1-2. Reference Signals (Continued)
Application Signal Function Basic Opt. Data busy (DBB) Indicates data busy Data Transfer Signals Data (DH[0-31];DL[0-31]) Data parity (DP[0-7]) Data parity error (DPE) Represents data being transferred Represents parity data bytes Forces processor data highimpedance state during write data tenure; other processor operations unaffected. Indicates processor that write transaction should stopped Data Transfer Termination Signals Transfer acknowledge (TA) Data retry (DRTRY) Indicates that single-beat data transfer completed successfully Invalidates read data sent processor with previous cycle. hard reset, used configure some alternate modes. Indicates that error occurred 2.8.1 2.8.2 2.7.1 2.7.2 2.7.3 2.7.4 2.7.5 2.6.4 Section
Data disable (DBDIS)
2.7.6
Transfer error acknowledgment (TEA)
2.8.3
System Status Signals Interrupt (INT) System management interrupt (SMI) Machine check (MCP) Checkstop input (CKSTP_IN) Checkstop output (CKSTP_OUT) Hard reset (HRESET) Soft reset (SRESET) Indicates external interrupt processor Indicates system management interrupt processor Indicates machine check exception Indicates processor must stop operation (checkstop) Indicates processor detected checkstop condition Initiates hard reset exception Initiates soft reset exception Processor State Signals Reservation (RSRV) External cache intervention (L2_INT) Time base enable (TBEN) Indicates that reservation generated lwarx instruction exists processor Indicates intervention from other masters Indicates time base should continue clocking 2.10.1 2.10.2 2.10.3 2.9.1 2.9.2 2.9.3 2.9.4 2.9.5 2.9.6 2.9.7
Chapter Overview
Table 1-2. Reference Signals (Continued)
Application Signal Function Basic Opt. TLBI synchronization (TLBISYNC) 603: Indicates execution should stop after tlbsync instruction Power Management Signals Quiescent request (QUIESC_REQ) System quiesced (SYS_QUIESC) Resume (RESUME) Quiescent request (QREQ) Quiescent acknowledge (QACK) Halted (HALTED) (RUN) 601: Indicates ready enter soft stop state 601: Indicates that system ready soft stop state 601: Indicates resume normal processing 603: Requests activity requiring snooping pause 603: Indicates activity that requires snooping paused 604: Indicates entered low-power state 604: Indicates keep snooping low-power state 2.11.1 2.11.2 2.11.3 2.11.4 2.11.5 2.11.6 2.11.7 2.10.4 Section
four columns under heading, `application' Table described follows: Basic operations-Signals column labeled `Basic' Table required build simple, uniprocessor system with bus, external cache, support pipelining. Within this signals, optional and, shown Table 3-1, used identify additional transactions that snooped. cache support-Signals `L2' column Table required support external cache. example, TC[0-2] necessary indicate type transaction. However, some these signals optional some system designs. instance, write-through external cache would need signal, cache that responds only burst operations would need signal. Multiprocessor support-The signals GBL, SHD, listed `MP' column, support memory coherency systems with masters other than processor including multiprocessor systems. Chapter "Memory Coherency," provides detailed information memory coherency. signal would used assign systems which shared multiple devices, which case signal would interconnected between devices ensure cache coherency. Optionally signals could connected bridge snooping. bridge would known state.
PowerPC Microprocessor Family: Interface 32-Bit Microprocessors
Enhanced operation-The signals `optional' column (labeled `Opt.') provide additional functions performance enhancements, including following: Address arbitration-The signal optional because derived from other signals masters refrain from taking address from beginning through AACK. Parity signals-Address data parity signals, AP[0-3], APE, DP[0-7], DPE, optional. Low-end low-cost systems, example some personal computers, check generate parity either addresses data. Highercost systems generate parity only data. High-end systems generate parity both addresses data processor-generated indications parity errors control other system components. Address pipeline-Separate data arbitration granting signals allow independent operation address data tenures. DBWO signal allows processor data tenure outstanding write address even read address pipelined before Data retry-The DRTRY signal used support speculative forwarding data. Interrupts-Some processors have additional system management interrupt addition hardware interrupt defined PowerPC architecture. This interrupt signaled asserting signal. Soft reset-The soft reset signal, SRESET, used initiate soft reset, type system reset that defined PowerPC architecture implemented most PowerPC processors. Power management-Some processors support QUIESC_REQ, SYS_QUIESC, RESUME, QREQ, QACK, RUN, HALTED signals control power consumption allowing power removed from certain portions processor when use. address translation-Because optimized low-power, uniprocessor systems, hardware support provided table search operations. Extended transfer start-The XATS signal supports direct-store accesses. Chapter "Direct-Store Interface," describes direct-store interface effect this protocol TT[0-4], TBST, TSIZ[0-2], A[0-31].
Chapter Overview
1-10
PowerPC Microprocessor Family: Interface 32-Bit Microprocessors
Chapter Signal Descriptions
This chapter describes external signals used PowerPC 601, PowerPC 603, PowerPC processors, identifying both signals that common processors well indicating characteristics individual processor implementations. contains concise description individual signals, showing behavior when signal asserted negated when signal input output. Note that descriptions this chapter intended provide quick summary signal functions. Subsequent chapters describe operation many these signals greater detail, both with respect individual signals function groups signals interact.
NOTE over signal name indicates that signal active low-for example, ARTRY (address retry) (transfer start). Active-low signals referred asserted (active) when they negated when they high. Signals that active low, such AP[0-3] (address parity signals) TT[0-4] (transfer type signals) referred asserted when they high negated when they low.
clock, power, test signals described this document. Refer user's manual particular processor this information. signal descriptions this chapter grouped categories shown Figure 1-2. section names this chapter correspond those groups defined Section 1.4, "Bus Interface Signals." sections describe state timing descriptions each signal indicate signal input output with respect PowerPC processor. signal both, output characteristics described first. description from perspective processor; attempt made describe these signals arbiter, slave, target would them. differences between signals implemented different processors summarized Section 2.12, "Summary Signal Differences."
Chapter Signal Descriptions
Address Arbitration Signals
access address bus, device must request gain mastership. arbitration signals collection input output signals devices request address bus, recognize when request granted, indicate other devices when mastership granted. detailed descriptions timing diagrams that show these signals interact, Section 3.2.1, "Address Arbitration."
2.1.1 Request (BR)-Output
Following state timing descriptions request (BR) output signal. Asserted-A device requesting address mastership. asserted more cycles then deasserted internal cancellation request (for example, loss memory reservation). Negated-No device requesting address bus. device have operation pending, parked, ARTRY input asserted previous clock cycle. Timing Comments Assertion-A transaction needed device does have qualified grant. This occur even maximum (two 601and 603, three 604) possible pipeline accesses have occurred. 603, asserted cycle during execution dcbz load instruction that hits touch load buffer. Negation-Occurs least clock cycle after accepted, qualified grant (see ABB), even another transaction pending. also negated least cycle after assertion ARTRY, unless that processor caused assertion ARTRY perform cache block push that snoop operation. State Meaning
2.1.2 Grant (BG)-Input
Following state timing descriptions grant (BG) input signal. State Meaning Asserted-The device may, with proper qualification, assume mastership address bus. qualified grant occurs given cycle when following conditions met: asserted. address cycle progress marked TSthrough-AACK interval). ARTRY negated negated previous cycle (not considered 601). assertion required qualified grant (for example, parked case).
PowerPC Microprocessor Family: Interface 32-Bit Microprocessors
Note that recognizes qualified grant cycle after AACK even ARTRY asserted long asserting ARTRY exclusive ownership data associated with snoop that caused ARTRY. ARTRY signals driven master. processor parked, need asserted qualified grant. Negated-The device next potential address master. Timing Comments Assertion-May occur time indicate device free address bus. After processor gains mastership, does check qualified grant again until cycle which address tenure completes (assuming another transaction run). processor does accept cycles between assertion XATS through assertion AACK. Negation-May occur time indicate device cannot bus. However, device still assumes mastership clock cycle negated because, previous cycle, indicated device that could take mastership qualified).
2.1.3 Address Busy (ABB)-Output
Following state timing descriptions address busy (ABB) output signal. Asserted-The device address master. Negated-The device using address bus. negated clock cycle after qualified grant, device accept mastership, even asserted. This occur potential transaction aborted internally before started. Timing Comments Assertion-Occurs clock cycle after qualified grant that accepted device (see Negated). Negation-Occurs fraction clock cycle after AACK asserted. negated clock cycle after qualified device accept mastership, even asserted. High Impedance-Occurs during fractional portion cycle which negated. guaranteed design high impedance cycle which negated. specific information, particular processor's user's manual. State Meaning
Chapter Signal Descriptions
2.1.4 Address Busy (ABB)-Input
Following state timing descriptions input signal. State Meaning Asserted-The address being used another master, which effectively keeps device from assuming address ownership, regardless input. processor will take address sequence cycles beginning with ending with AACK, which effectively makes optional other masters respond same processor.
Negated-The address owned another device available when accompanied qualified grant. Timing Comments Assertion-May occur when other devices must prevented from using address (and processor currently asserting ABB). Negation-May occur whenever master address bus.
Address Transfer Start Signals
Address transfer start signals input output signals that indicate that address transfer begun. transfer start (TS) signal identifies operation memory transaction; extended address transfer start (XATS) identifies transaction directstore operation. detailed information about XATS interact with other signals, refer Section 3.2.2, "Address Transfer," Chapter "Direct-Store Interface," respectively.
2.2.1 Transfer Start (TS)-Output
Following state timing descriptions transfer start (TS) output signal. Asserted-The master begun memory transaction address transfer attribute signals valid. When asserted with appropriate TT[0-4] signals, also implied data request memory transaction (unless output addressonly operation). Negated-Has special meaning. However, negated throughout entire direct-store address tenure. Timing Comments Assertion-Coincides with assertion ABB. Negation-Occurs clock cycle after asserted. High Impedance-(601 603) Occurs clock cycle after negated, which coincident with negation ABB. High Impedance-(604) Occurs clock cycle after negation 604, negation only cycle long, regardless TS-to-AACK delay. State Meaning
PowerPC Microprocessor Family: Interface 32-Bit Microprocessors
2.2.2 Transfer Start (TS)-Input
Following state timing descriptions input signal. State Meaning Asserted-Another master began transaction address transfer attribute signals valid snooping (see GBL). Negated-No transaction occurring. Timing Comments Assertion-May occur time outside address tenure window: either interval that includes cycle previous assertion through cycle after AACK cycles which asserted previous address tenure, whichever greater. Negation-Must occur clock cycle after asserted.
2.2.3 Extended Address Transfer Start (XATS)-Output (Direct-Store)
Following state timing descriptions extended address transfer start (XATS) output signal. Asserted-The master began direct-store operation first address cycle valid. When asserted with appropriate extended address transfer code (XATC) signals, also implied data request certain direct-store operations (unless addressonly operation). Negated-Has special meaning; however, XATS remains negated throughout entire memory address tenure. Timing Comments Assertion-Coincides with assertion ABB. Negation-Occurs clock cycle after assertion XATS. High Impedance-(601 603) Occurs clock cycle after negation XATS, which coincides with negation ABB. High Impedance-(604) Occurs clock cycle after negation XATS. 604, XATS negation only cycle long, regardless XATS-to-AACK delay. State Meaning
2.2.4 Extended Address Transfer Start (XATS)-Input (Direct-Store)
Following state timing descriptions XATS input signal. Asserted-The master must check direct-store operation reply. Negated-There need check direct-store reply. Timing Comments Assertion-May occur time outside cycles that define window address tenure. This window marked either interval that includes cycle previous XATS assertion through cycle after AACK cycles which asserted previous address tenure, whichever greater. Negation-Must occur clock cycle after XATS asserted. State Meaning
Chapter Signal Descriptions
Address Transfer Signals
address transfer signals used transmit address generate monitor parity address transfer. detailed descriptions these signals interact, Section 3.2.2, "Address Transfer."
2.3.1 Address (A[0-31])-Output (Memory Operations)
Following state timing descriptions address (A[0-31]) output signals during memory operations. State Meaning Asserted/Negated-Represents physical address data transferred. burst transfers, address presents doubleword-aligned address (quad-word-aligned 601) with critical data that missed cache read operation, first double word cache clock write operation. Note that address output during burst operations incremented. Timing Comments Assertion/Negation-Occurs clock cycle after qualified grant (coincides with assertion TS). High Impedance-Occurs clock cycle after AACK asserted.
2.3.2 Address (A[0-31])-Input (Memory Operations)
Following state timing descriptions A[0-31] input signals memory operations. State Meaning Asserted/Negated-Carries address snoop operation. Timing Comments Assertion/Negation-Must occur same clock cycle assertion sampled processor only this cycle.
2.3.3 Address (A[0-31])-Output (Direct-Store Operations)
Following state timing descriptions A[0- output signals direct-store operations. State Meaning Asserted/Negated-For direct-store operations from this device, address tenure consists packets (each requiring cycle). packet these signals convey control information. packet they represent physical address data transferred. reply operations other devices, address carries control, status, information. Timing Comments Assertion/Negation-An address tenure consists beats. first occurs clock cycle after qualified grant, coinciding with XATS. address makes transition second beat next clock cycle. High Impedance-Occurs clock cycle after AACK asserted.
PowerPC Microprocessor Family: Interface 32-Bit Microprocessors
2.3.4 Address (A[0-31])-Input (Direct-Store Operations)
Following state timing descriptions A[0-31] input signals direct-store operations. State Meaning Asserted/Negated-When processor receiving A[0-31] signals master, snoops (and checks address parity) only first address beat direct-store operations reply operations whose receiver tags match processor identification (PID) tag. Section 7.1, "Direct-Store Transaction Protocol Details."
Timing Comments Assertion/Negation-The first beat transfer address tenure coincides with XATS, with second address beat next cycle.
2.3.5 Address Parity (AP[0-3])-Output
Following state timing descriptions address parity signals (AP[0-3]) output signals. Asserted/Negated-Represents parity each four address bytes. parity means number bits, including parity bit, driven high. Signal assignments follows: A[0-7] A[8-15] A[16-23] A[24-31] more information, Section 3.2.2.1, "Address Parity." Timing Comments Assertion/Negation/High Impedance-The same A[0-31]. State Meaning
2.3.6 Address Parity (AP[0-3])-Input
Following state timing descriptions AP[0-3] input signals. Asserted/Negated-Represents parity each four address bytes snooping direct-store operations. Depending MSR[ME] various HID0 bits, detecting even parity either causes processor enter checkstop state take machine check exception. address parity check enabled HID0, detection even parity unconditionally causes checkstop 601. (See signal description.) Timing Comments Assertion/Negation-The same A[0-31]. State Meaning
Chapter Signal Descriptions
2.3.7 Address Parity Error (APE)-Output
Following state timing descriptions address parity error (APE) output signal. Note that open-drain type output requires external pull-up resistor assure proper deassertion. State Meaning Asserted-The processor detected incorrect address parity snoop transaction type recognizes respond such first address beat direct-store operation. does assert address parity checking disabled. Negated-The processor detect even address parity. Timing Comments Assertion-Occurs second clock cycle after XATS asserted. High Impedance-Occurs third clock cycle after XATS asserted.
Address Transfer Attribute Signals
transfer attribute signals further characterize transfer-indicating such things transfer size, whether read write, whether burst single-beat transfer. detailed description these signals interact, Section 3.2.2, "Address Transfer." Some signals that function memory operations work differently direct-store accesses; Chapter "Direct-Store Interface."
2.4.1 Transfer Type (TT[0-4])-Output
Following state timing descriptions transfer type signals (TT[0-4]) output signals. State Meaning Asserted/Negated-Table defines transactions identified TT[0-4] signals. table gives type transaction type data transferred, source cause transfer, processors that support these transaction types master when snooping. Some codes this table reserved. Notice that encoding been chosen simplify decoding. example, generally zero writes reads generally zero address-only operation. full description coherency actions, Appendix "Coherency Action Tables." direct-store operations, these signals part extended address transfer code (XATC) along with TSIZn TBST:
XATC(0-7) TT(0-3)||TBST||TSIZ(0-2). driven negated output 601. Timing Comments Assertion/Negation/High Impedance-The same A[0-31].
PowerPC Microprocessor Family: Interface 32-Bit Microprocessors
2.4.2 Transfer Type (TT[0-4])-Input
Following state timing descriptions TT[0-4] input signals. State Meaning Asserted/Negated-Table defines transactions identified TT[0-4]. full description coherency actions, Appendix "Coherency Action Tables." direct-store operations, TT[0-3] form part XATC snooped XATS asserted.
Timing Comments Assertion/Negation-The same A[0-31].
Table 2-1. Transfer Encoding PowerPC 601, 603, Processors
[0-4] Master Transactions Transaction Transfer Address only Address only Address only Address only Address only dcbst dcbf sync Store shared block dcbz, dcbi, icbi eieio Source Processor Support Initiator 601, 601, 601, Snooper 601, 601, 601,
00000 Clean block 00100 Flush block 01000 SYNC 01100 Kill block 10000 Ordered operation
601/603/604 601/603/604
10100 External control word write Single-beat write ecowx 11000 invalidate Address only tlbie
601/603/604 601/604 601/604
11100 External control word read Single-beat read eciwx 00001 lwarx reservation 00101 Reserved 01001 synchronize 01101 Invalidate instruction cache copy 00010 Write-with-flush 00110 Write-with-kill 01010 Read Address only Address only Address only Single-beat write burst Burst Single-beat read burst lwarx cache execution tlbsync icbi Caching-inhibited writethrough store Snoop writeback, dcbf, dcbst, castout modified data
601/603/604
601/603/604 601/603/604 601/603/604 601/603/604
Cacheable load miss 601/603/604 601/603/604 (601/604), cacheable instruction miss cache-inhibited load Load miss (603) store miss 601/603/604 601/603/604 601/603/604 601/603/604
01110 Read-with-intent-to-modify Burst 10010 Write-with-flush-atomic 10110 Reserved 11010 Read-atomic
Single-beat write stwcx. Single-beat read burst lwarx
601/603/604 601/603/604
Chapter Signal Descriptions
Table 2-1. Transfer Encoding PowerPC 601, 603, Processors (Continued)
[0-4] Master Transactions Transaction Transfer Burst Single-beat read burst Source stwcx. miss with valid reservation Snooped only Processor Support Initiator Snooper
11110 00X11 Reserved 01011 Read-with-no-intent-tocache 01111 Reserved 1XXX1 Reserved customer
601/603/604 601/603/604 603/604
2.4.3 Transfer Burst (TBST)-Output
Following state timing descriptions transfer burst (TBST) output signal. State Meaning Asserted-A burst transfer progress. Negated-A burst transfer progress. Also, part extended address transfer code (XATC); Section 2.4.1, "Transfer Type (TT[0-4])-Output." external control instructions (eciwx/ecowx), TBST outputs EAR[28], which part resource (TBST||TSIZ[0-2]).
Timing Comments Assertion/Negation/High Impedance-The same A[0-31].
2.4.4 Transfer Burst (TBST)-Input
Following state timing descriptions TBST input signal. Asserted-For direct-store operations, TBST forms part XATC; Section 2.4.2, "Transfer Type (TT[0-4])-Input." Negated-A burst transfer progress. Timing Comments Assertion/Negation/High Impedance-The same A[0-31]. State Meaning
2.4.5 Transfer Size (TSIZ[0-2])-Output
Following state timing descriptions transfer size signals TSIZ[0-2] output signals. State Meaning Asserted/Negated-For memory accesses, these signals with TBST indicate data transfer size current operation, shown Table 2-2. This table shows transfer sizes indicated combinations TBST TSIZ[0-2]. Note that combination defined system use. This combination could generated systems would output from PowerPC processor.
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PowerPC Microprocessor Family: Interface 32-Bit Microprocessors
direct-store operations, these signals form part extended address transfer code (XATC); description Section 2.4.1, "Transfer Type (TT[0-4])-Output." external control instructions, eciwx/ecowx, these signals output EAR[29-31], form resource (TBST||TSIZ[0-2]). Timing Comments Assertion/Negation/High Impedance-The same A[0-31].
Table 2-2. Data Transfer Size
TBST Asserted Asserted Asserted Asserted Asserted Negated Negated Negated Negated Negated Negated Negated Negated TSIZ[0-2] Reserved Burst bytes) reserved system Burst bytes) Reserved (64-byte bursts) Reserved bytes byte bytes bytes bytes bytes bytes bytes Transfer Size
2.4.6 Transfer Size (TSIZ[0-2])-Input
Following state timing descriptions TSIZ[0-2] input signals. State Meaning Asserted/Negated-For direct-store operations, TSIZ[0-2] part XATC; Section 2.4.2, "Transfer Type (TT[0-4])-Input."
Timing Comments Assertion/Negation-The same A[0-31].
2.4.7 Transfer Code (TCn)-Output
transfer code (TCn) consists three output signals (TC[0-2]) output signals (TC[0-1]). These signals provide information about current transaction that useful implementing external caches. Following state timing descriptions TCn. Asserted/Negated-Represents special encoding transfer progress gives supplemental information certain transaction types. Table 2-3, Table 2-4, Table 2-5. Timing Comments Assertion/Negation/High Impedance-The same A[0-31].
Chapter Signal Descriptions 2-11
State Meaning
Table shows transfer code definitions 601.
Table 2-3. Transfer Code Signal Encoding PowerPC Processor
Signal State Asserted Definition Read: operation instruction fetch. Write: Operation invalidating cache line 601. Kill block (address only): Operation invalidating cache block 601. Deasserted Read: operation instruction fetch. Write: Operation invalidating cache line 601. Kill block (address only): Operation invalidating cache block 601. Asserted next access likely same page; sector been loaded low-priority load adjacent sector queued.
Deasserted next access isn't likely next page; load adjacent sector queued.
Table shows transfer code meanings 603.
Table 2-4. Transfer Code Signal Encoding PowerPC Processor
TC[0-1] Data transaction Touch load Instruction fetch Reserved Read Write write
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PowerPC Microprocessor Family: Interface 32-Bit Microprocessors
Table shows transfer code options gives transaction type, encoding TC[0-2] signals, type cycle.
Table 2-5. Transfer Code Signal Encoding PowerPC Processor
From after WriteTransfer Asserted ARTRYd Back Type [0-2] Snoop4 Buffer Write with kill Never Always Don't care Final Cache State5 Cache copy-back
Comments
distinguish between cache copy-back, block clean (dcbst), block flush (dcbf), this transaction must ARTRYd. This transaction eventually returns (before anything another snoop push directly from data cache) indicating another WT/TC code combination. Block flush (dcbf) Block clean (dcbst)-The dcbst instruction changes cache state when modified block copy-back buffer. Before lowpriority write-back buffer entry completes address tenure, cache state changed store dcbi cache miss. Snoop push6 directly from data cache (read readatomic)-The read read-atomic snoop changes data cache state when modified block placed snoop-push buffer. Before buffer completes address tenure, cache changed dcbi cache miss.
Don't care
Chapter Signal Descriptions
2-13
Table 2-5. Transfer Code Signal Encoding PowerPC Processor (Continued)
From after WriteTransfer Asserted ARTRYd Back Type [0-2] Snoop4 Buffer Write with kill Final Cache State5
Comments
Don't care
Snoop push6 from write-back buffer (read readatomic)-The data cache shared copy buffer held block clean (dcbst) transaction. held block flush (dcbf) cache write-back transaction, cache valid copy after transaction. know processor kept shared copy invalidated this block, this transaction must ARTRYd. originated from write-back buffers snoops occur, transaction returns next indicates DCBF, DCBST, write-back WT/TC code. returns snoop push read, came from data cache. Snoop push6 directly from data cache (RWITM, RWITM-atomic, flush, write w/flush, write w/flushatomic, kill) Snoop push6 from write-back buffers (RWITM, RWITM-atomic, flush, write w/flush-atomic, write w/flush, write w/kill, kill) Snoop push6 from data cache (clean RWNITC)- clean RWNITC snoop changes data cache state when modified block snoop-push buffer. Before buffer completes address tenure, cache state changed store either dcbi instruction cache miss. Snoop push6 from write-back buffers (clean RWNITC)-If this snoop block-flush (dcbf) cache write-back write-back buffers, cache does have valid copy this address after this transaction. this snoop hits block-store (dcbst) write-back buffers, processor keep exclusive copy cache block. Kill block deallocate (dcbi) Kill block allocate castout required (dcbz) Kill block allocate castout required (dcbz) Kill block; write block marked
Don't care
Don't care
Don't care
Don't care (dcbst buffer) (cache writeback dcbf buffer) Don't care
Kill block
Never
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PowerPC Microprocessor Family: Interface 32-Bit Microprocessors
Table 2-5. Transfer Code Signal Encoding PowerPC Processor (Continued)
From after WriteTransfer Asserted ARTRYd Back Type [0-2] Snoop4 Buffer Read7 Never Final Cache State5
Comments
Don't care
Data read, castout required-The cache state asserted processor read read-atomic transaction. asserted transaction RWIor RWITM-atomic transaction, cache state Data read, castout required-The cache state asserted processor read read-atomic transaction. asserted, transaction RWIor RWITMatomic transaction, cache state Instruction read Kill block deallocate (icbi9)
ICBI Notes:
Never
Valid Don't care Invalid
value column reflects logic value seen signal. window assertion defined second cycle after AACK ARTRY were asserted cycle after AACK.
full condition this column "The corresponding this transaction asserted window last snoop this address." full condition this column "This transaction first asserted this processor after more ARTRYd snoop transactions address this transaction matches address least those ARTRYd snoop transactions." This column reflects final MESI state processor line referenced this transaction after transaction completes successfully without ARTRY. This snoop push guaranteed push most-recently modified data processor. more snoop operations required ensure that this snoop been fully processed processor. Read this case encompasses read RWITM, normal atomic. write-through from translation icbi distinguished from kill block assertion TT4.
2.4.8 Cache Inhibit (CI)-Output
Following state timing descriptions cache inhibit (CI) output signal. Asserted-Generally indicates that single-beat transfer will cached, reflecting setting block page that contains address current transaction. Negated-Generally indicates that burst transfer will allocate data cache block. negated castouts pushes. Section 4.8, "External Settings," describes exceptions above. Timing Comments Assertion/Negation/High Impedance-The same A[0-31]. State Meaning
Chapter Signal Descriptions
2-15
2.4.9 Write-Through (WT)-Output
Following state timing descriptions write-through (WT) output signal. State Meaning Asserted-Generally indicates that single-beat transaction writethrough, reflecting value block page that contains address current transaction. Negated-Generally indicates transaction write-through. Section 4.8, "External Settings," describes exceptions above. Timing Comments Assertion/Negation/High Impedance-The same A[0-31].
2.4.10 Global (GBL)-Output
Following state timing descriptions global signal (GBL) output signal. 604e, HID0[23] lets software control behavior instruction fetches through address-translation mechanism; refer 604e user documentation. Asserted-Generally indicates that transaction global, reflecting setting block page that contains address current transaction (except case write-back operations, which nonglobal.) Negated-Generally indicates that transaction global. 604, this signal negated instruction fetches. exceptions, Section 4.8, "External Settings." Timing Comments Assertion/Negation/High Impedance-The same A[0-31]. State Meaning
2.4.11 Global (GBL)-Input
Following state timing descriptions input signal. Asserted-A transaction snooped; however, processor will snoop reserved transaction types, operations associated with eieio, eciwx, ecowx instructions, address-only transactions associated with lwarx reservation set. Note that snoops reservation address register global nonglobal address transfers. This snooping required 603's implementation lwarx stwcx. instructions, which require snoops castouts snoop pushes (nonglobal). Snoops with affect cache state. Negated-A transaction snooped processor. Timing Comments Assertion/Negation-The same A[0-31]. State Meaning
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PowerPC Microprocessor Family: Interface 32-Bit Microprocessors
2.4.12 Cache Element (CSEn)-Output
number cache element signals each processor depends upon cache associativity that processor. There three cache element signals (CSE[0-2]), (CSE), 603e, 604, 604e (CSE[0-1]). Following state timing descriptions CSEn signals. some documentation these signals called cache entry cache enable signals. Asserted/Negated-Represents cache replacement element (also referred coherency class) current cache transaction. used with address transfer attribute signals externally track state each cache block processor. CSEn signals meaningful during data cache touch load operations 603. Timing Comments Assertion/Negation/High Impedance-The same A[0-31]. State Meaning
2.4.13 High-Priority Snoop Request (HP_SNP_REQ)-601 Only
Following state timing descriptions high-priority snoop request input signal (HP_SNP_REQ) 601. This signal enabled setting HID0[31]. State Meaning Asserted-The additional reserved queue position list available queue positions push transactions that result snoop hit. Negated-The will make reserved queue available snoop push resulting from transaction. This normal mode. Timing Comments Assertion/Negation-Must valid throughout address tenure.
Address Transfer Termination Signals
address transfer termination signals indicate either that address tenure completed successfully must repeated, when should terminated. Section 3.2.3, "Address Transfer Termination,"describes these signals interact.
2.5.1 Address Acknowledge (AACK)-Input
Following state timing descriptions address acknowledge (AACK) input signal. State Meaning Asserted-The address phase transaction complete. address goes high-impedance state next clock cycle. processor samples ARTRY clock cycle after assertion AACK. sample ARTRY second cycle after asserted. Negated-During assertion ABB, indicates address transfer attribute signals must remain driven.
Chapter Signal Descriptions
2-17
Timing Comments Assertion-Can occur soon clock cycle after XATS asserted, delayed extend address access time, example, support slow snooping devices. Negation-Must occur clock cycle after assertion AACK.
2.5.2 Address Retry (ARTRY)-Output
Following state timing descriptions address retry (ARTRY) output signal. Asserted-The master detects condition which snooped address tenure must retried. processor must update memory result snoop that caused retry, processor asserts during that snoop window, which defined second cycle after AACK ARTRY asserted cycle after AACK. Also invalidates data some cases; Section 3.3.1.1, "Effect ARTRY Assertion Data Transfer Arbitration PowerPC Processor." High Impedance-The master does need snooped address tenure retried. Timing Comments Assertion-Asserted second cycle after assertion retry required. Thus, when retry required, there only empty cycle between assertions ARTRY. Negation-Occurs second cycle after assertion AACK. Because ARTRY simultaneously driven multiple devices, driven negated following ways: 601-Occurs second cycle after assertion AACK. Since ARTRY simultaneously driven multiple devices, negates unique fashion. First buffer goes high impedance cycle, then driven high 2XPCLK cycle before returning high impedance. This method negation disabled setting HID0[29]. 603-Occurs second cycle after assertion AACK. Since ARTRY simultaneously driven multiple devices, negates unique fashion. First buffer goes high impedance minimum one-half processor cycle (dependent clock mode), then driven negated cycle before returning high impedance. This method negation disabled setting HID0[7]. 604-ARTRY becomes high impedance least one-half cycle, then driven high approximately cycle. ARTRY then guaranteed design become high impedance latest start third cycle after AACK. This method negation disabled setting HID0[7]. State Meaning
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PowerPC Microprocessor Family: Interface 32-Bit Microprocessors
2.5.3 Address Retry (ARTRY)-Input
Following state timing descriptions ARTRY input signal. Asserted-For address master, ARTRY indicates device must retry preceding address tenure immediately negate asserted). associated data tenure begun, also abort data tenure immediately even burst data been received. devices that address master, this input indicates they should immediately negate clock cycle after assertion ARTRY snooping master allow write-back operation. Negated/High Impedance-The master need retry last address tenure. Timing Comments Assertion-May occur soon second cycle after XATS asserted; must occur clock cycle immediately after assertion AACK address retry required. Negation-Must occur second cycle after AACK asserted. State Meaning
2.5.4 Shared (SHD)-Output
Following state timing descriptions shared (SHD) output signal. Asserted-If ARTRY negated, indicates that after this transaction completes successfully, master will keep valid shared copy address that reservation exists this address. ARTRY asserted snooping master, snoop modified data that will pushed master's next address transaction. Negated/High Impedance-After this address transferred, processor will have valid copy snooped address. Timing Comments Assertion/Negation-Same ARTRY. High Impedance-Same ARTRY. Because does support shared MESI state (S), does implement SHD. State Meaning
2.5.5 Shared (SHD)-Input
Following state timing descriptions input signal. Asserted-If ARTRY asserted, master must allocate incoming cache block shared self-generated transaction. Applies only read read atomic transactions. Negated-If ARTRY negated, master allocate incoming cache block exclusive self-generated read read-atomic transaction. Timing Comments Assertion/Negation-The same ARTRY. Because does support shared MESI state, does implement SHD.
Chapter Signal Descriptions 2-19
State Meaning
Data Arbitration Signals
Like address arbitration signals, data arbitration signals maintain orderly process determining data mastership. Note that there equivalent address arbitration signal (bus request), because, except address-only transactions, XATS imply data requests. detailed description these signals interact, Section 3.3.1, "Data Arbitration." DBWO signal lets processor configured dynamically write data order with respect read data.
2.6.1 Data Grant (DBG)-Input
Following state timing descriptions data grant (DBG) input signal. Asserted-With proper qualification device become data master. Note that some cases, assertion ARTRY invalidates data grant (see Section 3.3.1.1, "Effect ARTRY Assertion Data Transfer Arbitration PowerPC Processor"). device achieves qualified data grant when following conditions met: data busy (DBB negated). (This condition does apply 604e) data streaming mode.) DRTRY negated. (This condition does apply processor using data streaming no-DRTRY mode.) ARTRY negated ARTRY applies associated address tenure. Negated-The master must hold data tenures. Timing Comments Assertion-May occur time indicate that device free assume data mastership. processor sample early cycle that XATS asserted. data streaming mode, must asserted exactly cycle data tenure, cycle before data tenure begin. system cannot assert earlier park DBG, assert consecutive cycles. signal does participate determining qualified data grant. Therefore, system must assert that prevents data tenure collisions from different masters. Also, system must assert data tenures complete before providing another DBG. given early data streaming mode, processor drops current data tenure prematurely next cycle begins pending data tenure. State Meaning
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PowerPC Microprocessor Family: Interface 32-Bit Microprocessors
604e less restrictive timing requirements data streaming mode-DBG must asserted earlier than cycle before 604e's data tenure begin only when another master currently owns data (that when would normally asserted data tenure). other masters data (asserting DBB), 604e allows system park DBG. still output-only signal data streaming mode (that does participate qualified data grant), requiring system ensure that different masters don't collide data tenures. system tries stream back-to-back data tenures asserting with final first data tenure, processor accepts qualified data grant only current next data tenures both burst reads. Other combinations cannot streamed. Negation-May occur time indicate that master cannot assume control data bus.
2.6.2 Data Write Only (DBWO)-Input
Following state timing descriptions DBWO input signal. State Meaning Asserted-The processor data tenure outstanding write address even read address pipelined before write address. write data available, processor performs first pending read transfer. Section 3.3.2, "Data Write Only," detailed instructions using DBWO. Note that takes only pending data write operation read operation. Negated-The processor runs address data tenures same order. Tying DBWO negated preserved address/data ordering. Timing Comments Assertion-Must occur later than qualified pending write tenure. DBWO signal recognized processor only clock cycles qualified data grant. Negation-May occur time after qualified data grant before next qualified data grant.
2.6.3 Data Busy (DBB)-Output
Following state timing descriptions data busy (DBB) output signal. State Meaning Asserted-The device data master. processor always assumes data mastership needs data given qualified data grant (see DBG). Negated-The device using data bus, unless data tenure being extended assertion DRTRY. Note that 604e no-DRTRY mode, DRTRY tied asserted ignored.
Chapter Signal Descriptions
2-21
Timing Comments Assertion-Occurs clock cycle after qualified DBG. Negation-Occurs fractional clock cycle after assertion final within cycles assertion TEA. High Impedance-Occurs during fractional portion cycle which negated. signal designed high impedance cycle which negated. specific information, appropriate user's manual.
2.6.4 Data Busy (DBB)-Input
Following state timing descriptions input signal. data streaming mode, only output part qualified data grant; Chapter "Additional Configurations." Asserted-Another device data master. Note that cannot used systems that read data streaming. Negated-The device using data bus. arbiter designed assert exactly cycle before next data tenure starts, unnecessary pulled high. Timing Comments Assertion-Must occur when processor must kept from using data bus. Negation-May occur whenever data available. State Meaning
Data Transfer Signals
Like address transfer signals, data transfer signals used transmit data generate monitor parity data transfer. detailed description data transfer signals interact, Section 3.3.3, "Data Transfer."
2.7.1 Data (DH[0-31], DL[0-31])-Output
Following state timing descriptions output signals. State Meaning Asserted/Negated-Represents state data during data write. data halves-data high (DH) data (DL). Table shows data lane assignments. Direct-store operations exclusively (there 64-bit, direct-store operations). Unselected byte lanes supply valid data. Timing Comments Assertion/Negation-Initial beat coincides with and, bursts, transitions clock cycle after each assertion TA.The data driven once noncached transactions four times processor cache transactions (bursts). High Impedance-Occurs clock cycle after final assertion
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PowerPC Microprocessor Family: Interface 32-Bit Microprocessors
Table 2-6. Data Lane Assignments
Data Signals DH[0-7] DH[8-15] DH[16-23] DH[24-31] DL[0-7] DL[8-15] DL[16-23] DL[24-31] Byte Lane
2.7.2 Data (DH[0-31], DL[0-31])-Input
Following state timing descriptions input signals. Asserted/Negated-Represents state data during data read transaction. data halves, data high (DH) data (DL). Table shows byte lanes. Direct-store operations exclusively (there 64-bit direct-store operations). Timing Comments Assertion/Negation-Data must valid same clock cycle that asserted.The data driven once noncached transactions four times processor cache transactions (bursts). State Meaning
2.7.3 Data Parity (DP[0-7])-Output
Following state timing descriptions data parity (DP[0-7]) output signals. Asserted/Negated-Represents parity each eight bytes data write transaction. parity means that number bits, including parity bit, driven high. Table shows signal assignments. eight bits driven with valid parity write operations except direct-store operations which only DP[0-3] driven with valid parity. Timing Comments Assertion/Negation-The same DL[0-31]. High Impedance-The same DL[0-31].
Table 2-7. DP[0-7] Signal Assignments
Signal Name Signal Assignments DH[0-7] DH[8-15] DH[16-23] DH[24-31]
State Meaning
Chapter Signal Descriptions
2-23
Table 2-7. DP[0-7] Signal Assignments (Continued)
Signal Name Signal Assignments DL[0-7] DL[8-15] DL[16-23] DL[24-31]
2.7.4 Data Parity (DP[0-7])-Input
Following state timing descriptions DP[0-7] input signals. Asserted/Negated-Represents parity each byte read data. Parity checked data byte lanes during data read operations, regardless size transfer. During direct-store read operations, only DP[0-3] signals (corresponding byte lanes DH[0-31]) checked parity. data parity errors enabled, detected even parity causes checkstop machine check exception (and assertion DPE) depending state MSR[ME]. 601, data parity check enabled HID0, detection even parity unconditionally causes checkstop. Timing Comments Assertion/Negation-The same DL0-DL31. State Meaning
2.7.5 Data Parity Error (DPE)-Output
Following state timing descriptions data parity error (DPE) output signal. open-drain type output requires pull-up resistor proper deassertion. Asserted-The processor detected incorrect data parity incoming read data. Negated-Indicates correct data parity. Timing Comments Assertion-Occurs second clock cycle after asserted processor driven cycle. State Meaning
2.7.6 Data Disable (DBDIS)-Input
Following state meanings timing comments data disable (DBDIS) input signal. This signal 601. State Meaning Asserted-For write transaction, processor must release data DP[0-7] high impedance next cycle. data tenure remains active, remains driven, transfer termination signals still monitored processor. DBDIS signal ignored read transactions. Negated-The data should remain normally driven.
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PowerPC Microprocessor Family: Interface 32-Bit Microprocessors
Timing Comments Assertion/Negation-Should driven cycle before data driven processor. asserted clock cycle when processor driving, will driving, data remain asserted multiple cycles.
Data Transfer Termination Signals
Data termination signals required after each data beat data transfer. Note that single-beat transaction, data termination signals also indicate tenure, while burst accesses, data termination signals apply individual beats indicate tenure only after final data beat. detailed description these signals interact, Section 3.3.4, "Data Transfer Termination."
2.8.1 Transfer Acknowledge (TA)-Input
Following state timing descriptions transfer acknowledge (TA) input signal. Asserted-A single-beat data transfer data beat burst transfer completed successfully (unless DRTRY asserted next clock cycle reads). signal must asserted each data beat burst transaction. Negated-Until asserted, master must continue driving data current write must wait sample data reads. Timing Comments Assertion-During data tenure, which generally begins after qualified data grant continues through period defined DRTRY. This period affected ARTRY window. Section 3.3.1.1, "Effect ARTRY Assertion Data Transfer Arbitration PowerPC Processor." system withhold asserting indicate that master should insert wait states extend data tenure. Negation-Must occur after clock cycle final only) data beat transfer. burst transfer, system assert clock cycle then negate advance burst transfer next beat insert wait states during next beat. When configured clock mode performing burst read into data cache, requires wait state between assertion first assertion that transaction. no-DRTRY mode also selected, requires wait states. State Meaning
2.8.2 Data Retry (DRTRY)-Input
Following state timing descriptions data retry (DRTRY) input signal. State Meaning Asserted-The master must invalidate data from previous read operation. DRTRY ignored write transactions defined direct-store transfers.
Chapter Signal Descriptions
2-25
Negated-Data presented with previous read operation valid. This essentially late allow speculative forwarding data (with during reads. Timing Comments Assertion-Must occur during clock cycle immediately after asserted retry required. DRTRY signal held asserted multiple clock cycles. When negated, data must have been valid previous clock with asserted. Negation-Must occur during clock cycle after valid data beat. This occur several cycles after negated, effectively extending data tenure. Start-up-For 604e, DRTRY sampled negation HRESET; DRTRY asserted, no-DRTRY mode selected. DRTRY negated start-up, DRTRY enabled. no-DRTRY data streaming mode selected, DRTRY must negated during normal operation (after HRESET). no-DRTRY mode provides one-cycle faster read data streaming eliminates wasted cycles between data bursts. Section 6.1, "No-DRTRY Mode (603 604e)," description no-DRTRY mode Chapter "Additional Configurations," description data streaming.
2.8.3 Transfer Error Acknowledge (TEA)-Input
Following state timing descriptions transfer error acknowledge (TEA) input signal. State Meaning Asserted-A error occurred that causes machine check exception causes processor enter checkstop state machine check enable cleared (MSR[ME] 0)). more information, Section 5.3, "Machine Check Checkstops." Assertion terminates current transaction; that assertion DRTRY ignored. Asserting causes negation/high impedance next clock cycle. However, data entering cache invalidated. asserted during direct-store transaction, machine check checkstop action delayed subsequent direct-store transactions continue until transfers from directstore segment complete. signal must asserted every direct-store data tenure including last one. processor takes machine check checkstop sooner than last direct-store data tenure been terminated assertion TEA. load store reply necessary after last data tenure receives assertion. Negated-No error detected.
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PowerPC Microprocessor Family: Interface 32-Bit Microprocessors
Timing Comments Assertion-May asserted while asserted during valid DRTRY window. data streaming mode, 604/604e does recognize cycle after during read operation absence DRTRY assertion opportunity. should asserted cycle only. Negation-TEA must negated later than negation last DRTRY. processor deasserts within clock cycle after assertion TEA.
System Status Signals
Most system interrupt, checkstop, reset signals input signals that indicate when exceptions received, when checkstop conditions have occurred, when processor must reset. processor generates CKSTP_OUT when detects checkstop condition. detailed descriptions, Chapter "System Status Signals."
2.9.1 Interrupt (INT)-Input
Following state timing descriptions interrupt (INT) input signal. Asserted-The processor initiates external interrupt MSR[EE] remains asserted long enough; otherwise, processor ignores interrupt. Negated-Normal operation should proceed. Section 5.4, "External Interrupt Exception (0x00500)." Timing Comments Assertion-May occur time asserted asynchronously input clocks. input level-sensitive. Negation-Should occur until exception taken. 601, this signal negated after least three processor clock cycles. State Meaning
2.9.2 System Management Interrupt (SMI)-Input
Following state timing descriptions system management interrupt (SMI) input signal. This interrupt supports power management 601. Asserted-The processor initiates system management interrupt exception MSR[EE] set. Negated-Normal operation should proceed. Section 5.4, "External Interrupt Exception (0x00500)." Timing Comments Assertion-May occur time asserted asynchronously input clocks. input level-sensitive. Negation-Should occur until exception taken. State Meaning
Chapter Signal Descriptions
2-27
2.9.3 Machine Check Interrupt (MCP)-Input
Following state timing descriptions machine check interrupt (MCP) input signal. This signal 601. Asserted-The processor initiates machine check interrupt operation MSR[ME] HID0[EMCP] set; MSR[ME] cleared HID0[EMCP] set, processor must terminate operation internally gating clocks releasing outputs (except CKSTP_OUT) high-impedance state. HID0[EMCP] cleared, processor ignores interrupt condition. signal must remain asserted clock cycles. Negated-Normal operation should proceed. Timing Comments Assertion-May occur time asserted asynchronously input clocks. negative edge-sensitive. Negation-May negated cycles after assertion. State Meaning
2.9.4 Checkstop Input (CKSTP_IN)-Input
Following state timing descriptions checkstop input signal (CKSTP_IN). State Meaning Asserted-The processor must terminate operation internally gating clocks releasing outputs except CKSTP_OUT high-impedance state. Once asserted, CKSTP_IN must remain asserted until system been reset. Negated-Normal operation should proceed. Section 5.3, "Machine Check Checkstops." Timing Comments Assertion-May occur time asserted asynchronously input clocks. 601, CKSTP_IN must asserted least three PCLK_EN clock cycles. asserted synchronously meeting setup hold times (specified hardware specifications) must asserted least PCLK_EN clock cycles. Negation-May occur time after CKSTP_OUT asserted.
2.9.5 Checkstop Output (CKSTP_OUT)-Output
Following state timing descriptions checkstop output (CKSTP_OUT) output signal. Note that CKSTP_OUT open-drain type output requires external pull-up resistor assure proper deassertion. State Meaning Asserted-The processor detected checkstop condition ceased operation. Negated-The processor operating normally. Section 5.3, "Machine Check Checkstops."
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PowerPC Microprocessor Family: Interface 32-Bit Microprocessors
Timing Comments Assertion-Can occur time asynchronously input clocks. Negation-Is negated upon assertion HRESET.
2.9.6 Hard Reset (HRESET)-Input
hard reset (HRESET) input signal must used power-on properly reset processor. This input additional functionality certain test modes. Following state timing descriptions HRESET. State Meaning Asserted-Initiates hard reset operation when HRESET transitions from asserted negated. Causes reset exception described Section 5.2.1.1, "Hard Reset Settings." Output drivers released high impedance within five clocks (three clocks 601) after assertion HRESET.
Negated-Normal operation should proceed. Timing Comments Assertion-Can occur time asynchronous with processor input clock; must held asserted least (300 601) clock cycles. Negation-Can occur after minimum reset pulse width met.
2.9.7 Soft Reset (SRESET)-Input
soft reset (SRESET) input signal additional functionality certain test modes. Following state timing descriptions SRESET. State Meaning Asserted-Initiates processing soft reset exception described Section 5.2.2, "Soft Reset." Negated-Normal operation should proceed. Timing Comments Assertion-Can occur time asynchronous with processor input clock. SRESET negative edge-sensitive. Negation-May occur time after minimum soft reset pulse width 601) cycles met.
2.10 Processor State Signals
signals described this section provide inputs controlling time base processor, external cache access processor, output signal from processor indicate that memory reservation been set.
2.10.1 Reservation (RSRV)-Output
Following state timing descriptions reservation (RSRV) output signal. State Meaning Asserted/Negated-Reflects state reservation coherency used lwarx/stwcx. instructions. Section 4.5.1, "PowerPC Processor lwarx/stwcx. Implementation."
Chapter Signal Descriptions
2-29
Timing Comments Assertion-Occurs synchronously clock cycle after execution lwarx instruction that sets internal reservation condition. 604e, RSRV asserted late fourth cycle after AACK read-atomic operation lwarx instruction requires read-atomic operation. Negation-Occurs synchronously clock cycle after execution stwcx. instruction that clears reservation late second cycle after asserted snoop that clears reservation.
2.10.2 External Cache Intervention (L2_INT)-Input
Following state timing descriptions external cache intervention (L2_INT) input signal. This signal 603. State Meaning Asserted-The current data transaction required intervention from other devices. Negated-The current data transaction require intervention. Timing Comments Assertion/Negation-This signal sampled processor coincident with first assertion given data tenure.
2.10.3 Time Base Enable (TBEN)-Input
time base enable (TBEN) input signal essentially count enable time base. Following state timing descriptions TBEN. This signal 601. State Meaning Asserted-The time base should continue clocking. Negated-The time base should stop counting. Timing Comments Assertion/Negation-May occur cycle synchronous with system clock.
2.10.4 TLBI Synchronization (TLBISYNC)-Input
Following state timing descriptions TLBI synchronization (TLBISYNC) input signal. This signal 604. Asserted-Instruction execution should stop after tlbsync executes. Negated-Instruction execution resume after tlbsync completes. TLBISYNC sampled when HRESET negates select 32-bit data mode; TLBISYNC negated, 32-bit mode disabled. Section 6.3, "32-Bit Data Mode (603)." Timing Comments Assertion/Negation-May occur cycle. State Meaning
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PowerPC Microprocessor Family: Interface 32-Bit Microprocessors
2.11 Power Management Signals
Each processor input output signals defined support low-power modes processor system. These signals same between processors. signals each processor described this section.
2.11.1 Quiescent Request (QUIESC_REQ)-Output
Following state timing descriptions quiescent request (QUIESC_REQ) output signal, which uses request system enter soft-stop state. Asserted-The requesting soft stop state system. Negated-The requesting soft stop state. Timing Comments Assertion/Negation-May occur time. State Meaning
2.11.2 System Quiesced (SYS_QUIESC)-Input
Following state timing descriptions system quiesced (SYS_QUIESC) input signal which system uses indicate that ready enter soft-stop state. State Meaning Asserted-Enables soft stop 601. Negated-The soft-stop state enabled 601. Systems that SYS_QUIESC should low. Timing Comments Assertion/Negation-Must meet setup hold times described PowerPC RISC Microprocessor Hardware Specifications.
2.11.3 Resume (RESUME)-Input
Following state timing descriptions RESUME input signal, which system uses indicate that resume normal operations. State Meaning Asserted-The resume normal operations after soft stop. Negated-The cannot resume normal operations soft stop occurred. Systems that this signal should low. Timing Comments Assertion-Can occur time. asserted asynchronously input clock, must asserted least three clock cycles. asserted synchronously, must asserted least clock cycles. Negation-Can occur after minimum pulse width been met.
Chapter Signal Descriptions
2-31
2.11.4 Quiescent Request (QREQ)-Output
Following state timing descriptions quiescent request (QREQ) output signal, which uses request that system enter quiescent state. State Meaning Asserted-The requesting activity normally required snooped terminate pause enter lowpower (nap sleep) state. Once entered this state longer snoops activity. Negated-The requesting enter quiescent state.
Timing Comments Assertion-Can occur time indicate request enter quiescent state, during which keeps asserting QREQ. Negation-Can occur whenever quiescent state requested.
2.11.5 Quiescent Acknowledge (QACK)-Input
Following state timing descriptions quiescent acknowledge (QACK) input, which system uses indicate that ready enter low-power state. State Meaning Asserted-All activity that requires snooping terminated paused enter low-power state. Negated-The cannot enter low-power state. Timing Comments Assertion/Negation-May occur cycle after assertion QREQ must held minimum clock cycle. Start-up-QACK sampled negation HRESET select reduced-pinout mode; QACK asserted start-up, reducedpinout mode disabled. Section 6.4, "Reduced-Pinout Mode (603)," description reduced pinout mode.
2.11.6 Halted (HALTED)-Output
Following state timing descriptions HALTED output signal which uses indicate other system components that processor been halted. Asserted-The enters idle state result mode. Dispatch execution stops processor idle. Negated-The processor idle state. Timing Comments Assertion/Negation-Synchronous with processor clock. State Meaning
2.11.7 (RUN)-Input
Following state timing descriptions input signal, which used notify that snooping required.
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PowerPC Microprocessor Family: Interface 32-Bit Microprocessors
State Meaning
Asserted-Forces internal processor clocks continue running, even mode active, allowing snooping occur. HALTED deasserted indicate activity reasserted indicate when processor idle when deasserted. Negated-Internal processor clocks stop running mode.
Timing Comments Assertion-May occur time asynchronously input clocks. maximum latency between being asserted starting internal processor clocks three clock cycles. Negation-Can occur after HALTED signal asserted.
2.11.7.1 Going from Normal Doze State (604e)
only state transition allowed from normal state doze state. This transition requires system support. system must assert least cycles before software power management sequence begin. does affect 604e operation normal state, does affect operation during transition from normal doze state. software power management sequence following code:
sync mtmsr isync branch sync instruction
mtmsr instruction should modify power management MSR[POW] only. other values such external interrupt enable should before software power management sequence begun. When mtmsr executed, processor waits internal state idle then asserts HALTED, which point processor doze state. When entering doze state, system must assert least cycles after HALTED asserted. When processor doze state, HALTED deasserted when snoop-triggered write-back progress. system must keep asserted whenever HALTED deasserted doze mode snoop write-back operation. software power management sequence initiated from normal state with asserted, processor would attempt directly state. This transition supported cause system hang later when processor leaves state.
2.11.7.2 Going from Doze State
processor from doze state, system must first ensure that idle that HALTED asserted least cycles. system should then deassert continue prevent grants least additional cycles, which point processor state transactions resumed. processor does snoop subsequent transactions. going from doze state, 604e must idle, which here means that 604e cannot receive XATS assertions. system ensure this negating address grants other devices.
Chapter Signal Descriptions
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2.11.7.3 Going from Doze State
processor from doze state, system should ensure idle least cycles, assert RUN, withhold grants least additional cycles. this point processor doze state transactions snooped.
2.12 Summary Signal Differences
Table lists each signal describes substantive differences between different implementations. clock, power, test signals described this document. Refer user's manual particular processor this information.
Table 2-8. Processor Signal Differences
Signal(s) Difference Address Arbitration Signals request (BR) output, assertion occurs when transaction needed device does have qualified grant. This occur even maximu
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