Operating voltage: 2.2V~5.2V Eight bidirectional lines input lines ext
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HT49C10 8-Bit Microcontroller
Operating voltage: 2.2V~5.2V Eight bidirectional lines input lines external interrupt input 8-bit programmable timer/event counter Watchdog timer On-chip crystal oscillator program memory data memory Real Time Clock (RTC) 8-bit prescaler
Buzzer output Halt function wake-up feature reduce power consumption driver with segments 4-level subroutine nesting manipulation instruction 14-bit table read instruction instruction cycle with 4MHz system clock powerful instructions instructions machine cycles 48-pin SSOP package
General Description
HT49C10 8-bit high performance single chip microcontroller. single-cycle instruction two-stage pipeline architecture make suitable high speed applications. device also suited multiple power applications among which calculators, clock timers, games, scales, leisure products, other hand held products, battery systems particular.
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HT49C10
Block Diagram
ifte
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HT49C10
Assignment
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HT49C10
Assignment
PA3/PFD PA1/BZ PA0/BZ OSC1 OSC2 PB0/INT0 PB1/INT1 PB2/TMR VLCD COM0 COM1 COM2 SEG18/COM3 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 (0,0) SEG11 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10
OSC3
OSC4
substrate should connected layout artwork.
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HT49C10
Description
Name Mask Option Description PA0~PA7 constitute 8-bit bidirectional input/ output port with Schmitt trigger input capability. Each port configured wake-up input mask option. PA0~PA3 configured CMOS (output) NMOS (input/output) with without pull-high resistor mask option, PA4~PA7 always pull-high NMOS (input/output). eight bits, PA0~PA1 pins buzzer outputs mask option. output also mask option. PB0~PB5 constitute 6-bit Schmitt trigger input port. Each port pull-high resistor. bits, input external interrupt control (INT0) software application. input external interrupt control (INT1) software application. While input timer/event counter input also software application. Negative power supply, power supply Voltage pump SEG18 segment common output driver panel mask option. COM2~COM0 outputs panel plate. driver outputs panel segments Real time clock oscillators Positive power supply
PA0/BZ PA1/BZ PA3/PFD PA4~PA7
Wake-up Pull-high None CMOS NMOS
8~10
PB0/INT0 PB1/INT1 PB2/TMR PB3~PB5
13~16 19~17 21~38
VLCD V1,V2,C1,C2 SEG18/COM3 COM2~COM0 SEG17~SEG0 OSC4 OSC3 OSC2 OSC1
Duty
OSC1 OSC2 connected network Crystal crystal mask option) internal system clock. case operation, OSC2 output terminal system clock. Schmitt trigger reset input, active
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HT49C10
Absolute Maximum Ratings
Supply Voltage.-0.3V 5.5V Input Voltage .VSS-0.3V VDD+0.3V Storage Temperature.-50°C 125°C Operating Temperature .-25°C 70°C
Note: These stress ratings only. Stresses exceeding range specified under Maximum cause substantial damage device. Functional operation this device other conditions beyond those listed specification implied prolonged exposure extreme conditions affect device reliability.
D.C. Characteristics
Symbol IDD1 IDD2 ISTB1 ISTB2 VIL1 VIH1 Parameter Operating Voltage Operating Current (Crystal OSC) Operating Current OSC) Standby Current (RTC Enable, Standby Current (RTC Disable, Off) Input Voltage Ports Input High Voltage Ports Input Voltage (RES, INT0, INT1, TMR) Input High Voltage (RES, INT0, INT1, TMR) Ports Sink Current Ports Source Current Pull-high Resistance Ports INT0, INT1 Test Conditions Conditions load, fSYS=4MHz load, fSYS=2MHz load, system Halt load, system Halt RES=0.5VDD INT0/1=0.3VDD TMR=0.3VDD 0.8VDD VOL=0.3V VOL=0.5V VOH=2.7V VOH=4.5V Min. Typ. -1.5
Ta=25°C Max. 1.5/0.9 2.5/1.5 Unit
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A.C. Characteristics
Symbol fSYS1 fSYS2 fTIMER Parameter System Clock (Crystal OSC) System Clock OSC) Timer Frequency (TMR) Test Conditions Conditions Power-up wake-up from halt Min. Typ. 1024 Max. 4000 4000 2000 3000 4000 4000 Ta=25°C Unit tSYS
tWDTOSC Watchdog Oscillator tRES tSST tINT External Reset Pulse Width System Start-up Timer Period Interrupt Pulse Width
Note: tSYS=1/fSYS
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Functional Description
Execution flow system clock derived from either crystal oscillator. internally divided into four non-overlapping clocks. instruction cycle consists four system clock cycles. Instruction fetching execution pipelined such that fetch takes instruction cycle while decoding execution takes next instruction cycle. pipelining scheme causes each instruction effectively execute cycle. instruction changes value program counter, cycles required complete instruction. Program counter 10-bit program counter (PC) controls sequence which instructions stored program executed. contents specify maximum 1024 addresses. After accessing program memory word fetch instruction code, value incremented one. then points memory word containing next instruction code. When executing jump instruction, conditional skip execution, loading register, subroutine call, initial reset, internal interrupt, external interrupt, returning from subroutine, manipulates program transfer loading address corresponding each instruction.
conditional skip activated instructions. Once condition met, next instruction, fetched during current instruction execution, discarded dummy cycle replaces proper instruction; otherwise proceed with next instruction. lower byte (PCL) readable writeable register (06H). Moving data into performs short jump. destination within locations. When control transfer takes place, additional dummy cycle required. Program memory program memory (ROM) used store program instructions which executed. also contains data, table, interrupt entries, organized into bits which addressed table pointer. Certain locations reserved special usage:
Location 000H
Location 000H reserved program initialization. After chip reset, program always begins execution this location.
Location 004H
Location 004H reserved external interrupt service program. INT0 input activated, interrupt enabled, stack full, program begins execution location 004H.
Execution flow
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Location 008H
Location 008H reserved external interrupt service program. INT1 input activated, interrupt enabled, stack full, program begins execution location 008H.
Location 00CH
itia
Location 00CH reserved timer/event counter interrupt service program. timer interrupt resulting from timer/event counter overflow, interrupt enabled stack full, program begins execution location 00CH.
Location 010H
Location 010H reserved time base interrupt service program. time base interrupt occurs, interrupt enabled, stack full, program begins execution location 010H.
Location 014H
Program memory
Table location
Location 014H reserved real time clock interrupt service program. real time clock interrupt occurs, interrupt enabled, stack full, program begins execution location 014H. Mode Initial reset External interrupt External interrupt Timer/event Counter overflow Time Base Interrupt Interrupt Skip Loading Jump, Call Branch Return From Subroutine
location used look-up table. instructions (the current page, page=256 words) (the last page) transfer conProgram Counter
PC+2
Program counter Note: *9~*0: Program counter bits #9~#0: Instruction code bits
S9~S0: Stack register bits @7~@0: bits
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tents lower-order byte specified data memory, contents higher-order byte TBLH (table higher-order byte register) (08H). Only destination well-defined; other bits table word transferred lower portion TBLH, remaining bits both read TBLH read only, table pointer (TBLP) read/write register (07H), indicating table location. Before accessing table, location should placed TBLP. table related instructions require cycles complete operation. These areas function normal dependingupontherequirements. Stack register STACK stack register special part memory used save contents stack organized into four levels neither part data part program, neither readable writeable. activated level indexed stack pointer (SP) neither readable writeable. commencement subroutine call interrupt acknowledgment, contents pushed onto stack. subroutine interrupt routine, signaled return instruction (RET RETI), contents restored previous value from stack. After chip reset, will point stack. stack full non-masked interrupt takes place, interrupt request flag recorded acknowledgment still inhibited. Once decremented RETI), inInstruction(s) TABRDC TABRDL terrupt serviced. This feature prevents stack overflow, allowing programmer structure easily. Likewise, stack full, subsequently executed, stack overflow occurs first entry lost (only most recent four return addresses stored). Data memory data memory (RAM) designed with bits, divided into functional groups, namely special function registers general purpose data memory, most which readable/writeable, although some read only. types functional groups, special function registers consist indirect addressing register (00H), memory pointer register (MP0; 01H), indirect addressing register (02H), memory pointer register (MP1;03H), bank pointer (BP;04H), accumulator (ACC;05H), program counter lower-order byte register (PCL;06H), table pointer (TBLP;07H), table higher-order byte register (TBLH;08H), real time clock control register (RTCC;09H), status register (STATUS;0AH), interrupt control register (INTC0;0BH), timer/event counter (TMR;0DH), timer/event counter control register (TMRC; 0EH), registers (PA;12H, PB;14H), interrupt control register (INTC1;1EH). other hand, general purpose data memory, addressed from 5FH, used data control information under instruction commands. areas directly handle arithmetic, logic, increment, decrement, rotate operations. Except some dedicated bits, each reset They also indirectly accessible through memory pointer Table Location
Table location Note: *9~*0: Table location bits @7~@0: Table pointer bits
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P9~P8: Current program counter bits
HT49C10
register (MP0;01H) memory pointer register (MP1;03H).
(03H) respectively. Reading location indirectly returns result 00H, while, writing leads operation. function data movement between indirect addressing registers supported. memory pointer registers, MP1, both 7-bit registers used access combining corresponding indirect addressing registers. undefined reading will return result writing operation will only transfer lower 7-bit data. Only applied data memory, while applied data memory display memory. Accumulator accumulator (ACC) related operations. also mapped location capable carrying immediate data operations. data movement between data memory locations pass through ACC. Arithmetic logic unit This circuit performs 8-bit arithmetic logic operations provides following functions:
Arithmetic operations
(ADD, ADC, SUB, SBC, DAA)
Logic operations (AND, XOR, CPL) Rotation (RL, RLC, RRC) Increment Decrement (INC, DEC) Branch decision (SZ, SNZ, SIZ, etc.)
only saves results data operation also changes status register. Status register STATUS status register (0AH) 8-bit wide contains carry flag (C), auxiliary carry flag (AC), zero flag (Z), overflow flag (OV), power down flag (PD), watchdog time-out flag (TO). also records status information controls operation sequence. Except flags, bits status register altered instructions, similar other registers. Data written into status reg11 September 1999
mapping Indirect addressing register Location indirect addressing registers that physically implemented. read/write operation [00H] [02H] accesses pointed (01H)
HT49C10
Labels Bits Function operation results carry during addition operation borrow does take place during subtraction operation; otherwise cleared. also affected rotate through carry instruction. operation results carry nibbles addition borrow from high nibble into nibble subtraction; otherwise cleared. result arithmetic logic operation zero; otherwise cleared. operation results carry into highest-order carry highest-order bit, vice versa; otherwise cleared. cleared either system power-up executing instruction. executing instruction. cleared system power-up executing instruction. time-out. Undefined, read STATUS register ister does alter flags. Operations related status register, however, yield different results from those intended. flags only changed watchdog timer overflow, chip power-up, clearing watchdog timer executing instruction. flags reflect status latest operations. entering interrupt sequence executing subroutine call, status register will pushed onto stack automatically. contents status important, subroutine likely corrupt status register, precautions should taken save properly. Interrupts HT49C10 provides external interrupts, internal timer/event counter interrupt, internal time base interrupt, internal real time clock interrupt. interrupt control register (INTC0;0BH) interrupt control register (INTC1;1EH) both contain interrupt control bits that used enable/disable status interrupt request flags. Once interrupt subroutine serviced, other
interrupts blocked clearing bit). This scheme prevent further interrupt nesting. Other interrupt requests take place during this interval, only interrupt request flag will recorded. certain interrupt requires servicing within service routine, programmer corresponding INTC0 INTC1 order allow interrupt nesting. Once stack full, interrupt request will acknowledged, even related interrupt enabled, until decremented. immediate service desired, stack should prevented from becoming full. these interrupts have wake-up capability. When interrupt serviced, control transfer occurs pushing onto stack, followed branch subroutines specified locations ROM. Only pushed onto stack. contents register status register (STATUS) altered interrupt service program which corrupts desired control sequence, contents should saved first. External interrupts triggered high transition INT0 INT1, related
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Register INTC0 (0BH) INTC1 (1EH) Label EEI0 EEI1 EIF0 EIF1 ETBI ERTI Function Control master (global) interrupt enabled; disabled) Control external interrupt enabled; disabled) Control external interrupt enabled; disabled) Control timer/event counter interrupt enabled; disabled) External interrupt request flag active; inactive) External interrupt request flag active; inactive) Internal timer/event counter request flag active; inactive) Unused bit, read Control time base interrupt enabled; disabled) Control real time clock interrupt enabled; disabled) Unused bit, read Time base request flag active; inactive) Real time clock request flag active; inactive) Unused bit, read INTC register interrupt request flag (EIF0; INTC0, EIF1; INTC0) well. After interrupt enabled, stack full, external interrupt active, subroutine call location occurs. interrupt request flag (EIF0 EIF1) bits cleared disable other interrupts. internal timer/event counter interrupt initialized setting timer/event counter interrupt request flag (TF; INTC0), that caused timer overflow. After interrupt enabled, stack full, set, subroutine call location occurs. related interrupt request flag
(TF) reset, cleared disable further interrupts. time base interrupt initialized setting time base interrupt request flag (TBF; INTC1), that caused regular time base signal. After interrupt enabled, stack full, set, subroutine call location occurs. related interrupt request flag (TBF) reset cleared disable further interrupts. real time clock interrupt initialized setting real time clock interrupt request flag (RTF; INTC1), that caused
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regular real time clock signal. After interrupt enabled, stack full, set, subroutine call location occurs. related interrupt request flag (RTF) reset cleared disable further interrupts. During execution interrupt subroutine, other interrupt acknowledgments held until instruction executed related interrupt control both stack full). return from interrupt subroutine, invoked. RETI sets enables interrupt service, does not. Interrupts occurring interval between rising edges consecutive pulses serviced latter pulses corresponding interrupts enabled. case simultaneous requests, following table shows priority that applied. These masked resetting bit. Interrupt Source Priority Vector External interrupt External interrupt Timer/event counter overflow Time base interrupt Real time clock interrupt status interrupts. These bits prevent requested interrupt from being serviced. Once interrupt request flags (RTF, TBF, EIF1, EIF0) set, they remain INTC1 INTC0 respectively until interrupts serviced cleared software instruction. recommended that program within interrupt subroutine. because interrupts often occur unpredictable manner require serviced immediately some applications. this time, only stack left, enabling interrupt well controlled, operation interrupt subroutine damage original control sequence. Oscillator configuration HT49C10 provides oscillator circuits system clocks, i.e., oscillator crystal oscillator, determined mask option. matter what type oscillator selected, signal used system clock. HALT mode stops system oscillator ignores external signal conserve power. oscillators, oscillator used, external resistor between OSC1 required, range resistance should from 51kW 1MW. system clock,
timer/event counter interrupt request flag (TF), external interrupt request flag (EIF1), external interrupt request flag (EIF0), enable timer/event counter interrupt (ETI), enable external interrupt (EEI1), enable external interrupt (EEI0), enable master interrupt (EMI) make interrupt control register (INTC0) which located RAM. real time clock interrupt request flag (RTF), time base interrupt request flag (TBF), enable real time clock interrupt (ERTI), enable time base interrupt (ETBI), other hand, constitute other interrupt control register (INTC1) which located RAM. EMI, EEI0, EEI1, ETI, ETBI, ERTI used control enable/disable
illa
illa
System oscillator
oscillator
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divided available OSC2 with pull-high resistor, which used synchronize external logic. oscillator provides most cost effective solution. However, frequency oscillation vary with VDD, temperature, chip itself process variations. therefore, suitable timing sensitive operations where accurate oscillator frequency desired. other hand, crystal oscillator selected, crystal across OSC1 OSC2 needed provide feedback phase shift required oscillator, other external components required. resonator connected between OSC1 OSC2 replace crystal frequency reference, external capacitors OSC1 OSC2 needed. There another oscillator circuit designed real time clock. this case, only 32.768kHz crystal oscillator applied. crystal should connected between OSC3 OSC4, external capacitors along with external resistor required oscillator circuit order stable frequency. oscillator circuit controlled oscillate quickly setting (bit RTCC). recommended turn quick oscillating function upon power turn after seconds. oscillator free running on-chip oscillator, external components required. Although system enters power down mode, system clock stops, oscillator still works with period approximately oscillator disabled mask option conserve power. Watchdog timer clock source implemented dedicated oscillator (WDT oscillator) instruction clock (system clock/4) real time clock oscillator (RTC oscillator). timer designed prevent software malfunction sequence from jumping unknown location with unpredictable results. disabled mask option. disabled, executions related lead operation. After clock source selected, time-out period fs/215~fs/216. clock source chooses internal oscillator, time-out period vary with temperature, VDD, process variations. other hand, clock source selects instruction clock instruction executed, stop counting lose protecting purpose, logic only restarted external logic. When device operates noisy environment, using on-chip oscillator (WDT OSC) strongly recommended, since HALT stop system clock. overflow under normal operation initializes sets status HALT mode, overflow initializes only reset zero. clear contents WDT, there three methods adopted, i.e., external reset level RES), software instruction, instruction. There sets software instructions, other these types instructions, only type instruction active time depending mask option
Watchdog timer
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times selection selected (i.e., times equal one), execution instruction clears WDT. case that chosen (i.e., times equal two), these instructions have executed clear WDT; otherwise, reset chip because time-out. Multi-function timer HT49C10 provides multi-function timer WDT, time base with different time-out periods. multi-function timer consists 7-stage divider 8-bit prescaler, with clock source coming from instruction clock (i.e., system clock divided multi-function timer also provides selectable frequency signal (ranges from fs/22 fs/28) driver circuits, selectable frequency signal (ranges from fs/22 fs/29) buzzer output mask option. recommended select 4kHz signal driver circuits proper display. Time base time base offers periodic time-out period generate regular internal interrupt. time-out period ranges from fs/212 fs/215 selected mask option. time base time-out occurs, related interrupt request flag (TBF; INTC1) set. interrupt enabled, stack full, subroutine call location occurs. Real time clock real time clock (RTC) operated same manner time base that used supply regular internal interrupt.
time-out period ranges from fs/28 fs/215 software programming (recommand 212~215). Writing data RT2, (bits RTCC;09H) yields various time-out periods. time-out occurs, related interrupt request flag (RTF; INTC1) set. interrupt enabled, stack full, subroutine call location occurs. real time clock time-out signal also applied clock source timer/event counter longer time-out period. Clock Divided Factor
Power down operation HALT HALT mode initialized instruction results following.
system oscillator turns
oscillator keeps running oscillator real time clock selected). registers remain unchanged.
contents on-chip cleared start recounting
clock source from oscillator real time clock oscillator).
Time base
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ports maintain their original status. flag flag cleared. driver still running
selected).
system quits HALT mode external reset, interrupt, external falling edge signal port overflow. external reset causes device initialization, overflow performs After examining flags, reason chip reset determined. flag cleared system power-up executing instruction, executing instruction. other hand, flag time-out occurs, causes wake-up that only resets (Program Counter) leaves others their original state. port wake-up interrupt methods considered continuation normal execution. Each port independently selected wake device mask option. Awakening from port stimulus, program resumes execution next instruction. other hand, awakening from interrupt, sequences occur. related interrupt disabled interrupt enabled, stack full, program resumes execution next instruction. interrupt enabled, stack full, regular interrupt response takes place. When interrupt request flag before entering status, system cannot awaken using that interrupt. wake-up event occurs, takes 1024 tSYS (system clock period) resume normal operation. other words, dummy period inserted. wake-up results from interrupt
acknowledgment, actual interrupt subroutine execution delayed more than cycle. However, wake-up results next instruction execution, execution will performed immediately after dummy period finished. minimize power consumption, pins should carefully managed before entering HALT status. Reset There three ways which reset occur.
reset during normal operation reset during HALT time-out reset during normal operation
time-out during HALT differs from other chip reset conditions, perform that resets only leaves other circuits their original state. Some registers remain unaffected during other reset conditions. Most registers reset once reset conditions met. Examining flags, program distinguish between different RESET Conditions reset during power-up reset during normal operation wake-up HALT time-out during normal operation wake-up HALT
Note: means
Real time clock
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functional unit chip reset status shown below. Interrupt Prescaler, divider Reset timing chart
000H Disabled Cleared Clear. After master reset, begins counting Input mode Points stack
WDT, RTC, time base Timer/event counter Input/output ports
Reset circuit
Reset configuration guarantee that crystal oscillator started stabilized, (System Start-up Timer) provides extra-delay 1024 system clock pulses when system powers awakes from HALT state. Awaking from HALT state system power-up, delay added. extra delay added during power-up period, wake-up from HALT enable delay only.
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states registers summarized below. Register TMRC Program Counter TBLP TBLH STATUS INTC0 INTC1 RTCC Reset (Power xxxx xxxx 0000 1-000H xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx -000 0000 0111 1111 1111 1111 Time-out (Normal Operation) uuuu uuuu 0000 1-000H uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -000 0000 0111 1111 1111 1111 Reset (Normal Operation) uuuu uuuu 0000 1-000H uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -000 0000 0111 1111 1111 1111 Reset (HALT) uuuu uuuu 0000 1-000H uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -000 0000 0111 1111 1111 1111 Time-out (HALT) uuuu uuuu uuuu u-000H* uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu uuuu uuuu uuuu uuuu
Note: means means means
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HT49C10
Timer/event counter timer/event counter (TMR) implemented HT49C10. timer/event counter contains 8-bit programmable count-up counter, clock source come from system clock instruction clock (system clock/4) time-out signal external source. System clock source instruction clock selected mask option. external clock input allows user count external events, measure time intervals pulse widths, generate accurate time base. There registers related timer/event counter, i.e., ([0DH]) TMRC ([0EH]). physical registers mapped location; writing locates starting value timer/event counter preload register, while reading yields contents timer/event counter. TMRC timer/event counter control register which defines some options. bits define operation mode. event count mode used count external events, which means that clock source from external (TMR) pin. timer mode functions normal timer with clock source coming from internal selected clock source. Finally, pulse width measurement mode used count high level duration external signal (TMR), counting based internal selected clock source.
event count timer mode, timer/event counter starts counting current contents timer/event counter ends FFH. Once overflow occurs, counter reloaded from timer/event counter preload register, generates interrupt request flag (TF; INTC0). pulse width measurement mode with values bits equal one, after received transient from high high will start counting until returns original level resets TON. measured result remains timer/event counter even activated transient occurs again. other words, only cycle measurement done. Until setting TON, cycle measurement will re-function long receives further transient pulse. this operation mode, timer/event counter begins counting according logic level transient edges. case counter overflows, counter reloaded from timer/event counter preload register issues interrupt request, other modes, i.e., event timer modes. enable counting operation, Timer (TON; TMRC) should pulse width measurement mode, automatically cleared after measurement cycle completed. other modes,
Timer/event counter
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Label (TMRC) Bits Unused bits, read Defines active edge timer/event counter (0=active high; 1=active high low) Enable/disable timer counting (0=disabled; 1=enabled) multiplexer control inputs select timer/event counter clock source (0=RTC output; 1=system clock system clock/4) Defines operating mode 01=Event count mode (external clock) 10=Timer mode (internal clock) 11=Pulse Width measurement mode (external clock) 00=Unused TMRC register only reset instructions. overflow timer/event counter wake-up sources also applied (Programmable Frequency Divider) output mask option. matter what operation mode writing disables interrupt service. When function selected, executing instruction enable output executing instruction disable output. case timer/event counter condition, writing data timer/event counter preload register also reloads that data timer/event counter. timer/event counter timer/event counter kept only timer/event counter preload register. timer/event counter still goes operating until overflow occurs. When timer/event counter (reading TMR) read, clock blocked avoid errors. this results counting error, this should taken into account programmer. strongly recommended load first specific value into register, then turn timer/event counter proper operation. Because initial value unknown. Input/output ports There 8-bit bidirectional input/output port 6-bit input port HT49C10, labeled which mapped [12H] [14H] RAM, respectively. PA0~PA3 configured CMOS (output) NMOS (input/output) with without pull-high resistor mask option, PA4~PA7 always pull-high NMOS (input/output). only used input operation, each port with pull-high resistor. Both input operation, these ports non-latched, that inputs should ready rising edge instruction (m=12H 14H). output operation, data latched remain unchanged until output latch rewritten. When structures open drain NMOS type, should noted that, before reading data from pads, should written related bits disable NMOS device. That executing first instruction (i=0~7 disable related NMOS device, then stable data. Function
TN0,
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input/output port
input lines After chip reset, these input lines remain high level left floating mask option). Each these output latches cleared (m=12H) instructions.
Some instructions first input data then follow output operations. example, read entire port states into CPU, execute defined operations (bit-operation), then write results back latches accumulator. display memory HT49C10 provides area embedded data memory display. This area located from Bank Bank pointer (BP; located RAM) switch between display memory. When data
Display memory
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HT49C10
Register Label Read/Write Reset RTCC (09H) QOSC Function multiplexer control inputs select real time clock prescaler output Unused bits, read Control oscillate quickly. enable disable Unused bits, read
RTCC register written into 40H~52H will affect display. When cleared data written into 40H~52H means access general purpose data memory. display memory read written only indirect addressing mode using MP1. When data writxten into display data area automatically read driver which then generates corresponding driving signals. turn display Off, written corresponding display memory, respectively. figure illustrates mapping between display memory pattern HT49C10. driver output output number HT49C10 driver mask option (i.e., duty duty duty). bias type driver type type. bias type selected, external capacitor required. bias type selected, capacitor mounted between pins needed. bias voltage driver bias bias mask option. bias selected, capacitor mounted between ground required. bias selected, capacitors needed pins. Please refer application diagram. Buzzer HT49C10 provides pair buzzer output which share pins with respectively, determined mask option. output frequency selected mask option. When buzzer function selected, setting PA.0 PA.1 simultaneously will enable buzzer output setting PA.0 will disable buzzer output.
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HT49C10
driver output (1/3 duty, bias, type)
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HT49C10
driver output (1/4 duty, bias, type)
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HT49C10
Mask option following shows kinds mask options HT49C10. these options should defined order ensure proper system functioning. Mask Option type selection. This option decide crystal oscillator selected system clock. Clock source selection WDT, Time Base. There three types selection: system clock/4 OSC. enable/disable selection. enabled disabled mask option. times selection. This option defines clear instruction. time means that clear WDT. means only both have been executed, cleared. Time Base time-out period selection. Time Base time-out period ranges from fs/2 fs/2 means clock source selected mask option.
Buzzer output frequency selection. There eight types frequency signals buzzer out2 put: fs/2 ~fs/2 means clock source selected mask option. Wake-up selection. This option defines wake-up function activity. External pins only) have capability wake-up chip from HALT falling edge. Pull-high selection. This option decide whether pull-high resistance viable PA0~PA3. CMOS NMOS selection. PA0~PA3 selected CMOS NMOS structure, PA4~PA7 always NMOS. When CMOS selected, related pins only used output operations. When NMOS selected, related pins used input output operations. Clock source selection timer/event counter. There types selection: system clock system clock/4. pins share with other functions selection. PA0/BZ, PA1/BZ: pins buzzer outputs. PA3/PFD: pins output. common selection. There three types selection: commons (1/2 duty) commons (1/3 duty) commons (1/4 duty). commons selected, segment output will common output. bias power supply selection. There types selection: bias bias. bias type selection. This option decide what kind bias selected, type type. driver clock selection. There seven types frequency signals driver circuits: fs/2 ~fs/2 means clock source selected mask option.
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HT49C10
Application Circuits
illa illa
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Instruction Summary
Mnemonic Arithmetic A,[m] ADDM A,[m] A,[m] ADCM A,[m] A,[m] SUBM A,[m] A,[m] SBCM A,[m] Logic Operation A,[m] A,[m] A,[m] ANDM A,[m] A,[m] XORM A,[m] CPLA Increment Decrement INCA DECA Rotate RRCA RLCA Rotate data memory right with result Rotate data memory right Rotate data memory right through carry with result Rotate data memory right through carry Rotate data memory left with result Rotate data memory left Rotate data memory left through carry with result Rotate data memory left through carry None None None None Increment data memory with result Increment data memory Decrement data memory with result Decrement data memory data memory data memory Exclusive-OR data memory data memory data memory Exclusive-OR data memory immediate data immediate data Exclusive-OR immediate data Complement data memory Complement data memory with result data memory data memory immediate data data memory with carry register with carry Subtract immediate data from Subtract data memory from Subtract data memory from with result data memory Subtract data memory from with carry Subtract data memory from with carry result data memory Decimal adjust addition with result data memory Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Description Flag Affected
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HT49C10
Mnemonic Data Move A,[m] [m],A Operation [m].i [m].i Branch addr [m].i [m].i SIZA SDZA CALL addr RETI Table Read TABRDC TABRDL Miscellaneous WDT1 WDT2 SWAP SWAPA HALT operation Clear data memory data memory Clear Watchdog timer Pre-clear watchdog timer Pre-clear watchdog timer Swap nibbles data memory Swap nibbles data memory with result Enter power down mode None None None TO,PD TO*,PD* TO*,PD* None None TO,PD Read code (current page) data memory TBLH Read code (last page) data memory TBLH None None Jump unconditionally Skip data memory zero Skip data memory zero with data movement Skip data memory zero Skip data memory zero Skip increment data memory zero Skip decrement data memory zero Skip increment data memory zero with result Skip decrement data memory zero with result Subroutine call Return from subroutine Return from subroutine load immediate data Return from interrupt None None None None None None None None None None None None None Clear data memory data memory None None Move data memory Move data memory Move immediate data None** None None Description Flag Affected
Note: 8-bit immediate data bits data memory address accumulator number bits addr: 10-bit program memory address Flag affected Flag affected Flag affected execution status
version E.V. chip, zero flag affected executing A,[M] instruction. version E.V. chip, zero flag cannot changed executing A,[M] instruction.
September 1999
HT49C10
Instruction Definition
A,[m] Description Operation Affected flag(s) ADCM A,[m] Description Operation Affected flag(s) A,[m] Description Operation Affected flag(s) Description Operation Affected flag(s) data memory carry accumulator contents specified data memory, accumulator carry flag added simultaneously, leaving result accumulator. ACC+[m]+C
accumulator carry data memory contents specified data memory, accumulator carry flag added simultaneously, leaving result specified data memory. ACC+[m]+C
data memory accumulator contents specified data memory accumulator added. result stored accumulator. ACC+[m]
immediate data accumulator contents accumulator specified data added, leaving result accumulator. ACC+x
September 1999
HT49C10
ADDM A,[m] Description Operation Affected flag(s) A,[m] Description Operation Affected flag(s) Description Operation Affected flag(s) ANDM A,[m] Description Operation Affected flag(s) accumulator data memory contents specified data memory accumulator added. result stored data memory. ACC+[m]
Logical accumulator with data memory Data accumulator specified data memory perform bitwise logical_AND operation. result stored accumulator.
Logical immediate data accumulator Data accumulator specified data perform bitwise logical_AND operation. result stored accumulator.
Logical data memory with accumulator Data specified data memory accumulator perform bitwise logical_AND operation. result stored data memory.
September 1999
HT49C10
CALL addr Description Subroutine call instruction unconditionally calls subroutine located indicated address. program counter increments once obtain address next instruction, pushes this onto stack. indicated address then loaded. Program execution continues with instruction this address. Stack PC+1 addr Description Operation Affected flag(s) [m].i Description Operation Affected flag(s) Description Operation Affected flag(s)
Operation Affected flag(s)
Clear data memory contents specified data memory cleared zero.
Clear data memory specified data memory cleared zero. [m].i
Clear watchdog timer cleared (re-counting from zero). power down (PD) time-out (TO) cleared.
September 1999
HT49C10
WDT1 Description Preclear watchdog timer flags cleared (re-counting from zero), other preclear instruction been executed. Only execution this instruction without other preclear instruction sets indicated flag which implies that this instruction been executed flags remain unchanged. 00H* WDT2 Description
Operation Affected flag(s)
Preclear watchdog timer flags cleared (re-counting from zero), other preclear instruction been executed. Only execution this instruction without other preclear instruction sets indicated flag which implies that this instruction been executed flags remain unchanged. 00H*
Operation Affected flag(s)
Description
Complement data memory Each specified data memory logically complemented complement). Bits which previously contained changed zero vice-versa.
Operation Affected flag(s)
September 1999
HT49C10
CPLA Description Complement data memory place result accumulator Each specified data memory logically complemented complement). Bits which previously contained changed zero vice-versa. complemented result stored accumulator contents data memory remain unchanged. Description
Operation Affected flag(s)
Decimal-Adjust accumulator addition accumulator value adjusted (Binary Code Decimal) code. accumulator divided into nibbles. Each nibble adjusted code internal carry (AC1) will done nibble accumulator greater than adjustment done adding original value original value greater than carry set; otherwise original value remains unchanged. result stored data memory only carry flag affected. ACC.3~ACC.0 AC=1 then [m].3~[m].0 (ACC.3~ACC.0)+6, AC1=AC else [m].3~[m].0) (ACC.3~ACC.0), AC1=0 ACC.7~ACC.4+AC1 then [m].7~[m].4 ACC.7~ACC.4+6+AC1,C=1 else [m].7~[m].4 ACC.7~ACC.4+AC1,C=C
Operation
Affected flag(s)
Description Operation Affected flag(s)
Decrement data memory Data specified data memory decremented one. [m]-1
September 1999
HT49C10
DECA Description Operation Affected flag(s) HALT Description Decrement data memory place result accumulator Data specified data memory decremented one, leaving result accumulator. contents data memory remain unchanged. [m]-1
Enter power down mode This instruction stops program execution turns system clock. contents registers retained. prescaler cleared. power down (PD) time-out (TO) cleared. PC+1
Operation
Affected flag(s)
Description Operation Affected flag(s)
Increment data memory Data specified data memory incremented one. [m]+1
INCA Description Operation Affected flag(s)
Increment data memory place result accumulator Data specified data memory incremented one, leaving result accumulator. contents data memory remain unchanged. [m]+1
September 1999
HT49C10
addr Description Operation Affected flag(s) A,[m] Description Operation Affected flag(s) Description Operation Affected flag(s) [m],A Description Operation Affected flag(s) Description Operation Affected flag(s) Directly jump contents program counter replaced with directly-specified address unconditionally, control passed this destination. addr
Move data memory accumulator contents specified data memory copied accumulator.
Move immediate data accumulator 8-bit data specified code loaded into accumulator.
Move accumulator data memory contents accumulator copied specified data memory (one data memories).
operation operation performed. Execution continues with next instruction. PC+1
September 1999
HT49C10
A,[m] Description Logical accumulator with data memory Data accumulator specified data memory (one data memories) perform bitwise logical_OR operation. result stored accumulator. Description Operation Affected flag(s) A,[m] Description
Operation Affected flag(s)
Logical immediate data accumulator Data accumulator specified data perform bitwise logical_OR operation. result stored accumulator.
Logical data memory with accumulator Data data memory (one data memories) accumulator perform bitwise logical_OR operation. result stored data memory.
Operation Affected flag(s)
Description Operation Affected flag(s)
Return from subroutine program counter restored from stack. This two-cycle instruction. Stack
September 1999
HT49C10
Description Operation Affected flag(s) RETI Description Return place immediate data accumulator program counter restored from stack accumulator loaded with specified 8-bit immediate data. Stack
Return from interrupt program counter restored from stack, interrupts enabled setting bit. enable master (global) interrupt (bit register INTC). Stack
Operation Affected flag(s)
Description Operation Affected flag(s)
Rotate data memory left contents specified data memory rotated left with rotated into [m].(i+1) [m].i; [m].i:bit data memory (i=0~6) [m].0 [m].7
Description
Rotate data memory left place result accumulator Data specified data memory rotated left with rotated into leaving rotated result accumulator. contents data memory remain unchanged. ACC.(i+1) [m].i; [m].i:bit data memory (i=0~6) ACC.0 [m].7
Operation Affected flag(s)
September 1999
HT49C10
Description Rotate data memory left through carry contents specified data memory carry flag rotated left. replaces carry bit; original carry flag rotated into position. [m].(i+1) [m].i; [m].i:bit data memory (i=0~6) [m].0 [m].7 RLCA Description
Operation
Affected flag(s)
Rotate left through carry place result accumulator Data specified data memory carry flag rotated left. replaces carry original carry flag rotated into position. rotated result stored accumulator contents data memory remain unchanged. ACC.(i+1) [m].i; [m].i:bit data memory (i=0~6) ACC.0 [m].7
Operation
Affected flag(s)
Description Operation Affected flag(s)
Rotate data memory right contents specified data memory rotated right with rotated [m].i [m].(i+1); [m].i:bit data memory (i=0~6) [m].7 [m].0
September 1999
HT49C10
Description Rotate right-place result accumulator Data specified data memory rotated right with rotated into leaving rotated result accumulator. contents data memory remain unchanged. ACC.(i) [m].(i+1); [m].i:bit data memory (i=0~6) ACC.7 [m].0 Description
Operation Affected flag(s)
Rotate data memory right through carry contents specified data memory carry flag together rotated right. replaces carry bit; original carry flag rotated into position. [m].i [m].(i+1); [m].i:bit data memory (i=0~6) [m].7 [m].0
Operation
Affected flag(s)
RRCA Description
Rotate right through carry-place result accumulator Data specified data memory carry flag rotated right. replaces carry original carry flag rotated into position. rotated result stored accumulator. contents data memory remain unchanged. ACC.i [m].(i+1); [m].i:bit data memory (i=0~6) ACC.7 [m].0
Operation
Affected flag(s)
September 1999
HT49C10
A,[m] Description Operation Affected flag(s) SBCM A,[m] Description Subtract data memory carry from accumulator contents specified data memory complement carry flag ACC+[m]+C
Subtract data memory carry from accumulator contents specified data memory complement carry flag subtracted from accumulator, leaving result data memory. ACC+[m]+C
Operation Affected flag(s)
Description
Skip decrement data memory zero contents specified data memory decremented one. result zero, next instruction skipped. result zero, following instruction, fetched during current instruction execution, discarded dummy cycle replaced proper instruction (two cycles). Otherwise proceed with next instruction (one cycle). Skip ([m]-1)=0, ([m]-1)
Operation Affected flag(s)
SDZA Description
Decrement data memory place result ACC, skip zero contents specified data memory decremented one. result zero, next instruction skipped. result stored accumulator data memory remains unchanged. result zero, following instruction, fetched during current instruction execution, discarded dummy cycle replaced proper instruction (two cycles). Otherwise proceed with next instruction (one cycle). Skip ([m]-1)=0, ([m]-1)
Operation Affected flag(s)
September 1999
HT49C10
Description Operation Affected flag(s) [m].i Description Operation Affected flag(s) Description data memory Each specified data memory one.
data memory Biti specified data memory one. [m].i
Skip increment data memory zero contents specified data memory incremented one. result zero, following instruction, fetched during current instruction execution, discarded dummy cycle replaced proper instruction (two cycles). Otherwise proceed with next instruction (one cycle). Skip ([m]+1)=0, ([m]+1)
Operation Affected flag(s)
SIZA Description
Increment data memory place result ACC, skip zero contents specified data memory incremented one. result zero, next instruction skipped result stored accumulator. data memory remains unchanged. result zero, following instruction, fetched during current instruction execution, discarded dummy cycle replaced proper instruction (two cycles). Otherwise proceed with next instruction (one cycle). Skip ([m]+1)=0, ([m]+1)
Operation Affected flag(s)
September 1999
HT49C10
[m].i Description Skip data memory zero specified data memory zero, next instruction skipped. data memory zero, following instruction, fetched during current instruction execution, discarded dummy cycle replaced proper instruction (two cycles). Otherwise proceed with next instruction (one cycle). Skip A,[m] Description Operation Affected flag(s) SUBM A,[m] Description Operation Affected flag(s) Description Operation Affected flag(s)
Operation Affected flag(s)
Subtract data memory from accumulator specified data memory subtracted from contents accumulator, leaving result accumulator. ACC+[m]+1
Subtract data memory from accumulator specified data memory subtracted from contents accumulator, leaving result data memory. ACC+[m]+1
Subtract immediate data from accumulator immediate data specified code subtracted from contents accumulator, leaving result accumulator. ACC+x+1
September 1999
HT49C10
SWAP Description Operation Affected flag(s) SWAPA Description Swap nibbles within data memory low-order high-order nibbles specified data memory (one data memories) interchanged. [m].3~[m].0 [m].7~[m].4
Swap data memory-place result accumulator low-order high-order nibbles specified data memory interchanged, writing result accumulator. contents data memory remain unchanged. ACC.3~ACC.0 [m].7~[m].4 ACC.7~ACC.4 [m].3~[m].0
Operation Affected flag(s)
Description
Skip data memory zero contents specified data memory zero, following instruction, fetched during current instruction execution, discarded dummy cycle replaced proper instruction (two cycles). Otherwise proceed with next instruction (one cycle). Skip [m]=0
Operation Affected flag(s)
Description
Move data memory ACC, skip zero contents specified data memory copied accumulator. contents zero, following instruction, fetched during current instruction execution, discarded dummy cycle replaced proper instruction (two cycles). Otherwise proceed with next instruction (one cycle). Skip [m]=0,
Operation Affected flag(s)
September 1999
HT49C10
[m].i Description Skip data memory zero specified data memory zero, following instruction, fetched during current instruction execution, discarded dummy cycle replaced proper instruction (two cycles). Otherwise proceed with next instruction (one cycle). Skip [m].i=0 TABRDC Description
Operation Affected flag(s)
Move code (current page) TBLH data memory byte code (current page) addressed table pointer (TBLP) moved specified data memory high byte transferred TBLH directly. code (low byte) TBLH code (high byte)
Operation Affected flag(s)
TABRDL Description Operation Affected flag(s)
Move code (last page) TBLH data memory byte code (last page) addressed table pointer (TBLP) moved data memory high byte transferred TBLH directly. code (low byte) TBLH code (high byte)
A,[m] Description Operation Affected flag(s)
Logical accumulator with data memory Data accumulator indicated data memory perform bitwise logical Exclusive_OR operation result stored accumulator.
September 1999
HT49C10
XORM A,[m] Description Logical data memory with accumulator Data indicated data memory accumulator perform bitwise logical Exclusive_OR operation. result stored data memory. zero flag affected. Description
Operation Affected flag(s)
Logical immediate data accumulator Data accumulator specified data perform bitwise logical Exclusive_OR operation. result stored accumulator. zero flag affected.
Operation Affected flag(s)
September 1999
HT49C10
Holtek Semiconductor Inc. (Headquarters) No.3 Creation Science-based Industrial Park, Hsinchu, Taiwan, R.O.C. Tel: 886-3-563-1999 Fax: 886-3-563-1189 Holtek Semiconductor Inc. (Taipei Office) No.576, Sec.7 Chung Hsiao Rd., Taipei, Taiwan, R.O.C. Tel: 886-2-2782-9635 Fax: 886-2-2782-9636 Fax: 886-2-2782-7128 (International sales hotline) Holtek Microelectronics Enterprises Ltd. RM.711, Tower Cheung Plaza, Cheung Rd., Kowloon, Hong Kong Tel: 852-2-745-8288 Fax: 852-2-742-8657 Copyright 1999 HOLTEK SEMICONDUCTOR INC. information appearing this Data Sheet believed accurate time publication. However, Holtek assumes responsibility arising from specifications described. applications mentioned herein used solely purpose illustration Holtek makes warranty representation that such applications will suitable without further modification, recommends products application that present risk human life malfunction otherwise. Holtek reserves right alter products without prior notification. most up-to-date information, please visit site http://www.holtek.com.tw.
September 1999
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