16-48K HCMOS WITH SCREEN DISPLAY VOLTAGE TUNING OUTPUT FUNCTIONAL

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16-48K HCMOS WITH SCREEN DISPLAY VOLTAGE TUNING OUTPUT FUNCTIONAL

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ST9291
16-48K HCMOS WITH SCREEN DISPLAY VOLTAGE TUNING OUTPUT
FUNCTIONAL DESCRIPTION
Register oriented 8/16 CORE with RUN, HALT modes Minimum instruction cycle time: 500ns (12MHz internal) bytes ROM, 384/640 bytes RAM, general purpose registers available RAM, accumulators index registers (Register File) 42-lead Shrink package 56-lead Shrink package Interrupt handler Serial Peripheral Interface standard features package) package) fully programmable pins character rows software programmable Screen Display module with colour, italic, underline, flash, transparent fringe attribute options 14-bit Voltage Synthesis tuning reference voltage. 8-bit outputs with repetition frequency 32kHz Open Drain Capability Timer with Prescaler, able used Watchdog Timer 16-bit programmable Slice Timer with 8-bit prescaler channel Analog Digital Converter, with integral sample hold, fast 5.75µs conversion time, 6-bit guaranteed resolution Rich Instruction Addressing modes Division-by-Zero trap generation Versatile Development tools, including assembler, linker, C-compiler, archiver, graphic oriented debugger hardware emulators Real Time Operating System Windowed EPROM parts available prototyping pre-production development phases
PSDIP42
PSDIP56
(Ordering Information Datasheet)
DEVICE SUMMARY
Device ST9291J2/N2 ST9291J3/N3 ST9291J4/N4 ST9291J5/N5 ST9291J6/N6 ST9291J7/N7 PACKAGE PSDIP42/56 PSDIP42/56 PSDIP42/56 PSDIP42/56 PSDIP42/56 PSDIP42/56
July 1995
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ST9291
Figure Shrink Pinout
Figure Shrink Pinout
VR01740B
VR01740A
ST9291J Description
name P2.0/INT7 RESET P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 P3.7 P3.6 P3.5 P3.4 P3.3/B P3.2/G P3.1/R P3.0/FB P5.1/SDIO P5.0/SCK/INT2 name P2.1/INT5/AIN1 P2.2/INT0/AIN2 P2.3/INT6/VSO1 P2.4/NMI P2.5/AIN3/VSO2 OSCIN OSCOUT P4.7/PWM7/ EXTRG (AD) P4.6/PWM6 P4.5/PWM5 P4.4/PWM4 P4.3/PWM3 P4.2/PWM2 P4.1/PWM1 P4.0/PWM0 VSYNC HSYNC AVDD PLLR PLLF
ST9291N Description
name P2.1/INT5/AIN1 P2.0/INT7 RESET P0.7 P0.6 P0.5 N.C.(1) P0.4 P0.3 P0.2 P0.1 P0.0 N.C.(1)
name P2.2/INT0/AIN2 P2.3/INT6/VSO1 P2.4/NMI P2.5/AIN3/VSO2 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 OSCIN OSCOUT P4.7/PWM7/ EXTRG (AD) P4.6/PWM6 P4.5/PWM5 P4.4/PWM4 P4.3/PWM3 P4.2/PWM2 P4.1/PWM1 P4.0/PWM0 VSYNC HSYNC AVDD PLLR PLLF
N.C.
P3.7 P3.6 P3.5 P3.4 P3.3/B P3.2/G P3.1/R P3.0/FB P5.3 P5.2 P5.1/SDIO P5.0/SCK/INT2
Notes Package only) N.C. means "not connected" Pins (VDD) internally connected
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GENERAL DESCRIPTION ST9291 member family microcontrollers, completely developed produced SGS-THOMSON Microelectronics using proprietary n-well HCMOS process. parts fully compatible with their EPROM (One-Time Programmable) versions, which used prototyping pre-production phases development. nucleus ST9291 advanced Core which includes Central Processing Unit (CPU), Register File, 16-bit Timer/Watchdog with 8-bit Prescaler, Serial Peripheral Interface supporting S-bus, I2C-bus IM-bus Interface, plus 8-bit ports. Core independent memory register buses allowing high degree pipelining efficiency code execution speed extensive instruction set. powerful capabilities demanded microcontroller applications fulfilled ST9291 with 32/42 lines dedicated digital Input/Output. These lines grouped into Ports configured basis under software control provide timing, status signals, timer inputs outputs, analog inputs, external interrupts, Screen Display) output serial parallel I/O. Three basic memory spaces available support this wide range configurations: Program Memory, Data Memory Register File, which includes control status registers on-chip peripherals. human interface provided Screen Display module, this produce lines characters from defined character set. 9x13 character modified different pixel sizes, with character rounding, formed into words with colour format attributes. 14-bit (Voltage Synthesis) output using (Pulse Width Modulation)/BRM (Bit Rate Modulation) present generate tuning voltages low-mid range applications. tuning voltage output separate output pins. 16-bit Slice Timer with 8-bit Prescaler also present.
Figure ST9291 Block Diagram
16-Bit TIMER/WATCHDOG+SPI
Bytes EPROM
Bytes
Bytes REGISTER FILE
SLICE TIMER
VOLTAGE SYNTHESIS
MEMORY Address Data REGISTER Address Data
PORT
PORT Analog Inputs
Converter
PORT
Screen Display
PORT P.W.M. Outputs AVDD
P.W.M. Converter
PORT
VSYNC HSYNC
Note SDIP shown
PLLR PLLF
VR01995E
Note EPROM version only
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GENERAL DESCRIPTION (Continued) control Satellite receiver setting done eight 8-bit outputs, with frequency maximum 23,437Hz 8-bit resolution (INTCLK 12MHz). resolutions with higher frequency operation programmed. addition thereis channelAnalog Digital Converter with integral sample hold, fast 5.75µs conversion time 6-bit guaranteedresolution. DESCRIPTION VSYNC. Vertical Sync. Vertical video synchronisation input OSD. Positive negative polarity. HSYNC. Horizontal Sync. Horizontal video synchronisation input OSD. Positive negative polarity. PLLF. Filter input. Filter input feed-back. PLLR. Resistor connection pin. resistor connection select gain adjust. RESET. Reset (input, active low). initialised Reset signal. With deactivationof RESET, program execution begins from Program memory location pointed vector contained program memory locations 01h. OSCIN, OSCOUT. Oscillator (input output). These pins connect parallel-resonant crystal (24MHz maximum), external source on-chip clock oscillator buffer. OSCIN input oscillator inverter internal clock generator; OSCOUT output oscillator inverter. AVDD. Analog PLL. This must tied externally ST9291. VDD. Main Power Supply Voltage (5V±10%) VSS. Digital Circuit Ground. P0.0-P0.7, P2.0-P2.5, P3.0-P3.7, P4.0-P4.7, P5.0-P5.1 suffix) P0.0-P0.7, P1.0-P1.7, P2.0-P2.5, P3.0-P3.7, P4.0-P4.7, P5.0-P5.3 suffix) Port Lines (Input/Output, CMOS compatible). 32/42 lines grouped into ports, programmable under program control general purpose Alternate functions (see next section). P4.0 P4.7 high voltage (12V) open drain outputs. voltage open drain output mode other bits must exceed VDD. Port Alternate Functions. Each ports ST9291 assume software programmable Alternative Functions shown Configuration Drawings. Table shows Functions allocated each Port pin.
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DESCRIPTION (Continued) Table 1.ST9291 Port Alternative Function Summary
PORT Port.bit P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P2.0 P2.1 P2.1 P2.2 P2.2 P2.3 P2.3 P2.4 P2.5 P2.5 P3.0 P3.1 P3.2 P3.3 INT7 INT5 AIN1 INT0 AIN2 INT6 VSO1 AIN3 VSO2 Name Function External Interrupt with Schmitt Trigger External Interrupt with Schmitt Trigger Analog Input External Interrupt Analog Input External Interrupt Voltage Synthesis Output Non-Maskable Interrupt Analog Input Voltage Synthesis Output Fast Blanking output Video Colour output Green Video Colour output Blue Video Colour output Alternate Function Assignment 9291J 9291N
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DESCRIPTION (Continued) Table ST9291 Port Alternative Function Summary (Continued)
PORT Port.bit P3.4 P3.5 P3.6 P3.7 P4.0 P4.1 P4.2 P4.3 P4.4 P4.5 P4.6 P4.7 P4.7 P5.0 P5.0 P5.1 P5.2 P5.3
Notes. alternate functions SCK/INT2 SDIO swapped using SWAP Register Function. Schmitt trigger options available mask option input pin.
Name
Function
Alternate Function
Assignment 9291J 9291N
PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 EXTRG INT2 SDIO
Output Output Output Output Output Output Output Output External Trigger Serial Clock
External Interrupt
Serial Data Input/Output
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CORE DESCRIPTION
CORE ARCHITECTURE 1.1.1 INTRODUCTION Core Central Processing Unit (CPU) includes Arithmetic Logic Unit Program Counter, System User Stack Pointers. microcoded Instruction highly optimised both byte bit) word bit) data, Boolean data types, with addressing modes. Three independent buses controlled Core, Memory bus, Register addressing Interrupt/DMA connected interrupt controllers on-chip peripherals Core. This multiple architecture allows high degree pipelining parallel operation, giving efficiency both numerical calculations communication with on-chip peripherals. 1.1.2 ADDRESS SPACES three separate address spaces: Register File: 8-bit registers plus pages bytes each, located on-chip peripherals. Data memory with (65536) bytes Program memory with (65536) bytes Data Program memory spaces will addressed further detail section 1.3. 1.1.2.1 Register File Register File consists general purpose registers R223 system registers System Group (R224 R239). depending pageseach containing configuration ST9, registers, with paging facilities based group (R240 R255).
Figure 1-4. Address Spaces
PROGRAM MEMORY REGISTER FILE
DATA MEMORY
VA00430
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ADDRESS SPACES (Continued) Figure 1-5. Register Grouping
PAGES
Figure 1-6. Page Pointer Configuration
PAGE
PAGED REGISTERS SYSTEM REGISTERS
PAGE R255 PAGE
R240 PAGE POINTER
GENERAL PURPOSE REGISTERS
R224
VA00432
VA00433
Figure 1-7. Addressing Register File
REGISTER FILE PAGE REGISTERS
SYSTEM REGISTERS
VR000118
GROUP R195 (R0C3h) R207
(1100) (0011) GROUP
R195 R192 GROUP
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ADDRESS SPACES (Continued) 1.1.2.2 Addressing Registers registers Register File pages specified using decimal, binary address, e.g. R231, RE7h R11100111b same register. registers referred their hexadecimal group address, that registers R0-R15 form group R160-R175 form group Working Register Addresses 8-bit register address formed nibbles, example, register R195 RC3h R11000011, 1100 specifies 13th group (i.e. group 0011 specifies register that group. Working registers addressed supplying least significant nibble instruction adding most significant nibble found Register Pointer (R233). Working register addressing shown Figure 1-7. System Registers system registers addresses R224 R239 form Group system registers addressable using register addressing modes most significant nibble will, cases, (0Eh). Paged Registers There maximum pages each containing registers. These addressed using register addressing modes with addition Page Pointer register, R234. This register selects page addressed group once set, does need changed more registers same page addressed succession. Therefore Page Pointer, R234, instructions R242, will load contents working register into third register (R242) page These paged registers hold data control registers related on-chip peripherals, thus configuration depends upon peripheral organisation each family member. i.e. pages only exist peripheral exists. Available pages shown Table 1-3. 1.1.2.3 Input/Output Ports Input/Output ports located areas. port registers Ports located bottom System register group locations R224 R229. Each Port three associated Control registers, which determine individual modes (I/O, Open-Drain etc). These registers located pages
Table 1-2. Register File Organization
Hex. Address F0-FF E0-EF D0-DF C0-CF B0-BF A0-AF 90-9F 80-8F 70-7F 60-6F 50-5F 40-4F 30-3F 20-2F 10-1F 00-0F Decimal Address 240-255 224-239 208-223 192-207 176-191 160-175 144-159 128-143 112-127 96-111 80-95 64-79 48-63 32-47 16-31 00-15 General Purpose Registers Function Paged Registers System Registers Register File Group Group Group Group Group Group Group Group Group Group Group Group Group Group Group Group Group
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ADDRESS SPACES (Continued) Table 1-3. Group Peripheral Organization Applicable ST9291
R255 R254 R253 R252 R251 R250 R249 R248 R247 R246 R245 R244 R243 R242 R241 R240 RESER CONV RESER RESER SLICE PORT PORT TIMER CHAR PORT1 PORT RESER T/WD PORT RESER RESER RESER CHAR CHAR RESER PORT RESER SWAP RESER RESER
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1.1.3 SYSTEM REGISTERS Following description System Registers. PORT0 PORT5 Registers, please refer Port Chapter. Figure 1-8. System Register
R239 (EFh) R238 (EEh) R237 (EDh) R236 (ECh) R235 (EBh) R234 (EAh) R233 (E9h) R232 (E8h) R231 (E7h) R230 (E6h) R229 (E5h) R228 (E4h) R227 (E3h) R226 (E2h) R225 (E1h) R224 (E0h) SYS. STACK POINTER SYS. STACK POINTER HIGH USER STACK POINTER USER STACK POINTER HIGH MODE REGISTER PAGE POINTER REGISTER POINTER REGISTER POINTER FLAGS CENTRAL INT. CNTL PORT5 PORT4 PORT3 PORT2 PORT1 PORT0
1.1.3.1 Central Interrupt Control Register This Register CICR located system Register Group address R230 (E6h). Please refer "INTERRUPT" "DMA" chapters order background interrupt philosophy. CICR R230 (E6h) System Read/Write Central Interrupt Control Register Reset Value 1000 0111 GCEN TLIP CPL2 CPL1 CPL0
GCEN: Global Counter Enable. This Global Counter Enable Multifunction Timers. GCEN ANDed with (Counter Enable) Timer Control Register (explained Timer chapter) order enable Timers when both bits set. This after Reset cycle. TLIP: Level Interrupt Pending. This automatically when Level Interrupt Request recognized. This also Software order simulate Level Interrupt Request. TLI: Level Interrrupt When this set, Level interrupt request acknowledged depending TLNM Nested Interrupt Control Register). reset level interrupt acknowledgement depends TLNM alone. IEN: Enable Interrupt. This bit, (when set), allows interrupts accepted. When reset interrupts other than acknowledged. cleared interrupt acknowledgement concurrent mode interrupt return (iret). managed hardware software instruction). IAM: Interrupt Arbitration Mode. This covers selection arbitration modes, Concurrent Mode being indicated value Fully Automatic Nested Mode value "1". This under software control. b2-b0 CPL2-CPL0: Current Priority Level. These three bits record priority level interrupt presently under service (i.e. Current Priority Level, CPL). these priority levels highest priority lowest priority. bits hardware software give reference which following interrupts either left pending able interrupt current interrupt. When present interrupt replaced greater priority, current priority value automatically stored until required.
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SYSTEM REGISTERS (Continued) 1.1.3.2 Flag Register Flag Register contains flags indicating statusof ST9. During interrupt flag register automatically stored system stack area recalled interrupt service routine that returned original status. This occurs interrupts and, when operating nested mode, seven versions flag register stored. FLAGR R231 (E7h) System Read/Write Flag Register Reset value: undefined Sign Flag. Sign flag affected same instructions Zero flag. Sign flag when (for byte operation) (for word operation) register used accumulator one. Overflow Flag. Overflow flag affected same instructions Zero Sign flags. When set, Overflow flag indicates that two'scomplement number, result register, error, since exceeded largest less than smallest), number that represented twos-complement notation. Decimal Adjust Flag. Decimal Adjust flag used arithmetic. Since algorithm correcting operations different addition subtraction, this flag used specify which type instruction executed last, that subsequent Decimal Adjust (da) operation perform function correctly. Decimal Adjust flag cannot normally used test condition programmer. Half Carry Flag. Half Carry flag indicates carry borrow into) result adding subtracting 8-bit bytes, each representing digits. Half Carry flag used Decimal Adjust (da) instruction convert binary result previous addition subtraction into correct result. Like Decimal Adjust flag, this flag normally accessed user. User Flag. flag register (UF) available user, must cleared instruction. Data/Program Memory Flag. This flag register indicates which memory area addressed. value affected Data Memory (sdm) Program Memory (spm) instructions. set, addresses Data Memory Area; when cleared, addresses Program Memory Area. reading this bit, user verify which memory area processor working. user writes this with instructions.
Carry Flag. carry flag affected following instructions: Addition (add, addw, adc, adcw), Subtraction (sub, subw, sbc, sbcw), Compare (cp, cpw), Shift Right Arithmetic (sra, sraw), Rotate (rrc, rrcw, rlc, rlcw, ror, rol), Decimal Adjust (da), Multiply Divide (mul, div, divws). When set, generally indicates carry most significant position register being used accumulator (bit byte word operations). carry flag Carry Flag (scf) instruction, cleared Reset Carry Flag (rcf) instruction, complemented (changed "1", vice versa) Complement Carry Flag (ccf) instruction. Zero Flag. Zero flag affected following instructions: Addition (add, addw, adc, adcw), Subtraction (sub, subw, sbc, sbcw), Compare (cp, cpw), Shift Right Arithmetic (sra, sraw), Rotate (rrc, rrcw, rlc, rlcw, ror, rol), Decimal Adjust (da), Multiply Divide (mul, div, divws), Logical (and, andw, orw, xor, xorw, cpl), Increment Decrement (inc, incw, dec, decw), Test (tm, tmw, tcm, tcmw, btset). most cases, Zero flag when register being used accumulator register zero, following above operations.
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SYSTEM REGISTERS (Continued) 1.1.3.3 Register Pointing Techniques registers, R232 R233, within system register group, available register pointing. R232 R233 used together single pointer register working space separately register spaces, which case R232 becomes Register Pointer (RP0) R233 becomes Register Pointer (RP1). instructions srp, srp0 srp1 (the Register Pointer instructions) automatically inform whether Register File operate with single 16-register group 8-register groups. srp0 srp1 instructions automatically twin 8-register group mode while instruction sets single 16-register group mode. There limitation order positions these chosen register groups other than they must register boundaries. addressing working registers involves Register Pointer value plus offset value given number addressed working register. When addressing register, most significant nibble (bits 4-7) gives group address least significant nibble (bits 0-3) gives register within that group. REGISTER POINTER R232 (E8h) System Read/Write Register Pointer Reset Value undefined REGISTER POINTER R233 (E9h) System Read/Write Register Pointer Reset Value undefined
b7-b3 RG7-RG3: Register Group number. These bits contain number (from group working registers indicated instructions srp0 srp. When using 16-register group, number between must used instruction indicating adjacent 8-register group working registers used. MSB. RPS: Register Pointer Selector. This instructions srp0 srp1 indicate that double register pointing mode used. Otherwise, instruction resets zero indicate that single register pointing mode used. b1,b0 D1,D0: These bits fixed hardware zero affected writing instruction trying modify their value.
This register used only with double register pointing mode; otherwise, using single register pointing mode, RP1R register considered reserved usable general purpose register. b7-b3 RG7-RG3: Register Group number. These bits contain number (from group working registers indicated instructions srp1. MSB. RPS: Register Pointer Selector. This automatically instructions srp0 srp1 indicate that double register pointing mode used. Otherwise instruction reset zero indicate that single register pointing mode used. b1,b0 D1,D0: These bits hardware fixed zero affected writing instruction trying modify their value. Note. working twin 8-register group mode only using srp0 (i.e. only using 8-register group) unused register (R233) considered reserved usable general purpose register. group registers immediately below system registers (i.e. group R208-R223) only accessed Register Pointers. address group then, necessary Register Pointer group then addressing procedure working registers. programmer required remember that group should used stacking area. This point also covered Stack Pointers paragraph.
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SYSTEM REGISTERS (Continued) EXAMPLES Using Single Register Group When system operating single 16-register group mode, registers referred r0-r15. this mode, offset value (i.e. number working register referred supplied address (preceded small e.g. added Register Pointer value give absolute address. example, Register Pointer contains value 70h, then working register would have absolute address, R77h. this mode, single 16-registers group will always start from lowest even number equal lower number given instruction. Example: equivalent Using Twin 8-Register Group When working twin working group mode, registers pointed Register Pointer (RP0R), referred r0-r7 those pointed Register Pointer (RP1R), referred r8-r15, regardless their absolute addresses. this mode, when operating with first working registers (i.e. working register number acts offset which added value Register Pointer Register Pointer contains value then working register absolute address working register absolute address 101, second group working registers, r8-r15, offset values respectively (i.e. offset value offset value on), this offset value being added value Register Pointer example, given that value Register Pointer then working register supplies offset value (given minus value Register Pointer give absolute address Figure 1-10. Double Register pointing Mode
GROUP GROUP GROUP REGISTER POINTER REGISTER POINTER GROUP
Figure 1-9. Single Register pointing Mode
REGISTER POINTER
GROUP GROUP WORKING REGISTER WORKING REGISTER
GROUP WORKING REGISTER
VA00097
VA00098
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SYSTEM REGISTERS (Continued) 1.1.3.4 Page Configuration pages available used storage control information (such interrupt vector pointers) relevant particular peripherals. There pages (each with registers) based registers R240-R255. These paged registers addressable page pointer register (PPR), which system register R234. address paged register page pointer register (R234) must loaded with relevant page number using instruction (Set Page Pointer) subsequently address from group (R240-R255) will referred that page. example register contains value following sequence loads third register R242 page with value R242, R234 (EAh) System Read/Write Page Pointer Register Reset value undefined 1.1.3.5 Mode Registers This register MODER located System Register Group address 235. Using this register possible: select either internal external System User Stack area, manage clock frequency enable request Wait signals when interfacing external memory. MODER R235 (EBh) System Read/Write Mode Register Reset value 1110 0000 DIV2 PRS2 PRS1 PRS0 BRQEN HIMP
b7-b2 PP7-PP2: Page Pointer. These bits contain number (between page chosen instruction (Set Page Pointer). page address. Once page pointer been set, there need refresh unless different page required. b1-b0 D1,D0: These bits fixed hardware zero affected writing instruction trying modify their value. PAGE contains control registers external interrupt watchdog timer wait logic states serial peripheral interface (SPI)
SSP: System Stack Pointer. This selects internal Register File) external external Data Memory) System Stack area, logical internal, logical external. After Reset value this "1". USP: User Stack Pointer. Same User Stack Pointer; DIV2: OSCIN Clock Divided This controls divide circuit which operates OSCIN Clock. logical value means that OSCIN clock internally divided logical value means that division OSCIN Clock occurs. b4-b2 PRS2-PRS0: CPUCLK Prescaler. These bits load prescaling module internal clock (INTCLK). prescaling value selects frequency clock, which divided Clock chapter more information. BRQEN: Request Enable. This must held "0". HIMP: High Impedance Enable. This must held "0".
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SYSTEM REGISTERS (Continued) 1.1.3.6 Stack Pointers There separate, double register stack pointers available (named System Stack Pointer User Stack Pointer), both which address registers memory. stack pointers point bottom stacks which filled using push commands emptied using commands. stack pointer automatically pre-decremented when data "pushed post-incremented when data "popped out". example, register address space selected stack corresponding stack pointer register contains 220. When byte data "pushed"into stack, stack pointer register decremented 219, then data byte "loaded" into register 219. Conversely, stack pointer register contains byte data "popped" out, byte data then extracted from stack then stack pointer register incremented 190. push commands used manage system stack area made applicable user stack adding suffix while stack instruction word added. example push inserts data into system stack, added indicates user stack means word, instruction pushuw loads word into bottom user stack. User Stack Pointer register contains (working register space) instruction pushuw will decrement User Stack Pointer register then load word into register R222 R221. When bytes words) "popped out" values those registers left unchanged until fresh data loaded into those locations. Thus when data "popped" from stack area, stack content remains unchanged. Note. Stacks must located pages system register area. System Stack area System Stack Pointer System Stack area used storage temporarily suspended system and/or control registers, i.e. Flag register Program counter, while interrupts being serviced. subroutine execution only Program Counter needs saved System stack area. There situations when this occurs automatically, being when interrupt occurs other when instruction call subroutine used. When system stack area Register File, stack pointer, which points bottom stack, only needs byte addressing, which case System Stack Pointer Register (R239) sufficient addressing purposes. result System Stack Pointer High Register (R238) becomes redundant must considered reserved (please refer also "spurious" memory access section). Clearly when stack external full word address necessary both registers used point, even register providing register providing LSB. User Stack area User Stack Pointer User Stack area completely free from interference from automatic operations provides totally user controlled stacking area, that area being part memory which nature, first groups general Register File i.e. System register Paged group. User Stack Pointer consists registers, R236 R237, which both used addressing external stack, while, when stacking Register File, User Stack Pointer High Register, R236, becomes redundant must considered reserved.
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SYSTEM REGISTERS (Continued) Stack location Care necessary when managing stacks there limit stack sizes apart from bottom address space which stack placed. Consequently programmers advised stack pointer value high possible, particularly when using Register File stacking area. This will also benefit programmers locate stacks group using, example instruction R237, #223 which loads value Figure 1-11. System and/or User Stack Register Stack Mode
REGISTER FILE R255
into User Stack Pointer Register. Programmer will need remember Register Pointer gain access registers D-group, problem outlined Register Pointing Techniques paragraph. Stacks located anywhere first groups Register File (internal stacks) data memory (external stacks). necessary data memory using instruction external stack instructions automatically data memory. Figure 1-12. System and/or User Stack Memory Stack Mode
DATA MEMORY SYSTEM REGISTERS
STACK POINTER STACK POINTER
STACK POINTER STACK POINTER
STACK
STACK
VA00434
VA00435
R236 (ECh) System Read/Write User Stack Pointer High Byte Reset value: undefined
System Stack Pointer High Byte Reset value: undefined
USP15 USP14 USP13 USP12 USP11 USP10 USP9 USP8 R237 (EDh) System Read/Write User Stack Pointer Byte Reset value: undefined
SSP15 SSP14 SSP13 SSP12 SSP11 SSP10 SSP9 SSP8 R239 (EFh) System Read/Write System Stack Pointer Byte Reset value: undefined
USP7 USP6 USP5 USP4 USP3 USP2 USP1 USP0 R238 (EEh) System Read/Write
SSP7 SSP6 SSP5 SSP4 SSP3 SSP2 SSP1 SSP0 MEMORY
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1.2.1 INTRODUCTION memory ST9291 functionally divided into areas, Register File Memory. Memory optionallybe divided into spaces, Program Memory Program code Data Memory Data. memory spaces selected execution instructions (Set Data Memory Program Memory, respectively). There need either these instructions again until memory area required changed. 1.2.1.1 Program Space Program memory space ST9291 consists bytes on-chip (addressed from BFFF) bytes on-chip (addressed from FD80h FFFFh); refer memory tables drawing following page memory mapping other sizes. first memory locations from address 00FFh (hexadecimal) hold Reset Vector, Top-Level (Pseudo Non-Maskable) interrupt, Divide Zero Trap vector and, optionally, interrupt vector table with on-chip
peripherals external interrupt sources. Each vector contained consecutive byte locations, high order address held lower (even) byte, order address held upper (odd) byte, forming address which loaded into Program Counter when selected interrupt vector provided interrupt source. This should point relevant Interrupt Service routine provided User immediate response interrupt. 1.2.1.2 Data Space ST9291 addresses bytes on-chip memory from addresses FD80h FFFFh both Program Data Space. On-chip general purpose Registers used additional memory minimum chip count systems. Data Space selected execution instruction. subsequ memory references will access Data Space. When separate Data Space required, data stored memory within Program Space.
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MEMORY (Continued) Table 1-4. Address Configuration
Device Suffix Size (Bytes) Addresses 16383 0000 3FFF J3/N3 16383 0000 3FFF J4/N4 24575 0000 5FFF J5/N5 24575 0000 5FFF J6/N6 32767 0000 7FFF J7/N7 00000 49151 0000 BFFF Size (Bytes) Addresses 64896 65279 FD80 FEFF 64896 65535 FD80 FFFF 64896 65299 FD80 FEFF 64896 65535 FD80 FFFF 64896 65535 FD80 FFFF 64896 65555 FD80 FFFF
J2/N2
Figure 1-13. ST9291 Memory
65535 64896 49151 32767
24575
16383
PROGRAM DATA
INTERNAL MAPPED BOTH INTO PROGRAM DATA SPACE
VR01354I
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Notes:
Information furnished believed accurate reliable. However, SGS-THOMSON Microelectronics assumes responsability consequences such information infringement patents other rights third parties which result from use. license granted implication otherwise under patent patent rights SGS-THOMSON Microelectronics. Specifications mentioned this publication subject change without notice. This publication supersedes replaces information previously supplied. SGS-THOMSON Microelectronics products authorized critical components life support devices systems without express written approval SGS-THOMSON Microelectronics.
1995 SGS-THOMSO Microelectronics rights reserved. Purchase Components SGS-THOMSON Microelectronics conveys license under Philips Patent. Rights these components system granted provided that system conforms Standard Specification defined Philips. SGS-THOMSON Microelectronics Group Companies Australia Brazil France Germany Hong Kong Italy Japan Korea Malaysia Malta Morocco Netherlands Singapore Spain Sweden Switzerland Taiwan Thailand United Kingdom U.S.A.
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16-48K HCMOS WITH SCREEN DISPLAY VOLTAGE TUNING OUTPUT FUNCTIONAL

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