DUAL MULTICLOCK GENERATOR FEATURES 27-MHz Master Clock Input Gene

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DUAL MULTICLOCK GENERATOR FEATURES 27-MHz Master Clock Input Gene

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PLL1707 PLL1708
DUAL MULTICLOCK GENERATOR
FEATURES 27-MHz Master Clock Input Generated Audio System Clock (PLL1707):
SCKO0: 44.1 kHz) SCKO1: kHz) SCKO2: 44.1, 88.2, kHz) SCKO3: 44.1, 88.2, kHz) Generated Audio System Clock (PLL1708): SCKO0: 44.1 kHz) SCKO1: kHz) SCKO2: 22.05, 44.1, 88.2, kHz) SCKO3: 22.05, 44.1, 88.2, kHz) Zero Error Output Clocks Clock Jitter: (Typical) Multiple Sampling Frequencies (PLL1707): 44.1, 88.2, Multiple Sampling Frequencies (PLL1708): 22.05, 44.1, 88.2, 3.3-V Single Power Supply PLL1707: Parallel Control PLL1708: Serial Control Package: 20-Pin SSOP (150 mil), Lead-Free Product
APPLICATIONS
Recorders Recorders Recorders Players Add-On Cards Multimedia Digital HDTV Systems Set-Top Boxes
DESCRIPTION
PLL1707 PLL1708 cost, phase-locked loop (PLL) multiclock generators. PLL1707 PLL1708 generate four system clocks from 27-MHz reference input frequency. clock outputs PLL1707 controlled sampling frequency-control pins those PLL1708 controlled through serial-mode control pins. device gives customers both cost space savings eliminating external components enables customers achieve very low-jitter performance needed high performance audio DACs and/or ADCs. PLL1707 PLL1708 ideal MPEG-2 applications which 27-MHz master clock such recorders, recorders, add-on cards multimedia PCs, digital HDTV systems, set-top boxes.
This integrated circuit damaged ESD. Texas Instruments recommends that integrated circuits handled with appropriate precautions. Failure observe proper handling installation procedures cause damage. damage range from subtle performance degradation complete device failure. Precision integrated circuits more susceptible damage because very small parametric changes could cause device meet published specifications. Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this data sheet. PLL1707 PLL1708 same they electrically identical except mode control.
PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters.
Copyright 2002, Texas Instruments Incorporated
PLL1707 PLL1708
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FUNCTIONAL BLOCK DIAGRAM
(MS) (MC) (MD) CSEL AGND VDD1-3 DGND1-3
Mode Control Interface Reset PLL2 PLL1
Power Supply
Divider
Divider
Divider
PLL1708
MCKO1
MCKO2
SCKO0
SCKO1
SCKO2
SCKO3
PACKAGE/ORDERING INFORMATION
PRODUCT PACKAGE PACKAGE CODE OPERATION TEMPERATURE RANGE -25°C 85°C 25°C -25°C 85°C 25°C PACKAGE MARKING PLL1707 PLL1708 ORDERING NUMBER PLL1707DBQ PLL1707DBQ PLL1708DBQ SSOP SSOP 20DBQ 20DBQ PLL1707DBQR PLL1708DBQ PLL1708DBQR TRANSPORT MEDIA Tube Tape reel Tube Tape reel
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1) PLL1705 PLL1706 Supply voltage: VCC, VDD1-VDD3 Supply voltage differences: VCC, VDD1-VDD3 Ground voltage differences: AGND, DGND1-DGND3 Digital input voltage: (MD), (MC), (MS), CSEL Analog input voltage, XT1, Input current (any pins except supplies) Ambient temperature under bias Storage temperature Junction temperature Lead temperature (soldering) ±0.1 ±0.1 (VDD 0.3) (VCC 0.3) -40°C 125°C -55°C 150°C 150°C 260°C,
Package temperature reflow, peak) 260°C Stresses beyond those listed under "absolute maximum ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated under "recommended operating conditions" implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability.
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PLL1707 PLL1708
ELECTRICAL CHARACTERISTICS
specifications 25°C, VDD1-VDD3 VDD) MHz, crystal oscillation, (unless otherwise noted) PARAMETER DIGITAL INPUT/OUTPUT Logic input Input logic level Input logic current Logic output Output logic level PLL1707 ling Sampling frequency PLL1708 Standard Double Half Standard CMOS 44.1 88.2 22.05 44.1 CMOS compatible 0.7VDD TEST CONDITIONS UNIT
Double 88.2 MASTER CLOCK (MCKO1, MCKO2) CHARACTERISTICS MHz, measurement pin) Master clock frequency Input level(3) Input current(3) Output voltage Output rise time Output fall time Duty cycle Clock jitter Power-up time CHARACTERISTICS (SCKO0-SCKO3) MHz, measurement pin) SCKO0 Fixed SCKO1 SCKO2 SCKO3 SCKO0 SCKO1 SCKO2 SCKO3 Output rise time Output fall time Output duty cycle Output system clock frequency PLL1708 PLL1707 Selectable Fixed Selectable 12.288 4.096 6.144 24.576 8.192 12.288 12.288 18.432 33.8688 24.576 12.288 18.432 36.864 24.576 36.864 crystal oscillation external clock 33.8688 36.864 24.576 36.864 26.73 27.27 Vp-p
Pins FS1/MD, FS2/MC, SR/MS, CSEL (Schmitt-trigger input with internal pulldown, 3.3-V tolerant) Pins SCKO2, SCKO3, MCKO1, MCKO2, SCKO0, SCKO1 Jitter performance specified standard deviation jitter 27-MHz crystal oscillation default SCKO frequency setting. Jitter performance varies with master clock mode, SCKO frequency setting load capacitance each clock output. delay time from power oscillation settling time when sampling frequency changed delay time from power lockup 27-MHz crystal oscillation, load MCKO1, MCKO2, SCKO0, SCKO1, SCKO2, SCKO3. Power supply current varies with sampling frequency selection load condition. (10) While bits CE[6:1] PLL1708 goes into power-down mode.
PLL1707 PLL1708
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ELECTRICAL CHARACTERISTICS (continued)
specifications 25°C, VDD1-VDD3 VDD) MHz, crystal oscillation, (unless otherwise noted) PARAMETER Output clock jitter Frequency Settling Time(7) Power-up time POWER SUPPLY REQUIREMENTS VCC, Supply voltage range Supply current Power dissipation TEMPERATURE RANGE Operating temperature Thermal resistance PLL1707/8DBQ: 20-pin SSOP (150 mil) °C/W Pins FS1/MD, FS2/MC, SR/MS, CSEL (Schmitt-trigger input with internal pulldown, 3.3-V tolerant) Pins SCKO2, SCKO3, MCKO1, MCKO2, SCKO0, SCKO1 Jitter performance specified standard deviation jitter 27-MHz crystal oscillation default SCKO frequency setting. Jitter performance varies with master clock mode, SCKO frequency setting load capacitance each clock output. delay time from power oscillation settling time when sampling frequency changed delay time from power lockup 27-MHz crystal oscillation, load MCKO1, MCKO2, SCKO0, SCKO1, SCKO2, SCKO3. Power supply current varies with sampling frequency selection load condition. (10) While bits CE[6:1] PLL1708 goes into power-down mode. Power down(10) TEST CONDITIONS SCKO0, SCKO1 SCKO2, SCKO3 PLL1707, stated output frequency PLL1708, stated output frequency stated output frequency UNIT
ASSIGNMENTS
PLL1707 (TOP VIEW) PLL1708 (TOP VIEW)
VDD1 SCKO2 SCKO3 DGND1 AGND
VDD3 SCKO1 SCKO0 DGND3 DGND2 MCKO2 MCKO1 VDD2 CSEL
VDD1 SCKO2 SCKO3 DGND1 AGND
VDD3 SCKO1 SCKO0 DGND3 DGND2 MCKO2 MCKO1 VDD2 CSEL
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PLL1707 PLL1708
PLL1707 Terminal Functions
TERMINAL NAME AGND CSEL DGND1 DGND2 DGND3 MCKO1 MCKO2 SCKO0 SCKO1 SCKO2 SCKO3 VDD1 VDD2 VDD3 Analog ground SCKO1 frequency selection control(1) Digital ground Digital ground Digital ground Sampling frequency group control 1(1) Sampling frequency group control 2(1) 27-MHz master clock output 27-MHz master clock output System clock output (33.8688 fixed) System clock output (selectable kHz) System clock output (256 selectable) System clock output (384 selectable) Sampling rate control(1) Analog power supply, Digital power supply Digital power supply Digital power supply 27-MHz crystal oscillator, external clock input 27-MHz crystal oscillator, must OPEN external clock input mode DESCRIPTION
Schmitt-trigger input with internal pulldown.
PLL1707 PLL1708
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PLL1708 Terminal Functions
TERMINAL NAME AGND CSEL DGND1 DGND2 DGND3 MCKO1 MCKO2 SCKO0 SCKO1 SCKO2 SCKO3 VDD1 VDD2 VDD3 Analog ground SCKO1 frequency selection control(1) Digital ground Digital ground Digital ground clock input serial control(1) 27-MHz master clock output 27-MHz master clock output Data input serial control(1) Chip select input serial control(1) System clock output (33.8688 fixed) System clock output (selectable kHz) System clock output (256 selectable) System clock output (384 selectable) Analog power supply, Digital power supply Digital power supply Digital power supply 27-MHz crystal oscillator, external clock input 27-MHz crystal oscillator, must OPEN external clock input mode DESCRIPTION
Schmitt-trigger input with internal pulldown.
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PLL1707 PLL1708
TYPICAL PERFORMANCE CURVES
JITTER SAMPLING FREQUENCY
MCKO1 MCKO2 SCKO0 SCKO1 SCKO2 SCKO3 SCKO1 Jitter psrms Jitter psrms SCKO3 SCKO0
JITTER LOAD CAPACITANCE
SCKO2
MCKO1 MCKO2
Sampling Frequency
Load Capacitance
Figure
JITTER SUPPLY VOLTAGE
Figure
JITTER FREE-AIR TEMPERATURE
SCKO1 SCKO0
SCKO1 SCKO0 Jitter psrms SCKO3
Jitter psrms
SCKO3 MCKO2
MCKO2
SCKO2
MCKO1
SCKO2
MCKO1
Supply Voltage
Free-Air Temperature
Figure
Figure
NOTE: specifications 25°C, VDD1-3 VDD) +3.3 MHz, crystal oscillation, default frequency (33.8688 SCKO0, 36.864 SCKO1, SCKO2 SCKO3), measurement pin, unless otherwise noted.
PLL1707 PLL1708
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DUTY CYCLE SUPPLY VOLTAGE
MCKO1 Duty Cycle SCKO3 SCKO1 SCKO0 MCKO2 SCKO2 Duty Cycle
DUTY CYCLE FREE-AIR TEMPERATURE
MCKO2 MCKO1 SCKO2 SCKO1
SCKO0
SCKO3
Supply Voltage
Free-Air Temperature
Figure
Figure
NOTE: specifications 25°C, VDD1-3 VDD) +3.3 MHz, crystal oscillation, default frequency (33.8688 SCKO0, 36.864 SCKO1, SCKO2 SCKO3), measurement pin, unless otherwise noted.
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PLL1707 PLL1708
THEORY OPERATION
MASTER CLOCK SYSTEM CLOCK OUTPUT
PLL1707/8 consists dual clock master clock generator which generates four system clocks buffered 27-MHz clocks from 27-MHz master clock. Figure shows block diagram PLL1707/8. designed accept 27-MHz master clock.
SCKO3
Counter SCKO0-3 Frequency Control Counter Phase Detector Loop Filter
Divider
Divider PLL2
PLL1
Counter Phase Detector Loop Filter Counter Divider
MCKO1
MCKO2
SCKO0 33.8688
SCKO1 36.864/24.576 (36.864/24.576 MHz) (18.432/12.288 MHz)
SCKO2
PLL1708
Figure Block Diagram
PLL1707 PLL1708
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master clock either crystal oscillator placed between (pin (pin 11), external input XT1. external master clock used, must open. Figure illustrates possible system clock connection options, Figure illustrates 27-MHz master clock timing requirement.
MCKO2
MCKO2
MCKO1
MCKO1
Crystal Crystal Circuit
27-MHz Internal Master Clock
External Clock
Crystal Circuit
27-MHz Internal Master Clock
PLL1707/PLL1708 Crystal Resonator Connection
PLL1707/PLL1708 External Clock Input Connection
Figure Master Clock Generator Connection Diagram
t(XT1H) t(XT1L)
DESCRIPTION Master clock pulse duration HIGH Master clock pulse duration
SYMBOL t(XT1H) t(XT1L)
UNIT
Figure External Master Clock Timing Requirement
PLL1707/8 provides very low-jitter, high-accuracy clock. SCKO0 outputs fixed 33.8688-MHz clock, SCKO1 outputs kHz) which selected hardware software control. output frequency remaining clocks determined sampling frequency (fS) under hardware software control. SCKO2 SCKO3 output 256-fS 384-fS system clocks, respectively. Table shows each sampling frequency which programmed. system clock output frequencies programmed sampling frequencies shown Table half sampling frequencies SCKO2 SCKO3 SCKO1 supported only PLL1708.
Table Generated System Clock SCKO1 Frequency
PLL1708 only SCKO1 FREQUENCY 12.288 18.432 24.576 36.864
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PLL1707 PLL1708
Table Sampling Frequencies
SAMPLING RATE Half sampling frequencies Standard sampling frequencies Double sampling frequencies PLL1708 only SAMPLING FREQUENCY (kHz) 22.05 44.1 88.2
Table Sampling Frequencies System Clock Output Frequencies
SAMPLING FREQUENCY (kHz) 22.05 44.1 88.2 PLL1708 only SAMPLING RATE Half Half Half Standard Standard Standard Double Double Double SCKO2 (MHZ) 4.096 5.6448 6.144 8.192 11.2896 12.288 16.384 22.5792 24.576 SCKO3 (MHZ) 6.144 8.4672 9.216 12.288 16.9344 18.432 24.576 33.8688 36.864
Response time from power applying clock XT1) SCKO settling time typically Delay time from sampling frequency change SCKO settling maximum. Figure illustrates SCKO transient timing PLL1708.
Clocks MCKO1, SCKO2 SCKO3 Stable Clock Transition Region Stable
SCKO0 SCKO1
33.8688 36.864, 24.576
Figure System Clock Transient Timing
delay time hardware control FS2, FS1, CSEL maximum. Figure illustrates SCKO transient timing PLL1707. Clock transient timing synchronized with SCKOs. External buffers recommended output clocks order avoid degrading jitter performance PLL1707/8.
PLL1707 PLL1708
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FS2, CSEL SCKO1 SCKO2 SCKO3 Stable Clock Transition Region Stable
SCKO0
33.8688
Figure SCKO Transient Timing
POWER-ON RESET
PLL1707/8 internal power-on reset circuit. mode register PLL1708 initialized with default settings power-on reset. Throughout reset period, clock outputs enabled with default settings after power-up time. Initialization internal power-on reset done automatically during 1024 master clocks (TYP). Power-on reset timing shown Figure
Reset Internal Reset
Reset Removal
1024 Master Clocks Master Clock
Figure Power-On Reset Timing
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PLL1707 PLL1708
FUNCTION CONTROL
built-in functions PLL1707 controlled parallel mode (hardware mode), which uses (pin (pin (pin PLL1708 controlled serial mode (software mode), which three-wire interface using (pin (pin (pin selectable functions shown Table
Table Selectable Functions
SELECTABLE FUNCTION Sampling frequency select kHz, 44.1 kHz, kHz) Sampling rate select (standard/double) Sampling rate select (half) Each clock output enable/disable Power down SCKO1 configuration PARALLEL MODE SERIAL MODE
PLL1707 (Parallel Mode)
parallel mode, following functions selected:
Sampling Frequency Group Select
sampling frequency group selected (pin (pin
(PIN HIGH HIGH (PIN HIGH HIGH SAMPLING FREQUENCY 44.1 Reserved
Sampling Rate Select
sampling rate selected (pin
(PIN HIGH SAMPLING RATE Standard Double
System Clock SCKO1 Frequency Select
System clock SCKO1 frequency selected CSEL (pin 12).
CSEL (PIN HIGH SCKO1 FREQUENCY 36.864 24.576
PLL1708 (Serial Mode)
built-in functions PLL1708 shown Table These functions controlled using serial control signals.
Table Selectable Functions
SELECTABLE FUNCTION Sampling frequency select kHz, 44.1 kHz, kHz) Sampling rate select (half, standard, double) Each clock output enable/disable Power down SCKO1 configuration DEFAULT 48-kHz group Standard Enabled Disabled 36.864 MHz, 24.576
PLL1707 PLL1708
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Program-Register Mapping
built-in functions PLL1708 controlled through 16-bit program register. This register loaded using After data bits clocked using rising edge used latch data into register. Table shows mapping register. serial mode control format control data input timing shown Figure Figure respectively.
Figure Serial Mode Control Format
t(MHH) t(MSL) VDD/2
t(MSS) t(MCH)
t(MCL) t(MSH)
t(MSS)
VDD/2 t(MCY)
t(MDH) t(MDS) DESCRIPTION
VDD/2
SYMBOL t(MCY) t(MCL) t(MCH) t(MDH) t(MDS) t(MSL) t(MHH) t(MSH)
UNIT clocks(1)
pulse cycle time pulse duration pulse duration HIGH hold time setup time low-level time high-level time hold time(2)
setup time(3) t(MSS) clocks: clock period rising edge rising edge rising edge next rising edge. clock stopped after LSB, rise time accepted.
Figure Control Data Input Timing
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PLL1707 PLL1708
Mode Register
Table Mode Register Mapping
REGISTER NAME Mode control SR[2:1] FS[2:1] DESCRIPTION MCKO2 output enable/disable MCKO1 output enable/disable SCKO1 output enable/disable SCKO3 output enable/disable SCKO2 output enable/disable SCKO0 output enable/disable Sampling rate select Sampling frequency select
FS[2:1]: Sampling Frequency Group Select
SAMPLING FREQUENCY (default) 44.1 Reserved
SR[2:1]: Sampling Rate Select
SAMPLING RATE Standard (default) Double Half Reserved
[6:1]: Clock Output Control
CE1-CE6 CLOCK OUTPUT CONTROL Clock output disable Clock output enable (default)
While bits [6:1] PLL1708 goes into power-down mode, dynamic operation including PLLs oscillator halts, serial mode control enabled resumption.
PLL1707 PLL1708
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Configuration Register
CFG1
Table Configuration Register Mapping
REGISTER Configuration NAME CFG1 DESCRIPTION Reserved, must SCKO1 configuration
CFG1: SCKO1 Configuration Control
CFG1 CONFIGURATION 36.864 MHz, 24.576 SCKO1 (default) 18.432 MHz, 12.288 SCKO1
system clock SCKO1 frequency selected CSEL (pin CFG1 (register).
CFG1 (REGISTER) CSEL (PIN HIGH HIGH SCKO1 36.864 24.576 18.432 12.288
CONNECTION DIAGRAM
Figure shows typical connection circuit PLL1707. There four grounds digital analog power supplies. However, common ground connection recommended avoid latch-up other power-supply-related troubles. Power supplies should bypassed close possible device.
MPEG-2 APPLICATIONS
Typical applications PLL1707/8 MPEG-2 based systems such recorders, recorders, players, add-on cards multimedia PCs, digital HDTV systems, set-top boxes. PLL1707/8 provides audio system clocks CD-DA DSP, DSP, Karaoke DSP, ADC(s), DAC(s) from 27-MHz video clock.
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PLL1707 PLL1708
PLL1707/8 (MD) (MC) SR(MS) AGND DGND2 MCKO2 MCKO1 VDD2 CSEL SCKO3 DGND1 SCKO0 DGND3 VDD1 SCKO2 VDD3 SCKO1
Clock Outputs 0.1-µF ceramic capacitor typical, depending quality power supply pattern layout 10-µF aluminum electrolytic capacitor typical, depending quality power supply pattern layout 27-MHz quartz crystal 10-33 ceramic capacitors, which generate appropriate amplitude oscillation XT1/XT2 This connection PLL1707 (parallel mode); when PLL1708 (serial mode) used, control pins must connected serial interfaced controller. good jitter performance, minimize load capacitance clock output. recommended drive clock outputs through buffers, especially there heavy loads SCKO0 SCKO1, minimize mutual interference separating them inserting guard pattern between them.
Figure Typical Connection Diagram
PLL1707 PLL1708
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BLOCK DIAGRAM PLAYER APPLICATION
PLL1707/8 SCKO3
Crystal
SCKO2 MCKO1/2 SCKO0
Front CD-DA/ MPEG/AC-3 Audio Decoder Surround PCM/DSD1608 Center, Subwoofer Down
BLOCK DIAGRAM HDD+DVD RECORDER APPLICATION
MPEG Encoder
PCM1802
SCKO1 PLL1707/8 MCKO1/2
SCKO2,
MPEG Decoder
PCM1742
27-MHz Master Clock
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PLL1707 PLL1708
MECHANICAL DATA
(R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
0.025 (0,64)
0.012 (0,30) 0.008 (0,20)
0.005 (0,13)
0.157 (3,99) 0.150 (3,81)
0.244 (6,20) 0.228 (5,80)
0.008 (0,20)
Gauge Plane 0°-8° 0.069 (1,75) 0.035 (0,89) 0.016 (0,40) 0.010 (0,25)
Seating Plane 0.010 (0,25) 0.004 (0,10) 0.004 (0,10)
PINS
0.197 (5,00) 0.189 (4,80)
0.344 (8,74) 0.337 (8,56)
0.344 (8,74) 0.337 (8,56)
0.394 (10,01) 0.386 (9,80)
M0-137 VARIATION
4073301/F 02/02 NOTES:A. linear dimensions millimeters. This drawing subject change without notice. Body dimensions include mold flash protrusion exceed 0.006 (0,15). Falls within JEDEC MO-137.
MECHANICAL DATA
MSOI004E JANUARY 1995 REVISED 2002
(R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
0.025 (0,64)
0.012 (0,30) 0.008 (0,20)
0.005 (0,13)
0.157 (3,99) 0.150 (3,81)
0.244 (6,20) 0.228 (5,80)
0.008 (0,20)
Gauge Plane 0°-8° 0.069 (1,75) 0.035 (0,89) 0.016 (0,40) 0.010 (0,25)
Seating Plane 0.010 (0,25) 0.004 (0,10) 0.004 (0,10)
PINS
0.197 (5,00) 0.189 (4,80)
0.344 (8,74) 0.337 (8,56)
0.344 (8,74) 0.337 (8,56)
0.394 (10,01) 0.386 (9,80)
M0-137 VARIATION
4073301/F 02/02 NOTES: linear dimensions millimeters. This drawing subject change without notice. Body dimensions include mold flash protrusion exceed 0.006 (0,15). Falls within JEDEC MO-137.
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DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO002E JANUARY 1995 REVISED DECEMBER 2001
(R-PDSO-G**)
PINS SHOWN 0,65 0,38 0,22 0,15
PLASTIC SMALL-OUTLINE
0,25 0,09 5,60 5,00 8,20 7,40
Gage Plane 0,25 0,95 0,55
Seating Plane 2,00 0,05 0,10
PINS
6,50
6,50
7,50
8,50
10,50
10,50
12,90
5,90
5,90
6,90
7,90
9,90
9,90
12,30 4040065 12/01
NOTES:
linear dimensions millimeters. This drawing subject change without notice. Body dimensions include mold flash protrusion exceed 0,15. Falls within JEDEC MO-150
POST OFFICE 655303
DALLAS, TEXAS 75265
IMPORTANT NOTICE Texas Instruments Incorporated subsidiaries (TI) reserve right make corrections, modifications, enhancements, improvements, other changes products services time discontinue product service without notice. Customers should obtain latest relevant information before placing orders should verify that such information current complete. products sold subject TI's terms conditions sale supplied time order acknowledgment. warrants performance hardware products specifications applicable time sale accordance with TI's standard warranty. Testing other quality control techniques used extent deems necessary support this warranty. Except where mandated government requirements, testing parameters each product necessarily performed. assumes liability applications assistance customer product design. Customers responsible their products applications using components. minimize risks associated with customer products applications, customers should provide adequate design operating safeguards. does warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right relating combination, machine, process which products services used. Information published regarding third-party products services does constitute license from such products services warranty endorsement thereof. such information require license from third party under patents other intellectual property third party, license from under patents other intellectual property Reproduction information data books data sheets permissible only reproduction without alteration accompanied associated warranties, conditions, limitations, notices. Reproduction this information with alteration unfair deceptive business practice. responsible liable such altered documentation. Resale products services with statements different from beyond parameters stated that product service voids express implied warranties associated product service unfair deceptive business practice. responsible liable such statements.
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Copyright 2002, Texas Instruments Incorporated

DUAL MULTICLOCK GENERATOR FEATURES 27-MHz Master Clock Input Gene

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