3.3-V DUAL MULTICLOCK GENERATOR FEATURES 27-MHz Master Clock Inpu

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3.3-V DUAL MULTICLOCK GENERATOR FEATURES 27-MHz Master Clock Inpu

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PLL1705 PLL1706
3.3-V DUAL MULTICLOCK GENERATOR
FEATURES 27-MHz Master Clock Input Generated Audio System Clock:
SCKO0: 44.1 kHz) SCKO1: 44.1 kHz) SCKO2: 44.1, 88.2, kHz) SCKO3: 44.1, 88.2, kHz)
APPLICATIONS Players Add-On Cards Multimedia Digital HDTV Systems Set-Top Boxes DESCRIPTION
PLL1705 PLL1706 cost, phase-locked loop (PLL) multiclock generators. PLL1705 PLL1706 generate four system clocks from 27-MHz reference input frequency. clock outputs PLL1705 controlled sampling frequency-control pins those PLL1706 controlled through serial-mode control pins. device gives customers both cost space savings eliminating external components enables customers achieve very low-jitter performance needed high performance audio DACs and/or ADCs. PLL1705 PLL1706 ideal MPEG-2 applications which 27-MHz master clock such players, add-on cards multimedia PCs, digital HDTV systems, set-top boxes.
Zero Error Output Clocks Clock Jitter: (Typical) Multiple Sampling Frequencies:
44.1, 88.2,
3.3-V Single Power Supply PLL1705: Parallel Control
PLL1706: Serial Control
Package: 20-Pin SSOP (150 mil), Lead-Free
Product
FUNCTIONAL BLOCK DIAGRAM
(ML) (MC) (MD) CSEL AGND VDD1-3 DGND1-3
Mode Control Interface Reset PLL2 PLL1
Power Supply
Divider
Divider
Divider
PLL1706
MCKO1
MCKO2
SCKO0
SCKO1
SCKO2
SCKO3
Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this data sheet. PLL1705 PLL1706 same they electrically identical except mode control.
PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters.
Copyright 2002, Texas Instruments Incorporated
PLL1705 PLL1706
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This integrated circuit damaged ESD. Texas Instruments recommends that integrated circuits handled with appropriate precautions. Failure observe proper handling installation procedures cause damage. damage range from subtle performance degradation complete device failure. Precision integrated circuits more susceptible damage because very small parametric changes could cause device meet published specifications.
PACKAGE/ORDERING INFORMATION
PRODUCT PACKAGE PACKAGE CODE OPERATION TEMPERATURE RANGE -25°C 85°C 25°C -25°C 85°C 25°C PACKAGE MARKING PLL1705 PLL1706 ORDERING NUMBER PLL1705DBQ PLL1705DBQ PLL1706DBQ SSOP SSOP 20DBQ 20DBQ PLL1705DBQR PLL1706DBQ PLL1706DBQR TRANSPORT MEDIA Tube Tape reel Tube Tape reel
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1) PLL1705 PLL1706 Supply voltage: VCC, VDD1-3 Supply voltage differences: VCC, VDD1-3 Ground voltage differences: AGND, DGND1-3 Digital input voltage: (MD), (MC), (ML), CSEL Analog input voltage, XT1, Input current (any pins except supplies) Ambient temperature under bias Storage temperature Junction temperature Lead temperature (soldering) ±0.1 ±0.1 (VDD 0.3) (VCC 0.3) -40°C 125°C -55°C 150°C 150°C 260°C,
Package temperature reflow, peak) 260°C Stresses beyond those listed under "absolute maximum ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated under "recommended operating conditions" implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability.
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PLL1705 PLL1706
ELECTRICAL CHARACTERISTICS
specifications 25°C, VDD1-VDD3 VDD) MHz, crystal oscillation, (unless otherwise noted) PARAMETER DIGITAL INPUT/OUTPUT Logic input Input logic level Input logic current Logic output Output logic level Sampling frequency Samplingfrequency Standard Double CMOS 44.1 88.2 27.27 crystal oscillation external clock 33.8688 16.9344 8.192 12.288 12.288 18.432 PLL1705, stated output frequency PLL1706, stated output frequency stated output frequency 33.8688 24.576 36.864 CMOS compatible 0.7VDD TEST CONDITIONS UNIT
MASTER CLOCK (MCKO1, CHARACTERISTICS MHz, measurement pin) Master clock frequency 26.73 Input level(3) Input current(3) Output voltage Output rise time Output fall time Duty cycle Clock jitter Power-up time CHARACTERISTICS (SCKO0-3) MHz, measurement pin) SCKO0 Fixed SCKO1 SCKO2 SCKO3 Output rise time Output fall time Output duty cycle Output clock jitter Frequency Settling Time(7) Power-up time Output system clock frequency Selectable 44.1
Vp-p
Pins FS1/MD, FS2/MC, SR/ML, CSEL (Schmitt-trigger input with internal pulldown, 3.3-V tolerant) Pins SCKO2, SCKO3, MCKO1, MCKO2, SCKO1, SCKO0 Jitter performance specified standard deviation jitter 27-MHz crystal oscillation default SCKO frequency setting. Jitter performance varies with master clock mode, SCKO frequency setting load capacitance each clock output. delay time from power oscillation settling time when sampling frequency changed delay time from power lockup 27-MHz crystal oscillation, load MCKO1, MCKO2, SCKO0, SCKO1, SCKO2, SCKO3. Power supply current varies with sampling frequency selection load condition. (10) While bits CE[6:1] PLL1706 goes into power-down mode.
PLL1705 PLL1706
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ELECTRICAL CHARACTERISTICS(continued)
specifications 25°C, VDD1-VDD3 VDD) MHz, crystal oscillation, (unless otherwise noted) PARAMETER POWER SUPPLY REQUIREMENTS VCC, Supply voltage range Supply current Power dissipation TEMPERATURE RANGE Operatingtemperature Thermal resistance PLL1705/6DBQ: 20-pin SSOP (150 mil) °C/W Pins FS1/MD, FS2/MC, SR/ML, CSEL (Schmitt-trigger input with internal pulldown, 3.3-V tolerant) Pins SCKO2, SCKO3, MCKO1, MCKO2, SCKO1, SCKO0 Jitter performance specified standard deviation jitter 27-MHz crystal oscillation default SCKO frequency setting. Jitter performance varies with master clock mode, SCKO frequency setting load capacitance each clock output. delay time from power oscillation settling time when sampling frequency changed delay time from power lockup 27-MHz crystal oscillation, load MCKO1, MCKO2, SCKO0, SCKO1, SCKO2, SCKO3. Power supply current varies with sampling frequency selection load condition. (10) While bits CE[6:1] PLL1706 goes into power-down mode. Power down(10) TEST CONDITIONS UNIT
ASSIGNMENTS
PLL1705 (TOP VIEW) PLL1706 (TOP VIEW)
VDD1 SCKO2 SCKO3 DGND1 AGND
VDD3 SCKO0 SCKO1 DGND3 DGND2 MCKO2 MCKO1 VDD2 CSEL
VDD1 SCKO2 SCKO3 DGND1 AGND
VDD3 SCKO0 SCKO1 DGND3 DGND2 MCKO2 MCKO1 VDD2 CSEL
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PLL1705 PLL1706
Terminal Functions
TERMINAL NAME AGND CSEL DGND1 DGND2 DGND3 FS1(MD) FS2(MC) MCKO1 MCKO2 SCKO0 SCKO1 SCKO2 SCKO3 SR(ML) VDD1 VDD2 VDD3 Analog ground SCKO1 frequency selection control(1) Digital ground Digital ground Digital ground Sampling frequency group control PLL1705, data input serial control PLL1706(1) Sampling frequency group control PLL1705, clock input serial control PLL1706(1) 27-MHz master clock output 27-MHz master clock output System clock output (33.8688 fixed) System clock output (selectable 44.1 kHz) System clock output (256 System clock output (384 Sampling rate control PLL1705, load strobe input serial control PLL1706(1) Analog power supply, Digital power supply Digital power supply Digital power supply 27-MHz crystal oscillator, external clock input 27-MHz crystal oscillator, must OPEN external clock input mode DESCRIPTION
Schmitt-trigger input with internal pulldown.
PLL1705 PLL1706
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TYPICAL PERFORMANCE CURVES
JITTER SAMPLING FREQUENCY
JITTER LOAD CAPACITANCE
Jitter psrms Jitter psrms
SCKO3 SCKO0
SCKO2 MCKO1 MCKO2 Sampling Frequency SCKO0 SCKO1 SCKO2 SCKO3
SCKO1 MCKO1 MCKO2
Load Capacitance
Figure
JITTER SUPPLY VOLTAGE
Figure
JITTER FREE-AIR TEMPERATURE
SCKO0 Jitter psrms SCKO1 SCKO3 Jitter psrms
SCKO0 SCKO3 SCKO1
SCKO2
MCKO2
MCKO1
SCKO2
MCKO2
MCKO1
Supply Voltage
Free-Air Temperature
Figure
Figure
NOTE: specifications 25°C, VDD1-3 VDD) +3.3 MHz, crystal oscillation, default frequency (33.8688 SCKO0, 33.8688 SCKO1, SCKO2 SCKO3), measurement pin, unless otherwise noted.
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PLL1705 PLL1706
DUTY CYCLE SUPPLY VOLTAGE
DUTY CYCLE FREE-AIR TEMPERATURE
Duty Cycle
Duty Cycle
SCKO0
SCKO2
SCKO2
SCKO3
SCKO1
SCKO1
SCKO0
SCKO3
MCKO2 MCKO1
MCKO2
MCKO1
Supply Voltage
Free-Air Temperature
Figure
Figure
NOTE: specifications 25°C, VDD1-3 VDD) +3.3 MHz, crystal oscillation, default frequency (33.8688 SCKO0, 33.8688 SCKO1, SCKO2 SCKO3), measurement pin, unless otherwise noted.
PLL1705 PLL1706
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THEORY OPERATION
MASTER CLOCK SYSTEM CLOCK OUTPUT
PLL1705/6 consists dual clock master clock generator which generates four system clocks buffered 27-MHz clocks from 27-MHz master clock. Figure shows block diagram PLL1705/6. designed accept 27-MHz master clock.
SCKO3
Counter SCKO0-3 Frequency Control Counter Phase Detector Loop Filter
Divider
Divider PLL2
PLL1
Counter Phase Detector Loop Filter Counter Divider
MCKO1
MCKO2
SCKO0 33.8688
SCKO1 33.8688/16.9344
SCKO2
Figure Block Diagram
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PLL1705 PLL1706
master clock either crystal oscillator placed between (pin (pin 11), external input XT1. external master clock used, must open. Figure illustrates possible system clock connection options, Figure illustrates 27-MHz master clock timing requirement.
MCKO2
MCKO2
MCKO1
MCKO1
Crystal Crystal Circuit
27-MHz Internal Master Clock
External Clock
Crystal Circuit
27-MHz Internal Master Clock
PLL1705/PLL1706 Crystal Resonator Connection
PLL1705/PLL1706 External Clock Input Connection
Figure Master Clock Generator Connection Diagram
t(XT1H) t(XT1L)
DESCRIPTION Master clock pulse duration HIGH Master clock pulse duration
SYMBOL tXT1H tXT1L
UNIT
Figure External Master Clock Timing Requirement
PLL1705/6 provides very low-jitter, high-accuracy clock. SCKO0 outputs fixed 33.8688-MHz clock, SCKO1 outputs 44.1 kHz) which selected CSEL (pin CD-DA DSP. output frequency remaining clocks determined sampling frequency (fS) under hardware software control. SCKO2 SCKO3 output 256-fS 384-fS system clocks, respectively. Table shows each sampling frequency, which programmed. system clock output frequencies programmed sampling frequencies shown Table
Table Generated System Clock SCKO1 Frequency
CSEL HIGH SCKO1 FREQUENCY 33.8688 16.9344
Table Sampling Frequencies
SAMPLING RATE Standard sampling frequencies Double sampling frequencies SAMPLING FREQUENCY (kHz) 44.1 88.2
PLL1705 PLL1706
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Table Sampling Frequencies System Clock Output Frequencies
SAMPLING FREQUENCY (kHz) 44.1 88.2 SAMPLING RATE Standard Standard Standard Double Double Double SCKO2 (MHZ) 8.192 11.2896 12.288 16.384 22.5792 24.576 SCKO3 (MHZ) 12.288 16.9344 18.432 24.576 33.8688 36.864
Response time from power applying clock XT1) SCKO settling time typically Delay time from sampling frequency change SCKO settling maximum. This clock transient timing synchronized with SCKOx signals. Figure illustrates SCKO transient timing PLL1706. External buffers recommended output clocks order avoid degrading jitter performance PLL1705/6.
Clocks MCKO1,2 SCKO2 SCKO3 Stable Clock Transition Region Stable
SCKO0 SCKO1
33.8688 MHz, 44.1
Figure System Clock Transient Timing
POWER-ON RESET
PLL1705/6 internal power-on reset circuit. mode register PLL1706 initialized with default settings power-on reset. Throughout reset period, clock outputs enabled with default settings after power time. Initialization internal power-on reset done automatically during 1024 master clocks (TYP). Power-on reset timing shown Figure
Reset Internal Reset
Reset Removal
1024 Master Clocks Master Clock
Figure Power-On Reset Timing
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PLL1705 PLL1706
FUNCTION CONTROL
built-in functions PLL1705 controlled parallel mode (hardware mode), which uses (pin (pin (pin PLL1706 controlled serial mode (software mode), which uses three-wire interface (pin (pin (pin selectable functions shown Table
Table Selectable Functions
SELECTABLE FUNCTION Sampling frequency select kHz, 44.1 kHz, kHz) Sampling rate select (standard/double) Each clock output enable/disable Power down PARALLEL MODE SERIAL MODE
PLL1705 (Parallel Mode)
parallel mode, following functions selected:
Sampling Frequency Group Select
sampling frequency group selected (pin (pin
(PIN HIGH HIGH (PIN HIGH HIGH SAMPLING FREQUENCY 44.1 Reserved
Sampling Rate Select
sampling rate selected (pin
(PIN HIGH SAMPLING RATE Standard Double
PLL1706 (Serial Mode)
built-in functions PLL1706 shown Table These functions controlled using serial control signals.
Table Selectable Functions
SELECTABLE FUNCTION Sampling frequency select kHz, 44.1 kHz, kHz) Sampling rate select (standard/double) Each clock output enable/disable Power down DEFAULT 48-kHz group Standard Enabled Disabled
PLL1705 PLL1706
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Program-Register Mapping
built-in functions PLL1706 controlled through 16-bit program register. This register loaded using After data bits clocked using rising edge used latch data into register. Table shows mapping register. serial mode control format control data input timing shown Figure Figure respectively.
Figure Serial Mode Control Format
t(MHH) t(MLL) VDD/2
t(MLS) t(MCH)
t(MCL) t(MLH)
t(MLS)
VDD/2 t(MCY)
t(MDH) t(MDS) DESCRIPTION
VDD/2
SYMBOL tMCY tMCL tMCH tMDH
tMDS
UNIT clocks(1)
pulse cycle time pulse duration pulse duration HIGH hold time setup time low-level time high-level time hold time(2)
tMLL
tMHH
tMLH
setup time(3) tMLS clocks: clock period rising edge rising edge rising edge next rising edge. clock stopped after LSB, rise time accepted.
Figure Control Data Input Timing
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PLL1705 PLL1706
Mode Register
Table Register Mapping
REGISTER NAME Mode control FS[2:1] DESCRIPTION MCKO2 output enable/disable MCKO1 output enable/disable SCKO1 output enable/disable SCKO3 output enable/disable SCKO2 output enable/disable SCKO0 output enable/disable Reserved, must Sampling rate select Sampling frequency select
FS[2:1]: Sampling Frequency Group Select
SAMPLING FREQUENCY 44.1 Reserved DEFAULT
Sampling Rate Select
SAMPLING RATE Standard Double DEFAULT
[6:1]: Clock Output Control
CE1-CE6 CLOCK OUTPUT CONTROL Clock output disable Clock output enable DEFAULT
While bits [6:1] PLL1706 goes into power-down mode, dynamic operation including PLLs oscillator halt, serial mode control enabled resumption.
CONNECTION DIAGRAM
Figure shows typical connection circuit PLL1705. There four grounds digital analog power supplies. However, common ground connection recommended avoid latch-up other power-supply-related troubles. Power supplies should bypassed close possible device.
MPEG-2 APPLICATIONS
Typical applications PLL1705/6 MPEG-2 based systems such players, add-on cards multimedia PCs, digital HDTV systems, set-top boxes. PLL1705/6 provides audio system clocks CD-DA DSP, DSP, Karaoke DSP, DAC(s) from 27-MHz video clock.
PLL1705 PLL1706
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PLL1705/6 (MD) (MC) SR(ML) AGND DGND2 MCKO2 MCKO1 VDD2 CSEL SCKO3 DGND1 SCKO1 DGND3 VDD1 SCKO2 VDD3 SCKO0
Clock Outputs 0.1-µF ceramic capacitor typical, depending quality power supply pattern layout 10-µF aluminum electrolytic capacitor typical, depending quality power supply pattern layout 27-MHz quartz crystal 10-33 ceramic capacitors, which generate appropriate amplitude oscillation XT1/XT2 This connection PLL1705 (parallel mode); when PLL1706 (serial mode) used, control pins must connected serial interfaced controller. good jitter performance, minimize load capacitance clock output.
Figure Typical Connection Diagram
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PLL1705 PLL1706
BLOCK DIAGRAM MPEG-2 BASED SYSTEM APPLICATION
PLL1705/6 SCKO3 27-MHz Crystal SCKO2
PCM1716
Front
MCKO1/2
SCKO0
PCM1716
Surround
Center CD-DA/ MPEG/AC-3 Audio Decoder PCM1716 Subwoofer
PLL1705 PLL1706
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MECHANICAL DATA
(R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
0.025 (0,64)
0.012 (0,30) 0.008 (0,20)
0.005 (0,13)
0.157 (3,99) 0.150 (3,81)
0.244 (6,20) 0.228 (5,80)
0.008 (0,20)
Gauge Plane 0°-8° 0.069 (1,75) 0.035 (0,89) 0.016 (0,40) 0.010 (0,25)
Seating Plane 0.010 (0,25) 0.004 (0,10) 0.004 (0,10)
PINS
0.197 (5,00) 0.189 (4,80)
0.344 (8,74) 0.337 (8,56)
0.344 (8,74) 0.337 (8,56)
0.394 (10,01) 0.386 (9,80)
M0-137 VARIATION
4073301/F 02/02 NOTES:A. linear dimensions millimeters. This drawing subject change without notice. Body dimensions include mold flash protrusion exceed 0.006 (0,15). Falls within JEDEC MO-137.
IMPORTANT NOTICE Texas Instruments Incorporated subsidiaries (TI) reserve right make corrections, modifications, enhancements, improvements, other changes products services time discontinue product service without notice. Customers should obtain latest relevant information before placing orders should verify that such information current complete. products sold subject TI's terms conditions sale supplied time order acknowledgment. warrants performance hardware products specifications applicable time sale accordance with TI's standard warranty. Testing other quality control techniques used extent deems necessary support this warranty. Except where mandated government requirements, testing parameters each product necessarily performed. assumes liability applications assistance customer product design. Customers responsible their products applications using components. minimize risks associated with customer products applications, customers should provide adequate design operating safeguards. does warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right relating combination, machine, process which products services used. Information published regarding third-party products services does constitute license from such products services warranty endorsement thereof. such information require license from third party under patents other intellectual property third party, license from under patents other intellectual property Reproduction information data books data sheets permissible only reproduction without alteration accompanied associated warranties, conditions, limitations, notices. Reproduction this information with alteration unfair deceptive business practice. responsible liable such altered documentation. Resale products services with statements different from beyond parameters stated that product service voids express implied warranties associated product service unfair deceptive business practice. responsible liable such statements.
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Copyright 2002, Texas Instruments Incorporated

3.3-V DUAL MULTICLOCK GENERATOR FEATURES 27-MHz Master Clock Inpu

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