SONET/SDH/AOC-12 TRANSMITTER RECEIVER BiCMOS PECL CLOCK GENERATOR SONE

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SONET/SDH/AOC-12 TRANSMITTER RECEIVER BiCMOS PECL CLOCK GENERATOR SONE

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DEVICE SPECIFICATION
SONET/SDH/AOC-12 TRANSMITTER RECEIVER BiCMOS PECL CLOCK GENERATOR SONET/SDH/AOC-12 TRANSMITTER RECEIVER TRANSMITTER RECEIVER GENERAL DESCRIPTION
S3017/S3018 S3017/S3018 S3017/S3018
FEATURES
Complies with ANSI, Bellcore, ITU-T specifications On-chip high-frequency clock generation clock recovery Supports 622.08 Mbit/s (OC-12/STM-4) Reference frequency 77.76 Interface both PECL logic 8-bit datapath Compact PQFP package Diagnostic loopback mode Lock detect jitter PECL interface Watt typically
S3017/S3018 SONET/SDH/Atransmitter receiver chips fully integrated serialization/ deserialization SONET OC-12 (622.08 Mbit/s) interface devices. With architecture developed PMC-Sierra, Inc., chipset performs necessary serial-to-parallel parallel-to-serial functions conformance with SONET/SDH transmission standards. devices suitable SONET-based Aapplications. Figure shows typical network application. On-chip clock synthesis performed highfrequency phase-locked loop S3017 transmitter chip allowing slower external transmit clock reference. Clock recovery performed S3018 receiver chip synchronizing on-chip directly incoming data stream. S3018 also performs SONET/SDH frame detection. chipset used with 19.44 77.76 reference clock, support existing system clocking schemes. jitter PECL interface guarantees compliance with bit-error rate requirements Bellcore, ANSI, ITU-T standards. S3017 S3018 packaged compact PQFP, offering designers small package outline.
APPLICATIONS
SONET/SDH-based transmission systems SONET/SDH modules SONET/SDH test equipment Aover SONET/SDH Section repeaters drop multiplexors Broad-band cross-connects Fiber optic terminators Fiber optic test equipment
Figure System Block Diagram
Network Interface Processor
S3017 SONET/ SDH/ATransmitter
S3018 SONET/ SDH/AReceiver
Network Interface Processor
December 1999 Revision
S3017/S3018 SONET OVERVIEW
SONET/SDH/AOC-12 TRANSMITTER RECEIVER
byte-interleaved STS-1 signals. optical counterpart each STS-N signal optical carrier level-N signal (OC-N). S3017/S3018 chipset supports OC12 rates (622.08 Mbit/s).
Frame Byte Boundary Detection SONET/SDH fundamental frame format STS-12 consists transport overhead bytes followed Synchronous Payload Envelope (SPE) bytes. This pattern overhead 1044 bytes repeated nine times each frame. Frame byte boundaries detected using bytes found transport overhead. (See Figure more details SONET operations, refer ANSI SONET standard document.
Synchronous Optical Network (SONET) standard connecting fiber system another optical level. SONET, together with Synchronous Digital Hierarchy (SDH) administered ITU-T, forms single international standard fiber interconnect between telephone networks different countries. SONET capable accommodating variety transmission rates applications. SONET standard layered protocol with four separate layers defined. These are: Photonic Section Line Path Figure shows layers their functions. Each layers overhead bandwidth dedicated administration maintenance. photonic layer simply handles conversion from electrical optical back with overhead. responsible transmitting electrical signals optical form over physical media. section layer handles transport framed electrical signals across optical cable from next. functions this layer framing, scrambling, error monitoring. line layer responsible reliable transmission path layer information stream carrying voice, data, video signals. main functions synchronization, multiplexing, reliable transport. path layer responsible actual transport services appropriate signaling rates. Data Rates Signal Hierarchy Table contains data rates signal designations SONET hierarchy. lowest level basic SONET signal referred synchronous transport signal level-1 (STS-1). STS-N signal made
Figure SONET Structure
Functions
Payload mapping Maintenance, protection, switching Scrambling, framing Optical transmission
Layer Overhead (Embedded Channel) Path layer Line layer Section layer Path layer Line layer Section layer
Kbps
Kbps
Photonic layer
Photonic layer
Fiber Cable
Equipment
Equipment
Table SONET Signal Hierarchy
Elec.
STS-1 STS-3 STS-12 STS-24 STS-48
ITU-T
STM-1 STM-4 STM-16
Optical Data Rate (Mbit/s)
OC-1 OC-3 OC-12 OC-24 OC-48 51.84 155.52 622.08 1244.16 2488.32
Figure STS-12/OC-12 Frame Format
Rows Bytes Bytes
Transport Overhead Columns bytes
Synchronous Payload Envelope 1044 Columns 1044 9396
µsec
December 1999 Revision
SONET/SDH/AOC-12 TRANSMITTER RECEIVER S3017/S3018 OVERVIEW
S3017 transmitter S3018 receiver implement SONET/SDH serialization/deserialization, transmission, frame detection/recovery functions. block diagrams Figures show basic operation both chips. These chips used implement front SONET equipment, which consists primarily serial transmit interface (S3017) serial receive interface (S3018). chipset handles functions these elements, including parallel-toserial serial-to-parallel conversion, clock generation recovery, system timing. system timing circuitry consists management datastream, framing, clock distribution throughout front end. Operation S3017/S3018 chips straightforward. sequence operations follows: Transmitter 8-bit parallel input Parallel-to-serial conversion Serial output
S3017/S3018
Receiver Clock data recovery from serial input Frame detection Serial-to-parallel conversion 8-bit parallel output Internal clocking control functions transparent user. Details data timing seen Figures through lock detect feature provided S3018, which indicates that locked (synchronized) data stream, facilitates continuous down-stream clocking absence data.
Suggested Interface Devices
AMCC CONGO (S1201) AMCC NILE (S1202) AT&T ASTROTEC1227/1230 Mitsubishi MF-622DF-T12-XXX Sumitomo ES-9304-TD AT&T ASTROTEC 1310 Sumitomo ES-9216-RD Finisar POS/ASONET Mapper ASONET Mapper Mbit/s Mbit/s Mbit/s Mbit/s Mbit/s Fiber Optic Transmitter Fiber Optic Transmitter Fiber Optic Transmitter Fiber Optic Receiver Fiber Optic Receiver Fiber Optic Receiver
Mitsubishi MF-622DS-R1X-XXX Mbit/s
1000 Mbit/s Fiber Optic Transceiver
Figure S3017 Transmitter Functional Block Diagram
TSCLKSEL LOCLPEN
PARALLEL SERIAL PICLK
LPDATOP/N SERDATOP/N
PIN[7:0]
PCLK TIMING
TSTCLKEN REFSEL REFCKINP/N
CLOCK SYNTHESIZER
RSTB TESTRST
CAP1
CAP2
December 1999 Revision
S3017/S3018 S3017 TRANSMITTER FUNCTIONAL DESIGN
SONET/SDH/AOC-12 TRANSMITTER RECEIVER
REFCKINP/N input must generated from differential PECL crystal oscillator which frequency accuracy better than order TSCLK frequency have same accuracy required operation SONET system. Lower accuracy crystal oscillators used applications less demanding than SONET/SDH. on-chip consists phase detector, which compares phase relationship between output REFCKINP/N input, loop filter which converts phase detector output into smooth voltage, VCO, whose frequency varied this voltage. loop filter generates control voltage based average level phase discriminator output pulses. single external clean-up capacitor utilized part loop filter. loop filter's corner frequency optimized minimize output phase jitter.
S3017 transmitter chip performs serializing stage processing transmit SONET STS-12 serial data stream. converts byte serial 77.76 Mbyte/sec data stream serial format 622.08 Mbit/sec. high-frequency clock generated from 77.76 frequency reference using integral frequency synthesizer consisting phase-locked loop circuit with divider loop. Diagnostic loopback provided (transmitter receiver) when used with compatible S3018. (See Other Operating Modes.)
Clock Synthesizer
Clock Synthesizer, shown block diagram Figure monolithic that generates serial output clock phase synchronized with input reference clock (REFCKINP/N).
Figure S3018 Receiver
SERIAL PARALLEL
POUT[7:0]
FRAME BYTE DETECT
TIMING
POCLK
LOCLPEN SERDATIP/N LPDATIP/N
BACKUP REFERENCE
REFSEL REFCKINP/N TSTCLKEN RSTB
CLOCK RECOVERY
LOCKDET
CAP1
CAP2
December 1999 Revision
SONET/SDH/AOC-12 TRANSMITTER RECEIVER
Timing Generator Timing Generation function, seen Figure provides byte rate version transmit serial clock. This circuitry also provides internally generated load signal, which transfers PIN[7:0] data from parallel input register serial shift register. PCLK output byte rate version transmit serial clock 77.76 MHz. PCLK intended byte speed clock upstream multiplexing overhead processing circuits. Using PCLK upstream circuits will ensure stable frequency phase relationship between data coming into leaving S3017 device. Parallel-to-Serial Converter Parallel-to-Serial converter shown Figure comprised byte-wide registers. first register latches data from PIN[7:0] rising edge PICLK. second register parallel loadable shift register which takes parallel input from first register.
S3017/S3018
load signal, which latches data from parallel serial shift register, fixed relationship PCLK. PICLK tied PCLK, PIN[7:0] data latched into parallel register will meet timing specifications with respect load signal. PICLK tied PCLK, delay must meet timing requirements shown Figure PICLK must frequency locked reference clock input.
Figure Clock Recovery Jitter Tolerance
Jitter Amplitude p-p)
Minimum proposed tolerance (TA-NWT-000253) OC-12
0.15
6.5k Jitter Frequency (Hz)
250k
December 1999 Revision
S3017/S3018 S3018 RECEIVER FUNCTIONAL DESIGN
SONET/SDH/AOC-12 TRANSMITTER RECEIVER
This transfer function yields typical capture time random incoming data. single external clean-up capacitor utilized part loop filter. total loop dynamics clock recovery yield jitter tolerance which meets, with ample margin, minimum tolerance proposed SONET equipment Bellcore TA-NWT-000253 standard, shown Figure Backup Reference Generator Backup Reference Generator seen Figure provides backup reference clock signals clock recovery block when clock recovery block detects loss signal condition. contains counter that divides clock output from clock recovery block down same frequency reference clock REFCKINP/N. Frame Byte Boundary Detection
S3018 receiver chip provides first stage digital processing receive SONET STS-12 bit-serial stream. converts bit-serial 622.08 Mbit/sec data stream into 77.76 Mbyte/sec byte-serial data format. Clock recovery performed incoming scrambled data stream. 77.76 reference clock required phase locked loop start-up proper operation under loss signal conditions. integral prescaler phase locked loop circuit used multiply this reference nominal rate. loopback mode provided diagnostic loopback (transmitter receiver), when used with compatible S3017 device. Clock Recovery Clock Recovery PLL, shown block diagram Figure generates clock that same frequency incoming data rate SERDATI LPDATI inputs. clock phase aligned that samples data center data pattern. phase relationship between edge transitions data those generated clock compared phase/frequency discriminator. Output pulses from discriminator indicate required direction phase corrections. These pulses smoothed integral loop filter. output loop filter controls frequency Voltage Controlled Oscillator (VCO), which generates recovered clock. Frequency stability without incoming data guaranteed alternate reference input (REFCKIN) that locks onto when data lost. clock recovery circuit monitors incoming data stream loss signal. incoming data stream transitions between times (depending upon state internal counter time last transistion), loss signal declared will switch from locking onto incoming data locking onto reference clock. Alternatively, lossof-signal (LOS) input used force loss-of-signal condition. When high, squelches incoming data stream, thus causes switch source reference within times. Loss-of-signal condition removed when low, good data, with acceptable pulse density length, returns incoming data stream. loop filter transfer function optimized enable track jitter, tolerate minimum transition density expected received SONET data signal.
Frame Byte Boundary Detection circuitry searches incoming data three consecutive bytes followed immediately three consecutive bytes. Framing pattern detection enabled disabled out-of-frame (OOF) input. Detection enabled rising edge OOF, remains enabled duration that high. disabled when framing pattern detected longer high. When framing pattern detection enabled, framing pattern used locate byte frame boundaries incoming data stream (SERDATI LPDATI). timing generator block takes located byte boundary uses block incoming data stream into bytes output parallel output data (POUT[7:0]). frame boundary reported frame pulse (FP) output when 48-bit pattern matching framing pattern detected incoming data stream. When framing pattern detection disabled, byte boundary frozen location found when detection previously enabled. Only framing patterns aligned fixed byte boundary indicated output. probability that random data STS-12 stream will generate 48-bit framing pattern extremely small. highly improbable that mimic pattern would occur within frame data. Therefore, time match first frame pattern verify with downstream circuitry, next occurrence pattern, expected less than required even extremely high error rates. Once down-stream overhead circuitry verified that frame byte synchronization correct, input disable frame search process from trying synchronize mimic frame pattern.
December 1999 Revision
SONET/SDH/AOC-12 TRANSMITTER RECEIVER
Serial Parallel Converter Serial Parallel Converter consists three 8-bit registers. first serial-in, parallel-out shift register, which performs serial parallel conversion clocked clock recovery block. second 8-bit internal holding register, which transfers data from serial parallel register byte boundaries determined frame byte boundary detection block. falling edge free running POCLK, data holding register transferred output holding register which drives POUT[7:0]. delay through Serial Parallel converter vary from byte periods serial periods) measured from first incoming byte beginning parallel output that byte. variation delay dependent alignment internal parallel load timing, which synchronized data byte boundaries, with respect falling edge POCLK, which independent byte boundaries. advantage this serial parallel converter that POCLK neither truncated extended during reframe sequences.
S3017/S3018
OTHER OPERATING MODES
Diagnostic Loopback Diagnostic Loopback consists alternate serial data outputs case S3017) inputs case S3018). S3017, differential PECL output LPDATO provides Diagnostic Loopback serial data. When Local Loopback Enable (LOCLPEN) input TSCLKSEL low, this data output replica SERDATO. When LPDATO connected S3018, loopback from transmitter receiver serial data rate diagnostic purposes. When LOCLPEN high TSCLKSEL low, LPDATO held inactive state, with positive output high negative output low. inactive state, there will interference from transmitter receiver. receiver side, differential PECL input LPDATI Diagnostic Loopback serial data input. When Local Loopback Enable (LOCLPEN) input low, LPDATI input routed place normal data stream (SERDATI).
Figure Loopback Diagram
Data Control S2030 Fiber S3017 Channel Transmitter S2031 Fiber S3018 Channel Receiver Data
Link Loopback
Local Diagnostic Loopback Loopback
Local Diagnostic Loopback Loopback
Data
S2031 Fiber Channel S3018 Receiver
S2030 Fiber Channel S3017 Transmitter
Link Loopback
Data Control
December 1999 Revision
S3017/S3018
SONET/SDH/AOC-12 TRANSMITTER RECEIVER
S3017 Assignment Descriptions
Name
PIN7 PIN6 PIN5 PIN4 PIN3 PIN2 PIN1 PIN0 PICLK
Level
Description
Parallel data input, 77.76 Mbyte/sec word, aligned PICLK parallel input clock. PIN7 most significant (corresponding first transmitted). PIN0 least significant (corresponding last transmitted). PIN(7-0) sampled rising edge PICLK.
Parallel input clock, 77.76 nominally duty cycle input clock, which PIN(7-0) aligned. PICLK used transfer data inputs into holding register parallel-toserial converter. rising edge PICLK samples PIN(7-0). Test clock enable signal, active high enable reference clock used place testing. Allows means testing functions chip without PLL. normal operation. Reference clock input used reference internal clock frequency synthesizer. Local loopback enables LPDATO output when TSCLKSEL low. When LOCLPEN high, LPDATO output held inactive state prevent interference between transmit receive devices. Reset input device, active low. During reset, PCLK does toggle. Active high transmit clock select input which, when enabled, directs transmit serial clock through LPDATOP/N output. Test reset, used reset portions clock recovery during production testing. Held normal operation. Reference select, used select reference clock frequency. select 77.76 MHz. high select 19.44 applications less demanding than SONET/SDH. loop filter capacitor connected these pins. capacitor value should 0.01µf ±10% tolerance, dielectric. recommended acceptable). High-speed, source-terminated differential PECL. Serial output data stream signals, normally connected optical transmitter module.
TESTCLKEN
REFCKINP REFCKINN LOCLPEN
Diff. PECL
RSTB
TSCLKSEL
TESTRST
REFSEL
CAP1 CAP2 SERDATOP SERDATON
Diff. PECL
December 1999 Revision
SONET/SDH/AOC-12 TRANSMITTER RECEIVER
S3017 Assignment Descriptions (Continued)
S3017/S3018
Name
LPDATOP LPDATON
Level
Diff. PECL
Description
Loopback serial data stream signals, normally connected companion S3018 device diagnostic loopback purposes. They held inactive when LOCLPEN high TSCLKSEL low. serial data stream output when LOCLPEN TSCLKSEL low. When enabled TSCLKSEL input, transmit serial clock will output through this pin. transmit serial clock buffered version internal frequency synthesizer clock, which phase-aligned with SERDATO output signal. SERDATO updated falling edge transmit serial clock. Parallel reference clock generated dividing internal clock eight. normally used coordinate byte-wide transfers between upstream logic S3017 device.
PCLK
AVEE
Analog Analog Digital Digital Digital Digital Connection
AVCC
ECLVCC
ECLVEE
TTLGND TTLVCC
December 1999 Revision
S3017/S3018
SONET/SDH/AOC-12 TRANSMITTER RECEIVER
S3018 Assignment Descriptions
Name
SERDATIP SERDATIN LPDATIP LPDATIN
Level
Diff. PECL Diff. PECL
Description
Serial data stream signals normally connected optical receiver module. clock recovered from transitions SERDATI inputs. Serial data stream signal, normally connected companion S3017 device diagnostic loopback purposes. Clock recovered from transitions LPDATI inputs while diagnostic loopback. Selects diagnostic loopback. When LOCLPEN high, S3018 device uses primary data (SERDATI) input. When low, S3018 device uses diagnostic loopback data (LPDATI) input. Test clock enable signal, high enable reference clock used place testing. Allows means testing functions chip without PLL. normal operation. frame indicator used enable framing pattern detection logic S3018. This logic enabled rising edge OOF, remains enabled until frame boundary detected when low, whichever longer. asynchronous signal with minimum pulse width POCLK period. (See Figures 14.) active-high, single-ended input driven external optical receiver module indicate loss received optical power. When high, data Serial Data (SERDATIP/N) pins will internally forced constant zero, LOCKDET will forced low, will lock REFCKINP/N inputs. This signal must used assure correct automatic reacquisition serial data following interruption subsequent reconnection optical path. (This ensures that does "wander" reacquisition range tracking random phase/frequency content optical detector's noise floor while monitoring "dark" fiber.) When low, data SERDATIP/N pins will processed normally. Input normally used reference integral clock recovery PLL. Master reset input device, active low. Initializes device known state forces acquire reference clock. reset least should applied power-up whenever user wishes force reacquire reference clock. S3018 will also re-acquire reference clock serial data input held quiescent least
LOCLPEN
TSTCLKEN
PECL
REFCKINP REFCKINN RSTB
Diff. PECL
December 1999 Revision
SONET/SDH/AOC-12 TRANSMITTER RECEIVER
S3018 Assignment Descriptions (Continued)
S3017/S3018
Name
REFSEL
Level
Description
Reference select used select reference clock frequency. select 77.76 MHz. high select 19.44 applications less demanding than SONET/SDH. loop filter capacitor connected these pins. capacitor value should 0.1µf ±10% tolerance, X7'R dielectric. recommended (16V acceptable). Parallel data bus, 77.76 Mbyte/sec word, aligned POCLK parallel output clock. POUT7 most significant (corresponding each word, first received). POUT0 least significant (corresponding each word, last received). POUT(7-0) updated falling edge POCLK.
CAP1 CAP2 POUT7 POUT6 POUT5 POUT4 POUT3 POUT2 POUT1 POUT0
Frame pulse. Indicates frame boundaries incoming data stream (SERDATI). framing pattern detection enabled, controlled input, pulses high POCLK cycle when 48-bit sequence matching framing pattern detected serial data inputs. When framing pattern detection disabled, pulses high when incoming data stream, after byte alignment, matches framing pattern. updated falling edge POCLK. Parallel output clock, 77.76 nominally duty cycle, byte rate output clock, that aligned POUT(7-0) byte serial output data. POUT(7-0) updated falling edge POCLK. Clock recovery indicator. high when internal clock recovery locked onto incoming data stream. LOCKDET asynchronous output.
POCLK
LOCKDET
AVEE AVCC ECLVCC ECLVEE TTLGND TTLVCC
Analog Analog Digital Digital Digital Digital Connection
December 1999 Revision
S3017/S3018
Figure PQFP Package
SONET/SDH/AOC-12 TRANSMITTER RECEIVER
10.0
12.0
Embedded Heatsink
1.40 0.65
VIEW
10.0 12.0
dimensions nominal
Heatsinks DW0045-28 DW0045-29
DW0045-28 DW0045-29
dimensions nominal
December 1999 Revision
SONET/SDH/AOC-12 TRANSMITTER RECEIVER
Performance Specifications
S3017/S3018
Parameter
Nominal Center Frequency PECL Data Output Jitter OC-12/STS-12 Reference Clock Frequency Tolerance Clock Synthesis Clock Recovery OC-12/STS-12 Capture Range Lock Range
622.08
Units
Condition
(rms)
mode, given jitter REFCKIN 12KHz band Required meet SONET output frequency specification
-100
+100
±200ppm +2,-8%
With respect fixed reference frequency Minimum transition density With device already powered valid reference clock
Acquisition Lock Time
µsec
Reference Clock Input Duty Cycle Reference Clock Rise Fall Times PECL Output Rise Fall Times (S3017 LPDATOP/N) Source Terminated Diff. PECL Compatible Output Rise Fall Times (S3017 SERDATOP/N)
period amplitude 80%, equivalent load,
80%, line line
December 1999 Revision
S3017/S3018
SONET/SDH/AOC-12 TRANSMITTER RECEIVER
Absolute Maximum Ratings
Parameter Case Temperature Under Bias Junction Temperature Under Bias Storage Temperature Voltage with Respect Ground Voltage Input Voltage PECL Input Output Sink Current Output Source Current High Speed PECL Output Source Current
Ratings S3017/S3018 rated following voltages based human body model: pins rated above 1000
-0.5 -0.5 VCC-3
+7.0 +5.5
Units
Recommended Operating Conditions
Parameter Ambient Temperature Under Bias Junction Temperature Under Bias Voltage with Respect Ground Voltage Input Voltage PECL Input S3017 S3018 4.75 VCC-2 +125 5.25 Units
December 1999 Revision
SONET/SDH/AOC-12 TRANSMITTER RECEIVER
Input/Output Characteristics
-40°C +85°C, ±5%)
S3017/S3018
Symbol
VIL1 VIH1
Parameter
Input Voltage Input HIGH Voltage Input Current Input HIGH Current Input HIGH current Max. Output Short Circuit Current Input Clamp Diode Voltage Output Voltage Output HIGH Voltage
-400.0
Unit
Volts Volts
Conditions
Guaranteed Input Voltage Guaranteed Input HIGH Voltage MAX, 0.5V MAX, 2.7V MAX, 5.5V MAX, VOUT 0.5V MIN, MIN, MIN,
50.0 -100.0 -1.2 -25.0
Volts Volts Volts
These input levels provide zero noise immunity should only tested static, noise-free environment.
Thermal Management
Theta-ja Still DW0045-28 Heatsink 32.7°C/W 32.7°C/W Still Air1 DW0045-28 Heatsink 89°C 85°C Required Air2 DW0045-29 Heatsink LFPM LFPM
Device S3017 S3018
Power 1.25W 1.36W
Notes: ambient temperature permitted still maintain <130°C. Airflow required 85°C ambient conditions maintain <130°C.
December 1999 Revision
S3017/S3018
SONET/SDH/AOC-12 TRANSMITTER RECEIVER
PECL Input/Output Characteristics1,2 -40°C +85°C, ±5%)
Symbol
Parameter
Input Voltage Input HIGH Voltage Input Voltage Input HIGH Voltage Input Diff. Voltage Input High Current Input Current Output Voltage Output HIGH Voltage Output Diff. Voltage
-2.000 -1.225 -2.000 -1.750 0.250 -0.500 -0.500 -2.000 -1.110 0.390
-1.441 -0.570 -0.700 -0.450
Unit
Volts Volts Volts Volts Volts Volts Volts Volts
Conditions
Guaranteed Input Voltage single-ended inputs Guaranteed Input HIGH Voltage single-ended inputs Guaranteed Input Voltage differential inputs Guaranteed Input HIGH Voltage differential inputs Differential Input Voltage 500mV 500mV termination termination Differential Output Voltage
0.500
1.400 20.000 20.000 -1.500 -0.670 1.330
These conditions will with airflow. When used, positive differential PECL negative differential ground 3.9K resistor.
Differential Input Output Applications
Electrical optical
S3017 SERDATOP/N Fiber Optic Transmitter
Reference Clock Crystal Oscillator Source (ECL Driver) REFCKINP/N Inputs. S3017 LPDATOP/N S3018 LPDATIP/N. Fiber Optic Receiver S3018 SERDATIP/N.
December 1999 Revision
SONET/SDH/AOC-12 TRANSMITTER RECEIVER
Table S3017 Timing Characteristics
Symbol
tDPICLK tSPIN tHPIN tDSER
S3017/S3018
-40°C +85°C, ±5%)
11.0
Description
PICLK Delay from PCLK [7:0] Set-up Time w.r.t. PICLK [7:0] Hold Time w.r.t. PICLK Serial Clock (LPDATOP) SERDATOP/N Valid Prop Delay Serial Clock (LPDATOP) Duty Cycle
Units
tDRP
REFCKINP High PCLK High Valid Prop Delay
Figure Input Timing
PCLK tDPICLK
PICLK tSPIN PIN[7:0]
Notes Output Timing:
When set-up time specified signals between input clock, setup time time nanoseconds from point input point clock. When hold time specified signals between input clock, hold time time nanoseconds from point clock point input.
tHPIN
Figure 10a. Clock Data Output Timing with TSCLKSEL Asserted
Figure 10b. REFCKIP High PCLK High Valid Prop Delay
LPDATOP
tDSER
REFCKINP
tDRP
SERDATOP/N
PCLK
Notes PECL Output Timing:
Output propagation delay time high speed PECL outputs time nanoseconds from cross-over point reference signal crossover point output.
December 1999 Revision
S3017/S3018
SONET/SDH/AOC-12 TRANSMITTER RECEIVER
-40°C +85°C, ±5%)
Table S3018 Timing Characteristics
Symbol
tSPOUT tHPOUT
Description
POCLK Duty Cycle POUT[7:0] Set-up Time w.r.t. POCLK POUT[7:0] Hold Time w.r.t. POCLK SERDATIP/N Minimum Pulse Width
Units
Figure Output Timing Diagram
POCLK tSPOUT POUT[7:0],
Notes Output Timing: Output propagation delay time outputs time nanoseconds from point reference signal point output. Maximum output propagation delays duty cycles outputs measured with load ohms ground outputs.
tHPOUT
December 1999 Revision
SONET/SDH/AOC-12 TRANSMITTER RECEIVER RECEIVER FRAMING
Figure shows typical reframe sequence which byte realignment made. frame byte boundary detection enabled rising edge remains enabled while high. Realignment occurs upon receipt first byte. frame boundary recognized upon receipt third byte, which first data byte reported with correct byte alignment outgoing data (POUT[7:0]). Concurrently, frame pulse high POCLK cycle. When interfacing with section terminating device, input remains high full frame after first frame pulse while section terminating device verifies internally that frame byte alignment
S3017/S3018
correct, shown Figure Since least framing pattern been detected since rising edge OOF, boundary detection disabled when low. frame byte boundary detection block activated rising edge OOF, stays active until first pulse until goes low, whichever occurs last. Figure shows typical timing pattern which occurs when S3018 connected down stream section terminating device. remains high full frame after first pulse. frame byte boundary detection block active until goes low. Figure shows frame byte boundary detection activation rising edge OOF, deactivated first pulse.
Figure Frame Byte Detection
NOTE Range input output delay POCLK cycles
Figure Operation Timing with PM5312 STTX PM5355 SUNI-622
BOUNDARY DETECTION ENABLED
Figure Alternate Timing
BOUNDARY DETECTION ENABLED
December 1999 Revision
APPLICATION NOTE
S3017/S3018 INTRODUCTION
S3017 WITH SONET/SDH/AOC-12 TRANSMITTER RECEIVER DATA CLOCK SYNCHRONOUS REFERENCE CLOCK
some applications necessary "forward clock" data SONET/SDH system. this application reference clock from which high speed serial clock synthesized parallel data clock both originate from same (usually TTL/CMOS) clock source. This application note explains AMCC S3017 configured operate this mode. Clock Control Logic Description timing control logic S3017 automatically generates internal load signal which fixed relationship reference clock. logic takes into account variation reference clock internal load signal over temperature voltage.
connections required implement design shown Figure timing specifications shown Figure setup hold times PICLK data must controller ASIC. recommend latching data falling edge output reference clock order meet required specifications. Possible Problems order meet jitter generation specifications required SONET, jitter reference clock must minimized. difficult meet SONET jitter generation specifications using reference clock input with reference source.
Figure S3017 with Data Clocked Reference Clock
TTL/PECL Converter <3.5
PECL REFCLK
ASIC
Output Reference Clock PICLK
S3017
Output Data Data DATAIN[7:0]
Serial Data
Figure Data Timing with Respect PICLK
PICLK DATAIN [7:0]
December 1999 Revision
SONET/SDH/AOC-12 TRANSMITTER RECEIVER
Figure System Block Diagram
Reference Clock REFCKINP/N
S3017/S3018
S3017
SERDATOP/N
TOUT[7:0]
PIN[7:0]
PM5355 SUNI-622 PM5312 STTX
TCLK
PCLK PICLK
LPDATOP/N
REFCKINP/N
S3018
LPDATIP/N
RIN[7:0] RIFP
POUT[7:0]
SERDATIP/N RICLK POCLK
December 1999 Revision
S3017/S3018
Ordering Information
SONET/SDH/AOC-12 TRANSMITTER RECEIVER
PREFIX
Integrated Circuit
DEVICE
3017
PACKAGE
PQFP
HEATSINK
w/DW0045-28 heatsink unattached w/DW0045-29 heatsink unattached
PREFIX
Integrated Circuit
DEVICE
3018
PACKAGE
PQFP
HEATSINK
w/DW0045-28 heatsink unattached w/DW0045-29 heatsink unattached
Prefix
XXXX
Device
Package
Heatsink (Heatsink identifier marked part)
Applied Micro Circuits Corporation 6290 Sequence Dr., Diego, 92121 Phone: (858) 450-9333 (800) 755-2622 Fax: (858) 450-9885 http://www.amcc.com
AMCC reserves right make changes products discontinue semiconductor product service without notice, advises customers obtain latest version relevant information verify, before placing orders, that information being relied current. AMCC does assume liability arising application product circuit described herein, neither does convey license under patent rights rights others. AMCC reserves right ship devices higher grade place those lower grade. AMCC SEMICONDUCTOR PRODUCTS DESIGNED, INTENDED, AUTHORIZED, WARRANTED SUITABLE LIFE-SUPPORT APPLICATIONS, DEVICES SYSTEMS OTHER CRITICAL APPLICATIONS. AMCC registered trademark Applied Micro Circuits Corporation. Copyright 1999 Applied Micro Circuits Corporation
December 1999 Revision

SONET/SDH/AOC-12 TRANSMITTER RECEIVER BiCMOS PECL CLOCK GENERATOR SONE

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