Quad Mapper TXC-04251 DATA SHEET FEATURES Add/drop four 1.544 Mbi
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QT1M Device
Quad Mapper TXC-04251 DATA SHEET FEATURES
Add/drop four 1.544 Mbit/s signals from STS-1, STS-3/AU-3, STM-1 VC-4 Independent drop timing modes Selectable B8ZS positive/negative rail interface. Performance counter provided coding violations Digital desynchronizer reduces systemic jitter presence multiple pointer movements. register also provided control internal FIFO leak rate Drop buses monitored parity, loss clock, upstream multiframe errors Performance counters provided VT/TU pointer movements, BIP-2 errors Block Errors (FEBEs) VT/TUs monitored Loss Pointer, Data Flags (NDFs), AIS, Remote Defect Indication (RDI), size errors (S-bits) Byte Signal Label Mismatch Unequipped detection facility line loopbacks, generation BIP-2 FEBE errors, send capability Multiplexed microprocessor interface with interrupt capability IEEE 1149.1 standard boundary scan 160-pin plastic quad flat package
Quad Mapper device designed add/drop multiplexer, terminal multiplexer, dual single unidirectional ring applications. Four 1.544 Mbit/s signals mapped from asynchronous Virtual Tributaries (VT1.5s) Tributary Unit-11s (TU-11s). QT1M interfaces multiple-segment, byte-parallel SONET/SDH-formatted 19.44 Mbit/s byte rate STS-3/STM-1 operation 6.48 Mbit/s byte rate STS-1 operation. 1.544 Mbit/s signals either AMI/B8ZS positive/negative rail- NRZ-formatted signals. QT1M provides performance counters, alarm detection, ability generate errors Alarm Indication Signals (AIS). facility line loopback capabilities also provided. interface connect other TranSwitch devices, such STM-1/STS-3/STS-3c Overhead Terminator (SOT-3), TXC-03003/TXC-03003B, form STS-3/STM-1 add/drop terminal system.
APPLICATIONS
STS-1/STS-3/STM-1 1.544 Mbit/s add/drop mux/demux Unidirectional bidirectional ring applications STS-1/STS-3/STM-1 termination terminal mode multiplexer STS-1/STS-3/STM-1 test equipment
STS-1/STS-3/S- SONET/SDH LINE SIDE side drop side side drop side
External Clock Boundary Scan
1.544 Mbit/s TERMINAL SIDE Port Port Port Port
data clock receive transmit, plus receive data zero-output control
QT1M Quad Mapper
TXC-04251
Microprocessor interface Controls
U.S. Patents No.: 4,967,405; 5,033,064; 5,040,170; 5,265,096; 5,289,057 U.S. and/or foreign patents issued pending Copyright 1995-1997 TranSwitch Corporation TranSwitch registered trademarks TranSwitch Corporation
Document Number: TXC-04251-MB December 1997
TranSwitch Corporation Enterprise Drive Shelton, Connecticut 06484 Tel: 203-929-8810 Fax: 203-926-9453 www.transwitch.com
QT1M TXC-04251 TABLE CONTENTS
Section Page List Figures Block Diagram. Block Diagram Description Diagram Descriptions Absolute Maximum Ratings Environmental Limitations Thermal Characteristics Recommended Operating Conditions Power Requirements Input, Output Parameters Timing Characteristics Operation 29-60 Interface Modes Mode Selection SONET/SDH Add/Drop Multiplexing Format Selections Add/Drop VT/TU Selection Timing Drop Multiframe Alignment Multiframe Alignment Performance Counters Alarm Structure Interrupt Structure SONET/SDH Detection VT/TU Pointer Tracking Pointer Leak Rate Calculations Remote Defect Indications (RDI) Overhead Communications Access TUG-3 Null Pointer Indicator Loopback Capability Resets Data Throughput Delay Boundary Scan Multiplex Format Mapping Information Memory Memory Descriptions Package Information Ordering Information Related Products Standards Documentation Sources List Data Sheet Changes Documentation Update Registration Form Please note that TranSwitch provides documentation products. Customers using TranSwitch Product, planning should register with TranSwitch Marketing Department receive relevant updated supplemental documentation issued. They should also contact Applications Engineering Department ensure that they provided with latest available information about product, especially before undertaking development designs incorporating product.
TXC-04251-MB December 1997
QT1M TXC-04251 LIST FIGURES
Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Page QT1M TXC-04251 Block Diagram 1544 kbit/s Mapping QT1M TXC-04251 Diagram Ports Transmit Timing Ports Receive Timing STS-1 Drop Signals, Timing Derived from Drop STS-3/STM-1 Drop Signals, Timing Derived from Drop STS-1 Signals, Timing Derived from STS-3/STM-1 Signals, Timing Derived from Microprocessor Read Cycle Timing Microprocessor Write Cycle Timing Boundary Scan Timing Byte Floating Mode Allocation VT/TU Pointer Tracking State Machine Facility Line Loopbacks Boundary Scan Schematic QT1M TXC-04251 160-Pin Plastic Quad Flat Package
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QT1M TXC-04251
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QT1M TXC-04251 BLOCK DIAGRAM
EXTCK QUIETn RPOn RNOn
Receive Drop)
VT/TU Terminate Side
Repeated Port
Destuff Receive Drop) VT/TU Terminate Side
Desync
AMI/B8ZS Coder
RCOn
Alarms Controls Alarms Controls, Timing
UPAD(7-0) INT/INT INTSH
Transmit Add)
VT/TU Build Side
Stuff/Sync Side AMI/B8ZS Decoder
TPIn TNIn/TLOSn TCIn
Drop
Drop
Transmit Add)
VT/TU Build Side
Stuff/Sync Side Repeated Port
IEEE 1149.1 Boundary Scan
Test Access Port
TEST ABUST HIGHZ RESET
Figure QT1M TXC-04251 Block Diagram
BLOCK DIAGRAM block diagram Quad Mapper shown Figure Quad Mapper interfaces four buses, designated Drop, Drop, Add, Add. four buses STS-3/STM-1 rate 19.44 Mbyte/s, STS-1 rate 6.48 Mbyte/s. North American applications, asynchronous signals carried floating Virtual Tributary 1.5s (VT1.5s) Synchronous Transport Signal (STS-1), STS-1s that carried Synchronous Transport Signal (STS-3). applications, signals carried floating mode Tributary Unit -11s (TU-11s) STM-1 Virtual Container structure (VC-4) using Tributary Unit Group (TUG-3), STM-1 Virtual Container structure (VC-3) using Tributary Unit Group (TUG-2) mapping schemes. Four signals dropped from Drop Drop), from both drop buses, lines. Four asynchronous signals formatted into VT1.5s added either buses, both, depending upon mode operation. When Quad Mapper configured drop timing, buses are, definition, byte- multiframe-synchronous with their like-named drop buses, delayed byte time because internal processing. example, byte STM-1 Virtual Container structure (VC-4) using Tributary Unit Group (TUG-3), VT1.5/ TU-11 added bus, time placement derived from Drop timing, from software instructions specifying which VT/TU number being dropped/added. When device configured timing, bus, parity, indicator signals derived from clock, C1J1V1 signals. -5TXC-04251-MB December 1997
QT1M TXC-04251
Receive block identical Receive block. VT/TU Terminate block repeated times, each port sides). Destuff, Desync, AMI/B8ZS Coder Blocks repeated four times, each port. interface between drop Receive block consists input leads (pins), optional output lead: byte clock, byte-wide data, C1J1 indicator which carrying indication making signal C1J1V1 indicator, indicator, parity last-named three signals. Parity selectable control bits even parity data byte only. output lead optional VT/TU select indicator signal. Drop C1J1V1 signal used conjunction with Drop signal determine location various pulses. pulse identifies location byte when signal low. single pulse identifies starting location byte VC-4 format, when signal high. Three pulses provided STS-3 format, each identifying starting location byte each STS-1 signals. Quad Mapper operate with pulse C1J1V1 signal, internal detector determining location pulse. pulse location used determine location pointer byte STM-1 VC-4 operation, C1J1V1 signal used, single pulse must occur three drop clock cycles every four frames following pulse. STS-3 operation, three pulses must present every four frames. Each three pulses must present three clock cycles after corresponding pulse, when signal high. example, VC-4 signal, pulse identifies byte location (defined starting location VC-4) bytes. next column (first clock cycle) rows assigned fixed stuff. Similarly, next column (second clock cycle) rows assigned fixed stuff. next column (third clock cycle) defines start TUG-3 This column where pulse occurs every four frames. However, actual byte location clock cycles after pulse. STS-1 operation, must present C1J1V1 signal used. pulse must occur next clock cycle after when signal high. pulse identifies byte location (defined starting location STS-1) bytes. next column (first clock cycle) start. Thus, pulse identifies starting location first byte signal. rest bytes VT1.5/TU-11s aligned regarding their starting point with respect pulse. Each monitored parity errors, loss clock, multiframe alignment selected, upstream SONET/SDH indication. Quad Mapper monitor either bytes H1/H2 bytes indication. Which byte H1/H2 bytes selected function VT/TU selected. Each VT/TU Terminate block side) performs pointer processing based location bytes. pointer bytes monitored loss pointer, indication, NDF. pointer tracking process based latest ETSI standard, which also meets ANSI/Bellcore requirements. Pointer increments decrements also counted, SS-bits monitored correct value. This block also monitors various alarms found bytes, including signal label mismatch detection, unequipped status detection, BIP-2 parity error detection error counter, FEBE counter, indications. control each port selects VT/TU from either Drop Drop bus. VT/TU destuffed Destuff block using majority logic rules three sets three justification control bits determine S-bits data bits frequency justification bits. Desync block removes effects output systemic jitter that might occur because signal mappings pointer movements network. Desync block contains parts, pointer leak buffer, loop buffer. pointer leak buffer accept five consecutive pointer movements, adjust effect over time. Loop Buffer consists digital loop filter, which designed track frequency received signal remove both transmission stuffing jitter.
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QT1M TXC-04251
option each port provides either data clock, AMI- B8ZS-encoded positive negative rail signal interface. Transmit data (towards line), four channels, clocked either rising falling edges clock. addition, control bits provided forcing data clock signals high impedance state. control lead provided forcing output leads state. direction, Quad Mapper accepts clock either data AMI- B8ZS-encoded positive negative rail signals. Data, four channels, clocked either negative rising edge clock. mode, external loss clock indication input signal provided. rail signal, coding violations counted, signal monitored loss signal. T1AIS detector also provided. data signal written into FIFO eight Stuff/Sync Blocks. Threshold modulation used frequency justification process. Timing information from drop used read FIFO perform VT/TU justification process. This block permits tracking incoming signal having average frequency offset high ppm, peak-to-peak jitter. Since Quad Mapper supports ring architecture, sets blocks provided each port. VT/TU selection same both blocks. control bit, transmit line alarms, generate T1AIS. eight VT/TU Blocks format VT/TU into STS-1, STS-3 STM-1 structure asynchronous 1544 kbit/s signals, shown Figure pointer value carried bytes transmitted with fixed value Transmit access provided overhead communications channel bits (O-bits) microprocessor. microprocessor also writes signal label, values bytes. Block Error (FEBE) inserted from BIP-2 errors detected receive side, BIP-2 parity generated. Control bits provided generating unequipped status, generating VT/TU AIS, inserting FEBE BIP-2 errors. ability generate Null Pointer Indicators (NPIs) also provided STM-1 VC-4 format. Transmit block identical Transmit block. interface between Transmit block consists three input pins eleven output pins, when timing mode selected. input pins byte clock, C1J1V1 indicator, indicator. output pins byte-wide data, parity indicator, indicator, optional VT/TU selection indicator signal. C1J1V1 signal used conjunction with signal determine location various pulses. option provided which drop side reference pulse, either from drop C1J1V1 indicator from multiframe detector, used side reference pulse. When drop timing selected, output pins byte-wide data, parity indicator, indicator, optional VT/TU selection indicator signal. clock, C1J1V1 signals disabled. microprocessor interface consists multiplexed address/data bus. Interrupt capability also provided. alarms that cause interrupt positive, negative, positive negative transitions, positive levels. Interrupt mask bits provided register byte locations, some defined bits. Control bits provided which enable facility line loopback. Because complexity SONET/ interface timing modes, SONET/SDH loopback VT/TUs supported. Boundary Scan Interface block provide five-pin Test Access Port (TAP) that conforms IEEE 1149.1 standard. This standard provides external boundary scan functions read write external pins from board component test.
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QT1M TXC-04251
Figure 1544 kbit/s Mapping
RRRRRRIR bytes (1.544 Mbit/s Data)
VT1.5 (Pointer Byte)
bytes
Information Overhead communications Justification control Justification opportunity Fixed stuff (set
(Pointer Byte)
bytes (1.544 Mbit/s Data)
bytes
bytes (1.544 Mbit/s Data)
(Action)
bytes
bytes (1.544 Mbit/s Data) Bytes
(Reserved)
bytes
Data Flag Normal 0110 1001
Size S1S2
Positive Justification Invert five I-bits Negative Justification Invert five D-bits Pointer Range decimal
Pointer Structure
BIP-2 Interleaved Parity bits) FEBE Block Error Indication Remote Failure Indication L1L2L3 Signal Label Remote Defect Indication
Path Overhead (V5) Byte
BIP-2 FEBE Signal Label
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QT1M TXC-04251 DIAGRAM
QUIET4 TCI4 TNI4/TLOS4 TPI4 RCO4 RNO4 RPO4 RCO2 RNO2 RPO2 QUIET2 TCI2 TNI2/TLOS2 TPI2 BAIND BDIND BDCLK BACLK BAC1J1V1 BASPE BDC1J1V1 BDSPE BDPAR
Reserved Reserved QUIET3 TCI3 TNI3/TLOS3 TPI3 RCO3 RNO3 RPO3 RCO1 RNO1 RPO1 QUIET1 TCI1 TNI1/TLOS1 TPI1 AAIND ADIND ADCLK AACLK AAC1J1V1 AASPE ADC1J1V1 ADSPE
Figure QT1M TXC-04251 Diagram
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Reserved UPAD0 UPAD1 UPAD2 UPAD3 UPAD4 UPAD5 UPAD6 UPAD7 Reserved HIGHZ EXTCK Reserved Reserved Reserved Reserved TEST INTSH INT/INT Reserved RESET Reserved ABUST Reserved Reserved Reserved
QT1M Diagram (Top View) TXC-04251
BADD BAPAR AAPAR AADD ADPAR
QT1M TXC-04251 DESCRIPTIONS
POWER SUPPLY, GROUND, CONNECT RESERVED Symbol 103, 115, 123, 131, 137, 142, 100, 108, 120, 127, 134, 139, (see Note I/O/P Type Name/Function VDD: +5-volt supply voltage, ±5%.
Ground: volt reference.
Connect: pins connected, even another pin, must left floating. pins used manufacturing test purposes, and/or assigned functions future versions device. Connection these pins impair performance even cause damage device, could prevent substitution future device versions application. Reserved: Reserved pins permit connection leads input/output signals which used/ provided QT1M device. Such signals used/provided other pin-compatible devices that could substituted QT1M applications, particularly future versions QT1M device which have additional features requiring these pins.
Reserved
135, 140, 143, 144, 156,
Input; Output; Power; Tri-state Note QT1M used application environment (e.g., PCB) that also used QE1M device, then must connected specified Data Sheet QE1M. This will have effect QT1M.
DROP Symbol ADCLK I/O/P Type TTLs Name/Function Drop Clock: This clock operates 19.44 STS-3/STM-1 operation, 6.48 STS-1 operation. Drop byte-wide data (AD7-AD0), parity (ADPAR), indication (ADSPE), C1J1V1 indication (ADC1J1) clocked falling edges this clock. This clock also used timing deriving like-named byte-wide data, VT/TU indications, parity bits. signals clocked rising edges clock during time slots that correspond selected VT/TU. Drop Parity Bit: parity input signal representing parity calculation each data byte, SPE, C1J1V1 signal from drop bus. Control bits provided which enable even parity calculated (control data byte only (control PDDO
ADPAR
Input, Output Parameters section Type definitions.
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Symbol AD(7-0) I/O/P Type Name/Function Drop Data Byte: Byte-wide data that corresponds STS-3/STM-1/STS-1 signal from drop bus. first received (dropped) corresponds Drop Indicator: signal that active high during each byte STS-3/STM-1/STS-1 payload, during Transport Overhead times. Drop C1J1V1 Indications: active high timing signal that carries STS-3/STM-1/STS-1 starting frame information. This signal works conjunction with ADSPE signal. pulse identifies location first byte STS-3/STM-1 signal, byte STS-1 signal, when ADSPE low. signal identifies starting location signal when ADSPE high. more pulses present depending upon format. pulses used place byte multiframe indication. Drop VT/TU Selection Indication: Enabled when control ADnEN written with active signal that clocked time slots determined VT/TU selection (VTNn register) each port. Clock: When timing mode selected, this input must provided timing. This clock operates 19.44 STS-3/STM-1 operation, 6.48 STS-1 operation. indication (AASPE), C1J1V1 indication (AAC1J1V1) clocked falling edges this clock. byte-wide data (AA7-AA0), indicator (AADD), parity (AAPAR) clocked rising edges clock during time slots that correspond selected VT/TU. When drop timing selected, this input disabled. Parity Bit: parity output signal that calculated over byte-wide data. This tristate only active when there data being added bus. When control even parity calculated. Data Byte: Byte-wide data that corresponds selected VT/TU.
ADSPE
ADC1J1V1
ADIND
CMOS
AACLK
TTLs
AAPAR
O(T)
CMOS
AA(7-0)
O(T)
CMOS
AASPE
Indicator: When timing mode selected, this signal must provided timing. This signal must high during each byte STS-3/STM-1/STS-1 payload, during Transport Overhead byte times.
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QT1M TXC-04251
Symbol AAC1J1V1 I/O/P Type Name/Function C1J1V1 Indications: When timing mode selected, this signal must provided timing. active high timing signal that carries STS-3/STM-1/STS-1 starting frame information. This signal works conjunction with AASPE signal. pulse identifies location first byte STS-3/STM-1 signal, byte STS-1 signal, when AASPE low. signal identifies starting location signal when AASPE high. signal identifies location byte. more pulses present depending upon format. pulses used place byte multiframe indication. VT/TU Selection Indication: Enabled when control AAnEN written with active signal that clocked time slots determined selection (VTNn register) each port. Data Present Indicator: This normally active signal present when output data valid. identifies location time slots being selected. When control ADDI indicator active high instead low.
AAIND
CMOS
AADD
CMOS
DROP Symbol BDCLK I/O/P Type TTLs Name/Function Drop Clock: This clock operates 19.44 STS-3/STM-1 operation, 6.48 STS-1 operation. Drop byte-wide data (BD7-BD0), parity (BDPAR), indication (BDSPE), C1J1V1 indication (BDC1J1) clocked falling edges this clock. This clock also used timing deriving like-named byte-wide data, VT/TU indications, parity bits. signals clocked rising edges clock during time slots that correspond selected VT/TU. Drop Parity Bit: parity input signal representing parity calculation each data byte, SPE, C1J1V1 signal from drop bus. Control bits provided which enable even parity calculated (control data byte only (control PDDO Drop Data Byte: Byte-wide data that corresponds STS-3/STM-1/STS-1 signal from drop bus. first received (dropped) corresponds
BDPAR
BD(7-0)
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QT1M TXC-04251
Symbol BDSPE I/O/P Type Name/Function Drop Indicator: signal that active high during each byte STS-3/STM-1/STS-1 payload, during Transport Overhead times. Drop C1J1V1 Indications: active high timing signal that carries STS-3/STM-1/STS-1 starting frame information. This signal works conjunction with BDSPE signal. pulse identifies location first byte STS-3/STM-1 signal, byte STS-1 signal, when BDSPE low. signal identifies starting location signal when BDSPE high. more pulses present depending upon format. pulses used place byte multiframe indication. Drop VT/TU Selection Indication: Enabled when control BDnEN written with active signal that clocked time slots determined VT/TU selection (VTNn register) each port. Clock: When timing mode selected, this input must provided timing. This clock operates 19.44 STS-3/STM-1 operation, 6.48 STS-1 operation. indication (BASPE), C1J1V1 indication (BAC1J1V1) clocked falling edges this clock. byte-wide data (BA7-BA0), indicator (BADD), parity (BAPAR) clocked rising edges clock during time slots that correspond selected VT/TU. When drop timing selected, this input disabled. Parity Bit: parity output signal that calculated over byte-wide data. This tristate only active when there data being added bus. When control even parity calculated. Data Byte: Byte-wide data that corresponds selected VT/TU.
BDC1J1V1
BDIND
CMOS
BACLK
TTLs
BAPAR
O(T)
CMOS
BA(7-0)
O(T)
CMOS
BASPE
Indicator: When timing mode selected, this signal must provided timing. This signal must high during each byte STS-3/STM-1/STS-1 payload, during Transport Overhead byte times.
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QT1M TXC-04251
Symbol BAC1J1V1 I/O/P Type Name/Function C1J1V1 Indications: When timing mode selected, this signal must provided timing. active high timing signal that carries STS-3/STM-1/STS-1 starting frame information. This signal works conjunction with BASPE signal. pulse identifies location first byte STS-3/STM-1 signal, byte STS-1 signal, when BASPE low. signal identifies starting location signal when BASPE high. signal identifies location byte. more pulses present depending upon format. pulses used place byte multiframe indication. VT/TU Selection Indication: Enabled when control BAnEN written with active signal that clocked time slots determined selection (VTNn register) each port. Data Present Indicator: This normally active signal present when output data valid. identifies location time slots being selected. When control ADDI indicator active high instead low.
BAIND
CMOS
BADD
CMOS
PORT LINE INTERFACE Symbol RCOn (n=1-4) 111, I/O/P O(T) Type CMOS Name/Function Receive Port Output Clock: 1.544 clock output. Data normally clocked rising edges this clock. When control RCKI data clocked falling edges this clock. When control RnEN this forced high impedance state. Receive Port Data Positive Rail NRZ: When control BYPASn positive rail data provided this lead. When control BYPASn signal provided this pin. When control RnEN this forced high impedance state. Receive Port Data Negative Rail: When control BYPASn negative rail data provided this pin. When control RnEN control BYPASn this forced high impedance state. Transmit Port Input Clock: 1.544 clock input. Data normally clocked falling edges this clock. When control TCKI data clocked rising edges this clock. Transmit Port Data Positive Rail NRZ: When control BYPASn positive rail input data provided this pin. When control BYPASn signal provided this pin. TXC-04251-MB December 1997
RPOn (n=1-4)
109,
O(T)
CMOS
RNOn (n=1-4)
110,
O(T)
CMOS
TCIn (n=1-4)
106,
TTLs
TPIn (n=1-4)
104,
QT1M TXC-04251
Symbol TNIn/ TLOSn (n=1-4) QUIETn (n=1-4) 107, 105, I/O/P Type Name/Function Transmit Port Data Negative Rail/External Loss Signal: When control BYPASn negative rail input data provided this pin. When control BYPASn this used input active external loss signal indicator from line interface device. Quiet Port high forces RPOn RNOn pins state either rail interface, overriding control RnEN. allows state RPOn RNOn pins controlled RnEN.
MICROPROCESSOR INTERFACE Symbol UPAD(7-0) 133, 132, 130, 129, 128, 126, 125, I/O/P Type Name/Function Address/Data Bus: These pins constitute timemultiplexed address data accessing registers which reside memory Quad Mapper. UPAD7 most significant bit. High logic Select: signal generated microprocessor accessing memory registers control, status, alarm information. Read: signal generated microprocessor reading registers which reside memory map. memory selected placing select pin. Write: signal generated microprocessor writing registers which reside memory map. memory selected placing select pin. Address Latch Enable: active high signal generated microprocessor holding address stable during read/write cycle. Interrupt: high this output signals interrupt request microprocessor. polarity this signal determined state INTSH pin. Interrupt Sense High Selection: high this causes interrupt sense high when interrupt occurs. causes interrupt sense when interrupt occurs.
TTLs
TTLs
TTLs
TTLs
INT/INT
O(T)
INTSH
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CONTROLS Symbol TEST EXTCK I/O/P Type TTLs CMOS Name/Function TranSwitch Test Bit: high must placed this pin. External Reference Clock: This clock used desynchronizer operation other purposes. clock frequency must 48.6360 (+/- over life) clock duty cycle must 10%. Hardware Reset: When active pulse applied this minimum nanoseconds after power applied, this pulse clears performance counters alarms, resets control bits (except those bits that force high impedance state buses), initializes internal FIFOs. microprocessor must write control states normal operation. High Impedance Select: forces output pins high impedance state testing purposes. Timing Select: active selects clock, C1J1V1 input signals deriving timing buses. active high selects like-named drop deriving timing (e.g., Drop bus). This control disabled when written control SBTEN.
RESET
TTLs
HIGHZ ABUST
TTLs TTLs
BOUNDARY SCAN INTERFACE SIGNALS Symbol I/O/P Type Name/Function IEEE 1149.1 Test Port Serial Scan Clock: This signal used shift data into rising edge, falling edge. maximum clock frequency MHz. IEEE 1149.1 Test Port Mode Select: sampled rising edge TCLK, used place Test Access Port controller into various states defined IEEE 1149.1. This input internal pull-up VDD. IEEE 1149.1 Test Port Serial Scan Data Serial test instructions data clocked into this rising edge TCK. This input internal pull-up VDD. IEEE 1149.1 Test Port Serial Scan Data Out: Serial test instructions data clocked this falling edge TCLK. When inactive, this 3-state output will into high impedance state. IEEE 1149.1 Test Port Reset Pin: This will asynchronously reset Test Access Port (TAP) controller. This input internal pull-up VDD.
TTLp
TTLp
TTLp
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QT1M TXC-04251 ABSOLUTE MAXIMUM RATINGS ENVIRONMENTAL LIMITATIONS
Parameter Supply voltage input voltage Operating junction temperature Storage temperature range Lead Temperature Time Moisture Exposure Level Relative Humidity, non-condensing Classification Symbol ±2000 -0.5 -0.5 +6.0
Unit
Conditions Note Note Note Note EIA/JEDEC JESD22-A112-A Note MIL-STD-883D Method 3015.7
Level
Notes: Conditions exceeding values cause permanent failure. Exposure conditions near values extended periods impair device reliability. Pre-assembly storage non-drypack conditions recommended warranted.
THERMAL CHARACTERISTICS
Parameter Thermal resistance: junction ambient -Typ -Max 41.4 Unit
Test Conditions ft/min linear airflow
RECOMMENDED OPERATING CONDITIONS POWER REQUIREMENTS
Parameter Ambient operating temperature 4.75 1010 1020 1225 1250 5.25 1130 1550 1575 Unit
Test Conditions ft/min linear airflow STS-1 (see Note STS-1 (see Note STS-3 (see Note STS-3 (see Note STM-1 (see Note STM-1 (see Note
Note values assume more than loading.
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QT1M TXC-04251 INPUT, OUTPUT PARAMETERS
INPUT PARAMETERS CMOS Parameter Input leakage current Input capacitance 3.15 1.65 Unit Test Conditions 4.75 5.25 4.75 5.25 5.25
INPUT PARAMETERS Parameter Input leakage current Input capacitance +1.0 Unit Test Conditions 4.75 5.25 4.75 5.25 5.25
INPUT PARAMETERS TTLs Parameter Negative going, threshold voltage Positive going, threshold voltage Input leakage current Input capacitance Vhys Hysteresis (VT+ VT-) Unit 5.25 Test Conditions
INPUT PARAMETERS TTLp, INPUT PADS WITH INTERNAL PULL Parameter Input leakage current Input capacitance Unit Test Conditions 4.75 5.25 4.75 5.25 5.25
Note: TTLp inputs disabled device testing applying TEST (pin 145).
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QT1M TXC-04251
OUTPUT PARAMETERS CMOS Parameter (HIGHZ output current) -4.0 +10.0 Unit Test Conditions 4.75; -4.0 4.75;
INPUT/OUTPUT PARAMETERS Parameter Input leakage current Input capacitance -8.0 +1.0 Unit 4.75; -8.0 4.75; Test Conditions 4.75 5.25 4.75 5.25 5.25
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QT1M TXC-04251 TIMING CHARACTERISTICS
Detailed timing diagrams QT1M device illustrated Figures through with values timing intervals tabulated below each timing diagram. output times measured with maximum load capacitance. Timing parameters measured voltage levels (VIH VIL)/2 input signals voltage levels (VOH VOL)/2 output signals. Figure Ports Transmit Timing
tCYC tPWL TCIn (INPUT) TPIn/TNIn (INPUT)
Note:
tPWH
Note: TCIn shown TCLKI where data clocked falling edges. Data clocked rising edges when TCLKI operation, TNIn used input external loss signal indication. Otherwise, this must held high.
Parameter TCIn Clock period TCIn clock time TCIn clock high time TPIn/TNIn data set-up time before TCIn TPIn/TNIn data hold time after TCIn
Symbol tCYC tPWL tPWH
647.7
Unit
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QT1M TXC-04251
Figure Ports Receive Timing
tCYC tPWH RCOn (OUTPUT) RPOn/RNOn (OUTPUT)
Note:
tPWL
Note: RCOn shown RCLKI=0, where data clocked rising edges. Data clocked falling edges when RCLKI=1.
Parameter RCOn clock period RCOn clock time RCOn clock high time RPOn/RNOn data delay from RCOn
Symbol tCYC tPWL tPWH
Unit
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QT1M TXC-04251
Figure STS-1 Drop Signals, Timing Derived from Drop
tCYC A/BDCLK (INPUT) tSU(1) A/BD(7-0) (INPUT) A/BDSPE (INPUT) tSU(3) A/BDC1J1V1 (INPUT) A/BDIND (OUTPUT) A/BA(7-0) (OUTPUT) tOD(1) A/BADD (OUTPUT) tOD(4) A/BAIND (OUTPUT)
VT/TU Time Slot when enabled
tPWH
tH(1) tSU(2) Data tH(2) tH(3) tD(1) tOD(2)
VT/TU Selected Occurs every four frames when provided place byte
Data
VT/TU Selected
Data
Data
Drop VT/TU Time Slot when enabled
tOD(3)
Note: illustration purposes, single VT/TU number shown. pulse present. pulse present, byte must provided. additional byte time delay A(7-0) provided when control written with
Parameter DCLK clock period DLCK duty cycle tPWH/tCYC D(7-0) data time before DCLK D(7-0) data hold time after DCLK DSPE time before DCLK DSPE hold time after DCLK DC1J1V1 time before DCLK DC1J1V1 hold time after DCLK DIND drop indication output delay from DCLK A(7-0) data (from tristate) delay from DCLK A(7-0) data tristate delay from DCLK indicator delayed from DCLK AIND indication output delay from DCLK
Symbol tCYC
154.32
Unit
tSU(1) tH(1) tSU(2) tH(2) tSU(3) tH(3) tD(1) tOD(2) tOD(3) tOD(1) tOD(4)
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Figure STS-3/STM-1 Drop Signals, Timing Derived from Drop
tCYC
A/BDCLK (INPUT) A/BD(7-0) (INPUT) A/BDSPE (INPUT) A/BDC1J1V1 (INPUT) A/BDIND (OUTPUT) A/BA(7-0) (OUTPUT) A/BADD (OUTPUT)
tPWH
tSU(1)
C1(1)
tH(1)
C1(2) C1(3) Data
VT/TU Selected Byte STS-1
STS-1
STS-1
Data STS-1
tSU(2)
tH(2)
Occurs every four frames when provided place byte STS-1 STS-1 STS-1 STS-1 STS-1 STS-1
tSU(3)
C1(1)
tH(3)
tD(1)
Drop VT/TU Time Slot selected when enabled
tOD(2)
VT/TU Selected
tOD(3)
tOD(1)
tOD(4)
A/BAIND (OUTPUT)
VT/TU Time Slot selected when enabled
Note: single VT/TU shown illustration purposes. also shows VT/TU selection drop (number STS-1 number format AU-3/STS-3. VC-4 operation, pulse optional pulse present. additional byte time delay A(7-0) provided when control written with
Parameter DCLK clock period DCLK duty cycle tPWH/tCYC D(7-0) data time before DCLK D(7-0) data hold time after DCLK DSPE time before DCLK DSPE hold time after DCLK DC1J1V1 time before DCLK DC1J1V1 hold time after DCLK DIND drop indication output delay from DCLK A(7-0) data (from tristate) delay from DCLK A(7-0) data tristate delay from DCLK indicator delayed from DCLK AIND indication output delay from DCLK
Symbol tCYC
51.44
Unit
tSU(1) tH(1) tSU(2) tH(2) tSU(3) tH(3) tD(1) tOD(2) tOD(3) tOD(1) tOD(4)
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Figure STS-1 Signals, Timing Derived from
tCYC A/BACLK (INPUT) tSU(2) A/BASPE (INPUT) tSU(1) A/BAC1J1V1 (INPUT) A/BA(7-0) (OUTPUT) tOD(1) A/BADD (OUTPUT) tOD(4) A/BAIND (OUTPUT)
VT/TU Time Slot when enabled
tPWH
tH(2)
Occurs every four frames when provided
tH(1) tOD(2)
VT/TU Selected
tOD(3)
Note: illustration purposes, single VT/TU shown. location this VT/TU corresponds VT/TU number additional byte time delay A(7-0) provided when control written with
Parameter ACLK clock period ACLK duty cycle, tPWH/tCYC AC1J1V1 time before ACLK AC1J1V1 hold time after ACLK ASPE time before ACLK ASPE hold time after ACLK A(7-0) data (from tristate) delay from ACLK A(7-0) data tristate delay from ACLK indicator delayed from ACLK AIND indication output delay from ACLK
Symbol tCYC
154.32
Unit
tSU(1) tH(1) tSU(2) tH(2) tOD(2) tOD(3) tOD(1) tOD(4)
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Figure STS-3/STM-1 Signals, Timing Derived from
tCYC
A/BACLK (INPUT) A/BASPE (INPUT) tSU(1) A/BAC1J1V1 (INPUT) A/BA(7-0) (OUTPUT)
C1(1)
tPWH tSU(2)
tH(2)
Occurs every four frames when enabled
tH(1)
STS-1 STS-1 STS-1
STS-1
STS-1
STS-1
tOD(2)
VT/TU Selected
tOD(3)
tOD(1)
(OUTPUT)
tOD(4)
A/BAIND (OUTPUT)
VT/TU Time Slot selected when enabled
Note: single VT/TU shown illustration purposes. also shows VT/TU selection drop (number STS-1 number format AU-3/STS-3. VC-4 operation, pulse optional pulse present. additional byte time delay A(7-0) provided when control written with
Parameter ACLK clock period ACLK duty cycle, tPWH/tCYC AC1J1V1 time before ACLK AC1J1V1 hold time after ACLK ASPE time before ACLK ASPE hold time after ACLK A(7-0) data (from tristate) delay from ACLK A(7-0) data tristate delay from ACLK indicator delayed from ACLK AIND indication output delay from ACLK
Symbol tCYC
51.44
Unit
tSU(1) tH(1) tSU(2) tH(2) tOD(2) tOD(3) tOD(1) tOD(4)
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Figure Microprocessor Read Cycle Timing tPW(1) tSU(1) UPAD(7-0) tH(1) Address tH(2) Data tOD(1) tW(1)
tSU(2)
tOD(2)
tH(3)
tW(2)
tPW(2)
Parameter pulse width UPAD(7-0) address set-up time before UPAD(7-0) address hold time after UPAD(7-0) data available delay after UPAD(7-0) data delay tristate after wait time after set-up before hold time after wait after pulse width
Symbol tPW(1) tSU(1) tH(1) tOD(2) tOD(1) tW(1) tSU(2) tH(3) tW(2) tPW(2)
Unit
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Figure Microprocessor Write Cycle Timing tPW(1) tSU(1) UPAD(7-0) tH(1) Address tSU(3) tW(2) tPW(2) tSU(2) Data tH(3) tH(2) tW(1)
Parameter pulse width wait after UPAD(7-0) address set-up time before UPAD(7-0) address hold time after UPAD(7-0) data set-up time before UPAD(7-0) data hold time after set-up time before hold time after wait after pulse width
Symbol tPW(1) tW(1) tSU(1) tH(1) tSU(2) tH(2) tSU(3) tH(3) tW(2) tPW(2)
Unit
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Figure Boundary Scan Timing
tPWL tPWH
(Input)
tH(1) tSU(1)
(Input)
tH(2) tSU(2)
(Input)
(Output)
Parameter clock high time clock time setup time before hold time after setup time before hold time after delay from
Symbol tPWH tPWL tSU(1) tH(1) tSU(2) tH(2)
Unit
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following sections detail internal operation Quad Mapper. INTERFACE MODES Quad Mapper supports following modes operation: Drop Mode Single Unidirectional Ring Mode Multiplexer Mode Dual Unidirectional Ring Mode Drop Mode drop mode operation, VT/TU terminated from either Drop receive output four ports, without return path transmit direction. Single Unidirectional Ring Mode single unidirectional ring mode operation, VT/TU dropped from Drop bus, with return path bus. Timing VT/TU added derived from either Drop bus, from bus. Multiplexer Mode multiplexer mode operation, VT/TU dropped from Drop bus, with return path bus. Timing VT/TU added derived from either Drop bus, from bus. Dual Unidirectional Ring Mode dual unidirectional ring mode operation, VT/TU dropped from Drop bus, with return path both buses. Timing VT/TU added derived from either Drop bus, from bus.
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MODE SELECTION VT/TU mode selection performed control bits defined table shown below. represents port number (1-4). Note: Both buses power high impedance state. must written control bits AAHZE BAHZE normal operation. Mode Type Dropping only, from Dropping only, from Single unidirectional ring Single unidirectional ring Multiplexer, Multiplexer Dual unidirectional ring Dual unidirectional ring TnSEL1 TnSEL0 RnSEL DROP from Drop-only Drop-only
Mode Selection Port
SONET/SDH ADD/DROP MULTIPLEXING FORMAT SELECTIONS control settings format selection given table shown below. When STS-1 format selected, buses configured operate rate 6.48 Mbyte/s, instead 19.44 Mbyte/s VC-4/ AU-3/STS-3 formats.
Format STS-1 Format STS-3 Format STM-1 AU-3 Format STM-1 TUG-3/VC-4 Format
MOD1
MOD0
Format Selection
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ADD/DROP VT/TU SELECTION Each four ports ability select transmit VT1.5 (VT/TU) either both neither) segment bus). VT1.5 (TU) number selection register labels, which consist seven bits, given following table. VT/TU selected valid both dropped (received) added (transmitted) VT/TU. Locations (port (port (port (port Meaning VT/TU Selected STS-1 AU-3/TUG-3 STS-1 AU-3/TUG-3 STS-1 AU-3/TUG-3 STS-1 VT/TU Selection VT/TU Group Number VT/TU Group Number VT/TU Group Number VT/TU Group Number VT/TU Group Number VT/TU Group Number VT/TU Group Number VT/TU Number VT/TU Number VT/TU Number VT/TU Number
AU-3/TUG-3 STS-1
VT/TU Group Number
VT/TU Number
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TIMING Timing adding VT/TU derived from like-named drop bus, from like-named bus. timing selectable using pin, through software. Upon power-up device reset, SBTEN (Software Timing Enable) control reset enable software control timing, SBTEN control must first written with which will override state placed ABUST pin. When SBTEN timing (add drop timing) controlled DRPBT control bit. various states associated with timing selection shown table below. ABUST High
Note: Don't Care
SBTEN
DRPBT*
Action timing selected. Drop timing selected. timing selected. ABUST disabled. Drop timing selected. ABUST disabled.
Timing Selection
DROP MULTIFRAME ALIGNMENT byte alignment receive direction (from drop bus) established using byte reference pulse ADC1J1V1 BDC1J1V1 signal. Depending format, three pulses will present this signal. When byte used establish byte alignment, pulse does have present ADC1J1V1 BDC1J1V1 signal. Writing control DV1SEL selects pulse ADC1J1V1 BDC1J1V1 signal used establish byte location reference, while selects byte multiframe detector establishing reference. multiframe detection circuits disabled when pulse used place byte. STM-1 VC-4 operation, single pulse must occur three drop clock cycles every four frames following pulse. STS-3/STM-1 AUG3 operation, three pulses must present every four frames. Each pulse must present three clock cycles after corresponding pulse, when signal high. example, VC-4 signal, pulse identifies byte location (defined starting location VC-4) bytes. next column (first clock cycle) rows assigned fixed stuff. Similarly, next column (second clock cycle) rows assigned fixed stuff. next column (third clock cycle) defines start TUG-3 This column where pulse occurs every four frames. However, actual byte occurs clock cycles after pulse. STS-1 operation, pulse must present. pulse must occur next clock cycle after when signal high. pulse identifies byte location (defined starting location STS-1) bytes. next column (first clock cycle) defines starting location. Thus, pulse identifies starting location first byte signal. rest bytes VT1.5s aligned regarding their starting point with respect pulse. timing relationships between other signals shown Timing Characteristics section.
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byte used identify location byte shown Figure below: 1544 kbit/s VT/TU (XXXX XX00) Previous Bytes (XXXX XX01) Bytes (XXXX XX10) Bytes (XXXX XX11) Bytes Figure Byte Floating Mode Allocation byte monitored multiframe alignment when enabled. Loss multiframe alignment declared (AnDH4E, BnDH4E) more byte values differ from those 2-bit counter consecutive multiframes. Recovery occurs when four consecutive sequential byte values detected once.
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MULTIFRAME ALIGNMENT When drop timing selected, alignment based using drop pulse (A/BDC1J1V1), reference signal that generated multiframe detectors drop side. When timing selected, byte alignment established using pulses that must present A/BAC1J1V1 signal, when written control DV1REF. When timing selected, drop reference from either A/BDC1J1V1 signal, from internal reference signal generated multiframe detector drop direction, also used reference when control DV1REF written with pulse present A/BAC1J1V1 signal ignored. This feature common three AU-3/STS-1 signals. Extreme care must taken when using this selection mode prevent byte alignment slips. control selection byte alignment given Table below. Timing Mode Drop timing selected DV1SEL DV1REF Action Drop multiframe detector determines dropped VT/TU byte starting location, added VT/TU byte starting location. pulse drop A/BDC1J1V1 signal ignored. Drop pulse A/BDC1J1V1 signal determines dropped VT/TU byte starting location, added VT/TU byte starting location. drop multiframe detector disabled. Drop multiframe detector determines dropped VT/TU byte starting location. pulse drop A/BDC1J1V1 signal ignored. alignment determined pulse A/BAC1J1V1 signal. Drop pulse A/BDC1J1V1 signal determines dropped VT/TU starting location. Drop multiframe detector disabled. alignment determined pulse A/BAC1J1V1 signal. Drop multiframe detector determines dropped VT/TU byte starting location. pulse drop A/BDC1J1V1 A/BAC1J1V1 signals ignored. alignment determined internal pulse generated drop byte detector. Drop pulse A/BDC1J1V1 signal determines dropped VT/TU byte starting location, Drop multiframe detector disabled. pulse A/BAC1J1V1 signal ignored. alignment determined pulse A/BAC1J1V1 signal.
Drop timing selected
timing selected
timing selected
timing selected
timing selected
Note: Don't care
Reference Selection
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PERFORMANCE COUNTERS performance counters saturating, with counters stopping their maximum count. counter reset when read microprocessor. performance counters port also reset when written control RnSETC. This self-clearing, does require microprocessor write into location. Counts that occur during read cycle held updated afterwards. 16-bit counter, order byte must read first, followed reading high order byte.
ALARM STRUCTURE alarm indications reported latched (events) unlatched states.The alarm event bits will latch positive, negative, positive negative transitions alarm. selection will also control interrupt indication. event transition controlled selection bits IPOS INEG. control also provided that allows positive level alarm latch event bits (latched positions) alarm register. this mode, alarm active during read cycle, latched alarm position clears, will immediately after completion read cycle. This mode activated writing control LATEN. written into this control will also disable alarm transition (and interrupt) selection bits IPOS INEG.
INTERRUPT STRUCTURE Interrupt indication interrupt mask registers provided, illustrated below. Status bits interrupt indication register indicate status latched alarm event bits registers associated with that status bit, provided corresponding interrupt mask that status bit.The hardware interrupt indication enabled when control HWDIE global software interrupt indication (INT) also provided. hardware interrupt (INT/INT) three-state PAD, with sense option active positive negative. Should they required, additional mask bits provided memory disabling alarms status registers associated with port These additional mask locations must initialized with hex. interrupt works following manner. Assume that hardware interrupt enable control HWDIE alarm mask bits IPOS LATEN bits INEG positive transition alarm causes alarm status (event) alarm register (where port latch. This causes software interrupt indication hardware interrupt occur. microprocessor reads interrupt indication register determine alarm registers read that alarm. microprocessor then reads latched alarm registers that correspond interrupt indication interrupt mask bit. read cycle determines what alarm been set. completion read cycle clears event (latched) alarm register releases hardware software interrupt indication (INT). there more than alarm more than alarm register, each corresponding event (latched) alarm registers must read before interrupt released. addition, hardware software interrupt released writing interrupt mask that corresponds interrupt indication register. second level mask bits also provided, required. alarm remains active during read cycle, latched alarm position will re-latch. unlatched alarm registers should read check alarm persistence. alarm recovered (i.e., state) prior read cycle, during read cycle register that contains alarm, alarm occurs again, will result latched alarm indication.
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Interrupt Registers Interrupt Indication Register (Address 20H) ASIDE BSIDE PORT4 PORT3 PORT2 PORT1
Interrupt Mask Register (Address 21H) ASMSK BSMSK P4MSK P3MSK P2MSK P1MSK
Additional Interrupt Mask Registers (Addresses 17H, 18H, 19H) RPT4A TFIFO4A TPORT4 RPT4B TFIFO4B TPORT3 RPT3A TFIFO3A TPORT2 RPT3B TFIFO3B TPORT1 RPT2A TFIFO2A RFIFO4 RPT2B TFIFO2B RFIFO3 RPT1A TFIFO1A RFIFO2 RPT1B TFIFO1B RFIFO1
Interrupt Indication ASIDE Registers (Addresses 22H, 24H)
Side Drop/Add Alarms (ASIDE) ADLOC AALOC ADPAR A3UAISI A3DH4E A2UAISI A2DH4E A1UAISI A1DH4E
Interrupt Indication BSIDE Registers (Addresses 26H, 28H)
Side Drop/Add Alarms (BSIDE) BDLOC BALOC BDPAR B3UAISI B3DH4E B2UAISI B2DH4E B1UAISI B1DH4E
Interrupt Indication PORTn Registers (Addresses 30H, 3AH, Port
Port Alarms (PORTn) AnAIS BnAIS RnFFE AnLOP BnLOP AnSIZE BnSIZE AnNDF BnNDF TAnFE AnRDI BnRDI TBnFE AnRFI BnRFI TnLOS AnUNEQ BnUNEQ TnLOC AnSLER BnSLER TnDAIS
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Interrupt Alarm Control Summary IPOS INEG HWDIE LATEN Interrupt Mask Action Alarm alarm event indication, interrupt register indication. Alarm event register sets positive levels alarm; software hardware interrupt indications. Alarm event register sets, software interrupt indication occurs, positive levels alarm; hardware interrupt. Alarm event register sets, software hardware interrupt indications occur, positive levels alarm. Alarm event register sets positive transitions alarm; software hardware interrupt indications. Alarm event register sets, software interrupt indication occurs, positive transitions alarm; hardware interrupt. Alarm event register sets, software hardware interrupt indications occur, positive transitions alarm. Alarm event register sets negative transitions alarm; software hardware interrupt indications. Alarm event register sets, software interrupt indication occurs, negative transitions alarm; hardware interrupt. Alarm event register sets, software hardware interrupt indications occur, negative transitions alarm. Alarm event register sets positive and/or negative transitions alarm; software hardware interrupt indications. Alarm event register sets, software interrupt indication occurs, positive and/or negative transitions alarm; hardware interrupt. Alarm event register sets, software hardware interrupt indications occur, positive and/or negative transitions alarm.
Note: Don't Care
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SONET/SDH DETECTION Quad Mapper detect upstream condition using H1/H2 (pointer) bytes (order wire) byte. When control SE1AIS H1/H2 bytes monitored upstream condition. When control bits select VC-4/TUG-3 format, bytes only monitored AIS. monitoring other H1n/H2n bytes disabled. When control bits select STS-3 AU-3 format, each three H1/H2 bytes Drop Drop buses monitored indication. Each three H1/H2 pointer bytes corresponds like-numbered AU-3/STS-1 signal. When control bits select STS-1 format, H1/H2 bytes Drop Drop buses monitored indication. ones detected H1/H2 bytes (whose location determined pulse) three consecutive frames, alarm bits AnUAISI detected H1/H2 byte upstream AIS) BnUAISI detected H1/H2 byte upstream AIS) will set. Recovery occurs when normal (bits through detected three consecutive frames. normal defined 0110 (and also 1110, 0010, 0100, 0111). H1/H2 byte detection circuits (when selected) both Drop buses disabled writing control HEAISE. When control SE1AIS bytes monitored upstream condition. When control bits select VC-4/TUG-3 format, byte both buses monitored AIS. detection upstream indication bytes disabled. When control bits select AU-3/ STS-3 format, each three bytes Drop buses monitored AIS. Each three bytes corresponds like-numbered AU-3/STS-1 signal. STS-1 operation, single byte checked upstream indication. Majority logic used determine byte carrying upstream indication. more ones least bits equal bits) detected once Drop byte (whose locations determined pulse), alarm bits AnUAISI detected H1/H2 Byte AIS) BnUAISI detected H1/H2 Byte AIS) set. Recovery occurs when more zeros least bits equal bits) detected more times. byte detection circuits (when selected) both Drop buses disabled writing control HEAISE.
VT/TU POINTER TRACKING starting location byte determined either pulses A/BC1J1V1 signals multiframe detection circuits. VT/TU pointer assignment bytes shown below. alignment necessary determine starting locations byte other bytes that carrying 1544 kbit/s format. Byte Byte
SS-bits
Increment Decrement Data Flag (enabled 1001 0001/1101/1011/1000, normal disabled 0110 1110/0010/0100/0111) Negative Justification: Inverted D-bits accept majority rule Positive Justification: Inverted I-bits accept majority rule SS-bits Size) 1544 kbit/s, Pointer Bytes Assignment TXC-04251-MB December 1997
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pointer value binary number with range 1544 kbit/s format. pointer offset indicates offset from byte first byte VT1.5 mapping. pointer bytes counted offset calculation. pointer offset arrangement this format shown below. 1544 kbit/s TU-11/VT1.5 79-102 1-24 27-50 53-76 VT/TU Pointer Offset Locations
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Eight independent pointer-tracking state machines used Quad Mapper, each four ports also both buses, bus. pointer tracking algorithm illustrated Figure pointer tracking state machine based pointer tracking machine found latest ETSI requirements, also valid both Bellcore ANSI. When control PTALTE transition from disabled (shown dotted), which required Bellcore recommendations.
AIS_ind (Offset Undefined)
inc_ind (Incr. Offset) any_point new_point (Accept Offset)
NDF_enable (Accept Offset) NDF_enable (Accept Offset)
AIS_ind (Offset Undefined)
new_point (Accept Offset) NDF_enable (Accept Offset) new_point (Accept Offset) any_point NDF_enable (Accept Offset) inv_point (Offset Undefined) dec_ind (Decr. Offset) any_point
NORM
new_point (Accept Offset) AIS_ind (Offset Undefined) new_point (Accept Offset)
new_point (Accept Offset)
AIS_ind NDF_enable (Offset Undefined) (Offset Undefined)
inv_point (Offset Undefined) NDF_enable (Accept Offset) AIS_ind (Offset Undefined)
Figure VT/TU Pointer Tracking State Machine
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POINTER LEAK RATE CALCULATIONS
FIFO Leak Rate (Note
Measure Second, (Note
Calculate FIFO Leak Rate (Note
Start AIS, LOS, RESET FIFO Leak Rate (Note
Subt Oldest Newest (Note
Measure Second (Note
Notes: procedure described Notes through below must performed independently each four ports QT1M device. procedure shown diagram above uses ten-second sliding window with resolution second. initial FIFO Leak Rate Register value memory address 49H, 79H, A9H, D9H) must first (reset value). Measure consecutive one-second samples from Positive Negative Stuff Counters being used. Store difference values, i.e., STUFF COUNT1 STUFF COUNT1, STUFF COUNT2 STUFF COUNT2, through STUFF COUNT10 STUFF COUNT10. There eight pairs stuff counters QT1M; care should taken pair appropriate programmed configuration device. counters located addresses 32H, 62H, (for A-Side) (for B-Side). Calculate leak rate (L.R.) using following equation: L.R. Hex[ 1180 where Then, L.R. L.R. 255, 255. FIFO Leak Rate Register (address 49H, 79H, A9H, D9H) with value between calculated above, then take another one-second sample (e.g., S11). Recalculate value subtracting oldest sample adding newest, calculate leak rate, described Note (e.g., using through S11). Continue repeat steps described Notes until AIS, LOP, received until reset QT1M.
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REMOTE DEFECT INDICATIONS (RDI) Byte Coding Bits byte, conjunction with byte, provide detection scheme which compliant with earlier versions standard also with enhanced TU/VT capability. enhanced version allows user differentiate between server, payload, connectivity defects. equal inverse which allows distinguish enhanced version from version RDI. should noted that when bits either indication also influenced shown table below. When bits either then determined solely This allows detection originating from older equipment that generates byte. following table lists defect indications carried bytes. Definition defect indications. defect indications. Remote Payload Defect Path Label Mismatch Loss Multiframe. defect indications. Remote defect (old equipment). Remote Server Defect Loss Pointer detected Upstream detected H1/H2 Bytes). Remote Connectivity Defect Unequipped Signal Label Remote defect (old equipment).
Assignment Detection Recovery alarms defined table below. number consecutive events detection recovery controlled V5AL10. value five selected when V5AL10 control value selected when V5AL10 control AnRDIC BnRDIC AnRDIP BnRDIP AnRDIS BnRDIS
Action Remote Server Defect Indication, equipment indication (Bit byte). Remote Payload Defect Indication. Remote Connectivity Indication.
Alarm Definition
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Remote Defect Indications Generation sent following unlatched alarm conditions overhead bytes added bus, depending states RnSEL (active selected), TnSEL1 TnSEL0 (bus enabled) control bits. following examples apply port corresponding examples ports through constructed substituting port number digit 1-digit symbols (except DV1SEL). When enable (RDIEN) remote payload defect indication sent for: Drop Error (A1DH4E, B1DH4E), when DV1SEL Mismatch signal label (A1SLER, B1SLER) When enable (RDIEN) remote server defect indication sent for: Loss Pointer (A1LOP, B1LOP) (A1AIS, B1AIS) Drop Upstream H1/H2 byte (AnUAISI, BnUAISI), HEAISE (where represents STS-1 which VT/TU been selected). When enable (RDIEN) remote connectivity defect indication sent for: Unequipped signal label (A1UNEQ, B1UNEQ) UQAE When enable (RDIEN) microprocessor control generation: Microprocessor writes T1RDIS generate remote server defect indication. Microprocessor writes T1RDIP generate remote payload defect indication. Microprocessor writes T1RDIC generate remote connectivity defect indication.
Note: microprocessor send writing above control bits time, including only mode. prevent contention between internal logic full microprocessor control, RDIEN control should written with when microprocessor control intended. three control bits TnRDIS, TnRDIP TnRDIC only activated time, since activation more same time cause decode errors.
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OVERHEAD COMMUNICATIONS ACCESS Microprocessor access provided eight overhead communications bits (O-bits) carried justification control (JC) bytes multiframe format, e.g., 1544 kbit/s VT/TU, shown partially below. bits justification control byte numbered through starting with Other Bytes Byte Byte
Bytes Information Byte Byte Byte Other Bytes O-bit Placement 1544 kbit/s VT/TU receive direction, eight O-bits stored eight 8-bit registers each ports) these registers updated each frame. O-bit nibbles that form byte registers receiving transmitting from same multiframe. Bits through O-bit register correspond bits through (C1C2 OOOO first justification control byte, bits through O-bit register correspond bits through second justification control byte, shown below. Second Justification Control Byte Register First Justification Control Byte
O-bit Assignment Memory
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TUG-3 NULL POINTER INDICATOR STM-1 TUG-3 format, Quad Mapper option generate transmit Null Pointer Indicator (NPI) more TUG-3s, shown below.
TUG-3A TUG-3B TUG-3C
VC-4
Structure Three control bits (NPIA, NPIB NPIC) provided selecting more TUG-3 NPIs. three control bits enabled when MOD1 MOD0 control bits (TUG-3/VC-4 format). consists three bytes, starting with table below shows assignment first bytes.
Assignment third byte (and other bytes column) assigned fixed stuff. Bytes which designated stuff (cross-hatched) will high impedance state.
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LOOPBACK CAPABILITY Quad Mapper provides types loopbacks, facility line (i.e., facility side line side). Facility loopback port enabled when written control FnLBK. internal transmit clock data output signals looped back receive clock data input signals shown Figure remain available output pins. receive clock data signals input disabled. Line loopback port enabled when written control LnLBK. receive clock data output signals (rail) looped back transmit data clock signals (rail), shown Figure receive line rail clock data output signals provided receive interface. transmit clock data signals (rail NRZ) input disabled.
AMI/B8ZS Coder Rail
Facility Loopback Receive Data Clock (NRZ, Rail)
Bypass SONET/SDH Line Loopback Data &Clock Line Facility Loopback Data &Clock Transmit Data Clock (NRZ, Rail)
AMI/B8ZS Decoder Bypass
Rail
XMIT
Line Loopback
Figure Facility Line Loopbacks
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RESETS Quad Mapper several reset options. These include full hardware software device reset, partial software resets, counter software resets. software reset bits self-clearing require written register location after reset applied setting Upon power-up, when RESET (bit hex) written with active placed RESET (pin 155), data port interfaces forced high impedance state until device initialized reinitialized. AAHZE, BAHZE, RnEN control bits must written with zeros order enable line interfaces. addition, AAIND, BAIND, AADD BADD pins forced off. performance counters reset, alarms (except AnLOP, BnLOP) reset. control bits also forced zero, various FIFOs recentered. hardware reset only applied after clocks stable, must present minimum nanoseconds. Writing RnSETS software reset control ports resets performance counters, re-centers FIFO, clears alarms, except AnLOP BnLOP alarms, which will port loss pointer alarms will recover when valid pointer received. control bits will reset. Writing RnSETC counter reset control ports resets performance counters that port. This feature allows performance measurements start same time port. Writing control bits RESTAB RESTBB resets alarms each buses, side side. DATA THROUGHPUT DELAY Receive side (SONET/SDH mapper delay times will from nominal delay clocks, maximum clocks with Leak Desynchronizer FIFOs near saturation point. When using Bypass AMI, there will eleven clock nominal reduction those figures, calculations were payload with assumption B8ZS encoding, which gives maximum delay. Transmit side SONET/SDH) maximum delay approximately clocks with nominal delay around times. delay less than B8ZS decoding.
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QT1M TXC-04251
BOUNDARY SCAN Introduction Boundary Scan Interface block provide five-pin Test Access Port (TAP) that conforms IEEE 1149.1 standard. This standard provides external boundary scan functions read write external pins from board component test. IEEE 1149.1 standard defines requirements boundary scan architecture that been specified IEEE Joint Test Action Group (JTAG). Boundary scan specialized scan architecture that provides observability controllability interface pins device. shown Figure cell boundary scan register assigned each input output observed tested (bidirectional pins have cells). boundary scan capability based Test Access Port (TAP) controller, instruction bypass registers, boundary scan register bordering input output pins. boundary scan test interface consists four input signals (Test Clock (TCK), Test Mode Select (TMS), Test Data Input (TDI) Test Reset (TRS)) Test Data Output (TDO) output signal. Boundary scan signal timing shown Figure TDI, pins have internal pull-up resistors. pull-up implemented with active device which disabled certain test situations putting TEST input (pin 145). normal state (i.e., power-up) device active, inputs held high absence external stimulus. tri-state output, normal state high impedance state. driven only during Shift_DR Shift_IR states controller state machine. controller receives external control information Test Clock (TCK) signal Test Mode Select (TMS) signal, sends control signals internal scan paths. Detailed information operation this state machine found IEEE 1149.1 standard. serial scan path architecture consists instruction register, boundary scan register bypass register. These three serial registers connected parallel between Test Data Input (TDI) Test Data Output (TDO) signals, shown Figure boundary scan function reset disabled holding low. When boundary scan testing being performed boundary scan register transparent, allowing input output signals pass from QT1M device's internal logic. During boundary scan testing, boundary scan register disable normal flow input output signals allow device controlled observed scan operations. Boundary Scan Operation1 maximum frequency QT1M device will support boundary scan MHz. timing diagrams boundary scan interface pins shown Figure QT1M device performs following four boundary scan test instructions: EXTEST test instruction (000) provides ability test connectivity QT1M device external circuitry. SAMPLE test instruction (010) provides ability examine boundary scan register contents without interfering with device operation. IDCODE test instruction (101) allows loading internal device Identification Register, shifting contents through Boundary Scan Register without interfering with normal device operation. contents Register 0109B0D7 (hex). BYPASS test instruction (111) provides ability bypass QT1M boundary scan instruction registers. During Capture_IR state controller state machine, loaded into 3-bit instruction register.
BSDL file this device contains further information regarding operation This file available upon request from Applications Engineering department TranSwitch.
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QT1M TXC-04251
Figure Boundary Scan Schematic
Boundary Scan Register
CORE LOGIC QT1M DEVICE
Signal input output pins
Instruction Register Bypass Register Controller
Controls Boundary Scan Serial Test Data
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Boundary Scan Chain There scan cells QT1M boundary scan chain. Bidirectional signals require scan cells. Additional scan cells used direction control needed. following table shows listed order scan cells their function. notes numbered through appear table. Scan Cell Direction Input Input Input Input Input Input 2-State 2-State Input Input Input Input 3-State Control
Name ADSPE ADC1J1V1 AASPE AAC1J1V1 AACLK ADCLK ADIND AAIND TPI1 TNI1/TLOS1 TCI1 QUIET1 RPO1 rn1_enb RNO1 rcp1_enb RCO1 RPO3 rn3_enb RNO3 rcp3_enb RCO3 TPI3 TNI3/TLOS3 TCI3 QUIET3 Reserved N.C. Reserved Reserved
Comments Drop Indicator Drop C1J1V1 Indicator Indicator C1J1V1 Indicator Clock Drop Clock Drop Slot Indicator Slot Indicator Port Positive Rail Port Neg. Rail In/LOS Port Transmit Clock Quiet Port Port Positive Rail Output Enable Port Negative Rail Output Enable Port Receive Clock Port Positive Rail Output Enable Port Negative Rail Output Enable Port Receive Clock Port Positive Rail Port Neg. Rail In/LOS Port Transmit Clock Quiet Port Unused: Observe-only Cell Unused: Observe-only Cell Unused: Observe-only Cell Unused: Observe-only Cell
3-State Control 3-State 3-State Control 3-State Control 3-State Input Input Input Input
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Scan Cell Direction -Input -Input -3-State Control Input Input Input Input Input Input -Input Input -Input 3-State Input Control
-150 -132 -129
Name Reserved Reserved ABUST Reserved RESET Reserved INT/INT hwint_enb INTSH TEST Reserved Reserved Reserved Reserved EXTCK HIGHZ Reserved UPAD7 UPAD7 UPAD6 Cado67_enb UPAD6 UPAD5 UPAD5 UPAD4 Cado45_enb UPAD4 UPAD3 UPAD3 UPAD2
Comments Unused: Observe-only Cell Unused: Observe-only Cell Timing Select Unused: Observe-only Cell Low-Active Device Reset Unused: Observe-only Cell Interrupt Out-Polarity Selectable Output Enable Interrupt Sense High Interface Add. Lat. Interface Write Line Interface Read Line Interface Select Line
Unused: Observe-only Cell Unused: Observe-only Cell Unused: Observe-only Cell Unused: Observe-only Cell External 48.6360 Clock Observe Control Unused: Observe-only Cell Address/Data Address/Data Address/Data Output Enable 132, Address/Data Address/Data Address/Data Address/Data Output Enable 129, Address/Data Address/Data Address/Data Address/Data
3-State Input 3-State Input Control 3-State Input 3-State Input
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Scan Cell Direction Control 3-State Input 3-State Input Control 3-State -Input Input Input Input 3-State 3-State Control Control 3-State 3-State 3-State Control Control 3-State Input Input Input Input 2-State 2-State Input Input Input Input Input -126 -124 -112 -109 Name Cado23_enb UPAD2 UPAD1 UPAD1 UPAD0 Cado01_enb UPAD0 Reserved N.C. QUIET4 TCI4 TNI4/TLOS4 TPI4 RCO4 RNO4 rn4_enb rcp4_enb RPO4 RCO2 RNO2 rn2_enb rcp2_enb RPO2 QUIET2 TCI2 TNI2/TLOS2 TPI2 BAIND BDIND BDCLK BACLK BAC1J1V1 BASPE BDC1J1V1 Comments Output Enable 126, Address/Data Address/Data Address/Data Address/Data Output Enable 124, Address/Data Unused: Observe-only Cell Unused: Observe-only Cell Quiet Port Port Transmit Clock Port Neg. Rail In/LOS Port Positive Rail Port Receive Clock Port Negative Rail Output Enable Output Enable 112, Port Positive Rail Port Receive Clock Port Negative Rail Output Enable Output Enable 109, Port Position Rail Quiet Port Port Transmit Clock Port Neg. Rail In/LOS Port Positive Rail Slot Indicator Drop Slot Indicator Drop Clock Clock C1J1V1 Indicator Indicator Drop C1J1V1 Indicator
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Scan Cell Direction Input Input Input Input Input Input Input Input Input Input 2-State 3-State 3-State Control 3-State 3-State 3-State Control 3-State 3-State 3-State Control 3-State 3-State 3-State Control 3-State 3-State 3-State Control 3-State 3-State 3-State 3-State Name BDSPE BDPAR BADD BAPAR Ba6p_enb Ba35_enb Ba02_enb Aa02_enb Aa35_enb AAPAR Comments Drop Indicator Drop Parity Drop Data Drop Data Drop Data Drop Data Drop Data Drop Data Drop Data Drop Data Data Present Parity Data Output Enable Data Data Data Output Enable Data Data Data Output Enable Data Data Data Output Enable Data Data Data Output Enable Data Data Data Parity
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Scan Cell
Notes: Input Pins have Observe-Only Boundary Scan Cells unless otherwise noted. 3-State Outputs indicate signals which can, normal circuit functioning, Active (High/Low), Inactive (Low/High), High Impedance State. This varies from 2-State Outputs, which although they Tri-Statable Output Buffers, always either High only regardless their Active polarity. These outputs High Impedance State only applying logic level HIGHZ input signal which puts Output Pins such state. Where Cells have "Control" Direction column, signifies that this cell observation control Output Enable 3-State Output Bidirectional Pin. Comments column will list number(s) signal(s) that controls. output enables active when (`0'), Bidirectional controls drive when (`0'). HIGHZ Signal special case Input that only function disable output pins device testing purposes. This input Observe Control Cell which allows Preloaded SAMPLE/PRELOAD command with High Logic ("1"). This value, which loaded into Registered Parallel Output Cell during Update state, applied signal during EXTEST, much same that Controls (Enables) Bidirectional Signals 3-State Outputs handled. Bidirectional Pins have cells, Observe-Only Cell Input Observe Control Cell Output. addition there will Control Observe Cell direction control pin, although most cases these serve more pins.
Direction Control Output Input Input Input Input Input Input Input Input Input
Name Aa6p_enb AADD ADPAR
Comments Output Enable Data Present Drop Data Drop Data Drop Data Drop Data Drop Data Drop Data Drop Data Drop Data Drop Parity
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MULTIPLEX FORMAT MAPPING INFORMATION STS-1 VT1.5 (1.544 Mbit/s) Multiplex Format following diagram table illustrate mapping VT1.5s into STS-1 SPE. Column assigned carry path overhead bytes.
VT1.5
COLUMNS
STS-1
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STS-1 Mapping (Port (Port (Port (Port Registers Selected
VT1.5 Column Numbers*
Note: Columns carry fixed stuff bytes. Column assigned bytes.
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STS-3/AU-3 VT1.5/TU-11 (1.544 Mbit/s) Multiplex Format Mapping following diagram table illustrate mapping VT1.5/TU-11s into STS-3/AU-3 SPE. Each STS-3 carries three STS-1s. Column each STS-1/AU-3 assigned carry path overhead bytes.
VT1.5
COLUMNS
STS-1
STS-3/AU-3
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STS-3 AU-3 Mapping (Port (Port (Port (Port Registers (Port (Port (Port (Port Registers (Port (Port (Port (Port Registers
VT/TU Column Numbers
VT/TU Column Numbers
VT/TU Column Numbers*
Selected
STS-1 AU-3 STS-1 AU-3 STS-1 AU-3
Note: Columns 175, 176, fixed stuff.
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TU-11 VC-4 Multiplex Format Mapping following diagram table illustrate mapping TU-11s into VC-4. QT1M provides control bits enabling Null Pointer Indicators (NPIs) columns indicated.
COLUMNS
TU-11
TUG-2
TUG-3
VC-4
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TU-11 VC-4 Multiplex Format Mapping (Port (Port (Port (Port Registers (Port (Port (Port (Port Registers (Port (Port (Port (Port Registers
VC-4 Column Numbers
VC-4 Column Numbers
VC-4 Column Numbers
Selected
TUG-3 TUG-3 TUG-3
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QT1M TXC-04251 MEMORY
QT1M memory consists counters register positions which accessed microprocessor. memory segment consists address locations. Addresses that unused unlisted register locations must accessed microprocessor. Unused positions within register locations will contain unspecified values when read, unless value indicated tables below, address been written microprocessor, which case unused positions must always counters saturate full count cleared when they read. Reserved registers state ensure proper operation when device given power-up reset. memory following address structure: Device Reserved Common Registers Port Port Port Port Reserved 00H-04H 05H-0FH 10H-21H 22H-25H 26H-29H 30H-5FH 60H-8FH 90H-BFH C0H-EFH F0H-FFH
common memory segment consists Control, Provisioning, Interrupt Indication, Interrupt Status registers. segment consists Drop status registers. segment consists Drop status registers. Each Port memory segment (e.g., Port consists Desynchronizer, Provisioning, Status, Operations registers. DEVICE Address (Hex) Status
Revision (Version) Level Mask Level (0000)
Growth (0000)
Note: Status codes R=Read Only; R(L)=Read Only (Latched); R/W=Read/Write; W=Write Only.
Address 00H, fixed value. 11-bit field from address 01H, (MSB) address 00H, (LSB) contains binary equivalent manufacturer assigned TranSwitch, which (decimal). 16-bit field from address 03H, (MSB) address 01H, (LSB) contains binary equivalent manufacturer's numeric code assigned QT1M device (04251 decimal).
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COMMON REGISTERS CONTROLS Address Status* (Hex) MOD1 SBTEN ADDI HEAISE MOD0 DRPBT DV1SEL AAHZE IPOS DV1REF BAHZE LATEN INEG RDIEN BLOCK TAISE DISRFI Unused NPIA TCLKI Unused DDIND NPIB RAISE UQAE NPIC RCLKI PDDO TOBWZ
COMMON REGISTERS PROVISIONING Address Status* (Hex) RESET Unused RESTAB RESTBB UEAME SE1AIS V5AL10 Unused PTALTE HDWIE
COMMON REGISTERS INTERRUPT INDICATION Address Status* (Hex) ASIDE BSIDE PORT4 PORT3 PORT2 PORT1
COMMON REGISTERS INTERRUPT STATUS Address Status* (Hex) RPT4A TPORT4 RPT4B RPT3A RPT3B RPT2A RFIFO4 P4MSK RPT2B RFIFO3 P3MSK RPT1A RFIFO2 P2MSK RPT1B RFIFO1 P1MSK
TFIFO4A TFIFO4B TFIFO3A TFIFO3B TFIFO2A TFIFO2B TFIFO1A TFIFO1B TPORT3 TPORT2 TPORT1 ASMSK BSMSK
DROP REGISTERS STATUS Address Status* (Hex) R(L) R(L) R(L) R(L) ADLOC ADLOC BDLOC BDLOC AALOC AALOC BALOC BALOC ADPAR ADPAR BDPAR BDPAR A3UAISI A3UAISI A3DH4E A3DH4E B3UAISI B3UAISI B3DH4E B3DH4E A2UAISI A2UAISI A2DH4E A2DH4E B2UAISI B2UAISI B2DH4E B2DH4E A1UAISI A1UAISI A1DH4E A1DH4E B1UAISI B1UAISI B1DH4E B1DH4E
Note: Status codes R=Read Only; R(L)=Read Only (Latched); R/W=Read/Write; W=Write Only.
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DESYNCHRONIZER CONTROL PORT Address Status* Port
Desynchronizer Pointer Leak Rate Register Port
PROVISIONING PORT Address Status* Port TnSEL1 ADnEN Unused TnSEL0 BDnEN RnSEL AAnEN RnEN TnB8ZS
UCHnE USCHnE BYPASn BAnEN VT/TU Select (VTNn) Unused
Unused
STATUS REGISTERS PORT SIDE) Address Status* Port R(L) R(L) AnRDIP AnRDIP AnRDIC AnRDIC Unused Unused Unused Receive Byte Receive Byte Receive Byte Receive O-Bits AnAIS AnAIS AnLOP AnLOP AnSIZE AnSIZE AnNDF AnNDF AnRDIS AnRDIS AnRFI AnRFI
AnUNEQ AnSLER AnUNEQ AnSLER
AnPJ Counter AnBIP2 Error Counter AnFEBE Error Counter
AnNJ Counter
Label
STATUS REGISTERS PORT SIDE) Address Status* Port R(L) Unused BnAIS BnAIS BnLOP BnLOP BnSIZE BnSIZE BnNDF BnNDF BnRDIS BnRDIS BnRFI BnRFI
BnUNEQ BnSLER BnUNEQ BnSLER
BnPJ Counter BnBIP2 Error Counter BnFEBE Error Counter
BnNJ Counter
Label
Note: Status codes R=Read Only; R(L)=Read Only (Latched); R/W=Read/Write; W=Write Only.
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Address Status* Port R(L)
BnRDIP BnRDIP
BnRDIC BnRDIC
Unused Unused Receive Byte Receive Byte Receive Byte Receive O-Bits
STATUS REGISTERS PORT SIDES) Address Status* Port R(L) RnFFE RnFFE TAnFE TAnFE TBnFE TBnFE TnLOS TnLOS TnLOC TnLOC TnDAIS TnDAIS
Transmit Port Coding Violation Counter (Low Byte) Transmit Port Coding Violation Counter (High Byte)
OPERATIONS REGISTERS PORT Address Status* Port RnSETS RnSETC Unused Unused Unused Transmit Byte Value Port Transmit Byte Value Port Transmit Byte Value Port Transmit O-Bits Port FnLBK LnLBK RnAIS TnAIS Unused Unused TnFB2 TnVTAIS TnRFI TnRDIS TnRDIP TnRDIC TnFFB Signal Label Signal Label Signal Label
Note: Status codes R=Read Only; R(L)=Read Only (Latched); R/W=Read/Write; W=Write Only.
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QT1M TXC-04251 MEMORY DESCRIPTIONS
COMMON CONTROL PROVISIONING DESCRIPTIONS Address Symbol MOD1 MOD0 Description Format Selection: format selection made according table given below. MOD1 AAHZE MOD0 Format (and rate) Selected STS-1 Format STS-3 Format STM-1 AU-3 Format STM-1 TUG-3/VC-4 Format
High Impedance Enable: forces A-side data output high impedance state. Upon power-up, hardware software reset, this Note: normal operation this position must written with High Impedance Enable: forces B-side data output high impedance state. Upon power-up, hardware software reset, this Note: normal operation this position must written with Block Count: enables BIP-2 errors counted single error (block) BIP-2 performance counters bytes). enables BIP-2 errors counted errors. Null Pointer Indicator Selection: enables null pointer indicator generated more TUG-3s when control MOD1 MOD0 (STM-1 format). null pointer indicator carried first bytes column TUG-3. null pointer indicator defined 1001 bits through bits equal five ones bits through followed five zeros bits through Software Timing Enable: This works conjunction with control DRPBT ABUST according following table (where Don't Care): SBTEN DRPBT ABUST Action timing selected. data derived from timing signals. Software control timing disabled. Drop timing selected. data derived from like-named drop bus. Software control timing disabled. timing selected. data derived from timing signals. Hardware control timing disabled. Drop timing selected. data derived from like-named drop bus. Hardware control timing disabled.
BAHZE
BLOCK
NPIA NPIB NPIC
SBTEN
High
This reset upon power-up device reset.
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Address (cont.) Symbol DRPBT Description Drop Timing: Enabled when written control SBTEN. selects drop timing mode, while selects timing mode. table above. Delay: delays data with respect drop clock cycle, when drop timing selected. delays data with respect drop additional clock cycle, total clock cycles. Latch Alarm Transitions Enable Bit: enables IPOS INEG control bits Address 12H, Bits disables states IPOS INEG control bits, causes event alarm bits (latched alarm bits registers) latch positive level alarm. Transmit Line Enable: common control four ports. enables (unframed ones) generated sent when line input loss signal, loss clock, occurs port Transmit Line Clock Inversion: common control four ports. enables transmit data clocked negative clock edges. enables data clocked positive clock edges. Receive Line Enable: common control four ports. enables receive sent when internal defined alarms occur port unframed ones signal. example, receive port 1will generated: When R1SEL RAISE (drop from side) Loss pointer detected (A1LOP) detected (A1AIS) Drop Loss Clock (ADLOC) Drop Upstream detected (AnUAISI) when HEAISE Drop Error (AnDH4E) when DV1SEL Unequipped signal label (A1UNEQ) UQAE Mismatch signal label (A1SLER) When R1SEL RAISE (drop from side) Loss pointer detected (B1LOP) detected (B1AIS) Drop Loss Clock (BDLOC) Drop Upstream detected (BnUAISI) HEAISE Drop Error (BnDH4E) when DV1SEL Unequipped signal label (B1UNEQ) UQAE Mismatch signal label (B1SLER) Receive FIFO Error (R1FFE) RAISE written send receive (R1AIS) will sent multiframe when receive FIFO error occurs. AnUAISI, BnUAISI, AnDH4E BnDH4E represents STS-1 which VT/TU been selected. RCLKI Receive Line Clock Inversion: common control four ports. enables receive data signal clocked positive clock edges. causes data clocked negative clock edges.
LATEN
TAISE
TCLKI
RAISE
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Address Symbol ADDI Description Indicator Inversion: causes output indicator signals (AADD BADD) active high instead active when time slot added bus. Even Parity Generated: enables even parity generated, while enables parity generated. Parity calculated over data byte only. Interrupt/Event Positive/Negative Alarm Transition Selection: event register will latch, software interrupt indication will occur, according transitions given table below. appropriate interrupt mask must set. hardware interrupt occurs when hardware interrupt also enabled (control HDWIE These bits disabled when written control LATEN. IPOS DISRFI INEG Action event interrupt indication Event interrupt positive alarm transition Event interrupt negative alarm transition Event interrupt positive negative alarm transitions
IPOS INEG
Disable Interrupt: common control four ports. disables indication (bit VT/TU) from causing interrupt. enables indication cause interrupt. Unused: This must written Drop Even Parity Detected: This works conjunction with PDDO control determine parity calculation drop direction. PDDO Action parity check over drop data, SPE, C1J1V1 both buses. parity check over drop data only. Even parity check over drop data, SPE, C1J1V1 both buses. Even parity check over drop data only.
Unused
Other than reporting event, action taken upon parity error indication. PDDO Drop Parity Detected Data Only: Common control both buses. causes parity calculated over data byte only both Drop buses. causes parity calculated over data byte, C1J1V1 signals both buses. H1/H2 Byte Enable: Common control both Drop buses. enables detected either SONET/SDH H1/H2 bytes, bytes generate receive line transmit (when enabled).
HEAISE
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Address (cont.) Symbol DV1SEL Description Drop Select: Common control both buses. selects byte used multiframe indicator. selects pulses present Drop C1J1V1 signals used multiframe alignment.
DV1REF Drop Reference Enable: Common control both buses. Enabled when timing selected. enables pulse from either drop C1J1V1 signal from multiframe detector used reference pulse. pulse AAC1J1V1 BAC1J1V1 signals ignored. RDIEN Transmit Remote Defect Indication Enable: Common control both buses. remote payload, server connectivity defect indication generated under conditions described below. These examples apply port corresponding examples ports through constructed substituting port number digit 1-digit symbols (except DV1SEL). When enable (RDIEN) remote payload defect indication sent for: Drop Error (A1DH4E, B1DH4E), when DV1SEL Mismatch signal label (A1SLER, B1SLER) When enable (RDIEN) remote server defect indication sent for: Loss Pointer (A1LOP B1LOP) (A1AIS, B1AIS) Drop Upstream H1/H2 byte (AnUAISI, BnUAISI), HEAISE (where represents STS-1 which VT/TU been selected). When enable (RDIEN) remote connectivity defect indication sent for: Unequipped signal label (A1UNEQ, B1UNEQ) UQAE When enable (RDIEN) microprocessor control generation: Microprocessor writes T1RDIS generate remote server defect indication. Microprocessor writes T1RDIP generate remote payload defect indication. Microprocessor writes T1RDIC generate remote connectivity defect indication.
Note: microprocessor send writing above control bits time, including only mode. prevent contention between internal logic full microprocessor control, RDIEN control should written with when microprocessor control intended.
Unused DDIND
Unused: This must written Delay Drop Indication Signal: increases delay drop indication signals (ADIND BDIND) additional clock cycle.
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Address (cont.) Symbol UQAE Description Unequipped Alarm Enable: common control both Drop buses. enables receive line transmitted when unequipped alarm detected either Drop signals. Transmit Overhead Bytes With Zeros: enables bytes written into memory microprocessor transmitted overhead communications channel bytes four ports. forces overhead communications channel bytes, unused bits (bits byte, transmitted zeros four ports.
TOBWZ
COMMON REGISTERS PROVISIONING DESCRIPTIONS Address Symbol Unused UEAME Description Unused: These bits must written Unequipped Modes Enable: enables unequipped channel unequipped supervisory channel generated multiplex mode only, according table given below: Drop Action Unequipped unequipped supervisory channel transmitted VT/TU selected Bus. Unequipped unequipped supervisory channel transmitted VT/TU selected Bus.
enables unequipped channel unequipped supervisory channel transmitted only active VT/TU selected. control bits UCHnE USCHnE below (Addresses associated control functions. SE1AIS Select E1AIS: disables H1/H2n detection circuit enables detection circuit bytes. enables detection circuit H1/H2n bytes. represents STS-1 signal being carried Alarm Detection Select selects consecutive assertions detection recovery. selects consecutive assertions detection recovery. Pointer Tracking Transition Enabled: enables transition pointer tracking state machine, required ETSI standards. will disable transition Bellcore ANSI standards. Hardware Interrupt Enable: enables interrupt activated when interrupt occurs, provided corresponding mask set.
V5AL10
PTALTE
HDWIE
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Address Symbol RESET Description Reset: clears controls (except high impedance bits), alarms, internal counters, performance counters, re-centers receive transmit FIFOs. This self-clearing, will reset after reset cycle completed.
RESTAB Reset Side Alarms: clears alarms associated with side bus. This self-clearing, will reset after reset cycle completed. RESTBB Reset Side Alarms: clears alarms associated with side bus. This self-clearing, will reset after reset cycle completed. Unused Unused: These bits must written
COMMON REGISTERS INTERRUPT INDICATION REGISTER DESCRIPTIONS Address Symbol Description Software Interrupt Indication: indicates that positive, negative, positive negative alarm transition occurred. corresponding interrupt mask must this indication occur. Unused: This reads Side Interrupt Indication: Enabled when written into AMSK bit. indicates that alarm occurred A-side alarm registers. Side Interrupt Indication: Enabled when written into BMSK bit. indicates that alarm occurred B-side alarm registers. Port Interrupt Indication: Enabled when written into P4MSK bit. indicates that alarm occurred port alarm registers. Port Interrupt Indication: Enabled when written into P3MSK bit. indicates that alarm occurred port alarm registers. Port Interrupt Indication: Enabled when written into P2MSK bit. indicates that alarm occurred port alarm registers. Port Interrupt Indication: Enabled when written into P1MSK bit. indicates that alarm occurred port alarm registers.
Unused ASIDE
BSIDE
PORT4
PORT3
PORT2
PORT1
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COMMON REGISTERS OPERATIONS DESCRIPTIONS Address Symbol RPTnA (n=4-1) Description Receive Side Status Interrupt Mask Bit: enables hardware interrupt software interrupt indication (INT) when alarm occurred A-side alarm register (mask bits registers when PnMSK port disables side receive alarms port from causing interrupt. Receive Side Status Interrupt Mask Bit: enables hardware interrupt software interrupt indication (INT) when alarm occurred B-side alarm register (mask bits registers when PnMSK port disables side receive alarms port from causing interrupt.
RPTnB (n=4-1)
TFIFOnA Transmit FIFO Error Side Status Interrupt Mask Bit: enables (n=4-1) hardware interrupt software interrupt indication (INT) when alarm occurred A-side transmit FIFO (mask bits registers when PnMSK port disables transmit FIFO error side alarm port from causing interrupt. TFIFOnB Transmit FIFO Error Side Status Interrupt Mask Bit: enables (n=4-1) hardware interrupt software interrupt indication (INT) when alarm occurred B-side transmit FIFO (mask bits registers when PnMSK port disables transmit FIFO error side alarm port from causing interrupt. TPORTn Transmit Status Interrupt Mask Bit: enables hardware interrupt (n=4-1) software interrupt indication (INT) when alarm occurred transmit alarms (mask bits TnLOS (bit TnLOC (bit TnDAIS (bit registers when PnMSK port disables transmit alarm from causing interrupt. RFIFOn (n=4-1) Receive FIFO Error Status Interrupt Mask Bit: enables hardware interrupt software interrupt indication (INT) when alarm occurred receive FIFO (mask bits registers when PnMSK port disables receive FIFO error alarm port from causing interrupt.
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Address Symbol Unused ASMSK BSMSK P4MSK Description Unused: These bits must written Side Interrupt Mask Bit: enables Side Interrupt Indication (ASIDE). Side Interrupt Mask Bit: enables Side Interrupt Indication (BSIDE). Port Interrupt Mask Bit: enables Port Interrupt Indication (PORT4). permits hardware interrupt software interrupt indication (INT) when alarm occurred alarm registers port when corresponding RPT4A, RPT4B, TFIFO4A, TFIFO4B, RFIFO4 TPORT4 mask set. Port Interrupt Mask Bit: enables Port Interrupt Indication (PORT3). permits hardware interrupt software interrupt indication (INT) when alarm occurred alarm registers port when corresponding RPT3A, RPT3B, TFIFO3A, TFIFO3B, RFIFO3 TPORT3 mask set. Port Interrupt Mask Bit: enables Port Interrupt Indication (PORT2). permits hardware interrupt software interrupt indication (INT) when alarm occurred alarm registers port when corresponding RPT2A, RPT2B, TFIFO2A, TFIFO2B, RFIFO2 TPORT2 mask set. Port Interrupt Mask Bit: enables Port Interrupt Indication (PORT1). permits hardware interrupt software interrupt indication (INT) when alarm occurred alarm registers port when corresponding RPT1A, RPT1B, TFIFO1A, TFIFO1B, RFIFO1 TPORT1 mask set.
P3MSK
P2MSK
P1MSK
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DROP STATUS REGISTER DESCRIPTIONS Address ADLOC Symbol Description Same definitions register hex, except bits latched. Drop Loss Clock: indicates that Drop detected loss clock. alarm occurs when input drop clock stuck high equivalent 1000 Recovery occurs first clock transition. Loss Clock: indicates that detected loss clock, when timing selected. loss clock alarm forces data parity high impedance state, indicator duration alarm. alarm occurs when input clock stuck high more clock cycles. Recovery occurs first clock transition. Drop Parity Error Detected: indicates that even parity error been detected Drop signals. Other than alarm indication, action taken. Parity monitored each drop clock cycle. Unused: These bits read side Received Upstream Indication AU-3 C/STS-1 When control SE1AIS indicates that been detected bytes AU-3 C/STS-1 When control SE1AIS indicates that been detected byte AU-3 C/STS-1 Disabled when format AU-4 VC-4, STS-1. side Received Upstream Indication AU-3 B/STS-1 When control SE1AIS indicates that been detected bytes AU-3 B/STS-1 When control SE1AIS indicates that been detected byte AU-3 B/STS-1 Disabled when format AU-4 VC-4, STS-1. side Received Upstream Indication AU-3 A/STS-1 AU-4 VC-4, STS-1: When control SE1AIS indicates that been detected H1/H2 bytes AU-3 A/STS-1 AU-4 VC-4 signal. When control SE1AIS indicates that been detected byte AU-3 A/STS-1 AU-4 VC-4, STS-1 signal. Same definitions register hex, except bits latched. Unused Unused: These bits read A3DH4E Drop Loss Indication AU-3 C/STS-1 Loss multiframe AUG-3 C/STS-1 No.3 declared more values differ from those two-bit counter once multiframe consecutive multiframes, when control DV1SEL received multiframe sequence multiframe detector will continue operate free running mode, will lock sequence after multiframe sequence been received correctly. This detector disabled when format AU-4 VC-4, STS-1. This forced power-up.
AALOC
ADPAR
Unused A3UAISI
A2UAISI
A1UAISI
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Address (cont.) Symbol Description
A2DH4E Drop Loss Indication AU-3 B/STS-1 Loss multiframe AUG-3 B/STS-1 declared more values differ from those two-bit counter once multiframe consecutive multiframes, when control DV1SEL received multiframe sequence multiframe detector will continue operate free running mode, will lock sequence after multiframe sequence been received correctly. This detector disabled when format AU-4 VC-4, STS-1. This forced power-up. A1DH4E Drop Loss Indication AU-3 A/STS-1 AU-4 VC-4, STS-1: Loss multiframe AUG-3 A/STS-1 AU-4 VC-4 declared more values differ from those two-bit counter once multiframe consecutive multiframes, when control DV1SEL received multiframe sequence multiframe detector will continue operate free running mode, will lock sequence after multiframe sequence been received correctly. This forced power-up. Same definitions register hex, except bits latched. BDLOC Drop Loss Clock: indicates that Drop detected loss clock. alarm occurs when input drop clock stuck high equivalent 1000 Recovery occurs first clock transition. Loss Clock: indicates that detected loss clock, when timing selected. loss clock alarm forces data parity high impedance state, indicator duration alarm. alarm occurs when input drop clock stuck high more clock cycles. Recovery occurs first clock transition. Drop Parity Error Detected: indicates that even parity error been detected Drop signals. Other than alarm indication, action taken. Parity monitored each drop clock cycle. Unused: These bits read side Received Upstream Indication AU-3 C/STS-1 When control SE1AIS indicates that been detected bytes AU-3 C/STS-1 When control SE1AIS indicates that been detected byte AU-3 C/STS-1 Disabled when format AU-4 VC-4, STS-1. side Received Upstream Indication AU-3 B/STS-1 When control SE1AIS indicates that been detected bytes AU-3 B/STS-1 When control SE1AIS indicates that been detected byte AU-3 B/STS-1 Disabled when format AU-4 VC-4, STS-1
BALOC
BDPAR
Unused B3UAISI
B2UAISI
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Address (cont.) Symbol B1UAISI Description side Received Upstream Indication AU-3 A/STS-1 AU-4 VC-4, STS-1: When control SE1AIS indicates that been detected H1/H2 bytes AU-3 A/STS-1 AU-4 VC-4 signal. When control SE1AIS indicates that been detected byte AU-3 A/STS-1 AU-4 VC-4, STS-1 signal. Same definitions register hex, except bits latched. Unused Unused: These bits read B3DH4E Drop Loss Indication AU-3 C/STS-1 Loss multiframe AUG-3 C/STS-1 No.3 declared more values differ from those two-bit counter once multiframe consecutive multiframes, when control DV1SEL received multiframe sequence multiframe detector will continue operate free running mode, will lock sequence after multiframe sequence been received correctly. This detector disabled when format AU-4 VC-4, STS-1. This forced power-up. B2DH4E Drop Loss Indication AU-3 B/STS-1 Loss multiframe AUG-3 B/STS-1 No.2 declared more values differ from those two-bit counter once multiframe consecutive multiframes, when control DV1SEL received multiframe sequence multiframe detector will continue operate free running mode, will lock sequence after multiframe sequence been received correctly. This detector disabled when format AU-4 VC-4, STS-1. This forced power-up. B1DH4E Drop Loss Indication AU-3 A/STS-1 AU-4 VC-4, STS-1: Loss multiframe AUG-3 A/STS-1 No.1 AU-4 VC-4 declared more values differ from those two-bit counter once multiframe consecutive multiframes, when control DV1SEL multiframe detector will continue operate free running mode, will lock sequence after multiframe sequence been received correctly. This forced power-up.
PORT DESYNCHRONIZER CONTROL REGISTER DESCRIPTIONS Address Port Port Port Port Symbol Pointer Leak Rate Value Description Desynchronizer Pointer Leak Rate Register Port count written into this location used internal leak rate buffer, represents average leak rate. count represents frames, multiframes, rate occurrence pointer movements from number counts read from positive negative stuff counters.
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PORT PROVISIONING REGISTER DESCRIPTIONS Address Port Port Port Port Symbol TnSEL1 TnSEL0 RnSEL Description Transmit Port Drop/Add Selection: table below lists selection criteria eight available modes operation port TnSEL1 TnSEL0 UCHnE RnSEL Operating Mode Drop only Drop only Drop Drop Drop Drop Drop Drop
Unequipped Channel Port Enabled: UCHnE control works conjunction with USCHnE control position according following table: UCHnE USCHnE Action Normal Operation. Unequipped VT/TU generated. unequipped VT/TU consists normal NDF, size bits equal fixed pointer equal other bytes equal Unequipped supervisory VT/TU generated. unequipped supervisory VT/TU consists normal NDF, size bits equal fixed pointer equal valid byte. byte will consist valid BIP-2, with zeros signal label other bits. bytes, other bytes, will equal 00H.
Note: don't care USCHnE Unequipped Supervisory Channel Port Enabled: Works conjunction with UCHnE according table given above. BYPASn Bypass CODEC Port disables AMI/B8ZS CODEC (coder decoder) port operation. This also works conjunction with TnB8ZS control bit, according following table: BYPASn TnB8ZS Action CODEC function enabled. Rail interface selected receive transmit ports. B8ZS CODEC function enabled. Rail interface selected receive transmit ports. AMI/B8ZS CODEC function disabled. interface selected receive transmit ports.
Note: don't care
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Address Port Port Port Port (cont.) Symbol RnEN Description Receive Port Enable: enables receive data (NRZ rail) output clock output port when QUIETn low. forces data clock output pins high impedance state. four bits power reset must written these control bits enable port outputs. Port B8ZS CODEC Enable: enables B8ZS CODEC function port enables CODEC function port Also refer table given BYPASn. Side Drop Port VT/TU Selection Output Enable: enables drop ADIND signal output. This signal will active time slots corresponding VT/TU selected port Side Drop Port VT/TU Selection Output Enable: enables drop BDIND signal output. This signal will active time slots corresponding VT/TU selected port Side Port VT/TU Selection Output Enable: enables AAIND signal output. This signal will active time slots corresponding VT/TU selected port Side Port VT/TU Selection Output Enable: enables BAIND signal output. This signal will active time slots corresponding VT/TU selected port Unused: These bits must written Unused: This must written VT/TU Selection Port seven-bit code binary code written into this location selects that dropped from B-side drop bus, added B-side bus. VT/TU selected, microprocessor should either write control RnAIS thereby forcing AIS, should write RnEN, which will tristate port data clock output pins.
TnB8ZS
Port Port Port Port
ADnEN
BDnEN
AAnEN
BAnEN
Port Port Port Port
Unused Unused VTNn
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PORT RECEIVE STATUS REGISTER DESCRIPTIONS following descriptions pertain status registers assigned port where There readable positions alarm. odd-numbered address) indicates detected alarm unlatched. second preceding even-numbered address) provides alarm status latched alarm indication. latched position positive, negative, positive/negative transition alarm, positive level alarm. latched alarm cleared microprocessor read cycle address. During read cycle, internal logic holds increment counter until read cycle complete, then updates counter afterwards. Address Port Port Port Port Port Port Port Port Symbol Latched Alarms AnAIS AnLOP Description Same alarms following address locations, except these alarm states latched.
Drop Port VT/TU Alarm: indicates that been detected V1/V2 pointer bytes VT/TU selected. Drop Port Loss VT/TU Pointer Alarm: indicates that loss pointer been detected V1/V2 pointer bytes VT/TU selected. Drop Port VT/TU Pointer Size Error Indication: indicates that receive size indicator pointer (Bits pointer byte) VT/TU selected. detection recovery time immediate. Drop Port Data Flag Indication: indicates that Data Flag (1001 0001/1101/1011/1000) been detected pointer byte VT/TU selected (i.e., bits byte inverse normal 0110 pattern differ only bit). Drop Port Remote Server Defect Indication: indicates that either remote server defect alarm been detected (bits equal 101), been detected coming from older equipment (bit equals when bits equal 11). number consecutive events used detection recovery determined control V5AL10. Drop Port Remote Failure Indication: indicates that byte equal VT/TU selected. detection recovery time immediate.
AnSIZE
AnNDF
AnRDIS
AnRFI
AnUNEQ Drop Port Unequipped Indication: indicates that Unequipped status been detected signal label (Bits VT/TU selected side drop bus. unequipped signal label equal 000. Five more consecutive received unequipped signal labels will cause this alarm. Recovery occurs when five more consecutive signal labels received equal 000. following alarms will cause unequipped indication: alarm (AnDH4E) when DV1SEL Loss pointer alarm (AnLOP) VT/TU alarm (AnAIS) Upstream detected (AnAISI) when HEAISE STS-1 AU-3 identifier). TXC-04251-MB December 1997
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Address Port Port Port Port (cont.) Symbol AnSLER Description Drop Port Signal Label Mismatch Indication: indicates that receive signal label (Bits does match microprocessorwritten signal label VT/TU selected side drop bus. Five more consecutive signal label mismatches (against microprocessor-written value), received labels equal 001, results alarm. Recovery occurs upon receipt five more consecutive correct signal labels, values.The following alarms will cause signal label mismatch indication: Port Port Port Port AnPJ Counter AnNJ Counter AnBIP2 Error Counter zeros (unequipped) (all ones) alarm (AnDH4E) when DV1SEL Loss pointer alarm (AnLOP) VT/TU alarm (AnAIS) Upstream detected (AnAISI) when HEAISE STS-1 AU-3 identifier).
Drop Port Positive Pointer Justification Counter: four-bit counter that increments positive pointer movement VT/TU selected. counter saturates full count cleared when read. Drop Port Negative Pointer Justification Counter: four-bit counter that increments negative pointer movement VT/TU selected. counter saturates full count cleared when read. Drop Port BIP-2 Error Counter: 8-bit counter which counts number BIP-2 errors detected VT/TU selected. maximum errors occur each frame. These errors cause single count BLOCK control counter saturates full count cleared when read. Drop Port FEBE Error Counter: 8-bit counter which counts number FEBE errors received (Bit VT/TU selected. counter saturates full count cleared when read. Unused: These bits read Drop Port Received Signal Label: three positions correspond three signal label bits bits through VT/TU selected. This location updated every microseconds. corresponds byte. These bits also compared against microprocessor-written mismatch signal label bits unequipped mismatch indication. Code (001) been implemented hardware does have written into this location. Same alarms corresponding address positions, except that these alarms latched.
Port Port Port Port Port Port Port Port Port Port Port Port
AnFEBE Error Counter Unused Label
Port Port Port Port
Latched Alarms
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Address Port Port Port Port Symbol AnRDIP Description Drop Port Remote Payload Defect Indication: indicates that remote payload defect alarm been detected (bits equal 010). number consecutive events used detection recovery determined control V5AL10. Drop Port Remote Connectivity Defect Indication: indicates that remote connectivity defect alarm been detected (bits equal 110). number consecutive events used detection recovery determined control V5AL10. Unused: These bits read Drop Port Byte: eight bits this register position correspond byte received VT/TU selected. corresponds byte. Drop Port Byte: eight bits this register position correspond byte received VT/TU selected. corresponds byte. Drop Port Byte: eight bits this register position correspond byte received VT/TU selected. corresponds byte. Drop Port O-bits: nibbles (bits 3-0) this register correspond sets four overhead communication bits received VT/TU selected. corresponds second justification control byte, while corresponds first justification control byte. nibbles written into this register location will from same frame. Same alarms following address locations, except these alarm states latched.
AnRDIC
Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port
Unused Receive Byte Receive Byte Receive Byte Receive O-Bits
Port Port Port Port Port Port Port Port
Latched Alarms BnAIS BnLOP
Drop Port VT/TU Alarm: indicates that been detected V1/V2 pointer bytes VT/TU selected. Drop Port Loss VT/TU Pointer Alarm: indicates that loss pointer been detected V1/V2 pointer bytes VT/TU selected. Drop Port Pointer Size Error Indication: indicates that receive size indicator pointer (Bits pointer byte) VT/TU selected. detection recovery time immediate. Drop Port Data Flag Indication: indicates that Data Flag (1001 0001/1101/1011/1000) been detected pointer byte VT/TU selected (i.e., bits byte inverse normal 0110 pattern differ only bit).
BnSIZE
BnNDF
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Address Port Port Port Port (cont.) Symbol BnRDIS Description Drop Port Remote Server Defect Indication: indicates that either remote server defect alarm been detected (bits equal 101), been detected coming from older equipment (bit equals when bits equal 11). number consecutive events used detection recovery determined control V5AL10. Drop Port Remote Failure Indication: indicates that byte equal VT/TU selected. detection recovery time immediate.
BnRFI
BnUNEQ Drop Port Unequipped Indication: indicates that Unequipped status been detected signal label (Bits VT/TU selected side drop bus. unequipped signal label equal 000. Five more consecutive received unequipped signal labels will cause this alarm. Recovery occurs when five more consecutive signal labels received equal 000. following alarms will cause unequipped indication: alarm (BnDH4E) when DV1SEL Loss pointer alarm (BnLOP) VT/TU alarm (BnAIS) Upstream detected (BnAISI) when HEAISE STS-1 AU-3 identifier).
BnSLER
Drop Port Signal Label Mismatch Indication: indicates that receive signal label (Bits does match microprocessorwritten signal label VT/TU selected side drop bus. Five more consecutive signal label mismatches (against microprocessor-written value), received labels equal 001, results alarm. Recovery occurs upon receipt five more consecutive correct signal labels, values.The following alarms will cause signal label mismatch indication: zeros (unequipped) (all ones) alarm (BnDH4E) when DV1SEL Loss pointer alarm (BnLOP) VT/TU alarm (BnAIS) Upstream detected (BnAISI) when HEAISE STS-1 AU-3 identifier).
Port Port Port Port
BnPJ Counter BnNJ Counter BnBIP2 Error Counter
Drop Port Positive Pointer Justification Counter: four-bit counter that increments positive pointer movement VT/TU selected. counter saturates full count cleared when read. Drop Port Negative Pointer Justification Counter: four-bit counter that increments negative pointer movement VT/TU selected. counter saturates full count cleared when read. Drop Port BIP-2 Error Counter: 8-bit counter which counts number BIP-2 errors detected VT/TU selected. maximum errors occur each frame. These errors cause single count BLOCK control counter saturates full count cleared when read.
Port Port Port Port
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Address Port Port Port Port Port Port Port Port Symbol BnFEBE Error Counter Unused Label Description Dr
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