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Single-Channel XF-HDLC Controller
AllianceCORE
Facts
Core Specifics Table Provided with Core 7810 South Hardy Drive, Suite Tempe, Arizona 85284 Phone: 888-845-5585 (USA) 480-753-5585 Fax: 480-753-5899 E-mail: info@memecdesign.com URL: www.memecdesign.com Documentation User's guide Design File Formats Verilog source RTL1 Constraint Files hdlc.ucf Verification Verilog Testbench, test vectors Instatiation Templates VHDL, Verilog Reference Designs Application Note Application Notes Additional Items None Simulation Tool Used Silos Support Support provided Memec Design Services
Notes: Synplify 5.08A used synthesis
Features
Supports 4000X, Spartan, VirtexTM, VirtexTM-E, SpartanTM-II devices. Conforms International Standard ISO/IEC 3309 Specification Starting point custom design 16-bit/32-bit CCITT-CRC generation checking Flag Zero insertion detection Full Duplex Operation allowed Mbps (STS-1) data rate Full synchronous operation Interface customized user FIFO requirements
Applications
Frame Relay, ISDN X.25 protocols Logic consolidation
Table Core Implementation Data CLBs2 Core+ Core logic 1832 1832 1832 1832 Clock IOBs IOBs1 Core+ Core logic Performance3 (MHz)
Supported Family Spartan-II Virtex-E Virtex Spartan 4000X
Device Tested 2S15-5 V50E-6 V50-4 S10-4 4005XL-2
Xilinx Tools M2.1i M2.1i M2.1i M1.5i M1.5i
Special Features None None None None None
Notes: Assuming core I/Os routed off-chip. Utilization numbers Virtex, Virtex-E, Spartan-II, slices. Minimum guaranteed speed
February 2000
Single-Channel XF-HDLC Controller
External Logic XF-HDLC CORE
Transmitter TX_DATA [7:0]
8-bit Parallel Serial Shift Register 16/32-bit Generator Flag Abort Generation
External Logic
Zero Insertion
IDLE_SEL
TX_DATA_VALID
IPad
TX_LOAD
TX_EOF
BUFG
Flag Abort Detection
Transmit Control
TX_UNDERRUN
TX_CE
Zero Detection
16/32-bit Checker
8-bit Serial Parallel Shift Register Status
RX_DATA [7:0]
FCS16_32
RX_SPACE_AVAIL
BUFG
RX_READY RX_SOF
IPad
RX_CE
Receive Control
RX_EOF RX_STATUS
STARTUP
RESET
Receiver
X9011
Figure HDLC Controller Block Diagram
General Description
XF-HDLC performs most common functions HDLC controller. Data bytes clocked into device based divided version transmit clock. This data then serialized framed according rules HDLC sent serial transmit data pin. Receive frames clocked into receive data synchronous receive clock. framing overhead then stripped data bytes converted from serial parallel passed through parallel receive bus. Figure shows block diagram. cores designed with philosophy that global elements should embedded within core itself. Global elements include following components: STARTUP, STARTBUF, BSCAN, READBACK, Global Buffers, Fast Output Primitives, Elements, Clock Delay Components, Oscillator Macros. cores contain resources present only array. This done allow flexibility using cores with other logic. instance, global clock buffer embedded within core, some external logic also requires that same clock, then additional global buffer would have used. instance, where cores generates clock, that signal brought core, through global buffer, then brought back into core. This philosophy
allows external logic that clock without using another global buffer. result this philosophy that cores self-contained. External logic must connected core order complete cores include tested sample designs that external logic required complete functionality. This datasheet describes both core supplied external logic.
Functional Description
Transmitter
transmitter portion HDLC core will begin transmit when user's external logic asserts TX_DATA_VALID signal. transmitter will respond asserting TX_LOAD signal load first byte packet. timing diagram assumes that IDLE_SEL tied transmitter generating continuous bits between frames. IDLE_SEL `0', number clocks from assertion TX_DATA_VALID TX_LOAD will vary from Before transmitter begin send data serially, must send opening flag (7E). Immediately after flag sent, first byte clocked input shift register. Once transmit frame begun, user required make sure that data available each subsequent requested byte. transmitter will continue request data asserting TX_LOAD until user February 2000
supplies TX_EOF signal. This informs transmitter that last byte data bus. transmitter then appends 32-bit Frame Checking Sequence (FCS) transmitted data. After sent, closing flag (7E) byte appended mark frame. HDLC Transmitter consists following blocks shown Figure
Transmit Control
control state machines interface timing transmitter driven rising edge TXC.
Receiver
receiver clocks serial HDLC frames continuously through pin. When opening flag recognized, receiver locks subsequent octet bytes. user informs receiver ability store frame asserting RX_SPACE_AVAILABLE input. receiver informs user that data byte available asserting RX_READY signal. receiver indicates beginning frame asserting RX_SOF signal. Bytes will continue being passed user until receiver recognizes closing flag. this point, last byte sequence will passed user coincident with RX_EOF signal. must stressed that core does contain additional pipeline registers "swallow" bytes FCS, these will therefore passed user. this undesirable, corresponding pipeline should added externally keep these bytes from passing part received frame. After reception frame completed, receiver will pass byte status information user placing status receive data asserting RX_STATUS signal. Receiver consists following blocks shown Figure
8-bit Parallel-to-Serial Shift Register
This block responsible capturing user's transmit data rising edge when TX_LOAD signal asserted. Data sent Generator same time.
16/32-bit Generator
Frame Checking Sequence (FCS) Generator used calculate across transmitted message. different polynomials selected statically controlling FCS16_32 pin. 16-bit uses polynomial selected when FCS16_32 logic LOW. 32-bit uses polynomial selected when FCS16_32 logic HIGH. Either type complemented before being transmitted.
Zero Insertion
transmitter responsible examining frame content between opening closing flags checking consecutive bits, including bits. consecutive bits detected, inserted into serial transmission. This will allow receiver distinguish between opening closing flag actual data.
Flag Abort Detection
receiver begins operation hunting opening flag character. Once flag been recognized. receiver begins receive incoming frame, continues monitor closing flag. Once closing flag been detected, frame complete. Once receiver detected opening flag, will monitor serial data stream consecutive bits detected. This condition defined receive abort reported user through receive status bit. receiver capable handling back-to-back frames where closing flag first frame also acts opening flag second frame. receiver will idle either contiguous bits repeating flag characters.
Flag Abort Generation
opening flag sent when user asserts TX_DATA_VALID signal. soon last byte been transmitted, closing flag sent. transmission been started TX_DATA_VALID signal deasserted while transmitter requesting another byte, underrun condition will occur. This condition will reported with TX_UNDERRUN pin, will also result transmitter sending consecutive bits. This defined "abort" condition. transmitter will inter-frame fill driving contiguous stream bits repeating flag. back-to-back frames available send (the user continues assert TX_DATA_VALID), transmitter will share closing flag first frame with opening flag second frame.
Zero Detection
receiver checks incoming data frame consecutive bits received. this condition detected, following zero deleted from incoming frame.
Serial Output
data exits transmitter transitions rising edge TXC.
16/32-bit Check
Frame Checking Sequence (FCS) Checker performs same generator polynomial division transmitter across entire transmitted message including field. result this polynomial division will constant remainder indicating packet integrity. receiver sup-
February 2000
Single-Channel XF-HDLC Controller ports same 16-bit 32-bit transmitter. version statically selected using FCS16_32 pin, 16-bit version selected logic 32-bit version selected with logic HIGH.
Receive Control
control state machines interface timing receiver driven rising edge RXC.
8-bit Serial Shift Register
serial data clocked into receiver, assembled back into bytes through serial-to-parallel shift register. receiver informs user valid byte asserting RX_READY signal. RX_READY further qualified with additional signals help user track progress incoming frame. RX_SOF asserted coincident with RX_READY indicate reception first octet frame. RX_EOF asserted coincident with RX_READY indicate last byte receive FCS. RX_STATUS signal asserted coincident with RX_READY indicate user that receive data contains valid byte status information.
Core Modifications
Customizing available through Memec Design Services.
Pinout
pinout Single-Channel XF-HDLC Controller core been fixed specific FPGA I/O, allowing flexibility with user's application. Signal names provided Table
Verification Methods
Complete functional timing simulation been performed HDLC using SILO III. Simulation vectors provided with core. HDLC core been hardware tested with Fireberd 6000A Frame Relay Option. This core also been used successfully customer designs.
Status Byte
ERROR FRAME ERROR FRAME ABORT OCTET ERROR OVERRUN ERROR RESERVED X9012
Ordering Information
Single Channel XF-HDLC Controller core provided under license from Memec Design Services Xilinx programmable logic devices Xilinx HardWire gate arrays. Please contact Memec pricing more information. Information furnished Memec Design Services believed accurate reliable. Memec Design Services reserves right change specifications detailed this data sheet time without notice, order improve reliability, function design, assumes responsibility errors within this document. Memec Design Services does make commitment update this information. Memec Design Services assumes obligation correct errors contained herein advise user this text correction, such made, does Company assume responsibility functioning undescribed features parameters. Memec Design Services will assume liability accuracy correctness support assistance provided user. Memec Design Services does represent that products described herein free from patent infringement from other third-party right. license granted implication otherwise under patent patent rights Memec Design Services. Memec Design Services products intended life support appliances, devices, systems. Memec Design Services product such application without written consent appropriate Memec Design Services officer prohibited. trademarks, registered trademarks, service marks property their respective owners. February 2000
status byte will presented user frame after receive error detected. receiver will inform user valid status RX_DATA coincident assertion RX_READY RX_STATUS. ERROR will frame remainder after polynomial division does match proper 16-bit 32-bit constant. FRAME ERROR status will frame received that shorter than bits when using 16-bit FCS, shorter than bits when using 32-bit CRC. There test check frame lengths that exceed certain length. This will also when OCTET ERROR set. FRAME ABORT status will receiver detected consecutive bits after frame reception begun. OCTET ERROR status whenever closing flag received boundary. receiver tests make sure frames integral number octets. remaining status bits reserved will presented `0'.
Table Core Signal Pinout Signal TX_DATA[7:0] Signal Direction Input Description Transmitter Parallel Data Bus: 8-bit transmit data loaded synchronously based TX_LOAD signal clock.This driven user's transmit FIFO buffer. Idle Select: Selects inter-frame idle fill type. When tied low, device sends continuous flags between frames; when tied high, device sends continuous ones between frames. Transmit Data Valid: active high user input, synchronous TXC, inform transmitter that external packet ready send. Transmit End-Of-Frame: active high user input pulse, synchronous with TXC, inform transmitter that current data byte last byte sending packet. This input should coincide with TX_LOAD. Serial Transmit Clock: user-provided clock transmit activity that takes place high transition TXC. Transmit Clock Enable: active high user input, synchronous with TXC. Serial Receive Data: input serial receive data, sampled rising edge RXC. Select: selects 16-bit FCS, when tied low. Selects 32bit FCS, when tied high. Receive Space Available: active high user input, synchronous RXC, inform receiver that external receive FIFO buffer accept more data. Serial Receive Clock: user provided clock receive activity that takes place high transition RXC. Receive Clock Enable: active high user input, synchronous with RXC. Global Reset: asynchronously resets internal registers. Serial Transmit Data: provides serial transmit data transitions rising edge clock. Transmit Load: output pulse from transmitter, synchronous TXC, that acts clock enable signal external transmit buffer request input byte. Transmit Underrun: active high output pulse, synchronous TXC, from transmitter indicating underrun error. This occurs upon start frame transmission, TX_DATA_VALID deasserted when TX_LOAD asserted. Receive Parallel Data Bus: 8-bit receive data providing user output data synchronous RX_READY clock. This tied user's receive FIFO buffer also reports frame status receive. Receive Ready: active high pulse from receiver, synchronous RXC, that acts clock enable signal external receive buffer output received byte. STATUS distinguishes receive data from frame status. Receive Start-Of-Frame: active high pulse, synchronous RXC, inform user that current receive data byte first byte frame. This pulse coincides with RX_READY pulse. Receive End-Of-Frame: active high pulse, synchronous RXC, inform user that current receive byte last byte (either frame checking sequence. This pulse coincident with RX_READY pulse. Receive Status: active high pulse, synchronous RXC, inform user that receive frame status being output RX_DATA bus. RX_STATUS coincident with RX_READY signal.
IDLE_SEL
Input
TX_DATA_VALID TX_EOF
Input Input
TX_CE FCS16_32
Input Input Input Input
RX_SPACE_AVAIL
Input
RX_CE RESET TX_LOAD
Input Input Input Output Output
TX_UNDERRUN
Output
RX_DATA[7:0]
Output
RX_READY
Output
RX_SOF
Output
RX_EOF
Output
RX_STATUS
Output
February 2000
Single-Channel XF-HDLC Controller
Recommended Design Experience
source version, users should familiar with Verilog entry, synthesis, simulation, Xilinx design flows.
Xilinx Programmable Logic
information Xilinx programmable logic development system software, contact your local Xilinx sales office, Xilinx, Inc. 2100 Logic Drive Jose, 95124 Phone: 408-559-7778 Fax: 408-559-7114 URL: www.xilinx.com general Xilinx literature, contact: Phone: E-mail: 800-231-3386 (inside 408-879-5017 (outside literature@xilinx.com
Related Information
ISO/IEC 3309 High-Level Data Link Control ProceduresFrame Structure ISO/IEC 4335 High-Level Data Link Control ProceduresElements Procedures ISO/IEC 8885 High-Level Data Link Control Procedures General Purpose Frame Information Field Content Format
AllianceCORE Phone: E-mail:
specific information, contact:
408-879-5381 alliancecore@xilinx.com
February 2000
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