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Intel® Xeon Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz

Document Number: 252135-003 March 2003

Intel® Xeon Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz
Product Features
512 KB Advanced Transfer L2 Cache (on-die, full speed Level 2 cache) with 8-way associativity and Error Correcting Code (ECC) Enables system support of up to 64 GB of physical memory Streaming SIMD Extensions 2 (SSE2) - 144 new instructions for double-precision floating point operations, media / video streaming, and secure transactions Enhanced floating point and multimedia unit for enhanced video, audio, encryption, and 3D performance Power Management capabilities - System Management mode - Multiple low-power states Advanced System Management Features - Thermal Monitor - Machine Check Architecture (MCA)
The Intel® Xeon Processor with 533 MHz Front Side Bus is designed for high-performance dual-processor workstation and server applications. Based on the Intel® NetBurst microarchitecture and the new Hyper-Threading Technology, it is binary compatible with previous Intel Architecture (IA-32) processors. The Intel Xeon processor with 533 MHz Front Side Bus is scalable to two processors in a multiprocessor system providing exceptional performance for applications running on advanced operating systems such as Windows XP, Windows 2000, Linux, and UNIX. The Intel Xeon processor with 533 MHz Front Side Bus delivers compute power at unparalleled value and flexibility for powerful workstations, internet infrastructure, and departmental server applications. The Intel® NetBurst microarchitecture and Hyper-Threading Technology deliver outstanding performance and headroom for peak internet server workloads, resulting in faster response times, support for more users, and improved scalability.
Document Number: 252135-003 March 2003
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Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Intel® Xeon processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.MPEG is an international standard for video compression /
Intel® Xeon Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz
Contents
1.0 Introduction............................................................. 7 1.1 1.2 1.3 2.0 Terminology...................................................... 8 1.1.1 Processor Packaging Terminology.............................. 8 State of Data ..................................................... 9 References ..................................................... 10
Electrical Specifications.................................................. 11 2.1 2.2 2.3 Front Side Bus and GTLREF ....................................... 11 Power and Ground Pins ........................................... 11 Decoupling Guidelines ............................................ 11 2.3.1 VCC Decoupling ........................................... 12 2.3.2 Front Side Bus AGTL+ Decoupling ............................ 12 Front Side Bus Clock (BCLK1:0) and Processor Clocking................ 12 2.4.1 Bus Clock ................................................ 13 PLL Filter ....................................................... 13 2.5.1 Mixing Processors ......................................... 15 Voltage Identification ............................................. 15 2.6.1 Mixing Processors of Different Voltages ........................ 16 Reserved Or Unused Pins.......................................... 17 Front Side Bus Signal Groups....................................... 17 Asynchronous GTL+ Signals........................................ 19 Maximum Ratings................................................ 19 Processor DC Specifications........................................ 19 AGTL+ Front Side Bus Specifications ................................. 26 Mechanical Specifications .......................................... 30 Processor Package Load Specifications ............................... 35 Insertion Specifications ............................................ 36 Mass Specifications............................................... 36 Materials....................................................... 36 Markings....................................................... 37 Pin-Out Diagram................................................. 38
Mechanical Specifications ................................................ 29
Pin Listing and Signal Definitions ........................................... 41 4.1 Processor Pin Assignments ........................................ 41 4.1.1 Pin Listing by Pin Name ..................................... 41 4.1.2 Pin Listing by Pin Number ................................... 50 Signal Definitions................................................. 60
Thermal Specifications ................................................... 69 5.1 5.2 Thermal Specifications ............................................ 70 Measurements for Thermal Specifications ............................. 72 5.2.1 Processor Case Temperature Measurement ..................... 72
Features .............................................................. 73 6.1 6.2 Power-On Configuration Options .................................... 73 Clock Control and Low Power States................................. 73
Intel® Xeon Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz
6.2.1 Normal State-State 1 ...................................... 73 6.2.2 AutoHALT Powerdown State-State 2 ......................... 74 6.2.3 Stop-Grant State-State 3 ................................... 74 6.2.4 HALT / Grant Snoop State-State 4 ............................ 75 6.2.5 Sleep State-State 5....................................... 75 6.2.6 Bus Response During Low Power States ....................... 76 Thermal Monitor ................................................. 76 6.3.1 Thermal Diode............................................ 77
Boxed Processor Specifications............................................ 79 7.1 7.2 Introduction ..................................................... 79 Mechanical Specifications.......................................... 80 7.2.1 Boxed Processor Heatsink Dimensions ......................... 80 7.2.2 Boxed Processor Heatsink Weight............................. 80 7.2.3 Boxed Processor Retention Mechanism and Heatsink Supports...... 80 Boxed Processor Requirements ..................................... 84 7.3.1 Intel® Xeon Processor with 533 MHz Front Side Bus ............ 84 7.3.2 1U Rack Mount Server Solution ............................... 88 Thermal Specifications............................................ 90 7.4.1 Boxed Processor Cooling Requirements ........................ 90
Debug Tools Specifications............................................... 91 8.1 Logic Analyzer Interface (LAI)....................................... 91 8.1.1 Mechanical Considerations .................................. 91 8.1.2 Electrical Considerations.................................... 91
Figures
Intel® Xeon Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz
Tables
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 38 39 41 42 43 44 45 46 47 Front Side Bus-to-Core Frequency Ratio .............................. 13 Front Side Bus Clock Frequency Select Truth Table for BSEL1:0.......... 13 Voltage Identification Definition ...................................... 16 Front Side Bus Signal Groups....................................... 18 Processor Absolute Maximum Ratings ................................ 19 Voltage and Current Specifications ................................... 21 Front Side Bus Differential BCLK Specifications......................... 23 AGTL+ Signal Group DC Specifications ............................... 24 TAP and PWRGOOD Signal Group DC Specifications.................... 24 Asynchronous GTL+ Signal Group DC Specifications .................... 25 BSEL1:0 and VID4:0 DC Specifications............................. 25 AGTL+ Bus Voltage Definitions...................................... 26 Miscellaneous Signals + Specifications ............................... 27 Dimensions for the Intel® Xeon Processor with 533 MHz Front Side Bus in the FC-mPGA2 Package................................. 32 Package Dynamic and Static Load Specifications ....................... 35 Processor Mass.................................................. 36 Processor Material Properties ....................................... 36 Pin Listing by Pin Name ........................................... 41 Pin Listing by Pin Number .......................................... 50 Signal Definitions................................................. 60 Processor Thermal Design Power.................................... 70 Power-On Configuration Option Pins ................................. 73 Thermal Diode Parameters ......................................... 77 Thermal Diode Interface........................................... 78 Fan Cable Connector Requirements.................................. 85 Fan Power and Signal Specifications................................. 85
Intel® Xeon Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz
Revision History
Date of Release November 2002 Revision No. -001 Initial Release Added 3.06 GHz information. Edited definitions with current terminology. Added two TDP loadline figures in chapter 6. Edited figures 18 and 19. Added notes to signal definition tables for symmetric agents. Edited Chapter 8.0 Boxed Processor Specifications. Deleted Chapter 3 and Removed Section 2.13, 2.14 Added Table 13 Description
February 2003
March 2003
Intel® Xeon Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz
Introduction
Intel® Xeon Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz
Terminology
Processor Packaging Terminology
Commonly used terms are explained here for clarification:
· 604-pin socket - The 604-pin socket contains an additional contact to accept the additional
keying pin on the Intel Xeon processor in the FC-mPGA2 packages at pin location AE30. The 604-pin socket will also accept processors with the INT-mPGA package. Since the additional contact for pin AE30 is electrically inert, the 604-pin socket will not have a solder ball at this location. Therefore, the additional keying pin will not require a baseboard via nor a surfacemount pad. See the mPGA604 Socket Design Guidelines for details regarding this socket.
· Central Agent - The central agent is the host bridge to the processor and is typically known as
the chipset.
Intel® Xeon Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz
· Flip Chip Ball Grid Array (FC-BGA) - Microprocessor packaging using "flip chip" design,
where the processor is attached to the substrate face-down for better signal integrity, more efficient heat removal and lower inductance.
· FC-mPGA2 - Packaging technology with the processor die mounted directly to a micro-Pin
Grid Array substrate with an integrated heat spreader (IHS).
· Front Side Bus - Front Side Bus (FSB) is the electrical interface that connects the processor to
the chipset. Also referred to as the processor system bus or the system bus. All memory and I / O transactions as well as interrupt messages pass between the processor and chipset over the FSB.
· Intel® Xeon processor with 512 KB L2 cache - The entire processor in its INT-mPGA
package, including processor core in its FC-BGA package, integrated heat spreader (IHS), and interposer.
· Intel® Xeon processor with 533 MHz Front Side Bus - The entire processor in its FCmPGA2 package, including processor core in its FC-BGA package, integrated heat spreader (IHS), and interposer.
· Integrated Heat Spreader (IHS) - The surface used to attach a heatsink or other thermal
solution to the processor.
specifications are to the pads of the processor core.
· Retention mechanism - The support components that are mounted through the baseboard to
the chassis to provide mechanical retention for the processor and heatsink assembly.
· Symmetric Agent - A symmetric agent is a processor which shares the same I / O subsystem
and memory array, and runs the same operating system as another processor in a system. Systems using symmetric agents are known as Symmetric Multiprocessing (SMP) systems. Intel® Xeon (DP - Dual Processor) processors should only be used in SMP systems which have two or fewer symmetric agents.
State of Data
The data contained in this document is subject to change. It is the best information that Intel is able to provide at the publication date of this document.
Intel® Xeon Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz
References
The reader of this specification should also be familiar with material and concepts presented in the following documents:.
Intel Order Number1 241618 245470 245471 245472 http://developer.intel.com 298348 249672 11299 249678 249206 249205 298646 298644 249679
Processor Voltage Regulator Down (VRD) Design
ITP700 Debug Port Design Guide Intel® Xeon Processor with 533 MHz Front Side Bus System Compatibility Guidelines Intel® Xeon Processor with 533 MHz Front Side Bus Signal Integrity Models Intel® Xeon Processor with 533 MHz Front Side Bus Mechanical Models in ProE Format IIntel® Xeon Processor with 533 MHz Front Side Bus Mechanical Models in IGES Format Intel® Xeon Processor with 512-KB L2 Cache Front Side Bus Thermal Models (FloTherm and ICEPAK format) Intel® Xeon Processor with 533 MHz Front Side Bus Core Boundary Scan Descriptor Language (BSDL) Model Wired for Management 2.0 Design Guide Boxed Integration Notes
http://developer.intel.com http://developer.intel.com http://developer.intel.com http://developer.intel.com http://developer.intel.com http://developer.intel.com http://support.intel.com / support / processors / xeon
NOTES:
1. Contact your Intel representative for the latest revision of documents without order numbers.
Intel® Xeon Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz
Electrical Specifications
Front Side Bus and GTLREF
Most Intel® Xeon Processor with 533MHz Front Side Bus signals use Assisted Gunning Transceiver Logic (AGTL+) signaling technology. This signaling technology provides improved noise margins and reduced ringing through low voltage swings and controlled edge rates. The processor termination voltage level is VCC, the operating voltage of the processor core. The use of a termination voltage that is determined by the processor core allows better voltage scaling on the processor front side bus. Because of the speed improvements to data and address busses, signal integrity and platform design methods become more critical than with previous processor families. Front side bus design guidelines are detailed in the appropriate platform design guide (refer to Section 1.3). The AGTL+ inputs require a reference voltage (GTLREF) which is used by the receivers to determine if a signal is a logical 0 or a logical 1. GTLREF must be generated on the baseboard (See Table 12 for GTLREF specifications). Termination resistors are provided on the processor silicon and are terminated to its core voltage (VCC). The on-die termination resistors are a selectable feature and can be enabled or disabled via the ODTEN pin. For end bus agents, on-die termination can be enabled to control reflections on the transmission line. For middle bus agents, on-die termination must be disabled. Intel chipsets will also provide on-die termination, thus eliminating the need to terminate the bus on the baseboard for most AGTL+ signals. Refer to Section 2.12 for details on ODTEN resistor termination requirements. Note: Some AGTL+ signals do not include on-die termination and must be terminated on the baseboard. See Table 4 for details regarding these signals. The AGTL+ signals depend on incident wave switching. Therefore timing calculations for AGTL+ signals are based on flight time as opposed to capacitive deratings. Analog signal simulation of the front side bus, including trace lengths, is highly recommended when designing a system. Please refer to http://developer.intel.com to obtain the Intel® Xeon Processor with 533 MHZ Front Side Bus Signal Integrity Models.
Power and Ground Pins
For clean on-chip power distribution, the Intel Xeon processor with 533 MHz Front Side Bus has 190 VCC (power) and 189 VSS (ground) inputs. All VCC pins must be connected to the system power plane, while all VSS pins must be connected to the system ground plane. The processor VCC pins must be supplied the voltage determined by the processor VID (Voltage ID) pins.
Decoupling Guidelines
Due to its large number of transistors and high internal clock speeds, the processor is capable of generating large average current swings between low and full power states. This may cause voltages on power planes to sag below their minimum values if bulk decoupling is not adequate. Larger bulk storage (CBULK), such as electrolytic capacitors, supply current during longer lasting changes in current demand by the component, such as coming out of an idle condition. Similarly, they act as a storage well for current when entering an idle condition from a running condition.
Intel® Xeon Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz
Care must be taken in the baseboard design to ensure that the voltage provided to the processor remains within the specifications listed in Table 6. Failure to do so can result in timing violations or reduced lifetime of the component. For further information and guidelines, refer to the appropriate platform design guidelines.
VCC Decoupling
Regulator solutions need to provide bulk capacitance with a low Effective Series Resistance (ESR) and the baseboard designer must ensure a low interconnect resistance from the regulator (or VRM pins) to the 604-pin socket. Bulk decoupling may be provided on the voltage regulation module (VRM) to meet help meet the large current swing requirements. The remaining decoupling is provided on the baseboard. The power delivery path must be capable of delivering enough current while maintaining the required tolerances (defined in Table 6). For further information regarding power delivery, decoupling, and layout guidelines, refer to the appropriate platform design guidelines.
Front Side Bus AGTL+ Decoupling
The Intel® Xeon processor with 533MHz Front Side Bus integrates signal termination on the die as well as part of the required high frequency decoupling capacitance on the processor package. However, additional high frequency capacitance must be added to the baseboard to properly decouple the return currents from the front side bus. Bulk decoupling must also be provided by the baseboard for proper AGTL+ bus operation. Decoupling guidelines are described in the appropriate platform design guidelines.
Front Side Bus Clock (BCLK1:0) and Processor Clocking
BCLK1:0 directly controls the front side bus interface speed as well as the core frequency of the processor. As in previous generation processors, the processor core frequency is a multiple of the BCLK1:0 frequency. The maximum processor bus ratio multiplier will be set during manufacturing. The default setting will equal the maximum speed for the processor. The BCLK1:0 inputs directly control the operating speed of the front side bus interface. The processor core frequency is configured during reset by using values stored internally during manufacturing. The stored value sets the highest bus fraction at which the particular processor can operate. Clock multiplying within the processor is provided by the internal PLL, which requires a constant frequency BCLK1:0 input with exceptions for spread spectrum clocking. Processor DC and AC specifications for the BCLK1:0 inputs are provided in Table 7 and Table 13, respectively. These specifications must be met while also meeting signal integrity requirements as outlined in Chapter 3.0. The processor utilizes a differential clock. Details regarding BCLK1:0 driver specifications are provided in the CK408 Clock Synthesizer / Driver Design Guidelines. Table 1 contains the supported bus fraction ratios and their corresponding core frequencies.
Intel® Xeon Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz
Intel® Xeon Processor with 533 MHz Front Side Bus
Table 1.
Front Side Bus-to-Core Frequency Ratio
Front Side Bus-to-Core Frequency Ratio 1 / 15 1 / 18 1 / 20 1 / 21 1 / 23 Core Frequency 2 GHz 2.40 GHz 2.66 GHz 2.80 GHz 3.06 GHz
Bus Clock
Table 2. Front Side Bus Clock Frequency Select Truth Table for BSEL1:0
BSEL1 L L H H BSEL0 L H L H Bus Clock Frequency 100 MHz 133 MHz Reserved Reserved
PLL Filter
VCCA and VCCIOPLL are power sources required by the processor PLL clock generator. This requirement is identical to that of the Intel Xeon processor with 512-KB L2 cache. Since these PLLs are analog in nature, they require quiet power supplies for minimum jitter. Jitter is detrimental to the system: it degrades external I / O timings as well as internal core timings (i.e. maximum frequency). To prevent this degradation, these supplies must be low pass filtered from VCC. A typical filter topology is shown in Figure 1. The AC low-pass requirements, with input at VCC and output measured across the capacitor (CA or CIO in Figure 1), is as follows:
Datasheet
The filter requirements are illustrated in Figure 2. For recommendations on implementing the filter refer to the appropriate platform design guidelines.
Figure 1. Typical VCCIOPLL, VCCA and VSSA Power Distribution
Socket pin
Processor interposer "pin" R-Socket VCCA PLL R-Socket VSSA C Processor
Baseboard via that connects filter to VCC plane
R-Trace L1 / L2
R-Socket
VCCIOPLL
Figure 2. Phase Lock Loop (PLL) Filter Requirements
0.2 dB 0 dB -0.5 dB forbidden zone
-28 dB
forbidden zone
-34 dB
DC passband
fpeak
66 MHz
fcore
high frequency band
Intel® Xeon Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz
NOTES: 1. Diagram not to scale. 2. No specifications for frequencies beyond fcore (core frequency). 3. fpeak, if existent, should be less than 0.05 MHz.
Mixing Processors
Intel only supports those processor combinations operating with the same front side bus frequency, core frequency, VID settings, and cache sizes. Not all operating systems can support multiple processors with mixed frequencies. Intel does not support or validate operation of processors with different cache sizes. Mixing processors of different steppings but the same model (as per CPUID instruction) is supported, and is outlined in the Intel® Xeon Processor Specification Update. Additional details are provided in AP-485, the Intel Processor Identification and the CPUID Instruction application note. The Intel Xeon processor with 533 MHz Front Side Bus does not sample the pins IGNNE#, LINT0 / INTR, LINT1 / NMI, and A20M# to establish the core to front side bus ratio. Rather, the processor runs at its tested frequency at initial power-on. If the processor needs to run at a lower core frequency, as must be done when a higher speed processor is added to a system that contains a lower frequency processor, the system BIOS is able to effect the change in the core to front side bus ratio.
Voltage Identification
Intel® Xeon Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz
Table 3. Voltage Identification Definition
Mixing Processors of Different Voltages
Mixing processors operating with different VID settings (voltages) is not supported and will not be validated by Intel.
Intel® Xeon Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz
Reserved Or Unused Pins
Front Side Bus Signal Groups
In order to simplify the following discussion, the front side bus signals have been combined into groups by buffer type. AGTL+ input signals have differential input buffers, which use GTLREF as a reference level. In this document, the term "AGTL+ Input" refers to the AGTL+ input group as well as the AGTL+ I / O group when receiving. Similarly, "AGTL+ Output" refers to the AGTL+ output group as well as the AGTL+ I / O group when driving. With the implementation of a source synchronous data bus comes the need to specify two sets of timing parameters. One set is for common clock signals whose timings are specified with respect to rising edge of BCLK0 (ADS#, HIT#, HITM#, etc.) and the second set is for the source synchronous signals which are relative to their respective strobe lines (data and address) as well as
Intel® Xeon Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz
rising edge of BCLK0. Asynchronous signals are still present (A20M#, IGNNE#, etc.) and can become active at any time during the clock cycle. Table 4 identifies which signals are common clock, source synchronous and asynchronous.
Table 4. Front Side Bus Signal Groups
Signal Group AGTL+ Common Clock Input Type Synchronous to BCLK1:0 Signals 1 BPRI#, BR3:1#3, 4, DEFER#, RESET#4, RS2:0#, RSP#, TRDY# ADS#, AP1:0#, BINIT#7, BNR#7, BPM5:0#2, BR0#2, DBSY#, DP3:0#, DRDY#, HIT#7, HITM#7, LOCK#, MCERR#7
AGTL+ Common Clock I / O
Synchronous to BCLK1:0
Signals
REQ4:0#, A16:3# 6
Associated Strobe
ADSTB0# ADSTB1# DSTBP0#, DSTBN0# DSTBP1#, DSTBN1# DSTBP2#, DSTBN2# DSTBP3#, DSTBN3#
AGTL+ Source Synchronous I / O
Synchronous to assoc. strobe
A35:17#
D15:0#, DBI0# D31:16#, DBI1# D47:32#, DBI2# D63:48#, DBI3#
AGTL+ Strobes Asynchronous GTL+ Input 4 Asynchronous GTL+ Output 4 Front Side Bus Clock TAP Input 2 TAP Output 2
Synchronous to BCLK1:0 Asynchronous Asynchronous Clock Synchronous to TCK Synchronous to TCK
Power / Other
Intel® Xeon Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz
Asynchronous GTL+ Signals
The Intel® Xeon Processor with 533 MHz Front Side Bus does not utilize CMOS voltage levels on any signals that connect to the processor silicon. As a result, legacy input signals such as A20M#, IGNNE#, INIT#, LINT0 / INTR, LINT1 / NMI, SLP#, and STPCLK# utilize GTL+ input buffers. Legacy output FERR# / PBE# and other non-AGTL+ signals IERR#, THERMTRIP# and PROCHOT# utilize GTL+ output buffers. All of these asynchronous GTL+ signals follow the same DC requirements as AGTL+ signals, however the outputs are not driven high (during the logical 0to-1 transition) by the processor (the major difference between GTL+ and AGTL+). Asynchronous GTL+ signals do not have setup or hold time specifications in relation to BCLK1:0. However, all of the asynchronous GTL+ signals are required to be asserted for at least two BCLKs in order for the processor to recognize them. See Table 10 for the DC specifications for the asynchronous GTL+ signal groups.
Maximum Ratings
Table 5. Processor Absolute Maximum Ratings
Symbol TSTORAGE VCC VinAGTL+ VinGTL+ IVID Parameter Processor storage temperature Any processor supply voltage with respect to V SS AGTL+ buffer DC input voltage with respect to V SS Async GTL+ buffer DC input voltage with respect to Vss Max VID pin current Min -40 -0.3 -0.1 -0.1 Max 85 1.75 1.75 1.75 5 Unit °C V V V mA Notes 2 1
1. This rating applies to any pin of the processor. 2. Contact Intel for storage requirements in excess of one year.
Processor DC Specifications
The processor DC specifications in this section are defined at the processor core (pads) unless noted otherwise. See Section 5.1 for the processor pin listings and Section 5.2 for the signal definitions. The voltage and current specifications for all versions of the processor are detailed in Table 6. For platform planning refer to Figure 3. Notice that the graphs include Thermal Design Power (TDP) associated with the maximum current levels. The DC specifications for the AGTL+ signals are listed in Table 8.
Intel® Xeon Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz
Table 6 through Table 11 list the processor DC specifications and are valid only while meeting specifications for case temperature (TCASE as specified in Chapter 6.0), clock frequency, and input voltages. Care should be taken to read all notes associated with each parameter.
Intel® Xeon Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz
Table 6. Voltage and Current Specifications
Symbol Parameter Core Freq Min Typ Max VID Unit Notes1
2 GHz VCC VCC for Intel Xeon processor with 533 MHz Front Side Bus 2.40 GHz 2.66 GHz 2.80 GHz 3.06 GHz SMBus supply voltage
1.353 1.344 1.334 1.331 1.352 Refer to Figure 3
All freq.
2 GHz ICC ICC for Intel Xeon processor with 533 MHz Front Side Bus 2.40 GHz 2.66 GHz 2.80 GHz 3.06 GHz ICC for PLL power pins ICC for GTLREF pins ICC Stop-Grant / Sleep ICC TCC active
All freq All freq All freq All freq
Intel® Xeon Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz
Figure 3. Intel® Xeon processor with 533 MHz Front Side Bus Voltage-Current Projections (VID 1.5V)
1.51 Maximum Processor Voltage (VDC) 1.50 1.49 1.48 1.47 1.46 1.45 1.44 0 10 20 30 40 50 60 70 Processor Current (A)
Intel® Xeon Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz
Figure 4. Intel Xeon processor with 533 MHz Front Side Bus Voltage-Current Projections (VID 1.525V)
Table 7. Front Side Bus Differential BCLK Specifications
Symbol VL VH VCROSS(abs) VCROSS(rel) VCROSS VOV VUS VRBM V Parameter Input Low Voltage Input High Voltage Absolute Crossing Point Relative Crossing Point Range of Crossing Points Overshoot Undershoot Ringback Margin Threshold Margin NOTES:. Min -.150 0.660 0.250 0.250 + 0.5(VHavg - 0.710) N / A N / A -0.300 0.200 Vcross - 0.100 Typ 0.000 0.710 N / A N / A N / A N / A N / A N / A N / A Max N / A 0.850 0.550 0.550 + 0.5(VHavg - 0.710) 0.140 VH + 0.3 N / A N / A Vcross + 0.100 Unit V V V V V V V V V Figure 7 7 7, 7 7, 7 7, 7 7 7 6 6 2, 8 2, 3, 8, 9 2, 10 4 5 Notes
Intel® Xeon Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. Crossing voltage is defined as the instantaneous voltage value when the rising edge of BCLK0 equals the falling edge of BCLK1. 3. VHavg is the statistical average of the VH measured by the oscilloscope. 4. Overshoot is defined as the absolute value of the maximum voltage. 5. Undershoot is defined as the absolute value of the minimum voltage. 6. Ringback Margin is defined as the absolute voltage difference between the maximum Rising Edge Ringback and the maximum Falling Edge Ringback. 7. Threshold Region is defined as a region entered around the crossing point voltage in which the differential receiver switches. It includes input threshold hysteresis. 8. The crossing point must meet the absolute and relative crossing point specifications simultaneously. 9. VHavg can be measured directly using "Vtop" on Agilent scopes and "High" on Tektronix scopes. 10.VCROSS is defined as the total variation of all crossing voltages as defined in note 2.
Table 8. AGTL+ Signal Group DC Specifications
Table 9. TAP and PWRGOOD Signal Group DC Specifications
Symbol VHYS VT+ VTVOH IOL IHI ILO Parameter TAP Input Hysteresis TAP input low to high threshold voltage TAP input high to low threshold voltage Output High Voltage Output Low Current Pin Leakage High Pin Leakage Low N / A N / A Min 200 Max 300 Unit Notes 1, 2 8 5 5 V mA µA µA 3, 5 6, 7 10 9
Intel® Xeon Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz
Buffer On Resistance
Table 10. Asynchronous GTL+ Signal Group DC Specifications
Symbol VIH VIL VOH IOL IHI ILO RON Parameter Input High Voltage Input Low Voltage Output High Voltage Output Low Current Pin Leakage High Pin Leakage Low Buffer On Resistance N / A N / A 7 Min 1.10 GTLREF 0.0 N / A Max VCC 0.90 GTLREF VCC 50 100 500 11 Unit V V V mA µA µA Notes1, 7 3, 5, 7 4, 6 2, 5, 7 8, 9 11 10 6
Table 11. BSEL1:0 and VID4:0 DC Specifications
Symbol Ron (BSEL) Ron (VID) IHI
Parameter Buffer On Resistance Buffer On Resistance Pin Leakage Hi
Max 14.3 12.8 100
Intel® Xeon Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. These parameters are not tested and are based on design simulations. 3. Leakage to Vss with pin held at 2.50V.
AGTL+ Front Side Bus Specifications
Table 12. AGTL+ Bus Voltage Definitions
Symbol GTLREF GTLREF
New Design
Parameter Bus Reference Voltage Bus Reference Voltage Termination Resistance Termination Resistance COMP Resistance COMP Resistance
Typ 2 / 3 VCC 0.63VCC 41 50 43.2 50
RTT RTT New Design COMP1:0 COMP1:0 New Design
Intel® Xeon Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz
Table 13. Miscellaneous Signals + Specifications
T# Parameter T39: THERMTRIP# to Vcc Removal Min Max 0.5 Unit S Figure 6 Notes
Figure 5. Electrical Test Circuit
Figure 6. THERMTRIP# to VCC Timing
THERMTRIP# Power Down Sequence
THERMTRIP#
Intel® Xeon Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz
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Intel® Xeon Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz
Mechanical Specifications
The Intel® Xeon Processor with 533 MHz Front Side Bus uses the Flip Chip Micro-Pin Grid Array (FC-mPGA) package containing the processor die covered by an integrated heat spreader (IHS) Mechanical specifications for the processor are given in this section. See Section 1.1 for terminology definitions. Figure 7 provides a basic assembly drawing and includes the components which make up the entire processor. Package dimensions are provided in Table 14. The Intel® Xeon processor with 533 MHz Front Side Bus utilizes a surface mount 604-pin zeroinsertion force (ZIF) socket for installation into the baseboard. See the 604-Pin Socket Design Guidelines for further details on the processor socket. For Figure 9 through Figure 13, the following notes apply: 1. Unless otherwise specified, the following drawings are dimensioned in millimeters. 2. All dimensions are not tested, but are guaranteed by design characterization. 3. Figures and drawings labelled as "Reference Dimensions" are provided for informational purposes only. Reference Dimensions are extracted from the mechanical design database and are nominal dimensions with no tolerance information applied. Reference Dimensions are NOT checked as part of the processor manufacturing process. Unless noted as such, dimensions in parentheses without tolerances are Reference Dimensions. 4. Drawings are not to scale. Figure 7. FC-mPGA2 Processor Package Assembly Drawing
Note:
applies to Intel Xeon processor in the FC-mPGA2 package. 1. Integrated Heat Spreader (IHS) 2. Processor die 3. FC-mPGA2 package 4. Land side Capacitors 5. Package Pin
Intel® Xeon Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz
Figure 8.
Mechanical Specifications
FC-mPGA Processor Package Top View: Component Placement Detail
Pin A1
Intel® Xeon Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz
Figure 9.
Intel® Xeon Processor with 533 MHz Front Side Bus in the FC-mPGA2 Package Drawing
Intel® Xeon Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz
Table 14. Dimensions for the Intel® Xeon Processor with 533 MHz Front Side Bus in the FC-mPGA2 Package
Symbol A B E F G H J K L M N R T P Pin Tp Milimeters Min Nominal 42.40 42.50 30.90 31.00 3.42 3.60 1.95 2.03 18.80 19.05 37.85 38.10 6.35 12.70 14.99 15.24 30.23 30.48 6.35 1.27 12.70 0.26 0.31 Notes Max 42.60 31.10 3.78 2.11 19.30 38.35 Nominal Component Keepin Nominal Component Keepin 15.49 30.73 Nominal Component Keepin Nominal 0.36 0.25 Pin Diameter
Figure 10 details the keep-in zone for components mounted to the top side of the processor interposer. The components include the EEPROM, thermal sensor, resistors and capacitors. Figure 10. FC-mPGA2 Processor Package Top View: Component Height Keep-in
COMPONENT KEEPOUT CROSS HATCHED AREA
2.27 mm MAX ALLOWABLE COMPONENT HEIGHT 7.5 15.5
Intel® Xeon Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz
Figure 11 details the keep-in specification for pin-side components. The processor may contain pin side capacitors mounted to the processor package. These capacitors will be exposed within the opening of the interposer cavity. Figure 11. FC-mPGA2 Processor Package Cross Section View: Pin Side Component Keep-in
IHS FC-mPGA2P 1.5 mm Component Keepin 12.7 mm Component Keepin
Intel® Xeon Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz
Figure 12.
FC-mPGA2 Processor Package: Pin Detail
1. Kovar pin with plating of 0.2 micrometers Au over 2.0 micrometer Ni. 2. 0.254 Diametric true position, pin to pin.
Intel® Xeon Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz
Figure 13 details the flatness and tilt specifications for the IHS of the Intel Xeon processor with 533 MHz Front Side Bus, respectively. Tilt is measured with the reference datum set to the bottom of the processor interposer. Figure 13. IHS Flatness and Tilt Drawing
Processor Package Load Specifications
Table 15 provides dynamic and static load specifications for the processor IHS. These mechanical load limits should not be exceeded during heat sink assembly, mechanical stress testing, or standard drop and shipping conditions. The heat sink attach solutions must not induce continuous stress onto the processor with the exception of a uniform load to maintain the heat sink-toprocessor thermal interface. It is not recommended to use any portion of the processor interposer as a mechanical reference or load bearing surface for thermal solutions.
Table 15. Package Dynamic and Static Load Specifications
Intel® Xeon Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz
Insertion Specifications
The processor can be inserted and removed 15 times from a 604-pin socket meeting the mPGA604 Socket Design Guidelines document. Note that this specification is based on design characterization and is not tested.
Mass Specifications
Table 16 specifies the processors mass. This includes all components which make up the entire processor product.
Table 16. Processor Mass
Processor Intel® Xeon Processor with 533 MHz Front Side Bus Mass (grams) 25
Materials
The processor is assembled from several components. The basic material properties are described in Table 17.
Table 17. Processor Material Properties
Component Integrated Heat Spreader FC-BGA Interposer Interposer pins Material Nickel plated copper BT Resin FR4 Kovar with Gold over nickel
Intel® Xeon Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz
Markings
The following section details the processor top-side laser markings. It is provided to aid in the identification of the processor. Figure 14. Processor Top-Side Markings
Dynamic Laser Mark Area with 2D Matrix
Group A Line1 Group A Line2
Group B Line1 Group B Line2
2D Matrix encodes ATPO number and Serial number
Pin A1
NOTE:
1. Character size for laser markings is: height 0.050" (1.27mm), width 0.032" (0.81mm). 2. All characters will be in upper case. Figure 15. Processor Bottom-Side Markings
Intel® Xeon Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz
Pin-Out Diagram
This section provides two view of the processor pin grid. Figure 16 and Figure 17 detail the coordinates of the processor pins.
Figure 16.
Processor Pin Out Diagram: Top View
COMMON CLOCK
ADDRESS
COMMON CLOCK
Async / JTAG
Vcc / Vss
CLOCKS
SMBus
Intel® Xeon Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz
Figure 17.
Processor Pin Out Diagram: Bottom View
Async / JTAG
COMMON CLOCK
ADDRESS
COMMON CLOCK
SMBus
CLOCKS
Intel® Xeon Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz
Vcc / Vss
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Intel® Xeon Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz
Intel® Xeon Processor with 533MHz Front Side Bus
Pin Listing and Signal Definitions
Processor Pin Assignments
Section 2.8 contains the front side bus signal groups in Table 4 for the Intel® Xeon Processor with 533 MHz Front Side Bus. This section provides a sorted pin list in Table 38 and Table 39. Table 38 is a listing of all processor pins ordered alphabetically by pin name. Table 39 is a listing of all processor pins ordered by pin number.
Pin Listing by Pin Name
Table 38. Pin Listing by Pin Name Table 38. Pin Listing by Pin Name
Pin Name A3# A4# A5# A6# A7# A8# A9# A10# A11# A12# A13# A14# A15# A16# A17# A18# A19# A20# A21# A22# A23# A24# A25# A26# A27# Pin No. A22 A20 B18 C18 A19 C17 D17 A13 B16 B14 B13 A12 C15 C14 D16 D15 F15 A10 B10 B11 C12 E14 D13 A9 B8 Signal Buffer Type
Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync
Pin Name A28# A29# A30# A31# A32# A33# A34# A35# A20M# ADS# ADSTB0# ADSTB1# AP0# AP1# BCLK0 BCLK1 BINIT# BNR# BPM0# BPM1# BPM2# BPM3# BPM4# BPM5# BPRI# BR0#
Pin No. E13 D12 C11 B7 A6 A7 C9 C8 F27 D19 F17 F14 E10 D9 Y4 W5 F11 F20 F6 F8 E7 F5 E8 E4 D23 D20
Signal Buffer Type
Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Async GTL+ Common Clk Source Sync Source Sync Common Clk Common Clk Sys Bus Clk Sys Bus Clk Common Clk Common Clk Common Clk Common Clk Common Clk Common Clk Common Clk Common Clk Common Clk Common Clk
Direction Input / Output Input / Output Input / Output Input / Output Input / Output Input / Output Input / Output Input / Output Input Input / Output Input / Output Input / Output Input / Output Input / Output Input Input Input / Output Input / Output Input / Output Input / Output Input / Output Input / Output Input / Output Input / Output Input Input / Output
Direction Input / Output Input / Output Input / Output Input / Output Input / Output Input / Output Input / Output Input / Output Input / Output Input / Output Input / Output Input / Output Input / Output Input / Output Input / Output Input / Output Input / Output Input / Output Input / Output Input / Output Input / Output Input / Output Input / Output Input / Output Input / Output
Datasheet
Intel® Xeon Processor with 533MHz Front Side Bus Table 38. Pin Listing by Pin Name
Pin Name BR1# BR2# BR3#
Table 38. Pin Listing by Pin Name
Pin Name D32# D33# D34# D35# D36# D37# D38# D39# D40# D41# D42# D43# D44# D45# D46# D47# D48# D49# D50# D51# D52# D53# D54# D55# D56# D57# D58# D59# D60# D61# D62# D63# DBSY# DEFER# DBI0# DBI1# DBI2# DBI3# DP0# Pin No. AB16 AA16 AC17 AE13 AD18 AB15 AD13 AD14 AD11 AC12 AE10 AC11 AE9 AD10 AD8 AC9 AA13 AA14 AC14 AB12 AB13 AA11 AA10 AB10 AC8 AD7 AE7 AC6 AC5 AA8 Y9 AB6 F18 C23 AC27 AD22 AE12 AB9 AC18 Signal Buffer Type
Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Common Clk Common Clk Source Sync Source Sync Source Sync Source Sync Common Clk
Pin No. F12 E11 D10 AA3 AB3 AD16 E16 Y26 AA27 Y24 AA25 AD27 Y23 AA24 AB26 AB25 AB23 AA22 AA21 AB20 AB22 AB19 AA19 AE26 AC26 AD25 AE25 AC24 AD24 AE23 AC23 AA18 AC20 AC21 AE22 AE20 AD21 AD19 AB17
Signal Buffer Type
Common Clk Common Clk Common Clk Power / Other Power / Other Power / Other Power / Other Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync
Direction Input Input Input Output2 Output2 Input Input Input / Output Input / Output Input / Output Input / Output Input / Output Input / Output Input / Output Input / Output Input / Output Input / Output Input / Output Input / Output Input / Output Input / Output Input / Output Input / Output Input / Output Input / Output Input / Output Input / Output Input / Output Input / Output Input / Output Input / Output Input / Output Input / Output Input / Output Input / Output Input / Output Input / Output Input / Output Input / Output
Direction Input / Output Input / Output Input / Output Input / Output Input / Output Input / Output Input / Output Input / Output Input / Output Input / Output Input / Output Input / Output Input / Output Input / Output Input / Output Input / Output Input / Output Input / Output Input / Output Input / Output Input / Output Input / Output Input / Output Input / Output Input / Output Input / Output Input / Output Input / Output Input / Output Input / Output Input / Output Input / Output Input / Output Input Input / Output Input / Output Input / Output Input / Output Input / Output
BSEL0 BSEL1 COMP0 COMP1 D0# D1# D2# D3# D4# D5# D6# D7# D8# D9# D10# D11# D12# D13# D14# D15# D16# D17# D18# D19# D20# D21# D22# D23# D24# D25# D26# D27# D28# D29# D30# D31#
Datasheet
Intel® Xeon Processor with 533MHz Front Side Bus Table 38. Pin Listing by Pin Name 1
Pin Name DP1# DP2# DP3# DRDY# DSTBN0# DSTBN1# DSTBN2# DSTBN3# DSTBP0# DSTBP1# DSTBP2# DSTBP3# FERR# GTLREF GTLREF GTLREF GTLREF HIT# HITM# IERR# IGNNE# INIT# LINT0 LINT1 LOCK# MCERR# ODTEN PROCHOT# PWRGOOD REQ0# REQ1# REQ2# REQ3# REQ4# Reserved Reserved Reserved Reserved Reserved Pin No. AE19 AC15 AE17 E18 Y21 Y18 Y15 Y12 Y20 Y17 Y14 Y11 E27 W23 W9 F23 F9 E22 A23 E5 C26 D6 B24 G23 A17 D7 B5 B25 AB7 B19 B21 C21 C20 B22 A1 A4 A15 A16 A26 Signal Buffer Type
Common Clk Common Clk Common Clk Common Clk Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Async GTL+ Power / Other Power / Other Power / Other Power / Other Common Clk Common Clk Async GTL+ Async GTL+ Async GTL+ Async GTL+ Async GTL+ Common Clk Common Clk Power / Other Async GTL+ Async GTL+ Source Sync Source Sync Source Sync Source Sync Source Sync Reserved Reserved Reserved Reserved Reserved
Table 38. Pin Listing by Pin Name
Reserved Reserved Reserved Reserved Reserved Anode Pin Cathode Pin Reserved Reserved Ground Reserved Reserved Common Clk Common Clk Common Clk Common Clk Common Clk Power / Other Async GTL+ Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Async GTL+ Async GTL+ TAP TAP TAP Power / Other Power / Other Power / Other Power / Other
Direction Input / Output Input / Output Input / Output Input / Output Input / Output Input / Output Input / Output Input / Output Input / Output Input / Output Input / Output Input / Output Output Input Input Input Input Input / Output Input / Output Output Input Input Input Input Input / Output Input / Output Input Output Input Input / Output Input / Output Input / Output Input / Output Input / Output Reserved Reserved Reserved Reserved Reserved
Direction Reserved Reserved Reserved Reserved Reserved Output Output Reserved Reserved VSS Reserved Reserved Input Input Input Input Input Output Input
Input Input Input Input Output Input Input Input Input
Datasheet
Intel® Xeon Processor with 533MHz Front Side Bus Table 38. Pin Listing by Pin Name
Pin Name TESTHI4 TESTHI5 TESTHI6
THERMTRIP#
Table 38. Pin Listing by Pin Name
Pin Name VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC Pin No. E26 E28 E30 F1 F4 F10 F16 F22 F29 F31 G2 G4 G6 G8 G24 G26 G28 G30 H1 H3 H5 H7 H9 H23 H25 H27 H29 H31 J2 J4 J6 J8 J24 J26 J28 J30 K1 K3 K5 Signal Buffer Type
Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other
Pin No. AA7 AD5 AE5 F26 A25 E19 F24 A2 A8 A14 A18 A24 A28 A30 B4 B6 B12 B20 B26 B29 B31 C2 C4 C10 C16 C22 C28 C30 D1 D8 D14 D18 D24 D29 D31 E2 E6 E12 E20
Signal Buffer Type
Power / Other Power / Other Power / Other Async GTL+ TAP Common Clk TAP Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other
Direction Input Input Input Output Input Input Input
Direction
TMS TRDY# TRST# VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
Datasheet
Intel® Xeon Processor with 533MHz Front Side Bus Table 38. Pin Listing by Pin Name
Pin Name VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC Pin No. K7 K9 K23 K25 K27 K29 K31 L2 L4 L6 L8 L24 L26 L28 L30 M1 M3 M5 M7 M9 M23 M25 M27 M29 M31 N1 N3 N5 N7 N9 N23 N25 N27 N29 N31 P2 P4 P6 P8 Signal Buffer Type
Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other
Table 38. Pin Listing by Pin Name
Pin Name VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC Pin No. P24 P26 P28 P30 R1 R3 R5 R7 R9 R23 R25 R27 R29 R31 T2 T4 T6 T8 T24 T26 T28 T30 U1 U3 U5 U7 U9 U23 U25 U27 U29 U31 V2 V4 V6 V8 V24 V26 V28 Signal Buffer Type
Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other
Direction
Datasheet
Intel® Xeon Processor with 533MHz Front Side Bus Table 38. Pin Listing by Pin Name
Pin Name VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC Pin No. V30 W1 W25 W27 W29 W31 Y10 Y16 Y2 Y22 Y30 AA1 AA4 AA6 AA12 AA20 AA26 AA31 AB2 AB8 AB14 AB18 AB24 AB30 AC3 AC4 AC10 AC16 AC22 AC31 AD2 AD6 AD12 AD20 AD26 AD30 AE3 AE8 AE14 Signal Buffer Type
Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other
Table 38. Pin Listing by Pin Name
Pin Name VCC VCC VCCA VCCIOPLL VCCSENSE VID0 VID1 VID2 VID3 VID4 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Pin No. AE18 AE24 AB4 AD4 B27 F3 E3 D3 C3 B3 A5 A11 A21 A27 A29 A31 B2 B9 B15 B17 B23 B28 B30 C1 C7 C13 C19 C25 C29 C31 D2 D5 D11 D21 D27 D28 D30 E1 E9 Signal Buffer Type Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Input Input Output Output Output Output Output Output Direction
Direction
Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other
Datasheet
Intel® Xeon Processor with 533MHz Front Side Bus Table 38. Pin Listing by Pin Name
Pin Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Pin No. E15 E17 E23 E29 E31 F2 F7 F13 F19 F25 F28 F30 G1 G3 G5 G7 G9 G25 G27 G29 G31 H2 H4 H6 H8 H24 H26 H28 H30 J1 J3 J5 J7 J9 J23 J25 J27 J29 J31 Signal Buffer Type Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Direction
Table 38. Pin Listing by Pin Name
Pin Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Pin No. K2 K4 K6 K8 K24 K26 K28 K30 L1 L3 L5 L7 L9 L23 L25 L27 L29 L31 M2 M4 M6 M8 M24 M26 M28 M30 N2 N4 N6 N8 N24 N26 N28 N30 P1 P3 P5 P7 P9 Signal Buffer Type Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Direction
Datasheet
Intel® Xeon Processor with 533MHz Front Side Bus Table 38. Pin Listing by Pin Name
Pin Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Pin No. P23 P25 P27 P29 P31 R2 R4 R6 R8 R24 R26 R28 R30 T1 T3 T5 T7 T9 T23 T25 T27 T29 T31 U2 U4 U6 U8 U24 U26 U28 U30 V1 V3 V5 V7 V9 V23 V25 V27 Signal Buffer Type Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Direction
Table 38. Pin Listing by Pin Name
Pin Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Pin No. V29 V31 W2 W4 W24 W26 W28 W30 Y1 Y5 Y7 Y13 Y19 Y25 Y31 AA2 AA9 AA15 AA17 AA23 AA30 AB1 AB5 AB11 AB21 AB27 AB31 AC2 AC7 AC13 AC19 AC25 AC30 AD3 AD9 AD15 AD17 AD23 AD31 Signal Buffer Type Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Direction
Datasheet
Intel® Xeon Processor with 533MHz Front Side Bus Table 38. Pin Listing by Pin Name
Pin Name VSS VSS VSS VSS VSSA Pin No. AE2 AE11 AE21 AE27 AA5 Signal Buffer Type Power / Other Power / Other Power / Other Power / Other Power / Other Input Direction
Table 38. Pin Listing by Pin Name
Pin Name VSSSENSE Pin No. D26 Signal Buffer Type Power / Other Direction Output
1. In systems utilizing the Intel Xeon processor, the system designer must pull-up these signals to the processor VCC 2. Baseboard treating AA3 and AB3 as Reserved will operate correctly with a bus clock of 133 MHz.
Datasheet
Intel® Xeon Processor with 533MHz Front Side Bus
Pin Listing by Pin Number
Table 39. Pin Listing by Pin Number Table 39. Pin Listing by Pin Number
Pin No. A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 B1 Pin Name Reserved VCC SKTOCC# Reserved VSS A32# A33# VCC A26# A20# VSS A14# A10# VCC Reserved Reserved LOCK# VCC A7# A4# VSS A3# HITM# VCC TMS Reserved VSS VCC VSS VCC VSS Reserved Signal Buffer Type Reserved Power / Other Power / Other Reserved Power / Other Source Sync Source Sync Power / Other Source Sync Source Sync Power / Other Source Sync Source Sync Power / Other Reserved Reserved
Common Clk
Pin No. B2 B3 B4
Pin Name VSS VID4 VCC OTDEN VCC A31# A27# VSS A21# A22# VCC A13# A12# VSS A11# VSS A5# REQ0# VCC REQ1# REQ4# VSS LINT0 PROCHOT# VCC VCCSENSE VSS VCC VSS VCC VSS VCC VID3
Signal Buffer Type Power / Other Power / Other Power / Other Power / Other Power / Other Source Sync Source Sync Power / Other Source Sync Source Sync Power / Other Source Sync Source Sync Power / Other Source Sync Power / Other Source Sync
Common Clk
Direction
Direction Reserved
Output
Output Reserved
Input
Input / Output Input / Output
B8 B9 B10
Input / Output Input / Output
B11 B12 B13
Input / Output Input / Output
B14 B15 B16
Input / Output
Reserved Reserved Input / Output
B17 B18 B19 B20
Input / Output Input / Output
Power / Other Source Sync Source Sync Power / Other Source Sync
Common Clk
Power / Other
Common Clk Common Clk
Input / Output Input / Output
B21 B22 B23
Input / Output Input / Output
Power / Other Async GTL+ Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Output Output Input Output
Input / Output Input / Output
B24 B25 B26
Power / Other TAP Reserved Power / Other Power / Other Power / Other Power / Other Power / Other Reserved Reserved Input Reserved
B27 B28 B29 B30 B31 C1 C2 C3
Datasheet
Intel® Xeon Processor with 533MHz Front Side Bus
Table 39. Pin Listing by Pin Number
Pin No. C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 Pin Name VCC Reserved RSP# VSS A35# A34# VCC A30# A23# VSS A16# A15# VCC A8# A6# VSS REQ3# REQ2# VCC DEFER# TDI VSS IGNNE# SMI# VCC VSS VCC VSS VCC VSS VID2 STPCLK# VSS INIT# MCERR# VCC AP1# BR3# 1 VSS Signal Buffer Type Power / Other Reserved
Common Clk
Table 39. Pin Listing by Pin Number
Pin No. D12 Pin Name A29# A25# VCC A18# A17# A9# VCC ADS# BR0# VSS RS1# BPRI# VCC Reserved VSSSENSE VSS VSS VCC VSS VCC VSS VCC VID1 BPM5# IERR# VCC BPM2# BPM4# VSS AP0# BR2# VCC A28# A24# VSS COMP1 VSS DRDY#
Direction
Signal Buffer Type Source Sync Source Sync Power / Other Source Sync Source Sync Source Sync Power / Other Common Clk Common Clk Power / Other
Common Clk Common Clk
Direction Input / Output Input / Output
Reserved Input
D13 D14 D15
Power / Other Source Sync Source Sync Power / Other Source Sync Source Sync Power / Other Source Sync Source Sync Power / Other Source Sync Source Sync Power / Other
Common Clk Common Clk
Input / Output Input / Output Input / Output
Input / Output Input / Output
D16 D17 D18
Input / Output Input / Output
D19 D20
Input / Output Input / Output
D21 D22 D23
Input Input
Input / Output Input / Output
D24 D25 D26
Power / Other Reserved Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other
Common Clk Common Clk
Reserved Output
Input / Output Input / Output
D27 D28 D29
Power / Other
Common Clk
Input Input Input Input Input
D30 D31 E1 E2 E3 E4 E5 E6 E7 E8 E9
TAP Power / Other Async GTL+ Async GTL+ Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Async GTL+ Power / Other Async GTL+
Common Clk
Output Input / Output Output
Power / Other
Common Clk Common Clk
Input / Output Input / Output
Power / Other
Common Clk Common Clk
Output Input
E10 E11 E12
Input / Output Input
Power / Other Source Sync Source Sync Power / Other Power / Other Power / Other
Common Clk
Input Input / Output
E13 E14 E15
Input / Output Input / Output
Power / Other
Common Clk Common Clk
Input / Output Input
E16 E17 E18
Input
Power / Other
Input / Output
Datasheet
Intel® Xeon Processor with 533MHz Front Side Bus
Table 39. Pin Listing by Pin Number
Pin No. E19 E20 E21 E22 E23 E24 E25 E26 E27 E28 E29 E30 E31 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 Pin Name TRDY# VCC RS0# HIT# VSS TCK TDO VCC FERR# VCC VSS VCC VSS VCC VSS VID0 VCC BPM3# BPM0# VSS BPM1# GTLREF VCC BINIT# BR1# VSS ADSTB1# A19# VCC ADSTB0# DBSY# VSS BNR# RS2# VCC GTLREF TRST# VSS THERMTRIP # Signal Buffer Type
Common Clk
Table 39. Pin Listing by Pin Number
Pin No. F27 F28 Pin Name A20M# VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS LINT1 VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VCC VSS VCC VSS VCC VSS VCC Signal Buffer Type Async GTL+ Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Async GTL+ Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Input Direction Input
Direction Input
Power / Other
Common Clk Common Clk
Input Input / Output
F29 F30 F31
Power / Other TAP TAP Power / Other Async GTL+ Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other
Common Clk Common Clk
Input Output
Output
G4 G5 G6 G7 G8 G9 G23
Output
G24 G25
Input / Output Input / Output
G26 G27 G28
Power / Other
Common Clk
Input / Output Input
G29 G30 G31
Power / Other Power / Other
Common Clk Common Clk
Input / Output Input
Power / Other Source Sync Source Sync Power / Other Source Sync
Common Clk
Input / Output Input / Output
Power / Other
Common Clk Common Clk
Input / Output Input
H23 H24 H25
Power / Other Power / Other TAP Power / Other Async GTL+ Output Input Input
H26 H27 H28 H29
Datasheet
Intel® Xeon Processor with 533MHz Front Side Bus
Table 39. Pin Listing by Pin Number
Pin No. H30 H31 J1 J2 J3 J4 J5 J6 J7 J8 J9 J23 J24 J25 J26 J27 J28 J29 J30 J31 K1 K2 K3 K4 K5 K6 K7 K8 K9 K23 K24 K25 K26 K27 K28 K29 K30 K31 L1 Pin Name VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS Signal Buffer Type Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Direction
Table 39. Pin Listing by Pin Number
Pin No. L2 L3 L4 L5 L6 L7 L8 L9 L23 L24 L25 L26 L27 L28 L29 L30 L31 M1 M2 M3 M4 M5 M6 M7 M8 M9 M23 M24 M25 M26 M27 M28 M29 M30 M31 N1 N2 N3 N4 Pin Name VCC VSS VCC VSS VCC VSS VCC VSS VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VCC VSS VCC VSS VCC VSS VCC VSS VCC VCC VSS VCC VSS Signal Buffer Type Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Direction
Datasheet
Intel® Xeon Processor with 533MHz Front Side Bus
Table 39. Pin Listing by Pin Number
Pin No. N5 N6 N7 N8 N9 N23 N24 N25 N26 N27 N28 N29 N30 N31 P1 P2 P3 P4 P5 P6 P7 P8 P9 P23 P24 P25 P26 P27 P28 P29 P30 P31 R1 R2 R3 R4 R5 R6 R7 Pin Name VCC VSS VCC VSS VCC VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC Signal Buffer Type Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Direction
Table 39. Pin Listing by Pin Number
Pin No. R8 R9 R23 R24 R25 R26 R27 R28 R29 R30 R31 T1 T2 T3 T4 T5 T6 T7 T8 T9 T23 T24 T25 T26 T27 T28 T29 T30 T31 U1 U2 U3 U4 U5 U6 U7 U8 U9 U23 Pin Name VSS VCC VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VCC Signal Buffer Type Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Direction
Datasheet
Intel® Xeon Processor with 533MHz Front Side Bus
Table 39. Pin Listing by Pin Number
Pin No. U24 U25 U26 U27 U28 U29 U30 U31 V1 V2 V3 V4 V5 V6 V7 V8 V9 V23 V24 V25 V26 V27 V28 V29 V30 V31 W1 W2 W3 W4 W5 W6 W7 W8 W9 W23 W24 W25 W26 Pin Name VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS Reserved VSS BCLK1 TESTHI0 TESTHI1 TESTHI2 GTLREF GTLREF VSS VCC VSS Signal Buffer Type Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Reserved Power / Other Sys Bus Clk Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Input Input Input Input Input Input Reserved Direction
Table 39. Pin Listing by Pin Number
Pin No. W27 W28 W29 W30 W31 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 Y23 Y24 Y25 Y26 Y27 Y28 Y29 Y30 Y31 AA1 AA2 AA3 Pin Name VCC VSS VCC VSS VCC VSS VCC Reserved BCLK0 VSS TESTHI3 VSS RESET# D62# VCC DSTBP3# DSTBN3# VSS DSTBP2# DSTBN2# VCC DSTBP1# DSTBN1# VSS DSTBP0# DSTBN0# VCC D5# D2# VSS D0# THERMDA THERMDC NC VCC VSS VCC VSS BSEL0 Signal Buffer Type Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Reserved Sys Bus Clk Power / Other Power / Other Power / Other
Common Clk
Direction
Reserved Input
Input
Input Input / Output
Source Sync Power / Other Source Sync Source Sync Power / Other Source Sync Source Sync Power / Other Source Sync Source Sync Power / Other Source Sync Source Sync Power / Other Source Sync Source Sync Power / Other Source Sync Anode Pin Cathode Pin
Reserved
Input / Output Input / Output
Input / Output Output Output
Power / Other Power / Other Power / Other Power / Other Power / Other Output2
Datasheet
Intel® Xeon Processor with 533MHz Front Side Bus
Table 39. Pin Listing by Pin Number
Pin No. AA4 AA5 AA6 AA7 AA8 AA9 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AA24 AA25 AA26 AA27 AA28 AA29 AA30 AA31 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 Pin Name VCC VSSA VCC TESTHI4 D61# VSS D54# D53# VCC D48# D49# VSS D33# VSS D24# D15# VCC D11# D10# VSS D6# D3# VCC D1# NC NC VSS VCC VSS VCC BSEL1 VCCA VSS D63# PWRGOOD VCC DBI3# D55# VSS Signal Buffer Type Power / Other Power / Other Power / Other Power / Other Source Sync Power / Other Source Sync Source Sync Power / Other Source Sync Source Sync Power / Other Source Sync Power / Other Source Sync Source Sync Power / Other Source Sync Source Sync Power / Other Source Sync Source Sync Power / Other Source Sync
Reserved Reserved
Table 39. Pin Listing by Pin Number
Pin No. AB12 Pin Name D51# D52# VCC D37# D32# D31# VCC D14# D12# VSS D13# D9# VCC D8# D7# VSS NC NC VCC VSS Reserved VSS VCC VCC D60# D59# VSS D56# D47# VCC D43# D41# VSS D50# DP2# VCC D34# DP0# VSS Signal Buffer Type Source Sync Source Sync Power / Other Source Sync Source Sync Source Sync Power / Other Source Sync Source Sync Power / Other Source Sync Source Sync Power / Other Source Sync Source Sync Power / Other
Reserved Reserved
Direction
Direction Input / Output Input / Output
Input
AB13 AB14
Input Input / Output
AB15 AB16 AB17
Input / Output Input / Output Input / Output
Input / Output Input / Output
AB18 AB19 AB20
Input / Output Input / Output
AB21 AB22 AB23
Input / Output Input / Output
Input / Output
AB24 AB25
Input / Output Input / Output
AB26 AB27 AB28
Input / Output Input / Output
AB29 AB30 AB31
Power / Other Power / Other Reserved Power / Other Power / Other Power / Other Source Sync Source Sync Power / Other Source Sync Source Sync Power / Other Source Sync Source Sync Power / Other Source Sync
Common Clk
Input / Output Input / Output
AC1 AC2 AC3
Reserved
Input / Output
AC4 AC5 AC6 AC7 AC8 AC9 AC10
Input / Output Input / Output
Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Power / Other Source Sync Power / Other Power / Other Source Sync Source Sync Power / Other Input / Output Input / Output Input Output2 Input
Input / Output Input / Output
AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19
Input / Output Input / Output
Power / Other Source Sync
Common Clk
Input / Output Input / Output
Power / Other
Datasheet
Intel® Xeon Processor with 533MHz Front Side Bus
Table 39. Pin Listing by Pin Number
Pin No. AC20 AC21 AC22 AC23 AC24 AC25 AC26 AC27 AC28 AC29 AC30 AC31 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 Pin Name D25# D26# VCC D23# D20# VSS D17# DBI0# NC NC VSS VCC Reserved VCC VSS VCCIOPLL TESTHI5 VCC D57# D46# VSS D45# D40# VCC D38# D39# VSS COMP0 VSS D36# D30# VCC D29# DBI1# VSS D21# D18# VCC Signal Buffer Type Source Sync Source Sync Power / Other Source Sync Source Sync Power / Other Source Sync Source Sync
Reserved Reserved
Table 39. Pin Listing by Pin Number
Reserved Reserved
Direction Input / Output Input / Output
Direction Input / Output
Input / Output Input / Output
AD30 AD31 AE2
Power / Other Power / Other Power / Other Power / Other Ground Power / Other Async GTL+ Source Sync Power / Other Source Sync Source Sync Power / Other Source Sync Source Sync Power / Other Reserved Reserved
Common Clk
Input / Output Input / Output
AE3 AE4 AE5 AE6