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Intel® XeonProcessor with Front Side 3.06
Available 2.40, 2.66, 2.80, 3.06 Dual processing server/workstation support Binary compatible with applications running previous members Intel's IA32 microprocessor line Intel® NetBurstmicro-architecture Hyper-Threading Technology Hardware support multithreaded applications Front Side Bandwidth GB/second Rapid Execution Engine: Arithmetic Logic Units (ALUs) twice processor core frequency Hyper Pipelined Technology Advance Dynamic Execution Very deep out-of-order execution Enhanced branch prediction Level Execution Trace Cache stores micro-ops removes decoder latency from main execution loops Includes Level data cache
Advanced Transfer Cache (on-die, full speed Level cache) with 8-way associativity Error Correcting Code (ECC) Enables system support physical memory Streaming SIMD Extensions (SSE2) instructions double-precision floating point operations, media/video streaming, secure transactions Enhanced floating point multimedia unit enhanced video, audio, encryption, performance Power Management capabilities System Management mode Multiple low-power states Advanced System Management Features Thermal Monitor Machine Check Architecture (MCA)
Intel® XeonProcessor with Front Side designed high-performance dual-processor workstation server applications. Based Intel® NetBurstmicroarchitecture Hyper-Threading Technology, binary compatible with previous Intel Architecture (IA-32) processors. Intel Xeon processor with Front Side scalable processors multiprocessor system providing exceptional performance applications running advanced operating systems such Windows XP*, Windows* 2000, Linux*, UNIX*. Intel Xeon processor with Front Side delivers compute power unparalleled value flexibility powerful workstations, internet infrastructure, departmental server applications. Intel® NetBurstmicroarchitecture Hyper-Threading Technology deliver outstanding performance headroom peak internet server workloads, resulting faster response times, support more users, improved scalability.
Document Number: 252135-003 March 2003
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*Other names brands claimed property others.
Designers must rely absence characteristics features instructions marked "reserved" "undefined." Intel reserves these future definition shall have responsibility whatsoever conflicts incompatibilities arising from future changes them.
Intel® Xeonprocessor contain design defects errors known errata which cause product deviate from published specifications. Current characterized errata available request.MPEG international standard video compression/
decompression promoted ISO. Implementations MPEG CODECs, MPEG enabled platforms require licenses from various entities, including Intel Corporation. Contact your local Intel sales office your distributor obtain latest specifications before placing your product order. Copies documents which have ordering number referenced this document, other Intel literature obtained calling 1-800548-4725 visiting Intel's website http://www.intel.com. Intel, Pentium, Pentium Xeon, Intel Xeon Intel NetBurst trademark registered trademarks Intel Corporation subsidiaries United States other countries. Copyright Intel Corporation, 2002-2003
Intel® XeonProcessor with Front Side 3.06
Contents
Introduction. Terminology. 1.1.1 Processor Packaging Terminology. State Data References
Electrical Specifications. Front Side GTLREF Power Ground Pins Decoupling Guidelines 2.3.1 Decoupling 2.3.2 Front Side AGTL+ Decoupling Front Side Clock (BCLK[1:0]) Processor Clocking. 2.4.1 Clock Filter 2.5.1 Mixing Processors Voltage Identification 2.6.1 Mixing Processors Different Voltages Reserved Unused Pins. Front Side Signal Groups. Asynchronous GTL+ Signals. Maximum Ratings. Processor Specifications. AGTL+ Front Side Specifications Mechanical Specifications Processor Package Load Specifications Insertion Specifications Mass Specifications. Materials. Markings. Pin-Out Diagram.
2.10 2.11 2.12
Mechanical Specifications
Listing Signal Definitions Processor Assignments 4.1.1 Listing Name 4.1.2 Listing Number Signal Definitions.
Thermal Specifications Thermal Specifications Measurements Thermal Specifications 5.2.1 Processor Case Temperature Measurement
Features Power-On Configuration Options Clock Control Power States.
Intel® XeonProcessor with Front Side 3.06
6.2.1 Normal State-State 6.2.2 AutoHALT Powerdown State-State 6.2.3 Stop-Grant State-State 6.2.4 HALT/Grant Snoop State-State 6.2.5 Sleep State-State 6.2.6 Response During Power States Thermal Monitor 6.3.1 Thermal Diode.
Boxed Processor Specifications. Introduction Mechanical Specifications. 7.2.1 Boxed Processor Heatsink Dimensions 7.2.2 Boxed Processor Heatsink Weight. 7.2.3 Boxed Processor Retention Mechanism Heatsink Supports. Boxed Processor Requirements 7.3.1 Intel® XeonProcessor with Front Side 7.3.2 Rack Mount Server Solution Thermal Specifications. 7.4.1 Boxed Processor Cooling Requirements
Debug Tools Specifications. Logic Analyzer Interface (LAI). 8.1.1 Mechanical Considerations 8.1.2 Electrical Considerations.
Figures
Typical VCCIOPLL, VCCA VSSA Power Distribution Phase Lock Loop (PLL) Filter Requirements Intel® Xeonprocessor with Front Side VoltageCurrent Projections (VID 1.5V). Intel Xeon processor with Front Side Voltage-Current Projections (VID 1.525V). Electrical Test Circuit THERMTRIP# Timing FC-mPGA2 Processor Package Assembly Drawing. FC-mPGA Processor Package View: Component Placement Detail. Intel® XeonProcessor with Front Side FC-mPGA2 Package Drawing FC-mPGA2 Processor Package View: Component Height Keep-in FC-mPGA2 Processor Package Cross Section View: Side Component Keep-in FC-mPGA2 Processor Package: Detail Flatness Tilt Drawing. Processor Top-Side Markings Processor Bottom-Side Markings. Processor Diagram: View Processor Diagram: Bottom View Processor with Thermal Mechanical Components Exploded View Processor Thermal Design Power Electrical Projections 1.500V.
Intel® XeonProcessor with Front Side 3.06
Processor Thermal Design Power Electrical Projections 1.525V Thermal Measurement Point Processor TCASE. Stop Clock State Machine Mechanical Representation Boxed Processor Passive Heatsink. Boxed Processor Retention Mechanism Clip Boxed Processor Retention Mechanism that Ships with Processor. Multiple View Space Requirements Boxed Processor Connector Electrical Sequence. Processor Wind Tunnel General Dimensions Processor Wind Tunnel Detailed Dimensions Exploded View Thermal Solution. Assembled View Thermal Solution
Tables
Front Side Bus-to-Core Frequency Ratio Front Side Clock Frequency Select Truth Table BSEL[1:0]. Voltage Identification Definition Front Side Signal Groups. Processor Absolute Maximum Ratings Voltage Current Specifications Front Side Differential BCLK Specifications. AGTL+ Signal Group Specifications PWRGOOD Signal Group Specifications. Asynchronous GTL+ Signal Group Specifications BSEL[1:0] VID[4:0] Specifications. AGTL+ Voltage Definitions. Miscellaneous Signals Specifications Dimensions Intel® XeonProcessor with Front Side FC-mPGA2 Package. Package Dynamic Static Load Specifications Processor Mass. Processor Material Properties Listing Name Listing Number Signal Definitions. Processor Thermal Design Power. Power-On Configuration Option Pins Thermal Diode Parameters Thermal Diode Interface. Cable Connector Requirements. Power Signal Specifications.
Intel® XeonProcessor with Front Side 3.06
Revision History
Date Release November 2002 Revision -001 Initial Release Added 3.06 information. Edited definitions with current terminology. Added loadline figures chapter Edited figures Added notes signal definition tables symmetric agents. Edited Chapter Boxed Processor Specifications. Deleted Chapter Removed Section 2.13, 2.14 Added Table Description
February 2003
-002
March 2003
-003
Intel® XeonProcessor with Front Side 3.06
Introduction
Intel® XeonProcessor with Front Side based Intel® NetBurstmicro-architecture, which operates significantly higher clock speeds delivers performance levels that significantly higher than previous generations IA-32 processors. While based Intel NetBurst micro-architecture, maintains tradition compatibility with IA-32 software. Intel NetBurst micro-architecture features begin with innovative techniques that enhance processor execution such Hyper Pipelined Technology, Rapid Execution Engine, Advanced Dynamic Execution, enhanced Floating Point Multimedia unit, Streaming SIMD Extensions (SSE2). Hyper Pipelined Technology doubles pipeline depth processor, allowing processor reach much higher core frequencies. Rapid Execution Engine allows integer ALUs processor twice core frequency, which allows many integer instructions execute half internal core clock period. Advanced Dynamic Execution improves speculative execution branch prediction internal processor. floating point multi-media units have been improved making registers bits wide adding separate register data movement. Finally, SSE2 adds instructions doubleprecision floating point, SIMD integer, memory management improvements video/ multimedia processing, secure transactions, visual internet applications. Also part Intel NetBurst micro-architecture, front side caches Intel Xeon processor with Front Side provide tremendous throughput server workstation workloads. Front Side provides high-bandwidth pipeline system memory I/O. quad-pumped running Front Side clock making Gigabytes second (4,300 Megabytes second) data transfer rates possible. Execution Trace Cache level cache that stores approximately twelve thousand decoded microoperations, which removes decoder latency from main execution path increases performance. Advanced Transfer Cache on-die level cache running speed processor core providing increased bandwidth over previous micro-architectures. addition Intel NetBurst micro-architecture, Intel Xeon processor with Front Side includes groundbreaking technology called Hyper-Threading technology, which enables multi-threaded software execute tasks parallel within processor resulting more efficient, simultaneous processor resources. Server applications realize increased performance from Hyper-Threading technology today, while workstation applications expected benefit from Hyper-Threading technology future through software processor evolution. combination Intel NetBurst micro-architecture Hyper-Threading technology delivers outstanding performance, throughput, headroom peak software workloads resulting faster response times improved scalability. Intel Xeon processor with Front Side intended high performance workstation server systems with processors single bus. processor supports both uniand dual-processor designs. Intel Xeon with Front Side processors incorporate system managment devices (PIROM, Scratchpad EEPROM, thermal sensor), offer direct access pins on-die thermal diode. These output pins interface with thermal sensor device that placed baseboard. Intel Xeon processor with Front Side packaged 604-pin flip chip micro-PGA2 (FC-mPGA2) package, utilizes surface mount socket with pins. FC-mPGA2 package contains extra (located location AE30) compared INTmPGA package. This additional serves keying mechanism prevent FC-mPGA2 package from being installed 603-pin socket since processors FC-mPGA2 package
Intel® XeonProcessor with Front Side 3.06
only supported 604-pin socket. Since additional contact AE30 electrically inert, 604-pin socket will have solder ball this location. Mechanical components used attaching thermal solutions baseboard should have high degree commonality with thermal solution components enabled Intel Xeon processor Heatsinks retention mechanisms have been designed with manufacturability high priority. Hence, mechanical assembly completed from baseboard. Intel Xeon processor with Front Side uses scalable front side protocol referred "Front Side Bus" this document. processor front side utilizes splittransaction, deferred reply protocol similar that introduced Pentium® processor Front Side Bus, compatible with Pentium processor front side bus. Intel Xeon processor with Front Side compatible with Intel Xeon processor Front Side Bus. front side uses Source-Synchronous Transfer (SST) address data improve performance, transfers data four times clock data transfer rate). Along with data bus, address deliver addresses times clock referred `double-clocked' address bus. addition, Request Phase completes clock cycle. Working together, data address provide data bandwidth Gigabytes second. Finally, front side also introduces transactions that used deliver interrupts. Signals front side Assisted GTL+ (AGTL+) level voltages which fully described appropriate platform design guide (refer Section 1.3).
Terminology
symbol after signal name refers active signal, indicating signal asserted state when driven level. example, when RESET# low, reset been requested. Conversely, when high, nonmaskable interrupt occurred. case signals where name does imply active state describes part binary sequence (such address data), symbol implies that signal inverted. example, D[3:0] `HLHL' refers `A', D[3:0]# `LHLH' also refers High logic level, logic level). Front Side (FSB): electrical interface that connects processor chipset. Also referred processor system system bus. memory transactions well interrupt messages pass between processor chipset over FSB.
1.1.1
Processor Packaging Terminology
Commonly used terms explained here clarification:
604-pin socket 604-pin socket contains additional contact accept additional
keying Intel Xeon processor FC-mPGA2 packages location AE30. 604-pin socket will also accept processors with INT-mPGA package. Since additional contact AE30 electrically inert, 604-pin socket will have solder ball this location. Therefore, additional keying will require baseboard surfacemount pad. mPGA604 Socket Design Guidelines details regarding this socket.
Central Agent central agent host bridge processor typically known
chipset.
Intel® XeonProcessor with Front Side 3.06
Flip Chip Ball Grid Array (FC-BGA) Microprocessor packaging using "flip chip" design,
where processor attached substrate face-down better signal integrity, more efficient heat removal lower inductance.
FC-mPGA2 Packaging technology with processor mounted directly micro-Pin
Grid Array substrate with integrated heat spreader (IHS).
Front Side Front Side (FSB) electrical interface that connects processor
chipset. Also referred processor system system bus. memory transactions well interrupt messages pass between processor chipset over FSB.
Intel® Xeonprocessor with cache entire processor INT-mPGA
package, including processor core FC-BGA package, integrated heat spreader (IHS), interposer.
Intel® Xeonprocessor with Front Side entire processor FCmPGA2 package, including processor core FC-BGA package, integrated heat spreader (IHS), interposer.
Integrated Heat Spreader (IHS) surface used attach heatsink other thermal
solution processor.
Interposer structure which processor core package pins mounted. Original Equipment Manufacturer. Processor core processor's execution engine. timing signal integrity
specifications pads processor core.
Retention mechanism support components that mounted through baseboard
chassis provide mechanical retention processor heatsink assembly.
Symmetric Agent symmetric agent processor which shares same subsystem
memory array, runs same operating system another processor system. Systems using symmetric agents known Symmetric Multiprocessing (SMP) systems. Intel® Xeon(DP Dual Processor) processors should only used systems which have fewer symmetric agents.
State Data
data contained this document subject change. best information that Intel able provide publication date this document.
Intel® XeonProcessor with Front Side 3.06
References
reader this specification should also familiar with material concepts presented following documents:.
Document AP-485, Intel® Processor Identification CPUID Instruction IA-32 Intel Architecture Software Developer's Manual Volume Basic Architecture Volume Instruction Reference Volume III: System Programming Guide Intel XeonProcessor with 512-KB Cache Intel® E7505 Chipset Platform Design Guide Intel® XeonProcessor Thermal Design Guidelines -Pin Socket Design Guidelines mPGA604 Socket Design Guidelines Intel® XeonProcessor Specification Update CK00 Clock Synthesizer/Driver Design Guidelines DC-DC Converter Design Guidelines DC-DC Converter Design Guidelines Dual Intel® Xeon Guidelines
Intel Order Number1 241618 245470 245471 245472 http://developer.intel.com 298348 249672 11299 249678 249206 249205 298646 298644 249679
Processor Voltage Regulator Down (VRD) Design
ITP700 Debug Port Design Guide Intel® XeonProcessor with Front Side System Compatibility Guidelines Intel® XeonProcessor with Front Side Signal Integrity Models Intel® XeonProcessor with Front Side Mechanical Models ProE* Format IIntel® XeonProcessor with Front Side Mechanical Models IGES* Format Intel® XeonProcessor with 512-KB Cache Front Side Thermal Models (FloTherm* ICEPAK* format) Intel® XeonProcessor with Front Side Core Boundary Scan Descriptor Language (BSDL) Model Wired Management Design Guide Boxed Integration Notes
http://developer.intel.com http://developer.intel.com http://developer.intel.com http://developer.intel.com http://developer.intel.com http://developer.intel.com http://support.intel.com/ support/processors/xeon
NOTES:
Contact your Intel representative latest revision documents without order numbers.
Intel® XeonProcessor with Front Side 3.06
Electrical Specifications
Front Side GTLREF
Most Intel® XeonProcessor with 533MHz Front Side signals Assisted Gunning Transceiver Logic (AGTL+) signaling technology. This signaling technology provides improved noise margins reduced ringing through voltage swings controlled edge rates. processor termination voltage level VCC, operating voltage processor core. termination voltage that determined processor core allows better voltage scaling processor front side bus. Because speed improvements data address busses, signal integrity platform design methods become more critical than with previous processor families. Front side design guidelines detailed appropriate platform design guide (refer Section 1.3). AGTL+ inputs require reference voltage (GTLREF) which used receivers determine signal logical logical GTLREF must generated baseboard (See Table GTLREF specifications). Termination resistors provided processor silicon terminated core voltage (VCC). on-die termination resistors selectable feature enabled disabled ODTEN pin. agents, on-die termination enabled control reflections transmission line. middle agents, on-die termination must disabled. Intel chipsets will also provide on-die termination, thus eliminating need terminate baseboard most AGTL+ signals. Refer Section 2.12 details ODTEN resistor termination requirements. Note: Some AGTL+ signals include on-die termination must terminated baseboard. Table details regarding these signals. AGTL+ signals depend incident wave switching. Therefore timing calculations AGTL+ signals based flight time opposed capacitive deratings. Analog signal simulation front side bus, including trace lengths, highly recommended when designing system. Please refer http://developer.intel.com obtain Intel® XeonProcessor with Front Side Signal Integrity Models.
Power Ground Pins
clean on-chip power distribution, Intel Xeon processor with Front Side (power) (ground) inputs. pins must connected system power plane, while pins must connected system ground plane. processor pins must supplied voltage determined processor (Voltage pins.
Decoupling Guidelines
large number transistors high internal clock speeds, processor capable generating large average current swings between full power states. This cause voltages power planes below their minimum values bulk decoupling adequate. Larger bulk storage (CBULK), such electrolytic capacitors, supply current during longer lasting changes current demand component, such coming idle condition. Similarly, they storage well current when entering idle condition from running condition.
Intel® XeonProcessor with Front Side 3.06
Care must taken baseboard design ensure that voltage provided processor remains within specifications listed Table Failure result timing violations reduced lifetime component. further information guidelines, refer appropriate platform design guidelines.
2.3.1
Decoupling
Regulator solutions need provide bulk capacitance with Effective Series Resistance (ESR) baseboard designer must ensure interconnect resistance from regulator pins) 604-pin socket. Bulk decoupling provided voltage regulation module (VRM) meet help meet large current swing requirements. remaining decoupling provided baseboard. power delivery path must capable delivering enough current while maintaining required tolerances (defined Table further information regarding power delivery, decoupling, layout guidelines, refer appropriate platform design guidelines.
2.3.2
Front Side AGTL+ Decoupling
Intel® Xeonprocessor with 533MHz Front Side integrates signal termination well part required high frequency decoupling capacitance processor package. However, additional high frequency capacitance must added baseboard properly decouple return currents from front side bus. Bulk decoupling must also provided baseboard proper AGTL+ operation. Decoupling guidelines described appropriate platform design guidelines.
Front Side Clock (BCLK[1:0]) Processor Clocking
BCLK[1:0] directly controls front side interface speed well core frequency processor. previous generation processors, processor core frequency multiple BCLK[1:0] frequency. maximum processor ratio multiplier will during manufacturing. default setting will equal maximum speed processor. BCLK[1:0] inputs directly control operating speed front side interface. processor core frequency configured during reset using values stored internally during manufacturing. stored value sets highest fraction which particular processor operate. Clock multiplying within processor provided internal PLL, which requires constant frequency BCLK[1:0] input with exceptions spread spectrum clocking. Processor specifications BCLK[1:0] inputs provided Table Table respectively. These specifications must while also meeting signal integrity requirements outlined Chapter 3.0. processor utilizes differential clock. Details regarding BCLK[1:0] driver specifications provided CK408 Clock Synthesizer/Driver Design Guidelines. Table contains supported fraction ratios their corresponding core frequencies.
Intel® XeonProcessor with Front Side 3.06
Intel® XeonProcessor with Front Side
Table
Front Side Bus-to-Core Frequency Ratio
Front Side Bus-to-Core Frequency Ratio 1/15 1/18 1/20 1/21 1/23 Core Frequency 2.40 2.66 2.80 3.06
2.4.1
Clock
front side frequency maximum supported individual processor. BSEL[1:0] outputs used select front side frequency. Table defines possible combinations signals frequency associated with each combination. frequency determined processor(s), chipset, clock synthesizer. front side agents must operate same frequency. Individual processors will only operate their specified front side clock frequency, (100 present generation processors). Intel® Xeon processor with Front Side designed baseboard with clock. these baseboards, BSEL[0:1] considered `reserved' processor socket.
Table Front Side Clock Frequency Select Truth Table BSEL[1:0]
BSEL1 BSEL0 Clock Frequency Reserved Reserved
Filter
VCCA VCCIOPLL power sources required processor clock generator. This requirement identical that Intel Xeon processor with 512-KB cache. Since these PLLs analog nature, they require quiet power supplies minimum jitter. Jitter detrimental system: degrades external timings well internal core timings (i.e. maximum frequency). prevent this degradation, these supplies must pass filtered from VCC. typical filter topology shown Figure low-pass requirements, with input output measured across capacitor Figure follows:
gain pass band attenuation pass band (see drop next requirements) attenuation from attenuation from core frequency
Datasheet
filter requirements illustrated Figure recommendations implementing filter refer appropriate platform design guidelines.
Figure Typical VCCIOPLL, VCCA VSSA Power Distribution
Trace 0.02 R-Trace
Socket
L1/L2
Processor interposer "pin" R-Socket VCCA R-Socket VSSA Processor
Baseboard that connects filter plane
R-Trace L1/L2
R-Socket
VCCIOPLL
Figure Phase Lock Loop (PLL) Filter Requirements
-0.5 forbidden zone
forbidden zone
passband
fpeak
fcore
high frequency band
Intel® XeonProcessor with Front Side 3.06
NOTES: Diagram scale. specifications frequencies beyond fcore (core frequency). fpeak, existent, should less than 0.05 MHz.
2.5.1
Mixing Processors
Intel only supports those processor combinations operating with same front side frequency, core frequency, settings, cache sizes. operating systems support multiple processors with mixed frequencies. Intel does support validate operation processors with different cache sizes. Mixing processors different steppings same model CPUID instruction) supported, outlined Intel® XeonProcessor Specification Update. Additional details provided AP-485, Intel Processor Identification CPUID Instruction application note. Intel Xeon processor with Front Side does sample pins IGNNE#, LINT[0]/INTR, LINT[1]/NMI, A20M# establish core front side ratio. Rather, processor runs tested frequency initial power-on. processor needs lower core frequency, must done when higher speed processor added system that contains lower frequency processor, system BIOS able effect change core front side ratio.
Voltage Identification
specification processor defined this datasheet, supported power delivery solutions designed according Dual Intel® Xeon Processor Voltage Regulator Down (VRD) Design Guidelines, DC-DC Converter Design Guidelines, DC-DC Converter Design Guidelines. minimum voltage provided Table varies with processor frequency. This allows processors running higher frequency have relaxed minimum voltage specification. specifications have been such that voltage regulator design work with supported processor frequencies. Note that pins will drive valid correct logic levels when Intel® Xeonprocessor with Front Side provided with valid voltage applied SM_VCC pins. VID_VCC must correct stable prior enabling output that supplies VCC. Similarly, output must disabled before VID_VCC becomes invalid. Refer Figure details. processor uses five voltage identification pins, VID[4:0], support automatic selection processor voltages. Table specifies voltage level corresponding state VID[4:0]. this table refers high voltage refers voltage level. processor socket empty (VID[4:0] 11111), cannot supply voltage that requested, must disable voltage output. further details, Dual Intel® XeonProcessor Voltage Regulator Down (VRD) Design Guidelines, DC-DC Converter Design Guidelines DC-DC Converter Design Guidelines.
Intel® XeonProcessor with Front Side 3.06
Table Voltage Identification Definition
Processor Pins VID4 VID3 VID2 VID1 VID0 VCC_VID output 1.100 1.125 1.150 1.175 1.200 1.225 1.250 1.275 1.300 1.325 1.350 1.375 1.400 1.425 1.450 1.475 1.500 1.525 1.550 1.575 1.600 1.625 1.650 1.675 1.700 1.725 1.750 1.775 1.800 1.825 1.850
2.6.1
Mixing Processors Different Voltages
Mixing processors operating with different settings (voltages) supported will validated Intel.
Intel® XeonProcessor with Front Side 3.06
Reserved Unused Pins
Reserved pins must remain unconnected system baseboard. Connection these pins VCC, VSS, other signal (including another) result component malfunction incompatibility with future processors. Chapter listing processor location Reserved pins. reliable operation, unused inputs bidirectional signals should always connected appropriate signal level. system-level design, on-die termination been included processor allow signal termination accomplished processor silicon. Most unused AGTL+ inputs should left connects, AGTL+ termination provided processor silicon. However, Table details AGTL+ signals that include on-die termination. Unused active high inputs should connected through resistor ground (VSS). Unused outputs left unconnected, however this interfere with some functions, complicate debug probing, prevent boundary scan testing. resistor must used when tying bidirectional signals power ground. When tying signal power ground, resistor will also allow system testability. unused AGTL+ input signals, pull-up resistors same value on-die termination resistors (RTT). Table TAP, Asynchronous GTL+ inputs, Asynchronous GTL+ outputs include on-die termination. Inputs used outputs must terminated baseboard. Unused outputs terminated baseboard left unconnected. Note that leaving unused outputs unterminated interfere with some functions, complicate debug probing, prevent boundary scan testing. Signal termination these signal types discussed ITP700 Debug Port Design Guide. TESTHI[6:0] pins should individually connected pull-up resistor which matches trace impedance within TESTHI[3:0] TESTHI[6:5] tied together pulled with single resistor desired. However, utilization boundary scan test will functional these pins connected together. TESTHI4 must always pulled independently from other TESTHI pins. optimum noise margin, pull-up resistor values used TESTHI[6:0] pins should have resistance value within percent impedance baseboard transmission line traces. example, trace impedance then pull-up resistor value between should used. TESTHI[6:0] termination recommendations provided Intel® XeonProcessor Datasheet also suitable Intel® Xeonprocessor with Front Side Bus. However, Intel recommends designs designs undergoing design updates follow trace impedance matching termination guidelines outlined this section.
Front Side Signal Groups
order simplify following discussion, front side signals have been combined into groups buffer type. AGTL+ input signals have differential input buffers, which GTLREF reference level. this document, term "AGTL+ Input" refers AGTL+ input group well AGTL+ group when receiving. Similarly, "AGTL+ Output" refers AGTL+ output group well AGTL+ group when driving. With implementation source synchronous data comes need specify sets timing parameters. common clock signals whose timings specified with respect rising edge BCLK0 (ADS#, HIT#, HITM#, etc.) second source synchronous signals which relative their respective strobe lines (data address) well
Intel® XeonProcessor with Front Side 3.06
rising edge BCLK0. Asynchronous signals still present (A20M#, IGNNE#, etc.) become active time during clock cycle. Table identifies which signals common clock, source synchronous asynchronous.
Table Front Side Signal Groups
Signal Group AGTL+ Common Clock Input Type Synchronous BCLK[1:0] Signals BPRI#, BR[3:1]#3,4, DEFER#, RESET#4, RS[2:0]#, RSP#, TRDY# ADS#, AP[1:0]#, BINIT#7, BNR#7, BPM[5:0]#2, BR0#2, DBSY#, DP[3:0]#, DRDY#, HIT#7, HITM#7, LOCK#, MCERR#7
AGTL+ Common Clock
Synchronous BCLK[1:0]
Signals
REQ[4:0]#,A[16:3]#
Associated Strobe
ADSTB0# ADSTB1# DSTBP0#, DSTBN0# DSTBP1#, DSTBN1# DSTBP2#, DSTBN2# DSTBP3#, DSTBN3#
AGTL+ Source Synchronous
Synchronous assoc. strobe
A[35:17]#
D[15:0]#, DBI0# D[31:16]#, DBI1# D[47:32]#, DBI2# D[63:48]#, DBI3#
AGTL+ Strobes Asynchronous GTL+ Input Asynchronous GTL+ Output Front Side Clock Input Output
Synchronous BCLK[1:0] Asynchronous Asynchronous Clock Synchronous Synchronous
ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]# A20M#5, IGNNE# INIT#6, LINT0/INTR5, LINT1/NMI5, SLP#, STPCLK# FERR#, IERR#, THERMTRIP#, PROCHOT# BCLK1, BCLK0 TCK, TDI, TMS, TRST# BSEL[1:0], COMP[1:0], GTLREF, ODTEN, Reserved, SKTOCC#, TESTHI[6:0],VID[4:0], VCC, VID_VCC8, VCCA, VCCIOPLL, VSSA, VSS, VCCSENSE, VSSSENSE, PWRGOOD
Power/Other
Power/Other
NOTES: Refer Section signal descriptions. These signal groups terminated processor. Refer ITP700 Debug Port Design Guide corresponding Design Guide termination requirements further details. Intel® Xeonprocessor with 533MHz Front Side utilizes only BR0# BR1#. BR2# BR3# driven processor must terminated VCC. additional details regarding BR[3:0]# signals, Section Section appropriate Platform Design Guidelines. These signals have on-die termination. Refer corresponding Platform Design Guidelines termination requirements. Note that Reset initialization function these pins software function Intel® Xeonprocessor with 533MHz Front Side Bus. value these pins during active-to-inactive edge RESET# determine processor configuration options. Section details. These signals driven simultaneously multiple agents (wired-or). VID_Vcc required correct logic operation Intel® Xeonprocessor with Front Side Bus. Refer Figure details.
Intel® XeonProcessor with Front Side 3.06
Asynchronous GTL+ Signals
Intel® XeonProcessor with Front Side does utilize CMOS voltage levels signals that connect processor silicon. result, legacy input signals such A20M#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, SLP#, STPCLK# utilize GTL+ input buffers. Legacy output FERR#/PBE# other non-AGTL+ signals IERR#, THERMTRIP# PROCHOT# utilize GTL+ output buffers. these asynchronous GTL+ signals follow same requirements AGTL+ signals, however outputs driven high (during logical 0to-1 transition) processor (the major difference between GTL+ AGTL+). Asynchronous GTL+ signals have setup hold time specifications relation BCLK[1:0]. However, asynchronous GTL+ signals required asserted least BCLKs order processor recognize them. Table specifications asynchronous GTL+ signal groups.
2.10
Maximum Ratings
Table lists processor's maximum environmental stress ratings. Functional operation absolute maximum minimum neither implied guaranteed. processor should receive clock while subjected these conditions. Functional operating parameters listed tables. Extended exposure maximum ratings affect device reliability. Furthermore, although processor contains protective circuitry resist damage from static electric discharge, should always take precautions avoid high static voltages electric fields.
Table Processor Absolute Maximum Ratings
Symbol TSTORAGE VinAGTL+ VinGTL+ IVID Parameter Processor storage temperature processor supply voltage with respect AGTL+ buffer input voltage with respect Async GTL+ buffer input voltage with respect current -0.3 -0.1 -0.1 1.75 1.75 1.75 Unit Notes
This rating applies processor. Contact Intel storage requirements excess year.
2.11
Processor Specifications
processor specifications this section defined processor core (pads) unless noted otherwise. Section processor listings Section signal definitions. voltage current specifications versions processor detailed Table platform planning refer Figure Notice that graphs include Thermal Design Power (TDP) associated with maximum current levels. specifications AGTL+ signals listed Table
Intel® XeonProcessor with Front Side 3.06
Table through Table list processor specifications valid only while meeting specifications case temperature (TCASE specified Chapter 6.0), clock frequency, input voltages. Care should taken read notes associated with each parameter.
Intel® XeonProcessor with Front Side 3.06
Table Voltage Current Specifications
Symbol Parameter Core Freq Unit Notes1
Intel Xeon processor with Front Side 2.40 2.66 2.80 3.06 SMBus supply voltage
1.353 1.344 1.334 1.331 1.352 Refer Figure
1.461 1.456 1.452 1.450 1.467
1.525
5,11, 5,11, 5,11, 5,11, 5,11,
SM_VCC
freq.
3.135
3.30
3.465
Intel Xeon processor with Front Side 2.40 2.66 2.80 3.06 power pins GTLREF pins Stop-Grant/Sleep active
45.4 51.4 57.1 59.1 69.1
ICC_PLL ICC_GTLREF ISGnt/ISLP ITCC
freq freq freq freq
18.6
NOTES: Unless otherwise noted, specifications this table apply processors. These voltages targets only. variable voltage source should exist systems event that different voltage required. Section Table more information. voltage specification requirements measured across vias platform VCC_SENSE VSS_SENSE pins close socket with bandwidth oscilloscope, maximum probe capacitance, milliohm minimum impedance. maximum length ground wire probe should less than Ensure external noise from system coupled scope probe. processor should subjected static level that exceeds voltage current load-line given current loading shown figure VID=1.500V figure VID=1.525V). Moreover, should never exceed Vcc_VID. Failure adhere this specification shorten processor lifetime. Vcc_max Vcc_min defined load Icc_max. Icc_max defined Vcc_max current specified also AutoHALT State. maximum instantaneous current processor will draw while thermal control circuit active indicated assertion PROCHOT#. VID_VCC required correct operation processor logic. Refer Figure details. This specification applies power pins VCCA VCCIOPLL. Section details. This parameter based design characterization tested 10.This specification applies each GTLREF pin. loadlines specify voltage limits measured VCC_SENSE VSS_SENSE pins. Voltage regulation feedback voltage regulator circuits must taken from processor pins. 12.Adherence this loadline specification required ensure reliable processor operation.
Intel® XeonProcessor with Front Side 3.06
Figure Intel® Xeonprocessor with Front Side Voltage-Current Projections (VID 1.5V)
1.51 Maximum Processor Voltage (VDC) 1.50 1.49 1.48 1.47 1.46 1.45 1.44 Processor Current
Intel® XeonProcessor with Front Side 3.06
Figure Intel Xeon processor with Front Side Voltage-Current Projections (VID 1.525V)
Table Front Side Differential BCLK Specifications
Symbol VCROSS(abs) VCROSS(rel) VCROSS VRBM VParameter Input Voltage Input High Voltage Absolute Crossing Point Relative Crossing Point Range Crossing Points Overshoot Undershoot Ringback Margin Threshold Margin NOTES:. -.150 0.660 0.250 0.250 0.5(VHavg 0.710) -0.300 0.200 Vcross 0.100 0.000 0.710 0.850 0.550 0.550 0.5(VHavg 0.710) 0.140 Vcross 0.100 Unit Figure 2,3,8,9 2,10 Notes
Intel® XeonProcessor with Front Side 3.06
Unless otherwise noted, specifications this table apply processor frequencies. Crossing voltage defined instantaneous voltage value when rising edge BCLK0 equals falling edge BCLK1. VHavg statistical average measured oscilloscope. Overshoot defined absolute value maximum voltage. Undershoot defined absolute value minimum voltage. Ringback Margin defined absolute voltage difference between maximum Rising Edge Ringback maximum Falling Edge Ringback. Threshold Region defined region entered around crossing point voltage which differential receiver switches. includes input threshold hysteresis. crossing point must meet absolute relative crossing point specifications simultaneously. VHavg measured directly using "Vtop" Agilent* scopes "High" Tektronix* scopes. 10.VCROSS defined total variation crossing voltages defined note
Table AGTL+ Signal Group Specifications
Symbol Parameter Input High Voltage Input Voltage Output High Voltage Output Current Leakage High Leakage Buffer Resistance 1.10 GTLREF 0.90 GTLREF (0.50 RTT_min RON_min) Unit Notes
NOTES: Unless otherwise noted, specifications this table apply processor frequencies cache sizes. defined minimum voltage level receiving agent that will interpreted logical high value. defined maximum voltage level receiving agent that will interpreted logical value. experience excursions above However, input signal drivers must comply with signal quality specifications Chapter 3.0. Refer Intel®XeonProcessor with Front Side Signal Integrity Models characteristics. referred these specifications refers instantaneous VOL_MAX 0.450 guaranteed when driving into test load indicated Figure with enabled. Leakage with held Leakage with held VCC.
Table PWRGOOD Signal Group Specifications
Symbol VHYS VTVOH Parameter Input Hysteresis input high threshold voltage input high threshold voltage Output High Voltage Output Current Leakage High Leakage Unit Notes
(VCC VHYS_MIN) (VCC VHYS_MAX) (VCC VHYS_MAX) (VCC VHYS_MIN)
Intel® XeonProcessor with Front Side 3.06
Buffer Resistance
8.75
13.75
NOTES:. Unless otherwise noted, specifications this table apply processor frequencies cache sizes. outputs open drain signal group must meet system signal quality specification Chapter 3.0. Refer Intel® XeonProcessor with Front Side Signal Integrity Models characteristics. referred these specifications refers instantaneous VCC. maximum output current based maximum current handling capability buffer specified into test load. VOL_MAX 0.300V guaranteed when driving test load. VHYS represents amount hysteresis, nominally centered about 0.5*VCC, inputs. Leakage with held 10.Leakage with held VCC.
Table Asynchronous GTL+ Signal Group Specifications
Symbol Parameter Input High Voltage Input Voltage Output High Voltage Output Current Leakage High Leakage Buffer Resistance 1.10 GTLREF 0.90 GTLREF Unit Notes1,
NOTES: Unless otherwise noted, specifications this table apply processor frequencies cache sizes. outputs open drain defined minimum voltage level receiving agent that will interpreted logical high value. defined maximum voltage level receiving agent that will interpreted logical value. experience excursions above VCC. However, input signal drivers must comply with signal quality specifications Chapter 3.0. Refer Intel®XeonTMProcessor with Front Side Signal Integrity Models characteristics. referred these specifications refers instantaneous VCC. maximum output current based maximum current handling capability buffer specified into test load. VOL_MAX 0.450 guaranteed when driving into test load indicated Figure with enabled. Leakage with held Leakage with held VCC. NOTES: Unless otherwise noted, specifications this table apply processor frequencies cache sizes. These parameters based design characterization tested.
Table BSEL[1:0] VID[4:0] Specifications
Notes
Symbol (BSEL) (VID)
Parameter Buffer Resistance Buffer Resistance Leakage
14.3 12.8
Unit
Intel® XeonProcessor with Front Side 3.06
Unless otherwise noted, specifications this table apply processor frequencies. These parameters tested based design simulations. Leakage with held 2.50V.
2.12
AGTL+ Front Side Specifications
Routing topologies dependent number processors supported chipset used design. Please refer appropriate platform design guidelines. most cases, termination resistors required these integrated into processor. Table details which AGTL+ signals include on-die termination.The termination resistors enabled disabled through ODTEN pin. enable termination, this should pulled through resistor disable termination, this should pulled down through resistor. optimum noise margin, pull-up pull-down resistor values used ODTEN should have resistance value within percent impedance baseboard transmission line traces. example, trace impedance then value between should used. processor's on-die termination must enabled agent only. Please refer Table termination resistor values. more details platform design appropriate platform design guidelines. Valid high levels determined input buffers comparing with reference voltage called GTLREF. Table lists GTLREF specifications. AGTL+ reference voltage (GTLREF) should generated baseboard using high precision voltage divider circuits. important that baseboard impedance held specified tolerance, that intrinsic trace capacitance AGTL+ signal group traces known well-controlled. more details platform design appropriate platform design guidelines.
Table AGTL+ Voltage Definitions
Symbol GTLREF GTLREF
Design
Parameter Reference Voltage Reference Voltage Termination Resistance Termination Resistance COMP Resistance COMP Resistance
0.63*VCC 42.77 49.55
0.63*VCC 43.2
0.63*VCC 43.63 50.45
Units
Notes
Design COMP[1:0] COMP[1:0] Design
NOTES: Unless otherwise noted, specifications this table apply processor frequencies. tolerances this specification have been stated generically enable system designer calculate minimum values across range VCC. GTLREF generated from baseboard voltage divider percent resistors. Refer appropriate platform design guidelines implementation details. on-die termination resistance measured from AGTL+ output driver. Refer Intel® XeonProcessor with 533MHz Front Side Signal Integrity Models characteristics. COMP resistors pull downs provided baseboard with tolerance. appropriate platform design guidelines implementation details. referred these specifications refers instantaneous COMP resistance value varies platform. Refer appropriate platform design guideline recommended COMP resistance value.
Intel® XeonProcessor with Front Side 3.06
values COMP noted `New Designs' apply designs that optimized Intel® Xeonprocessor with 533MHz Front Side Bus. Refer appropriate platform design guideline recommended COMP resistance value. This specification applies Intel® XeonTMprocessor with 533MHz Front Side when implemented platforms that include forward compatibility with future processors.
Table Miscellaneous Signals Specifications
Parameter T39: THERMTRIP# Removal Unit Figure Notes
Figure Electrical Test Circuit
ohms, d=420mils, So=169ps/in
Rload ohms 2.4nH 1.2pF Timings specified pad.
Figure THERMTRIP# Timing
THERMTRIP# Power Down Sequence
THERMTRIP#
seconds Note: THERMTRIP# undefined when RESET active
Intel® XeonProcessor with Front Side 3.06
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Intel® XeonProcessor with Front Side 3.06
Mechanical Specifications
Intel® XeonProcessor with Front Side uses Flip Chip Micro-Pin Grid Array (FC-mPGA) package containing processor covered integrated heat spreader (IHS) Mechanical specifications processor given this section. Section terminology definitions. Figure provides basic assembly drawing includes components which make entire processor. Package dimensions provided Table Intel® Xeonprocessor with Front Side utilizes surface mount 604-pin zeroinsertion force (ZIF) socket installation into baseboard. 604-Pin Socket Design Guidelines further details processor socket. Figure through Figure following notes apply: Unless otherwise specified, following drawings dimensioned millimeters. dimensions tested, guaranteed design characterization. Figures drawings labelled "Reference Dimensions" provided informational purposes only. Reference Dimensions extracted from mechanical design database nominal dimensions with tolerance information applied. Reference Dimensions checked part processor manufacturing process. Unless noted such, dimensions parentheses without tolerances Reference Dimensions. Drawings scale. Figure FC-mPGA2 Processor Package Assembly Drawing
Note:
applies Intel Xeon processor FC-mPGA2 package. Integrated Heat Spreader (IHS) Processor FC-mPGA2 package Land side Capacitors Package
Intel® XeonProcessor with Front Side 3.06
Figure
Mechanical Specifications
FC-mPGA Processor Package View: Component Placement Detail
Intel® XeonProcessor with Front Side 3.06
Figure
Intel® XeonProcessor with Front Side FC-mPGA2 Package Drawing
Intel® XeonProcessor with Front Side 3.06
Table Dimensions Intel® XeonProcessor with Front Side FC-mPGA2 Package
Symbol Milimeters Nominal 42.40 42.50 30.90 31.00 3.42 3.60 1.95 2.03 18.80 19.05 37.85 38.10 6.35 12.70 14.99 15.24 30.23 30.48 6.35 1.27 12.70 0.26 0.31 Notes 42.60 31.10 3.78 2.11 19.30 38.35 Nominal Component Keepin Nominal Component Keepin 15.49 30.73 Nominal Component Keepin Nominal 0.36 0.25 Diameter
Figure details keep-in zone components mounted side processor interposer. components include EEPROM, thermal sensor, resistors capacitors. Figure FC-mPGA2 Processor Package View: Component Height Keep-in
1.61
COMPONENT KEEPOUT CROSS HATCHED AREA
2.27 ALLOWABLE COMPONENT HEIGHT 15.5
15.5
1.61
Intel® XeonProcessor with Front Side 3.06
Figure details keep-in specification pin-side components. processor contain side capacitors mounted processor package. These capacitors will exposed within opening interposer cavity. Figure FC-mPGA2 Processor Package Cross Section View: Side Component Keep-in
FC-mPGA2P Component Keepin 12.7 Component Keepin
Intel® XeonProcessor with Front Side 3.06
Figure
FC-mPGA2 Processor Package: Detail
Kovar with plating micrometers over micrometer 0.254 Diametric true position, pin.
Intel® XeonProcessor with Front Side 3.06
Figure details flatness tilt specifications Intel Xeon processor with Front Side Bus, respectively. Tilt measured with reference datum bottom processor interposer. Figure Flatness Tilt Drawing
0.080
Processor Package Load Specifications
Table provides dynamic static load specifications processor IHS. These mechanical load limits should exceeded during heat sink assembly, mechanical stress testing, standard drop shipping conditions. heat sink attach solutions must induce continuous stress onto processor with exception uniform load maintain heat sink-toprocessor thermal interface. recommended portion processor interposer mechanical reference load bearing surface thermal solutions.
Table Package Dynamic Static Load Specifications
Parameter Static Dynamic input (AF) Unit Unit
NOTES: This specification applies uniform compressed load. This maximum static force that applied heatsink clip maintain heatsink processor interface. These parameters based design characterization tested. Dynamic loading specifications defined assuming maximum duration 11ms. heatsink weight assumed pound. Shock input system during shock testing assumed G's. amplification factor.
Intel® XeonProcessor with Front Side 3.06
Insertion Specifications
processor inserted removed times from 604-pin socket meeting mPGA604 Socket Design Guidelines document. Note that this specification based design characterization tested.
Mass Specifications
Table specifies processors mass. This includes components which make entire processor product.
Table Processor Mass
Processor Intel® XeonProcessor with Front Side Mass (grams)
Materials
processor assembled from several components. basic material properties described Table
Table Processor Material Properties
Component Integrated Heat Spreader FC-BGA Interposer Interposer pins Material Nickel plated copper Resin Kovar with Gold over nickel
Intel® XeonProcessor with Front Side 3.06
Markings
following section details processor top-side laser markings. provided identification processor. Figure Processor Top-Side Markings
Dynamic Laser Mark Area with Matrix
Group Line1 Group Line2
Group Line1 Group Line2
Matrix encodes ATPO number Serial number
NOTE:
Character size laser markings height 0.050" (1.27mm), width 0.032" (0.81mm). characters will upper case. Figure Processor Bottom-Side Markings
Intel® XeonProcessor with Front Side 3.06
Pin-Out Diagram
This section provides view processor grid. Figure Figure detail coordinates processor pins.
Figure
Processor Diagram: View
COMMON CLOCK
ADDRESS
COMMON CLOCK
Async JTAG
Vcc/Vss
Vcc/Vss
CLOCKS
Signal Power Ground
DATA
SM_VCC GTLREF Reserved
SMBus
Mechanical
Intel® XeonProcessor with Front Side 3.06
Figure
Processor Diagram: Bottom View
Async JTAG
COMMON CLOCK
ADDRESS
COMMON CLOCK
SMBus
DATA
Signal Power Ground SM_VCC GTLREF Reserved
CLOCKS
Mechanical
Intel® XeonProcessor with Front Side 3.06
Vcc/Vss
Vcc/Vss
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Intel® XeonProcessor with Front Side 3.06
Intel® XeonProcessor with 533MHz Front Side
Listing Signal Definitions
Processor Assignments
Section contains front side signal groups Table Intel® XeonProcessor with Front Side Bus. This section provides sorted list Table Table Table listing processor pins ordered alphabetically name. Table listing processor pins ordered number.
4.1.1
Listing Name
Table Listing Name Table Listing Name
Name A10# A11# A12# A13# A14# A15# A16# A17# A18# A19# A20# A21# A22# A23# A24# A25# A26# A27# Signal Buffer Type
Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync
Name A28# A29# A30# A31# A32# A33# A34# A35# A20M# ADS# ADSTB0# ADSTB1# AP0# AP1# BCLK0 BCLK1 BINIT# BNR# BPM0# BPM1# BPM2# BPM3# BPM4# BPM5# BPRI# BR0#
Signal Buffer Type
Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Async GTL+ Common Source Sync Source Sync Common Common Common Common Common Common Common Common Common Common Common Common
Direction Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input Input/Output Input/Output Input/Output Input/Output Input/Output Input Input Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input Input/Output
Direction Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output
Datasheet
Intel® XeonProcessor with 533MHz Front Side Table Listing Name
Name BR1# BR2# BR3#
Table Listing Name
Name D32# D33# D34# D35# D36# D37# D38# D39# D40# D41# D42# D43# D44# D45# D46# D47# D48# D49# D50# D51# D52# D53# D54# D55# D56# D57# D58# D59# D60# D61# D62# D63# DBSY# DEFER# DBI0# DBI1# DBI2# DBI3# DP0# AB16 AA16 AC17 AE13 AD18 AB15 AD13 AD14 AD11 AC12 AE10 AC11 AD10 AA13 AA14 AC14 AB12 AB13 AA11 AA10 AB10 AC27 AD22 AE12 AC18 Signal Buffer Type
Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Common Common Source Sync Source Sync Source Sync Source Sync Common
AD16 AA27 AA25 AD27 AA24 AB26 AB25 AB23 AA22 AA21 AB20 AB22 AB19 AA19 AE26 AC26 AD25 AE25 AC24 AD24 AE23 AC23 AA18 AC20 AC21 AE22 AE20 AD21 AD19 AB17
Signal Buffer Type
Common Common Common Power/Other Power/Other Power/Other Power/Other Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync
Direction Input Input Input Output2 Output2 Input Input Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output
Direction Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input Input/Output Input/Output Input/Output Input/Output Input/Output
BSEL0 BSEL1 COMP0 COMP1 D10# D11# D12# D13# D14# D15# D16# D17# D18# D19# D20# D21# D22# D23# D24# D25# D26# D27# D28# D29# D30# D31#
Datasheet
Intel® XeonProcessor with 533MHz Front Side Table Listing Name
Name DP1# DP2# DP3# DRDY# DSTBN0# DSTBN1# DSTBN2# DSTBN3# DSTBP0# DSTBP1# DSTBP2# DSTBP3# FERR# GTLREF GTLREF GTLREF GTLREF HIT# HITM# IERR# IGNNE# INIT# LINT0 LINT1 LOCK# MCERR# ODTEN PROCHOT# PWRGOOD REQ0# REQ1# REQ2# REQ3# REQ4# Reserved Reserved Reserved Reserved Reserved AE19 AC15 AE17 Signal Buffer Type
Common Common Common Common Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Async GTL+ Power/Other Power/Other Power/Other Power/Other Common Common Async GTL+ Async GTL+ Async GTL+ Async GTL+ Async GTL+ Common Common Power/Other Async GTL+ Async GTL+ Source Sync Source Sync Source Sync Source Sync Source Sync Reserved Reserved Reserved Reserved Reserved
Table Listing Name
Name Reserved Reserved Reserved Reserved Reserved THERMDA THERMDC Reserved Reserved SMB_PRT Reserved Reserved RESET# RS0# RS1# RS2# RSP# SKTOCC# SLP# SMI# STPCLK# TESTHI0 TESTHI1 TESTHI2 TESTHI3 AE15 AE16 AD28 AC28 AC29 AA29 AB29 AB28 AA28 AE28 AE29 AD29 Signal Buffer Type
Reserved Reserved Reserved Reserved Reserved Anode Cathode Reserved Reserved Ground Reserved Reserved Common Common Common Common Common Power/Other Async GTL+ Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Async GTL+ Async GTL+ Power/Other Power/Other Power/Other Power/Other
Direction Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Output Input Input Input Input Input/Output Input/Output Output Input Input Input Input Input/Output Input/Output Input Output Input Input/Output Input/Output Input/Output Input/Output Input/Output Reserved Reserved Reserved Reserved Reserved
Direction Reserved Reserved Reserved Reserved Reserved Output Output Reserved Reserved Reserved Reserved Input Input Input Input Input Output Input
Input Input Input Input Output Input Input Input Input
Datasheet
Intel® XeonProcessor with 533MHz Front Side Table Listing Name
Name TESTHI4 TESTHI5 TESTHI6
THERMTRIP#
Table Listing Name
Name Signal Buffer Type
Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other
Signal Buffer Type
Power/Other Power/Other Power/Other Async GTL+ Common Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other
Direction Input Input Input Output Input Input Input
Direction
TRDY# TRST#
Datasheet
Intel® XeonProcessor with 533MHz Front Side Table Listing Name
Name Signal Buffer Type
Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other
Table Listing Name
Name Signal Buffer Type
Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other
Direction
Direction
Datasheet
Intel® XeonProcessor with 533MHz Front Side Table Listing Name
Name AA12 AA20 AA26 AA31 AB14 AB18 AB24 AB30 AC10 AC16 AC22 AC31 AD12 AD20 AD26 AD30 AE14 Signal Buffer Type
Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other
Table Listing Name
Name VCCA VCCIOPLL VCCSENSE VID0 VID1 VID2 VID3 VID4 AE18 AE24 Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Input Input Output Output Output Output Output Output Direction
Direction
Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other
Datasheet
Intel® XeonProcessor with 533MHz Front Side Table Listing Name
Name Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Direction
Table Listing Name
Name Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Direction
Datasheet
Intel® XeonProcessor with 533MHz Front Side Table Listing Name
Name Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Direction
Table Listing Name
Name AA15 AA17 AA23 AA30 AB11 AB21 AB27 AB31 AC13 AC19 AC25 AC30 AD15 AD17 AD23 AD31 Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Direction
Datasheet
Intel® XeonProcessor with 533MHz Front Side Table Listing Name
Name VSSA AE11 AE21 AE27 Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Input Direction
Table Listing Name
Name VSSSENSE Signal Buffer Type Power/Other Direction Output
systems utilizing Intel Xeon processor, system designer must pull-up these signals processor Baseboard treating Reserved will operate correctly with clock MHz.
Datasheet
Intel® XeonProcessor with 533MHz Front Side
4.1.2
Listing Number
Table Listing Number Table Listing Number
Name Reserved SKTOCC# Reserved A32# A33# A26# A20# A14# A10# Reserved Reserved LOCK# HITM# Reserved Reserved Signal Buffer Type Reserved Power/Other Power/Other Reserved Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync Power/Other Reserved Reserved
Common
Name VID4 OTDEN A31# A27# A21# A22# A13# A12# A11# REQ0# REQ1# REQ4# LINT0 PROCHOT# VCCSENSE VID3
Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync Power/Other Source Sync Power/Other Source Sync
Common
Direction
Direction Reserved
Output
Output Reserved
Input
Input/Output Input/Output
Input/Output Input/Output
Input/Output Input/Output
Input/Output Input/Output
Input/Output Input/Output
Input/Output Input/Output
Input/Output
Reserved Reserved Input/Output
Input/Output Input/Output
Power/Other Source Sync Source Sync Power/Other Source Sync
Common
Power/Other
Common Common
Input/Output Input/Output
Input/Output Input/Output
Power/Other Async GTL+ Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Output Output Input Output
Input/Output Input/Output
Power/Other Reserved Power/Other Power/Other Power/Other Power/Other Power/Other Reserved Reserved Input Reserved
Datasheet
Intel® XeonProcessor with 533MHz Front Side
Table Listing Number
Name Reserved RSP# A35# A34# A30# A23# A16# A15# REQ3# REQ2# DEFER# IGNNE# SMI# VID2 STPCLK# INIT# MCERR# AP1# BR3# Signal Buffer Type Power/Other Reserved
Common
Table Listing Number
Name A29# A25# A18# A17# ADS# BR0# RS1# BPRI# Reserved VSSSENSE VID1 BPM5# IERR# BPM2# BPM4# AP0# BR2# A28# A24# COMP1 DRDY#
Direction
Signal Buffer Type Source Sync Source Sync Power/Other Source Sync Source Sync Source Sync Power/Other Common Common Power/Other
Common Common
Direction Input/Output Input/Output
Reserved Input
Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync Power/Other
Common Common
Input/Output Input/Output Input/Output
Input/Output Input/Output
Input/Output Input/Output
Input/Output Input/Output
Input/Output Input/Output
Input Input
Input/Output Input/Output
Power/Other Reserved Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other
Common Common
Reserved Output
Input/Output Input/Output
Power/Other
Common
Input Input Input Input Input
Power/Other Async GTL+ Async GTL+ Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Async GTL+ Power/Other Async GTL+
Common
Output Input/Output Output
Power/Other
Common Common
Input/Output Input/Output
Power/Other
Common Common
Output Input
Input/Output Input
Power/Other Source Sync Source Sync Power/Other Power/Other Power/Other
Common
Input Input/Output
Input/Output Input/Output
Power/Other
Common Common
Input/Output Input
Input
Power/Other
Input/Output
Datasheet
Intel® XeonProcessor with 533MHz Front Side
Table Listing Number
Name TRDY# RS0# HIT# FERR# VID0 BPM3# BPM0# BPM1# GTLREF BINIT# BR1# ADSTB1# A19# ADSTB0# DBSY# BNR# RS2# GTLREF TRST# THERMTRIP Signal Buffer Type
Common
Table Listing Number
Name A20M# LINT1 Signal Buffer Type Async GTL+ Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Async GTL+ Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Input Direction Input
Direction Input
Power/Other
Common Common
Input Input/Output
Power/Other Power/Other Async GTL+ Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other
Common Common
Input Output
Output
Output
Input/Output Input/Output
Power/Other
Common
Input/Output Input
Power/Other Power/Other
Common Common
Input/Output Input
Power/Other Source Sync Source Sync Power/Other Source Sync
Common
Input/Output Input/Output
Input/Output Input/Output
Power/Other
Common Common
Input/Output Input
Power/Other Power/Other Power/Other Async GTL+ Output Input Input
Datasheet
Intel® XeonProcessor with 533MHz Front Side
Table Listing Number
Name Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Direction
Table Listing Number
Name Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Direction
Datasheet
Intel® XeonProcessor with 533MHz Front Side
Table Listing Number
Name Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Direction
Table Listing Number
Name Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Direction
Datasheet
Intel® XeonProcessor with 533MHz Front Side
Table Listing Number
Name Reserved BCLK1 TESTHI0 TESTHI1 TESTHI2 GTLREF GTLREF Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Reserved Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Input Input Input Input Input Input Reserved Direction
Table Listing Number
Name Reserved BCLK0 TESTHI3 RESET# D62# DSTBP3# DSTBN3# DSTBP2# DSTBN2# DSTBP1# DSTBN1# DSTBP0# DSTBN0# THERMDA THERMDC BSEL0 Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Reserved Power/Other Power/Other Power/Other
Common
Direction
Reserved Input
Input
Input Input/Output
Source Sync Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync Power/Other Source Sync Anode Cathode
Reserved
Input/Output Input/Output
Input/Output Input/Output
Input/Output Input/Output
Input/Output Input/Output
Input/Output Input/Output
Input/Output Output Output
Power/Other Power/Other Power/Other Power/Other Power/Other Output2
Datasheet
Intel® XeonProcessor with 533MHz Front Side
Table Listing Number
AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AA24 AA25 AA26 AA27 AA28 AA29 AA30 AA31 AB10 AB11 Name VSSA TESTHI4 D61# D54# D53# D48# D49# D33# D24# D15# D11# D10# BSEL1 VCCA D63# PWRGOOD DBI3# D55# Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Source Sync Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync Power/Other Source Sync Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync Power/Other Source Sync
Reserved Reserved
Table Listing Number
AB12 Name D51# D52# D37# D32# D31# D14# D12# D13# Reserved D60# D59# D56# D47# D43# D41# D50# DP2# D34# DP0# Signal Buffer Type Source Sync Source Sync Power/Other Source Sync Source Sync Source Sync Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync Power/Other
Reserved Reserved
Direction
Direction Input/Output Input/Output
Input
AB13 AB14
Input Input/Output
AB15 AB16 AB17
Input/Output Input/Output Input/Output
Input/Output Input/Output
AB18 AB19 AB20
Input/Output Input/Output
Input/Output Input/Output
AB21 AB22 AB23
Input/Output Input/Output
Input/Output
AB24 AB25
Input/Output Input/Output
Input/Output Input/Output
AB26 AB27 AB28
Input/Output Input/Output
AB29 AB30 AB31
Power/Other Power/Other Reserved Power/Other Power/Other Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync Power/Other Source Sync
Common
Input/Output Input/Output
Reserved
Input/Output
AC10
Input/Output Input/Output
Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Source Sync Power/Other Power/Other Source Sync Source Sync Power/Other Input/Output Input/Output Input Output2 Input
Input/Output Input/Output
AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19
Input/Output Input/Output
Input/Output Input/Output
Power/Other Source Sync
Common
Input/Output Input/Output
Power/Other
Datasheet
Intel® XeonProcessor with 533MHz Front Side
Table Listing Number
AC20 AC21 AC22 AC23 AC24 AC25 AC26 AC27 AC28 AC29 AC30 AC31 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 Name D25# D26# D23# D20# D17# DBI0# Reserved VCCIOPLL TESTHI5 D57# D46# D45# D40# D38# D39# COMP0 D36# D30# D29# DBI1# D21# D18# Signal Buffer Type Source Sync Source Sync Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync
Reserved Reserved
Table Listing Number
AD27 AD28 AD29 Name SMD_PRT TESTHI6 SLP# D58# D44# D42# DBI2# D35# Reserved Reserved DP3# DP1# D28# D27# D22# D19# D16# VID_VCC VID_VCC Mechanical Signal Buffer Type Source Sync
Reserved Reserved
Direction Input/Output Input/Output
Direction Input/Output
Input/Output Input/Output
AD30 AD31
Power/Other Power/Other Power/Other Power/Other Ground Power/Other Async GTL+ Source Sync Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync Power/Other Reserved Reserved
Common
Input/Output Input/Output
Output Input Input Input/Output
Power/Other Power/Other Reserved Power/Other Power/Other Power/Other Power/Other Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync Power/Other Power/Other Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync Power/Other Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input Input Reserved
AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AE26 AE27 AE28 AE29 AE30
Input/Output Input/Output
Input/Output Input/Output
Reserved Reserved Input/Output
Power/Other
Common
Input/Output Input/Output
Source Sync Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync Power/Other Power/Other Power/Other
Input/Output Input/Output
Input/Output Input/Output
systems utilizing Intel Xeon processor, system designer must pull-up these signals processor VCC. Baseboards treating Reserved will operate correctly with clock MHz.
Datasheet
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Intel® XeonProcessor with Front Side 3.06
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Intel® XeonProcessor with Front Side 3.06
Signal Definitions
Table Signal Definitions (Sheet
Name Type Description A[35:3]# (Address) define byte physical memory address space. sub-phase address phase, these pins transmit address transaction. subphase these pins transmit transaction type information. These signals must connect appropriate pins agents front side bus. A[35:3]# protected parity signals AP[1:0]#. A[35:3]# source synchronous signals latched into receiving buffers ADSTB[1:0]#. active-to-inactive transition RESET#, processors sample subset A[35:3]# pins determine their power-on configuration. Section 6.1. A20M# (Address-20 Mask) asserted, processor masks physical address (A20#) before looking line internal cache before driving read/ write transaction bus. Asserting A20M# emulates 8086 processor's address wrap-around MByte boundary. Assertion A20M# only supported real mode. A20M# asynchronous signal. However, ensure recognition this signal following write instruction, must valid along with TRDY# assertion corresponding write transaction. ADS# (Address Strobe) asserted indicate validity transaction address A[35:3]# pins. agents observe ADS# activation begin parity checking, protocol checking, address decode, internal snoop, deferred reply match operations associated with transaction. This signal must connect appropriate pins front side agents. Address strobes used latch A[35:3]# REQ[4:0]# their rising falling edge. AP[1:0]# (Address Parity) driven request initiator along with ADS#, A[35:3]#, transaction type REQ[4:0]# pins. correct parity signal high even number covered signals number covered signals low. This allows parity high when covered signals high. AP[1:0]# should connect appropriate pins front side agents. following table defines coverage model these signals. AP[1:0]# Request Signals A[35:24]# A[23:3]# REQ[4:0]# Subphase AP0# AP1# AP1# Subphase AP1# AP0# AP0# Notes
A[35:3]#
A20M#
ADS#
ADSTB[1:0]#
BCLK[1:0]
differential pair BCLK (Bus Clock) determines frequency. processor front side agents must receive these signals drive their outputs latch their inputs. external timing parameters specified with respect rising edge BCLK0 crossing falling edge BCLK1.
Intel® XeonProcessor with Front Side 3.06
Table Signal Definitions (Sheet
Name Type Description BINIT# (Bus Initialization) observed driven processor front side agents used, must connect appropriate pins such agents. BINIT# driver enabled during power configuration, BINIT# asserted signal condition that prevents reliable future information. BINIT# observation enabled during power-on configuration (see Section 6.1) BINIT# sampled asserted, symmetric agents reset their LOCK# activity request arbitration state machines. agents reset their transaction tracking state machines upon observation BINIT# assertion. Once BINIT# assertion been observed, agents will re-arbitrate front side attempt completion their queue entries. BINIT# observation disabled during power-on configuration, central agent handle assertion BINIT# appropriate error handling architecture system. BNR# (Block Next Request) used assert stall agent unable accept transactions. During stall, current owner cannot issue transactions. BNR# Since multiple agents might need request stall same time, BNR# wire-OR signal which must connect appropriate pins processor front side agents. order avoid wire-OR glitches associated with simultaneous edge transitions driven multiple drivers, BNR# activated specific clock edges sampled specific clock edges. BPM[5:0]# (Breakpoint Monitor) breakpoint performance monitor signals. They outputs from processor which indicate status breakpoints programmable counters used monitoring processor performance. BPM[5:0]# should connect appropriate pins front side agents. BPM4# provides PRDY# (Probe Ready) functionality port. PRDY# processor output used debug tools determine processor debug readiness. BPM[5:0]# BPM5# provides PREQ# (Probe Request) functionality port. PREQ# used debug tools request debug operation processors. BPM[5:4]# must bussed agents. These signals have on-die termination must terminated agent. appropriate platform design guidelines additional information. BPRI# (Bus Priority Request) used arbitrate ownership processor front side bus. must connect appropriate pins processor front side agents. Observing BPRI# active asserted priority agent) causes other agents stop issuing requests, unless such requests part ongoing locked operation. priority agent keeps BPRI# asserted until requests completed, then releases deasserting BPRI#. Notes
BINIT#
BPRI#
Intel® XeonProcessor with Front Side 3.06
Table Signal Definitions (Sheet
Name Type Description BR[3:0]# (Bus Request) drive BREQ[3:0]# signals system. BREQ[3:0]# signals interconnected rotating manner individual processor pins. BR2# BR3# must utilized dual processor platform design. table below gives rotating interconnect between processor signals dual processor systems. BR[1:0]# Signals Rotating Interconnect, dual processor system Signal BREQ0# BREQ1# Agent Pins BR0# BR1# Agent Pins BR1# BR0# Notes
BR0# BR[1:3]#1
During power-up configuration, central agent must assert BR0# signal. symmetric agents sample their BR[1:0]# pins active-to-inactive transition RESET#. which agent samples active level determines agent agents then configure their pins match appropriate signal protocol shown below. BR[1:0]# Signal Agent BR[1:0]# Signals Rotating Interconnect, dual processor system BR0# BR1# Agent
During power-on configuration, central agent must assert BR0# signal. symmetric agents sample their BR[3:0]# pins active-to-inactive transition RESET#. which agent samples asserted determines it's agent These signals have on-die termination must terminated agent. appropriate platform design guidelines additional information. These output signals used select front side frequency. BSEL[1:0] "00" will select clock frequency. frequency determined processor(s), chipset, frequency synthesizer capabilities. front side agents must operate same frequency. Individual processors will only operate their specified front side (FSB) frequency. BSEL[1:0] baseboards which support operation only clocks these signals ignored. baseboards employing these signals, pull-up resistor used. Table "Front Side Clock Frequency Select Truth Table BSEL[1:0]" page output values. COMP[1:0] COMP[1:0] must terminated baseboard using precision resistors. These inputs configure AGTL+ drivers processor. Refer appropriate platform design guidelines Table implementation details.
Intel® XeonProcessor with Front Side 3.06
Table Signal Definitions (Sheet
Name Type Description D[63:0]# (Data) data signals. These signals provide 64-bit data path between processor front side agents, must connect appropriate pins such agents. data driver asserts DRDY# indicate valid data transfer. D[63:0]# quad-pumped signals, will thus driven four times common clock period. D[63:0]# latched falling edge both DSTBP[3:0]# DSTBN[3:0]#. Each group data signals correspond pair DSTBP# DSTBN#. following table shows grouping data signals strobes DBI#. Notes
D[63:0]#
Data Group D[15:0]# D[31:16]# D[47:32]# D[63:48]#
DSTBN/ DSTBP
DBI#
Furthermore, DBI# pins determine polarity data signals. Each group data signals corresponds DBI# signal. When DBI# signal active, corresponding data group inverted therefore sampled active high. DBI[3:0]# source synchronous indicate polarity D[63:0]# signals. DBI[3:0]# signals activated when data data inverted. agent will invert data signals more than half bits, within 16-bit group, change logic level next cycle. DBI[3:0] Assignment Data DBI[3:0]# Signal DBI0# DBI1# DBI2# DBI3# Data Signals D[15:0]# D[31:16]# D[47:32]# D[63:48]#
DBSY#
DBSY# (Data Busy) asserted agent responsible driving data processor front side indicate that data use. data released after DBSY# deasserted. This signal must connect appropriate pins processor front side agents. DEFER# asserted agent indicate that transaction cannot guaranteed in-order completion. Assertion DEFER# normally responsibility addressed memory agent. This signal must connect appropriate pins processor front side agents.
DEFER#
DP[3:0]#
DP[3:0]# (Data Parity) provide parity protection D[63:0]# signals. They driven agent responsible driving D[63:0]#, must connect appropriate pins processor front side agents. DRDY# (Data Ready) asserted data driver each data transfer, indicating valid data data bus. multi-common clock data transfer, DRDY# deasserted insert idle clocks. This signal must connect appropriate pins processor front side agents. Data strobe used latch D[63:0]#. Data strobe used latch D[63:0]#.
DRDY#
DSTBN[3:0]# DSTBP[3:0]#
Intel® XeonProcessor with Front Side 3.06
Table Signal Definitions (Sheet
Name Type Description FERR#/PBE# (floating point error/pending break event) multiplexed signal meaning qualified STPCLK#. When STPCLK# asserted, FERR#/ PBE# indicates floating-point error will asserted when processor detects unmasked floating-point error. When STPCLK# asserted, FERR#/ PBE# similar ERROR# signal Intel coprocessor, included compatibility with systems using MS-DOS*-type floating-point error reporting. When STPCLK# asserted, assertion FERR#/PBE# indicates that processor pending break event waiting service. assertion FERR#/ PBE# indicates that processor should returned Normal state. additional information pending break event functionality, including identification support feature enable/disable information, refer volume Intel Architecture Software Developer's Manual Intel Processor Identification CPUID Instruction application note. This signal does have on-die termination must terminated agent. appropriate Platform Design Guideline additional information. GTLREF GTLREF determines signal reference level AGTL+ input pins. GTLREF should 2/3Vcc. GTLREF used AGTL+ receivers determine signal logical logical HIT# (Snoop Hit) HITM# (Hit Modified) convey transaction snoop operation results. front side agent assert both HIT# HITM# together indicate that requires snoop stall, which continued reasserting HIT# HITM# together. Since multiple agents deliver snoop results same time, HIT# HITM# wire-OR signals which must connect appropriate pins processor front side agents. order avoid wire-OR glitches associated with simultaneous edge transitions driven multiple drivers, HIT# HITM# activated specific clock edges sampled specific clock edges. IERR# (Internal Error) asserted processor result internal error. Assertion IERR# usually accompanied SHUTDOWN transaction processor front side bus. This transaction optionally converted external error signal (e.g., NMI) system core logic. processor will keep IERR# asserted until assertion RESET#, BINIT#, INIT#. This signal does have on-die termination must terminated agent. appropriate Platform Design Guideline additional information. IGNNE# (Ignore Numeric Error) asserted force processor ignore numeric error continue execute noncontrol floating-point instructions. IGNNE# deasserted, processor generates exception noncontrol floating-point instruction previous floating-point instruction caused error. IGNNE# effect when control register (CR0) set. IGNNE# asynchronous signal. However, ensure recognition this signal following write instruction, must valid along with TRDY# assertion corresponding write transaction. INIT# (Initialization), when asserted, resets integer registers inside processors without affecting their internal caches floating-point registers. Each processor then begins execution power-on Reset vector configured during power-on configuration. processor continues handle snoop requests during INIT# assertion. INIT# asynchronous signal must connect appropriate pins processor front side agents. INIT# sampled active active inactive transition RESET#, then processor executes Built-in Self-Test (BIST). Notes
FERR#/PBE#
HIT# HITM#
IERR#
IGNNE#
INIT#
Intel® XeonProcessor with Front Side 3.06
Table Signal Definitions (Sheet
Name Type Description LINT[1:0] (Local APIC Interrupt) must connect appropriate pins front side agents. When APIC functionality disabled, LINT0 signal becomes INTR, maskable interrupt request signal, LINT1 becomes NMI, nonmaskable interrupt. INTR backward compatible with signals those names Pentium processor. Both signals asynchronous. Both these signals must software configured BIOS programming APIC register space used either NMI/INTR LINT[1:0]. Because APIC enabled default after Reset, operation these pins LINT[1:0] default configuration. LOCK# indicates system that transaction must occur atomically. This signal must connect appropriate pins processor front side agents. locked sequence transactions, LOCK# asserted from beginning first transaction last transaction. When priority agent asserts BPRI# arbitrate ownership processor front side bus, will wait until observes LOCK# deasserted. This enables symmetric agents retain ownership processor front side throughout locked operation ensure atomicity lock. Mechanical prevent compatibility with 603-pin socket. MCERR# (Machine Check Error) asserted indicate unrecoverable error without protocol violation. driven processor front side agents. MCERR# assertion conditions configurable system level. Assertion options defined following options: Enabled disabled. Asserted, configured, internal errors along with IERR#. MCERR# Asserted, configured, request initiator transaction after observes error. Asserted agent when observes error transaction. more details regarding machine check architecture, refer IA-32 Software Developer's Manual, Volume System Programming Guide. Since multiple agents drive this signal same time, MCERR# wire-OR signal which must connect appropriate pins processor front side agents. order avoid wire-OR glitches associated with simultaneous edge transitions driven multiple drivers, MCERR# activated specific clock edges sampled specific clock edges. ODTEN (On-die termination enable) should connected enable on-die termination agents. middle agents, pull this signal down resistor ground disable on-die termination. Whenever ODTEN high, on-die termination will active, regardless other states bus. PROCHOT# (processor hot) indicates that processor Thermal Control Circuit (TCC) been activated. Under most conditions, PROCHOT# will active when processor's thermal sensor detects that processor reached maximum safe operating temperature. Section more details. These signals have on-die termination must terminated agent. appropriate Platform Design Guideline additional information. Notes
LINT[1:0]
LOCK#
Mechanical
Inert
ODTEN
PROCHOT#
Intel® XeonProcessor with Front Side 3.06
Table Signal Definitions (Sheet
Name Type Description PWRGOOD (Power Good) input. processor requires this signal clean indication that processor clocks power supplies stable within their specifications. "Clean" implies that signal will remain (capable sinking leakage current), without glitches, from time that power supplies turned until they come within specification. signal must then transition monotonically high state. Figure illustrates relationship PWRGOOD RESET# signal. PWRGOOD driven inactive time, clocks power must again stable before subsequent rising edge PWRGOOD. must also meet minimum pulse width specification Table followed RESET# pulse. PWRGOOD signal must supplied processor; used protect internal circuits against voltage sequencing issues. should driven high throughout boundary scan operation. REQ[4:0]# (Request Command) must connect appropriate pins processor front side agents. They asserted current owner define currently active transaction type. These signals source synchronous ADSTB[1:0]#. Refer AP[1:0]# signal description details parity checking these signals. Asserting RESET# signal resets processors known states invalidates their internal caches without writing back their contents. power-on Reset, RESET# must stay active least millisecond after BCLK have reached their proper specifications. observing active RESET#, front side agents will deassert their outputs within clocks. RESET# must kept asserted more than 10ms. RESET# number signals sampled active-to-inactive transition RESET# power-on configuration. These configuration options described Section 6.1. This signal does have on-die termination must terminated agent. appropriate Platform Design Guideline additional information. RS[2:0]# RS[2:0]# (Response Status) driven response agent (the agent responsible completion current transaction), must connect appropriate pins processor front side agents. RSP# (Response Parity) driven response agent (the agent responsible completion current transaction) during assertion RS[2:0]#, signals which RSP# provides parity protection. must connect appropriate pins processor front side agents. correct parity signal high even number covered signals number covered signals low. While RS[2:0]# 000, RSP# also high, since this indicates being driven agent guaranteeing correct parity. SKTOCC# (Socket occupied) will pulled ground processor indicate that processor present. SLP# (Sleep), when asserted Stop-Grant state, causes processors enter Sleep state. During Sleep state, processor stops providing internal clock signals units, leaving only Phase-Locked Loop (PLL) still operating. Processors this state will recognize snoops interrupts. processor will recognize only assertion RESET# signal, deassertion SLP#, removal BCLK input while Sleep state. SLP# deasserted, processor exits Sleep state returns Stop-Grant state, restarting internal clock signals processor core units. grounded processor packages that contain SMBUS components (PIROM, Scratch EEPROM, thermal sensor). floating processor packages that contain SMBus components. Notes
PWRGOOD
REQ[4:0]#
RSP#
SKTOCC#
SLP#
SMB_PRT
Intel® XeonProcessor with Front Side 3.06
Table Signal Definitions (Sheet
Name Type Description SMI# (System Management Interrupt) asserted asynchronously system logic. accepting System Management Interrupt, processors save current state SMI# enter System Management Mode (SMM). Acknowledge transaction issued, processor begins program execution from handler. SMI# asserted during deassertion RESET# processor will tri-state outputs. STPCLK# (Stop Clock), when asserted, causes processors enter power Stop-Grant state. processor issues Stop-Grant Acknowledge transaction, stops providing internal clock signals processor core units except front side APIC units. processor continues snoop transactions service interrupts while Stop-Grant state. When STPCLK# deasserted, processor restarts internal clock units resumes execution. assertion STPCLK# effect clock; STPCLK# asynchronous input. (Test Clock) provides clock input processor Test (also known Test Access Port). (Test Data transfers serial test data into processor. provides serial input needed JTAG specification support. (Test Data Out) transfers serial test data processor. provides serial output needed JTAG specification support. TESTHI[6:0] pins should individually connected pull-up resistor which matches trace impedance within range ohms. TESTHI[3:0] TESTHI[6:5] tied together pulled with single resistor desired. However, utilization boundary scan test will functional these pins connected together. TESTHI4 must always pulled independently from other TESTHI pins. optimum noise margin, pull-up resistor values used TESTHI[6:0] pins should have resistance value within percent impedance baseboard transmission line traces. example, trace impedance then value between should used. TESTHI[6:0] termination recommendations provided Intel® Xeonprocessor datasheet still suitable Intel® Xeonprocessor with Front Side Bus. However, Intel recommends designs designs undergoing design updates follow trace impedance matching termination guidelines given this section. Activation THERMTRIP# (Thermal Trip) indicates processor junction temperature reached level beyond which permanent silicon damage occur. Measurement temperature accomplished through internal thermal sensor which configured trip approximately properly protect processor, power must removed upon THERMTRIP# becoming active. Figure appropriate power down sequence timing requirement. parallel, processor will attempt reduce temperature shutting internal clocks stopping program execution. Once activated, THERMTRIP# remains latched processor will stopped until RESET# asserted. RESET# pulse will reset processor execution will begin boot vector. temperature dropped below trip level, processor will assert THERMTRIP# return shutdown state. processor releases THERMTRIP# when RESET# activated even processor still hot. This signal have on-die termination must terminated agent. appropriate platform design guidelines additional information. THERMDA THERMDC Thermal Diode Anode. Thermal Diode Cathode. Notes
STPCLK#
TESTHI[6:0]
THERMTRIP#
Intel® XeonProcessor with Front Side 3.06
Table Signal Definitions (Sheet
Name Type Description (Test Mode Select) JTAG specification support signal used debug tools. This signal does have on-die termination must terminated agent.See appropriate platform design guidelines additional information. TRDY# (Target Ready) asserted target indicate that ready receive write implicit writeback data transfer. TRDY# must connect appropriate pins front side agents. TRST# (Test Reset) resets Test Access Port (TAP) logic. TRST# must driven during power Reset. appropriate Platform Design Guideline additional information. VCCA provides isolated power analog portion internal PLL's. discrete filter provide clean power. filter defined Section provide clean power PLL. tolerance total filter important. Refer appropriate platform design guidelines complete implementation details. VCCIOPLL provides isolated power digital portion internal PLL's. Follow guidelines VCCA (Section 2.5), refer appropriate platform design guidelines complete implementation details. Vccsense Vsssense pins points which processor minimum maximum voltage requirements specified. Uniprocessor designs utilize these pins voltage sensing processor's voltage regulator. However, multiprocessor designs must connect these pins sense logic, rather utilize them power delivery validation. VID[4:0] (Voltage pins used support automatic selection power supply voltages (VCC). Unlike previous processor generations, these pins driven processor logic. Hence voltage supply these pins (SM_VCC) must valid before supplying processor enabled. Conversely, output must disabled prior voltage supply these pins becomes invalid. pins needed support processor voltage specification variations. Table definitions these pins. power supply must supply voltage that requested these pins, disable itself. Voltage BSEL logic VSSA provides isolated, internal ground internal PLL's. connect directly ground. This connected VCCA VCCIOPLL through discrete filter circuit. Notes
TRDY#
TRST#
VCCA
VCCIOPLL
VCCSENSE VSSSENSE
VID[4:0]
VID_VCC VSSA
NOTES: Intel Xeon processors only support BR0# BR1#. However, Intel Xeon processors must terminate BR2# BR3# processor VCC. this Intel® Xeonprocessors, maximum number symmetric agents one. Maximum number Central Agents zero. this Intel® Xeonprocessors, maximum number symmetric agents two. Maximum number Central Agents zero. this Intel® Xeonprocessors, maximum number symmetric agents two. Maximum number Central Agents one.
Intel® XeonProcessor with Front Side 3.06
Thermal Specifications
This chapter provides thermal specifications necessary designing thermal solution Intel® XeonProcessor with Front Side Bus. Thermal solutions should include heatsinks that attach integrated heat spreader (IHS). provides common interface intended compatible with many heatsink designs. Thermal specifications based temperature top, referred case temperature, TCASE. Thermal solutions should designed maintain processor within TCASE specifications. information performing TCASE measurements, refer Intel® XeonProcessor Thermal Design Guidelines. Figure exploded view processor package thermal solution assembly. Note: processor either shipped alone with heatsink (boxed processor only). other components shown Figure must purchased separately.
Figure Processor with Thermal Mechanical Components Exploded View
Note:
This graphical representation. specifications, each component's respective documentation listed Section 1.3.
Intel® XeonProcessor with Front Side 3.06
Thermal Specifications
Table specifies thermal design power dissipation envelope Intel® Xeonprocessor with Front Side Bus. processor power listed Table described thermal design power. Analysis indicates that real applications unlikely cause processor consume maximum possible power consumption. Intel recommends that system thermal designs utilize Thermal Design Power indicated Table Thermal Design Power recommendations chosen through characterization server workstation applications processor. Thermal Monitor feature intended protect processor from overheating high power code that exceeds recommendations this table. more details Thermal Monitor feature, refer Section 6.3. cases, Thermal Monitor feature must enabled processor operating within specification. Table also lists minimum maximum processor TCASE temperature specifications. thermal solution should designed ensure temperature processor never exceeds these specifications.
Table Processor Thermal Design Power
Core Frequency 2.40 2.66 2.80 3.06 Thermal Design Power1 Maximum Power Minimum TCASE (°C) Maximum TCASE (°C) Notes
NOTE: Intel recommends that thermal solutions designed utilizing Thermal Design Power values. Refer Intel® XeonProcessor Thermal Design Guidelines. values specified point Vcc_max loadline corresponding Icc_TDP. Systems must designed ensure that processor subjected static combination wherein exceeds Vcc_max specified Icc. Please refer loadline specifications Chapter 2.0.
Figure Processor Thermal Design Power Electrical Projections 1.500V
Intel® XeonProcessor with Front Side 3.06
Figure Processor Thermal Design Power Electrical Projections 1.525V
Intel® XeonProcessor with Front Side 3.06
5.2.1
Measurements Thermal Specifications
Processor Case Temperature Measurement
minimum maximum case temperatures (TCASE) processors specified Table previous section. These temperature specifications meant ensure correct reliable operation processor. Figure illustrates thermal measurement point TCASE. This point geometric center integrated heat spreader (IHS).
Figure Thermal Measurement Point Processor TCASE
Note: Figure scale, reference only
Intel® XeonProcessor with Front Side 3.06
Features
Power-On Configuration Options
Intel® XeonProcessor with Front Side several configuration options that determined state specific processor pins active-to-inactive transition processor RESET# signal. These configuration options cannot changed except another reset. Both power software induced resets reconfigure processor(s).
Table Power-On Configuration Option Pins
Configuration Option Output state Execute BIST (Built-In Self Test) Order Queue de-pipelining (set depth Disable MCERR# observation Disable BINIT# observation APIC cluster (0-3) Disable parking Disable Hyper-Threading Technology Symmetric agent arbitration Pin1 SMI# INIT# A10# A[12:11]# A15# A31# BR[3:0]# Notes
NOTES: Asserting this signal during active-to-inactive edge RESET# will selects corresponding option. Intel® Xeonprocessor with Front Side does support this feature, therefore platforms utilizing this processor should these configuration pins. Intel Xeon processor with Front Side utilize only BR0# BR1# signals. 2-way platforms must utilize BR2# BR3# signals.
Clock Control Power States
processor allows AutoHALT, Stop-Grant Sleep states reduce power consumption stopping clock internal sections processor, depending each particular state. Figure visual representation processor power states. inability processors recognize transactions during Sleep state, multiprocessor systems allowed simultaneously have processor Sleep state other processor Normal Stop-Grant state.
6.2.1
Normal State-State
This normal operating state processor.
Intel® XeonProcessor with Front Side 3.06
6.2.2
AutoHALT Powerdown State-State
AutoHALT power state entered when processor executes HALT instruction. processor will transition Normal state upon occurrence BINIT#, INIT#, LINT[1:0] (NMI, INTR), interrupt delivered over front side bus. RESET# will cause processor immediately initialize itself. system generate STPCLK# while processor AutoHALT Power Down state. When system deasserts STPCLK# interrupt, processor will return execution HALT state.
Figure Stop Clock State Machine
HALT Instruction HALT Cycle Generated Auto HALT Power Down State BCLK running Snoops interrupts allowed INIT#, BINIT#, INTR, NMI, RESET# Normal State Normal execution
STPCLK# Asserted
STPCLK# De-asserted
Snoop Event Occurs
Snoop Event Serviced
HALT/Grant Snoop State BCLK running Service snoops caches
Snoop Event Occurs Snoop Event Serviced
Stop Grant State BCLK running Snoops interrupts allowed
SLP# Asserted
SLP# De-asserted
Sleep State BCLK running snoops interrupts allowed
6.2.3
Stop-Grant State-State
When STPC
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