High Density CMOS Gate Arrays DS2462 ISSUE March 1992

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

High Density CMOS Gate Arrays DS2462 ISSUE March 1992

Datasheet Thumbnail

Top Searches for this datasheet

CLA70000 Series
High Density CMOS Gate Arrays
DS2462
ISSUE
March 1992
Recent advances CMOS processing technology improvements design architecture have development generation array-based ASIC products with vastly improved gate integration densities. This family CLA70000 micron CMOS arrays brings considerable advantages design next generation systems combining high performance high complexity.
Overview
CLA70000 gate array family Zarlink Semiconductors' sixth generation CMOS gate array product. family consists nine arrays implemented latest generation micron) twin well epitaxial CMOS process. process conjunction with advanced layout route software, offers extremely high packing densities. array architecture based upon earlier well proven CLA60000 series with emphasis being placed high speed, high packing density, provision comprehensive cell libraries. cell libraries encompass other specialized macros. Full design support available major industry standard ASIC design software tools, well Zarlink Semiconductor's proprietary PDS2 design environment. Design support provided Zarlink Semiconductor's design centers, each offering variety design routes, which customized individual customer requirements.
Features
power channelless arrays from 5,000 250,000 available gates (5µW gate MHz) micron (0.8 micron effective) twin well epitaxial process Typical gate delays (NAND2 Fanout=2) Comprehensive cell library including DSP, JTAG/BIST compiled memory cells (ROM blocks bits blocks bits) Extensive Range Plastic Ceramic Packages both Surface Mount Through Board Assembly Flexible structure allows user define power locations Fully supported industry standard workstations in-house software High drive output stages with slew rate control Supports JTAG BIST test philosophies (IEEE 1149-1 Test Procedures) 883C compliant product available (paragraph 1.2.1)
Product Details
CLA70000 array series shown below with typical figures given usable gates. Actual gate utilization dependent circuit structure, giving range -70% layer metallisation.
DEVICE NUMBER CLA70000 CLA71000 CLA72000 CLA73000 CLA74000 CLA75000 CLA76000 CLA77000 CLA78000
POWER PADS
GATE COMPLEXITY 110K 182K 256K
ESTIMATED USABLE GATES 2.5K 9.5K 13.5K 17.5K 31.5K 49.5K 115K
CLA70000 Series
Core Cell Arrangement
Supports compact macros Allows high density routing
Supply
Supply
four transistor group NMOS PMOS) (fig.1) forms basic cell core array. This array element repeated regular fashion over complete core area give homogenous `Full Field' (sea gates) array. This lends itself hierarchical design, allowing pre-routed user defined subcircuits repeated anywhere array. core cell structure together with associated cell libraries have been carefully designed maximize number nets which routed through cell. This enables optimal routing both data flow control signal distribution schemes thus giving very high overall utilization factors. This feature particular benefit designs using highly structured blocks such memory arithmetic functions.
Programmable contacts
Buffer Arrangement
Several hundred different cell combinations Programmable Slew rate Control Outputs Excellent Latchup immunity
Supply Supply
Figure Diagrammatic representation Array Core Cell
controls, slew rate controlled output buffers. buffer locations configured supply pads (VDD VSS). Slew rate control output drivers useful feature when multiple high drive outputs need switched simultaneously, occur driving capacitive loads such buses. Using regular output buffers with their inherently fast edge speed lead significant power supply noise transients, with possible mis-operation result. overcome this problem. CLA70000 family includes slew rate controlled output drivers, which proprietary design techniques control turn-on output transistors (di/dt). These cells provide significant benefit trade between switching current magnitude number supply pads required.
buffers interface external circuitry therefore required robust flexible. Both inputs outputs incorporate electrostatic discharge (ESD) protection structures which withstand excess 2KV, highly resistant latch-up epitaxial process. addition construction concepts used cells provide designer with several hundred different options cell configuration. CLA70000 buffers (fig.2) contain components static protection, CMOS compatible input stages, wide variety intermediate output drive configurations. Included Schmitt triggers, tristate
SLEW RATE CONTROL
BLOCK
INPUT DATA
slew rate controlled driver
OPT3
Volts
Volts
Bonding
IBSK1, IBSK2 IBSK3 have been characterised give correct timing when connected OPT* cells.
BLOCK
Slew Control Block
CLA70000 Series
Power Supply Distribution
Three power rings good noise immunity Optimized efficient routing User defined placement Power Ground pads
Supply Intermediate Buffers
Supply Core Logic
power supply distribution scheme CLA70000 arrays (fig.3) flexibility meet varying applications needs. Three separate power rings used, each internal core logic, intermediate buffer cells, large output driver cells. Noise generated impedance output drivers isolated from core logic buffer areas. distribution supply rails automatically positioned layout software which allows greater design flexibility optimisation. power supply rings connected either separate locations combined single location. cell pads configured either power ground, giving complete flexibility designer.
Supply Buffers
Figure Power Supply Organisation
Process Technology
Advanced micron twin well process with epitaxial substrate Class inch wafer fabrication facility High density power process
CLA70000 arrays built using Zarlink Semiconductor micron drawn CMOS process, which third generation series process family. Manufacture Class10, 6-inch fabrication facility. process twin well, self aligned oxide-isolated technology epitaxial substrate, with effective channel length micron, giving defect density, high reliability, inherently power dissipation. process excellent immunity latchup, ESD, exhibits stable performance characteristics ideal commercial, industrial military applications.
Absolute Maximum Ratings
Parameter Supply Voltage Input Voltage Output Voltage protection Current Storage Temperature Ceramic Plastic -0.5 -0.5 -0.5 Units Volts
Recommended Maximum Operating Limits
Parameter Supply Voltage Input Voltage Output Voltage Operating Temperature Commercial Grade Industrial Grade Military Grade 125** Units
Operation outside these absolute maximum ratings permanently damage device characteristics affect
125°C maximum junction temperature plastic devices. **Subject maximum junction temperature 150°C ceramic devices.
CLA70000 Series
Manufacturing Facilty
Computer aided manufacturing Digital testers with large pinout capacity Vibration free reliable manufacture
Cell Library
Comprehensive range cells Specialized BIST sub-libraries Compatible with Megacell CLA60000
CLA70000 product manufactured near Plymouth, England latest purpose built facility sub-micron process geometries. factory uses latest automated equipment inch wafers Computer Aided Manufacturing techniques ensure production efficiency. Wafer fabrication carried Class better, clean room conditions vibration free environment assure lowest possible defect level. addition world class wafer facility there excellent probe final test areas equipped with latest analog digital testers capable handling complex test vectors large pinouts. This large investment shows Zarlink Semiconductors' commitment market areas needing state-of-the-art CMOS ASICS.
very comprehensive cell library available CLA70000 series. contains libraries which used specific applications areas such Digital Signal Processing (DSP) Built Self Test (BIST). More details these specialized libraries found applications notes design manual. micron (drawn) CMOS array (CLA60000) cell library converted equivalent cells CLA70000 allow system upgrades. Equivalent cells also available corresponding MVA70000 Megacell enable easy transition standard cell product minimize silicon area analog functions.
Cell Library Logic Array Cells
DELAY 2INV INV2 INV4 INV8 NAND2 NAND3 2NAND3 NAND4 NAND5 NAND6 NAND8 NOR2 NOR3 2NOR3 NOR4 NOR5 NOR6 NOR8 A2O21 O2A21 2A2O21 2O2A21 2ANOR 2ONAND Buffer driver Schmitt trigger Delay cell Dual driver Inverter, dual drive Inverter, quad drive Inverter, octal drive input NAND gate input NAND gate input NAND gate inverter Dual input NAND gate input NAND gate input NAND gate input NAND gate input NAND gate input gate input gate input gate inverter Dual input gate input gate input gate input gate input gate input input gate inverter input input NAND gate inverter Dual input input gate Dual input input NAND gate input ANDs input gate input input NAND gate
A2O31 O2A31 A3O21 O3A21 A4O21 O4A21 A2041 O2A41 3A2O31 3O2A31 O2A2O21 A2O2A21
input input gate input NAND gate input input gate input input NAND gate 4-input ANDs input gate 4-input input NAND gate 2-input input gate 2-input input NAND gate 2-input ANDs input gate 2-input input NAND gate input input input gate input input input NAND gate Exclusive gate NAND gate inverter Exclusive gate gate inverter input exclusive gate input exclusive gate Exclusive gate inverter Exclusive gate inverter input exclusive gate input exclusive gate input exclusive gate primitive Half adder inverter block block Carry block gate Carry block inverter Full adder gate Full adder Full adder multiplexer multiplexer multiplexer inverting multiplexer
EXOR EXNOR EXOR2 EXNOR2 EXN2 EXOR3 EXNOR3 EXPRIM HADD SUM2 CARRY CARRY2 FADD BMF1 BMF2 MUX2TO1 MUX4TO1 MUX8TO1 MUXI2TO1
CLA70000 Series
MUXI4TO1 MUXI8TO CLKA 2CLKA CLKAP CLKAM CLKB CLKBP CLKE1 CLKE2 CLKE3 2BDR DLRS DLARS DFRS MDFRS M3DF M3DF inverting multiplexer inverting multiplexer Basic clock driver Dual basic clock driver Basic clock driver inverter Basic clock driver inverter Large clock driver inverter Large clock driver inverter Clock driver with enable Clock driver with enable Clock driver with enable Buffered transmission gate Transmission gate multiplexing Internal driver Data latch Data latch Data latch with reset Data latch with reset Master-slave type flip flop Master-slave type flip flop with reset Multiplexed master-slave type flip flop Multiplexed master-slave type flip flop with reset Multiplexed type flip flop Multiplexed type flip flop with reset flip-flop flip-flop with reset JBAR-K flip-flop JBAR-K flip-flop with reset IBGATE IBCLKB IBDF IBDFA IBSK1 IBSK2 IBSK3 IBTRID IBTRID1 IBTRID2 IBTRID3 IB2BD DRV3 DRV6 NAND2/NOR2 gates Large clock driver Master-slave type flip flop Master-slave type flip flop Driver with slewed outputs Driver with slewed outputs Driver with slewed outputs Tri-state driver Tri-state driver with slewed outputs inverters Tri-state driver with slewed outputs inverters Tri-state driver with slewed outputs inverters Dual high powered inverters Clock driver Clock driver
Input Cells
IPNR IPR1P IPR1M IPR2P IPR2M IPR3P IPR3M IPR4P IPR4M Input cell with pull down resistors Input cell with 1KOhm pull resistor Input cell with 1KOhm pull down resistor Input cell with 2KOhm pull resistor Input cell with 2KOhm pull down resistor Input cell with 4KOhm pull resistor Input cell with 4KOhm pull down resistor Input cell with 75KOhm pull resistor Input cell with 75kOhm pull down resistor
JKRS JBARK JBARKRS BDLRS JBARKRS BDFRS
Oscillator Cells (crystal)
defined
Buffered data latch Buffered data latch with reset Buffered data latch with reset Buffered master-slave type flip-flop Buffered master-slave type flip-flop with reset BMDF Buffered mux. master-slave type flip-flop BMDFRS Buffered mux. type with reset BJBARK Buffered flip-flop BJBARKRS Buffered flip-flop with reset TRID Tristate driver Ground Cell Cell
Output Cells
OP12 OP5B OP11B OPT1 OPT2 OPT3 OPT6 OPT12 OP4B OP10B OPOD1 OPOD2 OPOD3 OPOD6 OPOD12 Smallest drive output cell Small drive output cell Standard drive output cell Medium drive output cell Large drive output cell Standard drive non-inverting output cell Large drive non-inverting output cell Smallest drive tri-state output cell Small drive tri-state output cell Standard drive tri-state output cell Medium drive tri-state output cell Large drive tri-state output cell Standard drive non-inverting tri-state output cell Large drive non-inverting tri-state output cell Smallest drive open-drain output cell Small drive open-drain output cell Standard drive open-drain output cell Medium drive open-drain output cell Large drive open-drain output cell
Intermediate Buffer Cells
IBCCMOS1 IBCCMOS2 IBTTL1 IBBTL2 IBST1 IBST2 CMOS input buffer large input NAND gate CMOS input buffer data latch input buffer large input NAND gate input buffer data latch Input Schmitt buffer with CMOS switching levels Input Schmitt buffer with switching levels
CLA70000 Series
Test Control Cells
OPOD5B OPOD11B Standard drive non-inverting open-drain output cell Large drive non-inverting open-drain output cell Smallest drive open-source output cell Small drive open-source output cell Standard drive open-source output cell Medium drive open-source output cell Large drive open-source output cell Standard drive non-inverting open-source output cell Large drive non-inverting open-source output cell JTAP JTCLK JTIDREG OPOS1 OPOS2 OPOS3 OPOS6 OPOS12 OPOS5B OPOS11B BIST JTAG Interface Controller PDS-BIST Clock Gating Buffer Cell PDS-BIST JTAG Identification Register
Test Register Component Cells
JTDUT Test register data (transparent) with update latch Test register data (transparent)] with update latch Test register data (transparent) Test register data (transparent) Test register data (clocked) with update latch Test register data (clocked) with update latch Test register data (clocked) Test register data (clocked) Test register local controller Test register driver 4-19 databits Test register driver 20-34 databits
JTDUF
JTDDT JTDDF JTCUT
Power Supply Cells
OPVP OPVM OPVPB OPVMB OPVPBB OPVMBB power (outputs) power (outputs) power (outputs) break power (outputs) break power (outputs) break power (outputs) break power (buffers) power (buffers) power (buffers) break power (buffers) break power (buffers) break power (buffers) break Power logic array
JTCUF
JTCDT JTCDF
IBVP IBVM IBVPB IBVMB IBVPBB IBVMBB
JTCT JTBF16 JTBF16
LAVP LAVM LAGND LAVDD
CLA70000 Macrocell Library Ripple Carry Adders
ADR1 ADR3 ADR8 ADR16 ADR24 ADR32 1bit adder adder adder adder adder adder
CLA70000 PDS-BIST (JTAG/IEEE1149-1) Library Test Register Cells
JTRDU4,8,16,24,32 4,8,16,24,32 Transparent Test registers with Update Latches 4,8,16,24,32 Transparent Test registers 4,8,16,24,32 Clocked Test registers with Update Latches 4,8,16,24,32 Clocked Test Registers
High Speed Carry Select Adders
ADS1 ADS3 ADS8 ADS16 ADS24 ADS32 1bit adder adder adder adder adder adder
JTRDD4,8,16,24,32
JTRCU4,8,16,24,32
JTRCD4,8,16,24,32
Carry Select Adders (Reduced Area)
ADT8 ADT16 ADT24 adder adder adder
CLA70000 Series
ADT32 adder BMB16X12 BMC24X24 BTHE1 BTHD1 BTHD2 Single pipeline multiplier bits) Mixed mode multiplier bits) Booth encoder Non-Inverting Booth decoder Inverting Booth decoder
Subtractor Blocks
ADSU4 ADSU8 ADSU16 ADSU24 ADSU32 subtractor add-on subtractor add-on subtractor add-on subtractor add-on subtractor add-on
Shifters Arithmetic Right (Padded with MSB)
SHA4 SHA8 SHA16 SHA24 SHA32 stage arithmetic right shifter stage arithmetic right shifter stage arithmetic right shifter stage arithmetic right shifter stage arithmetic right shifter
Many macro functions perform similar functions standard CMOS logic families. user warned, however, that logic functions differ slightly therefore recommended refer design manual rather than assume exact functional copy. simulator uses constituent microcell models circuit analysis. macrocells constructed from basic microcells placed routed give optimum chip area.
Shifters Barrel Right (Padded with Data Exiting Shifter)
SHB4 SHB8 SHB16 SHB24 SHB32 stage barrel right shifter stage barrel right shifter stage barrel right shifter stage barrel right shifter stage barrel right shifter
MACRO
FUNCTION
Adders
ADA4 ADG4 binary full adders with fast carry Look ahead carry generator
Counters Shifters Logic Right/Left (Padded with Zero's)
SHL4 SHL8 SHL16 SHL24 SHL32 stage logic right shifter stage logic right shifter stage logic right shifter stage logic right shifter stage logic right shifter CNA4 CNB4 CNC4 CND4 CND4A CNE4 CNF4 CNG4 counter/4 latch decoder/driver counter latch synchronous counter binary up/down Synchronous counter binary up/down counter with reset decade counter binary synchronous counter binary counter
Logic Units Function)
FGLO4 FGLO8 FGLO16 FGLO24 FGLO32 logic unit logic unit logic unit logic unit logic unit
Decoders
DRA3T8 DRA4T16 DRA4T16A DRB3T8 DRB3T8 DRD2T4 DRF4T10 DRG4T10 DRH4T10 DRI10 DRJ7 DRK7 DRL7 line line decoder/demultiplexer line line decoder/demultiplexer line line decoder/demultiplexer enable line line decoder/demultiplexer with address registers line line decoder/demultiplexer with address latches line line decoder line line decoder line line excess decimal decoder line line excess gray decimal decoder decoder decimal decoder/driver segment decoder/driver segment decoder/driver segment decoder/driver
Arithmetic Units Function)
FGAR4 FGAR8 FGAR16 FGAR24 FGAR32 logic unit logic unit logic unit logic unit logic unit
CLA70000 Macrocell Library Multiplers Associated Cells
BMA8X8 BMA16X16 BMA24X24 Mixed mode multiplier bits) Mixed mode multiplier bits) Mixed mode multiplier bits)
CLA70000 Series
Encoders
ENA8T3 ENB10T4 line line priority encoder line line priority encode SRB8A SRC8 SRD4 SRE4 SRF8 PISO shift register without clear PISO shift register with clear SIPO shift register with clear PIPO shift register with JKbar input shift store register with tristate outputs bidirectional universal shift register parallel access shift register shift register
Flip-Flop
FFA8 FFB6 FFC4 FFD8 bistable latches D-type flip-flop with clear D-type flip-flop with clear complimentary outputs Octal D-type flip-flop with clear
SRG4 SRJ4 SRK5
Process Monitor
PERF Performance monitor
ALU/Functional Generator
FGA5 ALU/function generator
BIST
RGBIT RGTBIT RGDIAG RGCTL RGHOLD Test register (one bit) Test register (one monitor bit) Diagnostic control unit Test register controller Test register hold circuitry
Adders
MCA4 magnitude comparators
Multiplers
MLA10 MLB4X4 Decade rate multiplier binary multiplier with tristate outputs Wallace trees with tristate outputs
(early built self test cells) CLA7BIST Library
CLA70000 Paracell Library Memory Cells
RBRAM 16384 bits block WORDS 2:128, bits 1:128 (min:max) 65536 bits block WORDS 2:2048, bits 2:64 (min:max)
MLW7
Multiplexors
MXA8T1 MXB4T1 MXB4T1A line line data selector multiplexer Dual line line data selector multiplexers Dual line line data selector multiplexer with inverted tristate outputs Quad data selector multiplexers Quad selector (inverted outputs) multiplexor with strobe multiplexor with strobe multiplexeor with storage
ROROM
MXC2T1 MXC2T1A MXD4T1 MXE4T1 MXF2T1
Parity Generator
PGA9 odd/even parity generator/checker
Shift Registers
SRA2 SRA4 SRA8 SRA8A SRB2 SRB4 SRB8 shift register with clear shift register with clear SIPO shift register with clear SIPO shift register without clear PISO shift register with clear PISO shift register with clear PISO shift register with clear
CLA70000 Series
Design Support Interfaces
Flexible design route approach Design center engineer assigned every customer circuit Full turnkey service capability check agree performance, packaging, specifications design timescales. Review Held after Logic Simulation prior Layout Checks ensure satisfactory functionality, timing performance, adequate fault coverage. Review Held after Layout Post Layout Simulation Verification satisfactory design performance after insertion actual track loads. Final check device specifications before prototype manufacture. Review Held after Prototype Delivery Confirm that devices meet specifications suitable full scale production.
Design layout support CLA70000 arrays available from various centers worldwide each which connected Headquarters high speed data links. design center engineer assigned each customer's circuit, ensure good communication smooth efficient design flow. should noted that sign-off simulation against 'golden' simulator also supported local design centers. Zarlink Semiconductor offers variety formal design routes illustrated table below. Differing interface methods allow varying levels involvement manner which complements individual customer design styles, whilst maintaining responsibility ensure first time working devices. part design process Zarlink Semiconductor operates thorough design audit procedure verify compliance with customer specification ensure manufacturability. procedure includes four separate review meetings, with customer, held stages design. Review Held beginning design cycle
Design Tools
focus Zarlink Semiconductor design tool methodology that maintaining open system with interfaces standardized EDIF This enables provide full support variety party ASIC design tools facilitates rapid updating associated libraries. also provides interface Zarlink Semiconductor (PDS2)
SUPPORT
Design Routes
THIRD PARTY SOFTWARE
OPTIONS
Design Review Schematic Capture Logical Design Design Review Physical Design Design Review Prototype Manufacturing Prototype Evaluation Design Review Production CUSTOMER CUSTOMER CUSTOMER CUSTOMER CUSTOMER
IN-HOUSE SOFTWARE
TURNKEY SERVICE
CUSTOMER
CUSTOMER
CUSTOMER
CLA70000 Series
design system, which offers total design environment including behavioral functional level modelling.
Specifications
Thermal Management
Third Party Software Support
Design Kits major industry standard ASIC design software tools libraries include fully detailed timing information EDIF Interface Post layout back annotation available Lower power CMOS better thermal management Improved reliability Power packages available
Zarlink Semiconductor supports wide range third party design tools including IKOS, Mentor, Verilog, Viewlogic time printing. Please check with Sales Offices most recent additions. design kits offer fully detailed timing information cell libraries, netlist extraction utilities, post layout back annotation capability where applicable. example workstation design flow shown below. Please contact your local Zarlink Semiconductor's sales office further information about support particular tools.
WORKSTATION ENVIRONMENT ENVIRONMENT
increase speed density available through CMOS process geometry reduction, results corresponding increase power dissipation. SemiCustom designers have ability design circuits 100,000 gates over, chip power consumption should very important concern. logic core 100K plus gates dominant factor power dissipation this complexity. essential offer ultra power core logic maintain acceptable overall chip power budget. minimize this problem Zarlink Semiconductor's CLA70000 arrays offer power factors selection power packages. Dissipation gate gate power gate load, lower than most competitive arrays, with reduced junction temperatures having added advantage improved performance reliability.
Schematic Symbols
Schematic Capture
Netlist Translation Back Annotation
Place Route
Libraries
Simulation Models
CLA70000 POWER DISSIPATION CALCULATION
Design Verification
Simulation Test Vector Generation
Vector Translation Test Program Generation
CLA70000 series power dissipation array estimated following example (calculated CLA76XXX) below. Number available gates Assume percent gates used Number used gates (110102 0.4) Assume gates switching during. each clock cycle (44045 0.15) Power dissipation/gate/Mhz (gate fanout typically loads) Total core dissipation/Mhz (6607 0.007) Number available pads Percent pads used Outputs Number pads used Outputs Number output buffers switching each clock cycle (20%) Dissipation/output buffers/Mhz/pF Output loading Power/output buffer/Mhz Total output buffer dissipation/Mhz Total Power dissipation/Mhz 110112 44045 6607 46.2 25µW 1.25mW 20mW 66.2mW
Figure Workstation Design Flow
PDS2 Zarlink Semiconductor ASIC Design System
Behavioral, Functional, Gate Level Modelling VHDL Third Party Links Supports Hierarchical Design Techniques EDIF Interface PDS2 Zarlink Semiconductor's proprietary ASIC design system. provides fully-integrated, technology independent VLSI design environment Zarlink Semiconductor CMOS SemiCustom products. PDS2 runs Digital Equipment Computers self configuring according available machine resources. comprises design capture (schematic capture VHDL), testability analysis, logic simulation, fault simulation, auto place route, back annotation. system offers full support hierarchical design techniques, maintained from design capture through layout, well advanced design management tools. PDS2 used either Zarlink Semiconductor Design Center under licence customer's premises. three training course available first time users.
Estimated dissipation circuit frequencies below Total Power clock rate Total Power 25Mhz clock rate 0.66W 1.65W
CLA70000 Series
Characteristics Selected Cells
CLA70000 technology library contains timing information each cell design library. This information accessible simulator, which calculates propagation delays signal paths circuit design. simulator automatically derate timings according various factors such Supply voltage variation (from nominal Junction temperature Processing tolerance manufacturing spreads Gate fanout logic loading gate outputs Interconnection wiring loading gate outputs initial assessments feasibility, path delay multipliers estimated referring following graphs conjunction with appropriate delays tables.
Normalised Delay Multiplier temperature
Delay Multiplier (normalised 25°C)
Temperature
Figure
Normalised Delay Multiplier Voltage
Delay Multiplier (normalised
Voltage
FIgure
CLA70000 Series
Charcteristics
Typical Worst case propagation Delay (ns) Commercial Fanout 0.70 0.47 1.01 0.79 1.30 0.57 1.40 1.44 0.84 0.56 1.29 1.04 1.81 0.80 1.60 1.55
INTERNAL CORE CELLS
Name Cells Description Symbol
Propagation Delay (ns) Fanout
INV2
tpLH Invertor Dual Drive tpHL
0.27 0.18 0.39 0.30 0.50 0.22 0.54 0.55
NAND2
2-Input NAND Gate
tpLH tpHL
NOR2
2-Input Gate
tpLH tpHL
Master Slave D-Type Flip-Flop
tpLH tpHL
Typical
Worst case propagation Delay (ns) Commercial Fanout 0.88 0.71 1.24 1.31 1.58 1.17 1.02 0.84 1.44 1.42 1.68 1.21
INTERMEDIATE BUFFER CELLS
Name Cells Description Symbol
Propagation Delay (ns) Fanout
IBGATE
Large Input NAND Gate Input Master Slave D-type Flip-Flop
tpLH tpHL tpLH tpHL tpLH tpLH
0.34 0.27 0.48 0.50 0.60 0.45
IBDF
IBCMOS1
CMOS input buffer with input NAND gate
Typical
Worst case propagation Delay (ns) Commercial Fanout 10pF 1.90 1.27 1.30 0.85 0.99 0.66 50pF 6.49 4.40 3.59 2.42 2.14 1.50 10pF
OUTPUT BUFFER CELLS
Name Cells Description Standard Output Buffer Medium Output Buffer Large Output Buffer Symbol tpLH tpHL tpHL tpLH tpLH tpHL
Propagation Delay (ns) Fanout =10pF 0.73 0.49 0.50 0.33 0.38 0.25
OP12
Note Commercial worst case 4.5V, 70°C operating Industrial worst case 4.5V, 85°C operating
CLA70000 Series
Electrical Characteristics
characteristics Commercial Grade voltage temperature (note1) Characteristic Symbol
Level Input Voltage Inputs (IBTTL1/IBTTL2) CMOS Inputs (IBCMOS1/IBCMOS2) High Level Input Voltage Inputs (IBTTL1/IBTTL2) CMOS Inputs (IBCMOS1/IBCMOS2) Input Hysterisis (IBST1) (IBST2) Rising Falling Rising Falling Input Current CMOS/TTL Inputs (without resistor) Inputs with resistor Inputs with resistor Inputs with resistor Inputs with resistor Resistor values nominal (note2) High Level Output Voltage Outputs Smallest drive cell OP1/OPOS1/OPT1 drive cell OP2/OPOS2/OPT2 Standard drive cell OP3/OPOS3/OPT3 Medium drive cell OP6/OPOS6,OPT6 Large drive cell OP12/OPOS12/OPT12 Level Output Voltage Outputs Smallest drive cell OP1/OPOD1/OPT1 drive cell OP2/OPOD2/OPT2 Standard drive cell OP3/OPOD3/OPT3 Medium drive cell OP6/OPOD6,OPT6 Large drive cell OP12/OPOD12/OPT12 Tristate Output Leakage Current
-1.00 VSS+0.05 0.20 0.20 0.20 0.20 0.20 1.00 67.00 37.00 IDDOP 135.00 75.00 1.00 5.00 5.00 7.00 270.00 150.00 µA/MHz Inputs (note Outputs (note (note DD=MAX out=V DD=MAX OH=V 0.40 0.40 0.40 0.40 0.40 IOL=1.00µA IOL=2.00mA IOL=4.00mA IOL=6.00mA IOL=12.00mA IOL=24.00mA -1.00 -1.00 -0.05 -0.50 =-1.00µA =-2.00mA =-4.00mA =-6.00mA =-12.00mA =-24.00mA VTVT+ VTIIN -1.00 ±2.20 ±1.10 ±0.56 ±18.00 ±5.00 ±2.50 ±1.25 ±66.00 3.09 1.89 1.72 1.10 +1.00 ±11.00 ±5.50 ±2.75 ±275.00 IN=V IN=V IN=V IN=V IN=V 2.00 -1.00 0.80 1.00
Min. Typ.
Max.
Units Conditions
-1.00 -0.50 -1.00 -0.50 -1.00 -0.50
-0.50
Output short Circuit Current Standard output OP3/OPT3/OPOD3 (Note OP3/OPT3/OPOS3 Operating Supply Current (per gate) (note4) Input Capacitance Output Capcitance Bidirectional Capacitance
Notes
Commercial grade power supply voltage Resistor value spreads (Min-Max): Value (Rtyp 0.5-2K High Value (Rtyp 2K-8K Value (Rtyp 1.0-4K High Value (Rtyp 75K) 20K-250K Standard driver output etc. Short circuit current other outputs will scale. more than output shorted time maximum duration second.
Excluding peripheral buffers. Excludes package leadframe capacitance bi-directional pins. Excludes package.
PACKAGING
CLA70000 Series
Wide range surface mount through board packages Ceramic equivalents most plastic packages fast prototyping Ongoing commitment package development
Production quantities CLA70000 family available industry-standard ceramic plastic packages according codes shown below. Prototype samples normally supplied ceramic only.
DILMON CERDIP PLASDIP P.G.A. POWER P.G.A. SMALL OUTLINE (S.O.) LEADED CHIP CARRIER LEADED CHIP CARRIER POWER LEADED CHIP CARRIER QUAD CERPAC CERAMIC QUAD FLATPACK PLCC PQFP Dual Line, Multilayer ceramic. Brazed leads Metal Sealed Lid. Through Board Dual Line, Ceramic body, Alloy leadframe, Glass Sealed, Through Board Dual Line, Copper Alloy leadframe, Plastic Moulded. Through Board Grid Array, Multilayer Ceramic. Metal Sealed lid. Through Board above with cavity down Cu/W heat plate Dual Line, 'Gullwing' Formed Leads. Plastic Moulded Surface Mount Leadless Chip Carrier. Multilayer Ceramic. Metal Sealed Lid. Surface Mount Quad Multilayer Ceramic. Brazed Formed Leads. Metal Sealed Lid. Surface Mount Quad Multilayer Ceramic. Brazed Leads. Metal Sealed Lid. Surface Mount above with cavity down, Cu/W heat plate Quad Ceramic Body, Formed Leads. Glass Sealed. Surface Mount. Quad Ceramic Body, `Gullwing' Formed Leads. Glass Sealed. Surface Mount. Quad Plastic Leaded Chip Carrier. Formed Leads. Plastic Moulded. Surface Mount Plastic Quad Flat Pack. `Gullwing' Formed Leads. Plastic Moulded. Surface Mount
Packaging Options
package style count information intended only guide. Detailed package specification available from Zarlink Semiconductor Design Centers request. Available packages being continuously updated, particular package listed, please enquire through your Zarlink Semiconductor Sales Representative.
CLA70000 Array Package Guide
AVAILABLE ARRAY PACKAGE COMBINATIONS. PROTOTYPES ONLY
PLASTIC QUAD FLAT PACK (GP)
GP44 GP52 GP64 GP80 GP100 GP120 GP144 GP160 1734 1734 1751 1756 1733 1710 1756 1733 1644 1755 1643 1644 1730 1643 1644 1730 1729 1758 1715 1715
CERAMIC QUAD FLAT PACK (GG)
GG44 GG52 GG64 GG80 GG100 GG120 GG144 GG160 1735 1735 1800 1773 1740 1800 1773 1740 1675 1773 1740 1675 1736 1771 1675 1736 1737 1770 1769* 1769
CLA70000 Series
PLASTIC SMALL OUTLINE (MP)
MP16L MP20 MP24 MP28 1575 1583 1587 1768
MC16 MC20 MC24 MC28
CERAMIC SMALL OUTLINE (MC)
1697 1698 1699 1700
PLASTIC LEADED CHIP CARRIER (HP)
HP28 HP44 HP68 HP84 1613 1490 1613 1490 1659 1490 1659 1660 1659 1660 HC28 HC44 HC68 HC84
CO-FIRED CERAMIC LEADED CHIP CARRIER (HC)
1624 1630 1625 1630 1625 1626 1621 1626
1624 1630
GLASS SEALED CERAMIC LEADED CHIP CARRIER (HG)
HG28 HG44 HG68 HG84 1560 1562 1560 1562 1564 1562 1564 1567 1564 1567
CERAMIC LEADLESS CHIP CARRIER (LC)
LC28 LC44 LC68 LC84 1450 1454
1450 1454
1365 1433 1455 1433 1455
CERAMIC LEADED CHIP CARRIER (GC)
GC132 GC172 GC196 1662 1668 1669 1672 1680
POWER CERAMIC LEADED CHIP CARRIER (GC)
GC132 GC172 GC196 GC256 1763 1762 1739
PLASTIC DUAL LINE (DP)
DP16 DP22 DP24 DP28 DP40 DP48 1558 1513 1516 1522 1524 1485 1513 1517 1522 1524 1485 1517 1522 1525 1485
CERAMIC DUAL LINE (DC)
DC16 DC22 DC24 DC28 DC40 DC48 1427 1396 1321 1348 1620 1470 1396 1321 1348 1620 1470 1321 1348 1620 1470
CLA70000 Series
CERAMIC GRID ARRAY (AC)
AC68 AC84 AC100 AC120 AC132 AC144 AC180 AC257 1462 1462 1479 1479 1480 1481 1466 1467 1483 1484 1469 1764
POWER CERAMIC GRID ARRAY (AC)
AC84 AC144 AC208 1692 1693
Quality Reliability
Statistical process control used manufacture Regular sample screening reliability testing Screening Industrial standards available
Quality reliability built into product statistical control processing operations minimizing random uncontrolled effects manufacturing operations. Process management involves full documentation procedures, recording batch-by-batch data, using traceability procedures provision appropriate equipment facilities perform sample screening conformance testing finished product. common information management system used monitor manufacturing Zarlink CMOS Bipolar processes. products benefit from this integrated monitoring system throughout manufacturing operations leading high quality standards technologies.
http://www.zarlink.com
World Headquarters Canada Tel: (613) 0200 Fax: (613) 1010
North America West Coast Tel: (858) 675-3400 Fax: (858) 675-3450
North America East Coast Tel: (978) 322-4800 Fax: (978) 322-4888
Asia/Pacific Tel: 6193 Fax: 6192
Europe, Middle East, Africa (EMEA) Tel: 1793 518528 Fax: 1793 518581
Information relating products services furnished herein Zarlink Semiconductor Inc. trading Zarlink Semiconductor subsidiaries (collectively "Zarlink") believed reliable. However, Zarlink assumes liability errors that appear this publication, liability otherwise arising from application such information, product service infringement patents other intellectual property rights owned third parties which result from such application use. Neither supply such information purchase product service conveys license, either express implied, under patents other intellectual property rights owned Zarlink licensed from third parties Zarlink, whatsoever. Purchasers products also hereby notified that product certain ways combination with Zarlink, non-Zarlink furnished goods services infringe patents other intellectual property rights owned Zarlink. This publication issued provide information only (unless agreed Zarlink writing) used, applied reproduced purpose form part order contract regarded representation relating products services concerned. products, their specifications, services other information appearing this publication subject change Zarlink without notice. warranty guarantee express implied made regarding capability, performance suitability product service. Information concerning possible methods provided guide only does constitute guarantee that such methods will satisfactory specific piece equipment. user's responsibility fully determine performance suitability equipment using such information ensure that publication data used date been superseded. Manufacturing does necessarily include testing functions parameters. These products suitable medical products whose failure perform result significant injury death user. products materials sold services provided subject Zarlink Semiconductor's conditions sale which available request.
Purchase Zarlink's components conveys licence under Philips Patent rights these components System, provided that system conforms Standard Specification defined Philips
Zarlink Zarlink Semiconductor logo trademarks Zarlink Semiconductor Inc. Copyright 2001, Zarlink Semiconductor Inc. rights reserved.
TECHNICAL DOCUMENTATION RESALE

High Density CMOS Gate Arrays DS2462 ISSUE March 1992

Top Searches for this datasheet

Other recent searches