MC68060 MC68LC060 MC68EC060 Superscalar 32-Bit Microprocessors
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MC68060 MC68LC060 MC68EC060
Superscalar 32-Bit Microprocessors
superscalar M68060 represents line Motorola microprocessor products. first generation M68060 product line consists MC68060, MC68LC060, MC68EC060. three microprocessors offer superscalar integer performance over MIPS MHz. MC68060 comes fully equipped with both floating-point unit (FPU) memory management unit (MMU) high-performance embedded control desktop applications. cost-sensitive embedded control desktop applications where required, additional cost justified, MC68LC060 offers high performance cost. Specifically designed low-cost embedded control applications, MC68EC060 eliminates both MMU, permitting designers leverage MC68060 performance while avoiding cost unnecessary features. Throughout this product brief, references MC68060 also refer MC68LC060 MC68EC060, unless otherwise noted. Figure illustrates block diagram MC68060.
EXECUTION UNIT INSTRUCTION FETCH UNIT CALCULATE INSTRUCTION FETCH EARLY DECODE
BRANCH CACHE
INSTRUCTION
INSTRUCTION CACHE ADDRESS
INSTRUCTION CACHE CONTROLLER INSTRUCTION MEMORY UNIT
INSTRUCTION BUFFER pOEP FLOATINGPOINT UNIT FETCH EXECUTE DECODE CALCULATE FETCH EXECUTE sOEP DECODE CALCULATE FETCH EXECUTE
DATA DATA CACHE DATA CACHE CONTROLLER
DATA
INTEGER UNIT
CONTROL
DATA AVAILABLE WRITE-BACK
DATA MEMORY UNIT
OPERAND DATA
Figure MC68060 Block Diagram
This document contains information product under development. Motorola reserves right change discontinue this product without notice.
SEMICONDUCTOR PRODUCT INFORMATION
MOTOROLA, 1994
Leveraging many same performance enhancements used RISC designs well providing innovative architectural techniques, MC68060 harnesses levels performance M68000 family. Incorporating million transistors single piece silicon, MC68060 employs deep pipeline, dual issue superscalar execution, branch cache, high-performance floating-point unit (MC68060 only), eight Kbytes each on-chip instruction data caches, dual on-chip demand paging MMUs (MC68060 MC68LC060 only). MC68060 allows simultaneous execution integer instructions integer floating-point instruction) branch instruction during each clock. MC68060 features full internal Harvard architecture. instruction data caches designed support concurrent instruction fetch, operand read, operand write references every clock. Separate 8Kbyte instruction 8-Kbyte data caches frozen prevent allocation over time-critical code data. independent nature caches allows instruction stream fetches, data-stream fetches, external accesses occur simultaneously with instruction execution. operand data cache four-way banked permit simultaneous read write access each clock. very high bandwidth internal memory system coupled with compact nature M68000 family code allows MC68060 achieve extremely high levels performance, even when operating from low-cost memory such 32-bit wide dynamic random access memory system. Instructions fetched from internal cache external memory four-stage instruction fetch pipeline. MC68060 variable-length instruction system internally decoded into fixed-length representation channeled into instruction buffer. instruction buffer acts FIFO which provides decoupling mechanism between instruction fetch unit operand execution units. Fixed format instructions dispatched dual four-stage pipelined RISC operand execution engines where they then executed. branch cache also plays major role achieving high performance levels MC68060. been implemented such that most branches executed zero cycles. Using technique known branch folding, branch cache allows instruction fetch pipeline detect change instruction prefetch stream before change flow affects instruction execution engines, minimizing need pipeline refill. addition substantial cost performance benefits, MC68060 also offers advantages power consumption power management. MC68060 automatically minimizes power dissipation using fully-static design, dynamic power management, low-voltage operation. automatically powers-down internal functional blocks that needed clock-by-clock basis. Explicitly, MC68060 power consumption controlled from operating system. Although MC68060 operates lower operating voltage, directly interfaces both peripherals logic. Complete code compatibility with M68000 family allows designer draw existing code past experience bring products market quickly. There also broad base established development tools, including real-time kernels, operating systems, languages, applications, assist product design. functionality provided MC68060 makes ideal choice range high-performance embedded applications computing applications. With M68000 family code compatibility, MC68060 provides range upgrade opportunities virtually existing MC68040 application.
MC68060 PRODUCT INFORMATION
MOTOROLA
following list primary featuresof MC68060: Fully User-Code Compatible with MC68040 Superscalar Implementation M68000 Architecture Dual Integer Instruction Execution Improves Performance Branch Cache Reduces Branches Zero Cycles Executes Three Instructions Clock Dual 8-Kbyte On-Chip Caches Separate Data Instruction Caches Simultaneous Access Data Cache Four-Way Banked Allow Read Write Access Each Clock Snooping Independent Instruction Data Paged MMUs (MC68060 MC68LC060 Only) Full 32-Bit Nonmultiplexed Address Data Optimized Achieve Very High Performance Using 32-Bit Memory System Operate 1/2-or 1/4-Speed Internal Clock 32-Bit Maximizes Data Throughput Nonmultiplexed Simplifies Design Four-Deep Store Buffer One-Deep Push Buffer Maximize Write Bandwidth MC68040-Compatible Provides Simple Hardware Migration Path Power Management Automatic Power-Down Unused Blocks Logic Clock-by-Clock Basis Low-Voltage Operation with 3.3-V Capability LPSTOP Mode Provides Idle State Lowest Standby Current Static CMOS Technology Reduces Power Normal Operation IEEE-Compatible On-Chip (MC68060 Only) Available 40-MHz (MC68EC060 only), 50-MHz, 66-MHz Speeds Packaging Ceramic Grid Array (PGA) Ceramic Quad Flat Pack (CQFP) (THIS PACKAGE AVAILABLE 3/25/98)
MOTOROLA
MC68060 PRODUCT INFORMATION
MC68060 SIGNALS
Figure shows MC68060 functional signal groups.
ADDRESS CONTROL
A31-A0
SNOOP
SNOOP CONTROL
DATA
D31-D0
ARBITRATION CONTROL
TRANSFER ATTRIBUTES
TLN1 TLN0 UPA1 UPA0 SIZ1 SIZ0 LOCK LOCKE CIOUT
CDIS MDIS RSTI RSTO IPL2 IPL1 IPL0 IPEND AVEC PST4 PST3 PST2 PST1 PST0 CLKEN JTAG TRST THERM1 THERM0
PROCESSOR CONTROL
INTERRUPT CONTROL
MC68060
STATUS CLOCKS
MASTER TRANSFER CONTROL
TEST
SLAVE TRANSFER CONTROL
THERMAL RESISTOR CONNECTIONS POWER SUPPLY
Figure Functional Signal Groups
MC68060 PRODUCT INFORMATION
MOTOROLA
EXECUTION UNIT
MC68060 execution unit carries logical arithmetic operations. execution unit contains instruction fetch unit, integer unit, branch cacheand floating-point unit. superscalar design MC68060 provides dual execution pipelines instruction integer unit, providing simultaneous instruction execution. superscalar operation execution unit disabled software, turning second execution pipeline debugging. Disabling superscalar operation also lowers power consumption.
INSTRUCTION FETCH UNIT
instruction fetch unit contains instruction fetch pipeline logic that interfaces branch cache. instruction fetch pipeline consists four stages, providing ability prefetch instructions advance their actual instruction execution controller. continuous fetching instructions keeps instruction execution unit busy greatest possible performance. Every instruction passes through each four stages before entering integer unit. four stages instruction fetch pipeline are: Instruction Address Calculation-The virtual address instruction determined. Instruction Fetch-The instruction fetched from memory. Early Decode-The instruction pre-decoded into fixed length format pipeline control information. Instruction Buffer-The instruction pipeline control information buffered until integer execution pipeline ready process instruction.
BRANCH CACHE
branch cache plays major role achieving performance levels MC68060. concept branch cache provide mechanism that allows instruction fetch pipeline detect change instruction stream before change flow affects integer unit. branch cache examined valid branch entry after each instruction fetch address generated instruction fetch pipeline. does occur branch cache, instruction fetch pipeline continues fetch instructions sequentially. occurs branch cache, indicating branch taken instruction, current instruction stream discarded instruction stream fetched starting location indicated branch cache.
INTEGER UNIT
integer unit contains dual integer execution pipelines, interface logic (MC68060 only), control logic data written data cache MMU. superscalar design dual integer execution pipelines provides simultaneous instruction execution, which allows processing more than instruction during each machine clock cycle. effect this software-invisible pipeline capable sustained execution rates less than machine clock cycle instruction M68000 instruction set.
MOTOROLA
MC68060 PRODUCT INFORMATION
integer unit control logic pulls instruction pair from instruction buffer every machine clock cycle, stopping only instruction information available integer execution pipeline hold condition exists. stages dual integer execution pipelines are: Instruction Decode-The instruction fully decoded. Effective Address Calculation-If instruction calls data from memory, location data calculated. Effective Address Fetch-Data fetched from memory location. Integer Execution-The data manipulated during execution. Data Available-The result available. Write-Back-The resulting data written back on-chip caches external memory. MC68060 optimized most integer instructions execute machine clock cycle. during instruction decode stage instruction determined floating-point instruction, will passed after effective address fetch stage. data written either on-chip caches external memory after instruction execution, write-back stage holds data until memory ready receive Temporarily holding data write-back stage adds overall performance MC68060 slowing down pipeline operations. MC68060 implements practically MC68040 instructions addressing modes hardware highest performance. However, optimize silicon usage, very infrequently used integer instructions fully implemented hardware. These instructions emulated software using M68060SP which available free from Motorola. This software package assures full binary compatibility. Since these instructions appear very infrequently instruction stream, software emulation instructions provides noticeable loss performance.
FLOATING-POINT UNIT (MC68060 ONLY)
Floating-point math distinguished from integer math, which deals only with whole numbers fixed decimal point locations. IEEE-compatible MC68060 computes numeric calculations with variable decimal point location. MC68060 features built-in that MC68040 MC68881/882 compatible. Consolidating this important function on-chip speeds overall processing eliminates interfacing overhead associated with external accelerators. MC68060 operates parallel with integer unit. performs numeric calculations while integer unit continues integer processing. been optimized most frequently used instructions data types provide highest possible performance. also disabled software reduce system power consumption. MC68060 implements most frequently used M68000 family floating-point instructions, data types, data formats hardware highest performance. remaining instructions emulated software with M68060SP provide complete IEEE compatibility. M68060SP provides following features: Arithmetic Transcendental Instructions IEEE-Compliant Exception Handlers Unimplemented Data Type Data Format Handlers
MC68060 PRODUCT INFORMATION
MOTOROLA
MEMORY MANAGEMENT UNITS
(MC68060 MC68LC060 ONLY)
MC68060 contains independent instruction data MMUs. Each contains cache memory called address translation cache (ATC). full addressing range MC68060 four Gbytes (4,294,967,296 bytes). Even though most MC68060 systems implement much smaller physical memory, using virtual memory techniques, system appear have full four Gbytes physical memory available each user program. Each fully supports demand-paged virtual-memory operating systems with either 8Kbyte page sizes. Each protects supervisor areas from accesses user programs provides write protection page-by-page basis. maximum efficiency, each operates parallel with other processor activities. MMUs disabled emulator debugging support. 64-entry, four-way, set-associative ATCs store recently used logical-to-physical address translation information page descriptors instruction data accesses. Each initiates address translation searching descriptor containing address translation information ATC. descriptor does reside ATC, performs external cycles through controller search translation tables physical memory. After being located, page descriptor loaded into ATC, address correctly translated access.
INSTRUCTION DATA CACHES
Studies have shown that typical programs spend much their execution time main routines tight loops. Earlier members M68000 family took advantage this locality-of-reference phenomenon varying degrees. MC68060 takes further advantage cache technology with two, independent, onchip physical caches, instructions data. caches reduce processor's external activity increase throughput lowering effective memory access time. typical system design, large caches MC68060 yield very high rate, providing substantial increase system performance. autonomous nature caches allows instruction-stream fetches, data-stream fetches, external accesses occur simultaneously with instruction execution. example, MC68060 requires both instruction access external peripheral access instruction resident on-chip cache, peripheral access proceeds unimpeded rather than being queued behind instruction fetch. data operand also required resident data cache, accessed without hindering either instruction access external peripheral access. parallelism inherent MC68060 also allows multiple instructions that require external accesses execute concurrently while processor performing external access previous instruction. Each MC68060 cache eight Kbytes accessed physical addresses. data cache configured write-through deferred copyback page basis. This choice allows optimizing system design high performance when deferred copyback used. Cachability data each memory page controlled bits page descriptor. Cachable pages either write-through copyback, with write-allocate misses write-through pages. MC68060 implements four-entry write buffer that maximizes system performance decoupling integer pipeline from external system bus. When needed, write buffer allows pipeline generate writes every clock cycle, even system runs slower speed than processor.
MOTOROLA
MC68060 PRODUCT INFORMATION
CACHE ORGANIZATION
instruction data caches each organized four-way associative, with 16-byte lines. Each line data associated with address state information that shows line's validity. data cache, state information indicates whether line invalid, valid, dirty.
CACHE COHERENCY
MC68060 ability watch, snoop, external during accesses other masters, maintaining coherency between MC68060 caches external memory systems. External cycles flagged snoopable nonsnoopable. When external cycle marked snoopable, snooper checks caches invalidates matching data. Although execution unit snooper circuit have access on-chip caches, snooper priority over execution unit.
CONTROLLER
implemented nonmultiplexed, fully synchronous protocol that clocked rising edge input clock. compatible with MC68040 bus. controller operates concurrently with other functional units MC68060 maximize system throughput. timing fully configurable match external memory requirements. CLKEN input used MC68060 enable clock edges which controller will respond. toggling CLKEN pin, possible operate MC68060 external speed processor clock. Although MC68060 compatible with MC68040, additional signals protocols have been added simplify designs requiring very high speeds.
IEEE 1149.1 TEST
system diagnostics, MC68060 includes dedicated user-accessible test logic that fully compliant with IEEE 1149.1 standard boundary scan testability, often referred Joint Test Action Group (JTAG).
MC68060 PRODUCT INFORMATION
MOTOROLA
POWER MANAGEMENT
MC68060 very power efficient static logic power management designed into basic architecture. Each stage integer unit pipelines pipeline draws power only when instruction executing, cache arrays draw power only when access made. FPU, secondary integer execution pipeline, branch cache, instruction data caches disabled reduce overall power usage. 3.3-V power supply reduces current consumption 40-60% over that microprocessors using power supply. MC68060 additional methods dynamically controlling power consumption during operation. Running special LPSTOP instruction shuts down active circuits processor, halting instruction execution. Power consumption this standby mode greatly reduced. Processing resumed resetting processor generating interrupt. frequency operation lowered reduce current consumption while device LPSTOP mode.
PHYSICAL
MC68060 available ceramic CQFP packaging configurations. parts operate from power supply directly interface peripherals logic. following table identifies operating frequencies available various M68060 microprocessors.
Processor MC68060 MC68LC060 MC68EC060
documents listed following table contain detailed information MC68060. These documents obtained from Literature Distribution Centers addresses listed back page.
Document Title
Order Number M68060UM/AD M68000PM/AD BR729/D BR1407/D
Contents Detailed information design M68000 Family Instruction Independent vendor listing supporting software development tools voltage interface components
M68060 User's Manual M68000 Family Programmer's Reference Manual Source Volt Logic Interface Circuits
MOTOROLA
MC68060 PRODUCT INFORMATION
Motorola reserves right make changes without further notice products herein. Motorola makes warranty, representation guarantee regarding suitability products particular purpose, does Motorola assume liability arising application product circuit, specifically disclaims liability, including without limitation consequential incidental damages. "Typical" parameters vary different applications. operating parameters, including "Typicals" must validated each customer application customer's technical experts. Motorola does convey license under patent rights rights others. Motorola products designed, intended, authorized components systems intended surgical implant into body, other applications intended support sustain life, other application which failure Motorola product could create situation where personal injury death occur. Should Buyer purchase Motorola products such unintended unauthorized application, Buyer shall indemnify hold Motorola officers, employees, subsidiaries, affiliates, distributors harmless against claims, costs, damages, expenses, reasonable attorney fees arising directly indirectly, claim personal injury death associated with such unintended unauthorized use, even such claim alleges that Motorola negligent regarding design manufacture part. Motorola registered trademarks Motorola, Inc. Motorola, Inc. Equal Opportunity/Affirmative Action Employer.
Literature Distribution Centers:
USA: Motorola Literature Distribution; P.O. 20912, Arizona 85036. EUROPE: Motorola Ltd.; European Literature Centre; Tanners Drive, Blakelands, Milton Keynes, MK14 5BP, England. JAPAN: Nippon Motorola Ltd.; 4-32-1, Nishi-Gotanda, Shinagawa-ku, Tokyo Japan. ASIA-PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, King Street, Industrial Estate, N.T., Hong Kong.
SEMICONDUCTOR PRODUCT INFORMATION
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