Description Lucent Technologies Microelectronics Group T7290A DS1

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Description Lucent Technologies Microelectronics Group T7290A DS1

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T7290A DS1/T1/CEPT/E1 Line Interface
Description
Lucent Technologies Microelectronics Group T7290A DS1/T1/CEPT/E1 Line Interface fully integrated line transceiver capable operation domestic DS1/T1 carrier rate (1.544 Mbits/s) international CEPT/E1 rate (2.048 Mbits/s). T7290A device combines features found existing line-interface devices with additional desirable features. on-chip, low-impedance output drivers provide shaped waveforms transformer, guaranteeing template conformance. T7290A device interfaces digital cross connect (DSX) lengths feet during operation interfaces line impedances during CEPT operation. device line interface also transmit waveforms compatible with lines. T7290A line interface provides phase-locked loop clock recovery data retiming received data. Also, on-chip, selectable jitter attenuation available. jitter attenuator placed receive transmit data path. external crystals required with T7290A device. Digital control circuitry allows multiple loopbacks, testing, alarm status monitoring. microprocessor interface option allows either control microprocessor direct pin-selectable control (hardware mode). T7290A device manufactured using lowpower CMOS technology available 28-pin, plastic package 28-pin, plastic package. Note: Modification existing T7290 application required when migrating T7290Abased architecture. functions TBS, TSC, LP1, DLOS, pins have been changed modified. Please refer T7290A Migration from T7290 section this data sheet.
Fully integrated DS1/T1/CEPT/E1 line interface systems that compliant with CB119, AT&T 43801, AT&T 43802, AT&T 62411, TR-TSY-000170, TR-TSY-000009, ITU-T G.703, G.735, G.823, I.431 specifications Dual-rail system interface On-chip transmit equalization On-chip jitter attenuator Monolithic clock recovery with frequencyacquisition aide High jitter accommodation (>0.4 U.I.) external crystal required Three clocking modes accommodate multiple system clocking requirements Multiple link-status alarm features Microprocessor interface option (blue alarm) transmission Loopback modes fault isolation Minimal external circuitry required
T7290A DS1/T1/CEPT/E1 Line Interface
Table Contents
Contents Page
Features Description. Information Receiver Data Interface Clock Recovery Data Retiming. Frequency-Acquisition Aide. Jitter. Data Patterns. Loss Signal Transmitter Output Pulse Shape Output Pulse Generation Jitter Attenuator Alarms Maintenance. Digital Loss Signal (DLOS). Output Loss Signal (OUT-LOS). Jitter Attenuator Alarm (ESA) Transmitter Short Circuit. (Blue Signal) Generator Loopbacks Microprocessor Interface In-Circuit Testing Absolute Maximum Ratings. Handling Precautions Electrical Characteristics Operating Conditions. Timing Characteristics Applications Line Termination. Outline Diagrams. 28-Pin, Plastic SOJ. 28-Pin, Plastic DIP. Ordering Information. T7290A Migration from T7290. DS98-190TIC Replaces DS97-197TIC Incorporate Following Updates.
Lucent Technologies Inc.
ALOS DLOS DLOS UGRCLK MODE1 MODE2 FREQ ACQUISITION JITTER ATTEN SCLK PULSE EQUALIZER DRIVERS EXCLK DLOS EXCLK
MODE1
IN-LOS
ALOS
Lucent Technologies Inc.
Description (continued)
RPDATA, RNDATA RCLK
TPDATA, TNDATA
Figure Block Diagram
TRANSMIT MONITOR UGRCLK EXCLK OUT-LOS LOSS CLOCK BLUE SIGNAL MODE2 DECODE
TCLK
EXCLK
MODE1 MODE2
INTERFACE
EXCLK MODE1 MODE2 LOOPA LOOPB VDDA, GNDA VDDD, GNDD
T7290A DS1/T1/CEPT/E1 Line Interface
5-2484(C)r.6
T7290A DS1/T1/CEPT/E1 Line Interface
Information
VDDA GNDA MODE2 MODE1 LOOPB LOOPA IN-LOS OUT-LOS GNDD VDDD RNDATA RPDATA RCLK TNDATA TPDATA TCLK EXCLK
5-1810 (F).a
T7290A
Figure Diagram Table Descriptions Symbol EC1, EC3, VDDA GNDA MODE2, MODE1 LOOPB, LOOPA IN-LOS Type* Name/Function Equalizer/Rate Control 1-3. Three control leads selecting transmit equalization. 3-State (Active-Low). This configure output buffers into high-impedance state during in-circuit testing. Analog Supply. powerup rise time 4.75 must less than Analog Ground. Receive Bipolar Ring. Negative bipolar receive data. Receive Bipolar Tip. Positive bipolar receive data. Mode Select control leads selecting clock data paths through jitter attenuator. Loopback Control control leads selecting clock data loopback paths. Transmit Blue Signal (AIS). This high transmit blue signal (all 1s). remote loopback (LP2) priority over transmit blue signal. Input Loss Signal. This high analog loss signal receiver inputs detected digital loss signal recovered data detected. IN-LOS tied directly initiate transmit blue signal upon loss signal.
input, output, input with pull-up, input with pull-down.
Lucent Technologies Inc.
T7290A DS1/T1/CEPT/E1 Line Interface
Information (continued)
Table Descriptions (continued) Symbol Type* Name/Function Jitter Attenuator Alarm. This high phase jitter incoming signal exceeds tolerance jitter attenuator's buffer. This result loss receive data. Output Loss Signal. This high when either transmit clock (TCLK) smoothing clock (SCLK) output jitter attenuator absent. Chip Select Microprocessor Interface (Active-Low). loads data into device falling edge latches data rising edge. hardware mode. External Clock. DS1/T1 clock signal (1.544 ppm) CEPT/E1 clock signal (2.048 ppm) transmit blue signal, jitter attenuator calibration, acquisition aid. EXCLK must independent clock guarantee device performance specifications. This clock should continuously active (i.e., ungapped unswitched) void jitter above features operate. Transmit Clock. DS1/T1 clock signal (1.544 ppm) CEPT/E1 clock signal (2.048 ppm). Transmit Positive Data. DS1/T1 (1.544 Mbits/s) CEPT/E1 (2.048 Mbits/s) positive bipolar data. Transmit Negative Data. DS1/T1 (1.544 Mbits/s) CEPT/E1 (2.048 Mbits/s) negative bipolar data. Receive Clock. Recovered receive clock signal terminal equipment. Receive Positive Data. DS1/T1 (1.544 Mbits/s) CEPT/E1 (2.048 Mbits/s) recovered positive data (NRZ). Receive Negative Data. DS1/T1 (1.544 Mbits/s) CEPT/E1 (2.048 Mbits/s) recovered negative data (NRZ). Transmit Bipolar Tip. Positive bipolar transmit data. Digital Supply. powerup rise time 4.75 must less than Transmit Bipolar Ring. Negative bipolar transmit data. Digital Ground.
OUT-LOS
EXCLK
TCLK TPDATA TNDATA RCLK RPDATA RNDATA VDDD GNDD
input, output, input with pull-up, input with pull-down.
Lucent Technologies Inc.
T7290A DS1/T1/CEPT/E1 Line Interface
Data Sheet April 1998 Frequency-Acquisition Aide
robust operation, enhanced with frequency-acquisition capability. frequency-acquisition circuitry intended guarantee proper phase locking during start-up situations, such powerup data activation. Once T7290A device phaselocked data, frequency-acquisition mode activated unless digital loss signal occurs, which case RCLK frequency-locked/phase-locked EXCLK. RCLK always active does have instantaneous phase hits discontinuities. continuously active (i.e., ungapped unswitched) reference clock must present EXCLK enable frequency-acquisition circuitry. EXCLK must independent reference such oscillator system clock proper operation. EXCLK clock frequency must 1.544 T1/DS1 operation 2.048 CEPT/E1 operation.
Receiver
Data Interface
receive line-interface transmission format T7290A device alternate mark inversion (AMI). receive digital output format dual-rail, nonreturn zero (NRZ). Receiver specifications shown Table
Clock Recovery Data Retiming
bipolar input signals from peakdetected sliced receiver front end. Timing recovery performed phase-locked loop (PLL) that locks internal free-running, current-controlled oscillator (ICO) data-rate component. EC1, EC2, rate control inputs must appropriately CEPT/E1 operation.
Table Receiver Specifications Parameter Receiver Sensitivity:* CEPT Analog Level: CEPT PLL: Bandwidth Peaking Free-run Frequency Error Input Density (1s) Return kHz-102 kHz-2.048 2.048 MHz-3.072 0.85 12.5 0.48 0.28 Unit
Values shown flat loss only. Receiver also meets ITU-T G.703 interface immunity test cable loss with interference) CEPT/E1 operation. Transfer characteristics (1/8 input). maximum number consecutive zeros Return loss specifications according ITU-T G.703/RC6367A (CEPT only).
Lucent Technologies Inc.
T7290A DS1/T1/CEPT/E1 Line Interface
Receiver (continued)
Jitter
designed accommodate large amounts input jitter with high power supply rejection operation noisy environments. minimum input jitter tolerance exceeding requirements shown Figure measured receiver jitter tolerance CEPT operation also shown Figure with pseudorandom input data (215 with EXCLK synchronous with data source. receiver transfers incoming jitter RCLK with more than gain frequency, which further reduced with jitter attenuator.
500.0
TRI-TSY-000170, 43801 62411 62411 (LOOP TIMED)
PEAK-TO-PEAK JITTER MAGNITUDE (U.I.)
100.0 50.0 28.0 TR-TSY-000009, 43802 MEASURED RECEIVER CEPT PERFORMANCE (JITTER ATTENUATOR ACTIVE) MEASURED RECEIVER PERFORMANCE (JITTER ATTENUATOR ACTIVE) ITU-T G.823 MINIMUM JITTER ATTENUATOR PERFORMANCE
10.0
1000 10,000 100,000
5-1157(C)r.4
JITTER FREQUENCY (Hz)
Data Points (Hz, U.I.) ITU-T G.823 TR-TSY-000170, AT&T 43801 TR-TSY-000009, AT&T 43802 AT&T 62411 AT&T 62411 Looped Timed 10k, 100k, Measured Receiver Performance (BER 10-6) 2.0k, 6.51 5.0k, 2.03 8.0k, 1.12 10k, 0.97 15k, 0.84 20k, 0.66 30k, 0.52 40k, 0.49 70k, 0.48 100k, 0.48 Measured Receiver CEPT Performance (BER 10-6) 2.0k, 9.43 5.0k, 2.84 8.0k, 1.70 10k, 1.38 15k, 1.00 20k, 0.84 30k, 0.57 40k, 0.48 70k, 0.47 100k, 0.47
2.4k, 18k, 100k,
10k, 50k,
500, 40k,
10k, 100k,
Figure Jitter Tolerance Requirements Lucent Technologies Inc.
T7290A DS1/T1/CEPT/E1 Line Interface
detector output becomes active. Hysteresis (250 provided analog detector eliminate ALOS chattering. Either analog digital detector sets IN-LOS high. time required detect analog loss signal (ALOS) depends incoming signal amplitude before disappears. Typical ALOS detection times given Table Table Typical ALOS Detection Times
Receiver (continued)
Data Patterns
data pattern with minimum long-term density 12.5% with fewer consecutive allowed.
Loss Signal
Both digital (DLOS) analog (ALOS) loss-of-signal detection used T7290A device. digital signal detector described later under Alarms Maintenance section. analog signal detector uses output receiver peak detector determine signal present input amplitude drops below approximately 0.48 DS1/T1 operation 0.28 CEPT/E1 operation, analog Signal Amplitude (Vp) Typical ALOS Detection Time (ms)
Transmitter
Output Pulse Shape
Transmitter specifications shown Table pulse shape template specified network interface shown Figure pulse shape template specified illustrated Figure CEPT transmit waveforms device output conform template shown Figure Table Transmitter Specifications Parameter Output Pulse Amplitude:* DSX) CEPT (into CEPT (into Output Pulse Width: CEPT Output Power Levels: band kHz) band 1544 kHz) band kHz) band 1544 kHz) Positive/Negative Pulse Imbalance: CEPT Zero Level**
Return Loss: kHz-102 kHz-2.048 2.048 MHz-3.072
2.13 12.0 12.6
2.37 16.5 16.5
2.61 19.0 17.9
Unit
accordance with interfaces described Line Termination section under Applications. Below power kHz. Total power difference. Percentage pulse amplitude pulse width. Percentage pulse amplitude. Meets CH-PTT return loss specifications (CEPT only).
Lucent Technologies Inc.
T7290A DS1/T1/CEPT/E1 Line Interface
Transmitter (continued)
Output Pulse Shape (continued)
NORMALIZED AMPLITUDE
NORMALIZED AMPLITUDE
-0.5 1000 1250
-0.5 1000 1250 TIME (ns)
5-1604(F)r.3 5-1160(C)r.6
TIME (ns)
Isolated-Pulse Corner Points According Part Maximum Curve Normalized Voltage 0.05 0.05 0.80 1.20 1.20 1.05 1.05 0.05 1000 0.05 0.05 1250 Minimum Curve Normalized Voltage -0.05 -0.05 0.50 0.90 0.95 0.90 0.50 -0.45 -0.45 -0.26 1100 -0.05 1250 -0.05
DSX-1 Pulse Template Corner Points According CB119 Maximum Curve Normalized Voltage 0.05 0.05 0.80 1.15 1.15 1.05 1.05 -0.07 0.05 1100 0.05 1250 Minimum Curve Normalized Voltage -0.05 -0.05 0.50 0.95 0.95 0.90 0.50 -0.45 -0.45 -0.20 1100 -0.05 1250 -0.05
Note: Successive corner points joined straight lines.
Note: Successive corner points joined straight lines.
Figure Isolated-Pulse Template
Figure DSX-1 Isolated-Pulse Template
Lucent Technologies Inc.
T7290A DS1/T1/CEPT/E1 Line Interface
Transmitter (continued)
Output Pulse Shape (continued)
(244
100%
(244
NOMINAL PULSE
(244
(244 244)
5-3145(C)r.7
Note: corresponds nominal peak value.
Figure ITU-T G.703 Pulse Template
Output Pulse Generation
transmitter accepts clock with positive negative data (dual-rail format) converts signal balanced bipolar data signal (AMI format). Positive produced positive pulse device negative produced positive pulse device Binary converted null pulses. pulse shapes controlled on-chip according equalizer control inputs, defined Table Transmitter specifications shown Table Table Equalizer/Rate Control Service Clock Rate 1.544 Transmitter Equalization* ft.-131 ft.-262 ft.-393 ft.-524 ft.-655 Maximum Cable Loss
1.544
CEPT
2.048
Distance feet 22-Ga. (ABAM) cable (DS1 only). maximum loss figures other cable types. kHz. According Part Subpart Option line build-out.
Lucent Technologies Inc.
T7290A DS1/T1/CEPT/E1 Line Interface
ITU-T I.431 qualification 2.048 data rate, which jitter filters Hz-100 (0.125 U.I.) Hz-100 (0.02 U.I.). jitter tolerance attenuator meets requirements TR-TSY-000009, AT&T 43802, ITU-T G.823 (see Figure attenuator also ensures that jitter accommodation minimum U.I. peak-to-peak (DS1) U.I. peak-to-peak (CEPT) U.I. [T1/DS1] [CEPT]) during attenuation. jitter attenuation function identical when placed either transmit receive path. Ideally, tolerance attenuator bits U.I.). However, (Hz) frequency (EXCLK) frequency (input clock) (DS1) 30.5 (CEPT), then tolerance degraded equals: (U.I.) Figure shows phase step response (DS1) attenuator given response based phase offset (U.I.) generated read pointer buffer. this phase offset that degrades attenuator's tolerance.
Jitter Attenuator
Jitter transfer functions describe amount jitter that transferred from input output specified equipment. jitter transfer functions affected jitter attenuator circuitry, which placed receive data path, placed transmit data path, bypassed. Placement this circuit controlled described Table external clock (EXCLK) must present attenuation function operate. When attenuation selected, T7290A device exhibits jitter transfer function that peaking single pole frequency (DS1) pole frequency (CEPT). Figure displays typical jitter transfer function constant input jitter amplitude U.I. peak-to-peak. amount generated output jitter when input jitter present measured using scheme shown Figure jitter filters depicted represent AT&T 62411 specification 1.544 data rate. jitter produced labeled points does exceed following peak-to-peak levels: 0.05 U.I. point 0.025 U.I. point 0.025 U.I. point 0.02 U.I. point similar test performed
JITTER ATTENUATION (dB)
dB/DECADE DECADE TYPICAL PERFORMANCE dB/DECADE
dB/DECADE
ITU-T G.735, ITU-T I.431 TR-TSY000009, 43802
2.5k
5-1311(C)r.4
JITTER FREQUENCY (Hz)
Data Points (Hz, TR-TSY-000009, AT&T 43802 350, 2.5k, -33.6 15k, -49.2 ITU-T G.735, ITU-T I.431 400, -19.5 15k, -19.5
Figure Jitter Transfer Function Jitter Attenuator
Lucent Technologies Inc.
T7290A DS1/T1/CEPT/E1 Line Interface
Jitter Attenuator (continued)
When T7290A device used only jitter attenuator, loopback (LP1) should active attenuator must placed transmit path (MODE1:2 01). Table Connectivity Jitter Attenuator Connectivity Jitter Attenuator* Bypass Transmit Path Receive Path Test Mode MODE1 MODE2
jitter attenuator must enabled after exceeds 4.75 during device powerup. Jitter attenuator powered down during this mode (see Table under Electrical Characteristics section). used normal operation. FILTERS (SLOPES MUST DECADE)
EACH POINT PEAK DETECTOR
MEASURED SIGNAL JITTER DETECTOR (700 (100 kHz)
TRUE VOLTMETER
(100 kHz)
EACH POINT
SPECTRUM ANALYZER
5-1163(F)r.2
Figure Measurement Generated Jitter
Lucent Technologies Inc.
T7290A DS1/T1/CEPT/E1 Line Interface
Jitter Attenuator (continued)
PHASE STEP RESPONSE (IfI READ COUNTER OFFSET (U.I.)
TIME (ms)
5-2485(C)r.3
Figure Jitter Attenuator Phase Response
Alarms Maintenance
Digital Loss Signal (DLOS)
digital loss signal (DLOS indicated more consecutive occur receive data stream during DS1/T1 operation. During CEPT operation, DLOS indicated when more consecutive occur receive data stream. DLOS then deactivated when ones density exceeds 12.5% there more than consecutive (T1, DS1, CEPT), signifying return good signal. DLOS deactivation monitors data fixed 32-bit windows. Each window must have least four with more than consecutive Consecutive also monitored across window boundary. This condition must persist consecutive 32-bit windows, which time DLOS deactivated window. Upon DLOS detection, RCLK phase-locked external clock (EXCLK) that other system devices slaved line clock continue operate without instantaneous phase hits discontinuities. Either analog loss signal (ALOS) digital loss signal (DLOS) activates IN-LOS output pin.
Output Loss Signal (OUT-LOS)
output loss signal (OUT-LOS indicated either transmit clock (TCLK) smoothing clock (SCLK) output jitter attenuator absent. jitter attenuator placed transmit path, SCLK monitored. jitter attenuator used transmit path, TCLK monitored. every clock periods oscillator clock, denoted UGRCLK Figure strobe generated. single transmit clock period occurs between strobes, then OUT-LOS transmit clock period occurs between strobes, then OUT-LOS output drivers placed into high-impedance state data transmitted. UGRCLK always present, even absence both EXCLK T1/R1 input data; therefore, UGRCLK most suitable clock monitoring OUT-LOS.
Lucent Technologies Inc.
T7290A DS1/T1/CEPT/E1 Line Interface
does corrupt looped data. IN-LOS alarm still monitors entire receive function. remote loopback (LP2) loops recovered clock retimed data into transmitter back onto line. receive front end, receive PLL, jitter attenuator engaged), transmit driver circuitry exercised. transmit clock, transmit data, inputs ignored. Valid receive output data continues sent RPDATA RNDATA. This loop used isolate failures between systems. digital local loopback (LP3) directly loops transmit clock data receive clock data output pins. blue signal transmitted when this loopback. (rather than LP1) must selected MODE2 Table Loopback Control Operation Normal Digital Local Loopback Remote Loopback Local Loopback
ignored.
Alarms Maintenance (continued)
Jitter Attenuator Alarm (ESA)
jitter attenuator alarm (ESA indicated phase jitter exceeds tolerance jitter attenuator. errors occur when active. This signal asserted until error-free operation resumes. Figure determine tolerance limits attenuator.
Transmitter Short Circuit
transmitter monitor provided detect nonfunctioning links protect device from damage. transmitter's line drivers shorted power supply ground, shorted together, internal circuitry protects device from damage. After transmit clock cycles, transmitter powered normal operating mode. drivers attempt correctly transmit next data (+1, -1). short still present, transmitter again internally protected transmit clock cycles. This process continuously repeated until short disappeared. alarm available off-chip.
Symbol LOOPA LOOPB LP2*
Microprocessor Interface (Blue Signal) Generator
When transmit blue signal (TBS continuous stream bipolar transmitted onto line synchronous with EXCLK. TPDATA TNDATA inputs ignored during this mode. IN-LOS output externally connected input, IN-LOS error initiates transmit blue signal long IN-LOS Also, input ignored when remote loopback selected. There microprocessor interface input, i.e., change directly into device impeded function. chip-select input (CS) configures device either hardware mode microprocessor mode. chip-select function applies following inputs: MODE1, MODE2, EC1, EC2, EC3, LOOPA, LOOPB. hardware mode, change these asynchronous input pins directly into device. maintain hardware mode, microprocessor mode, digital control inputs loaded into T7290A device falling edge latched rising edge Figure shows timing diagram this function. Note that there special requirements only when using microprocessor mode. example, state input should change while Also, state internal latch undefined (unknown user) until first falling edge encountered.
Loopbacks
T7290A device three independent loopback paths, which activated shown Table local loopback (LP1) connects jitter attenuator's output clock data receive clock data output pins. MODE1:2 must selected this loopback operate (jitter attenuator transmit path). Valid transmit output data continues sent network. However, transmit blue initiated (TBS all-1s signal sent network
In-Circuit Testing
device ability allow in-circuit testing activating high-impedance mode (TRI During this mode, output buffers (T2, RCLK, RPDATA, RNDATA, IN-LOS, ESA, OUT-LOS) 3-stated. During 3-stated condition, absolute maximum voltage ratings must exceeded pin.
Lucent Technologies Inc.
T7290A DS1/T1/CEPT/E1 Line Interface
Absolute Maximum Ratings
Stresses excess absolute maximum ratings cause permanent latent damage device. These absolute stress ratings only. Functional operation device implied these other conditions excess those given operational sections data sheet. Exposure absolute maximum ratings extended periods adversely affect device reliability. External leads soldered safely temperatures Parameter Supply Voltage Range Power Dissipation Storage Temperature Maximum Voltage (any pin) with Respect Minimum Voltage (any pin) with Respect Maximum Allowable Voltages (T1, with Respect Symbol Tstg -0.5 -0.5 -5.0 Unit
Handling Precautions
Although protection circuitry been designed into this device, proper precautions should taken avoid exposure electrostatic discharge (ESD) during handling mounting. Lucent employs human-body model (HBM) charged-device model (CDM) ESD-susceptibility testing protection design evaluation. voltage thresholds dependent circuit parameters used define model. industry-wide standard been adopted CDM. However, standard (resistance 1500 capacitance 1000 widely used and, therefore, used comparison purposes. threshold presented here obtained using these circuit parameters: Human-Body Model Threshold Device Voltage T7290A-EL >1200 T7290A-PL >1200
Lucent Technologies Inc.
T7290A DS1/T1/CEPT/E1 Line Interface
Electrical Characteristics
Operating Conditions
except noted. rise time 4.75 must less than Table Power Specifications Parameter Power Dissipation:* Without Jitter Attenuator: CEPT CEPT (120 With Jitter Attenuator: CEPT CEPT (120 Symbol Unit
Conditions with transmit side, Equalizer settings:
Table Logic Interface Characteristics internal pull-up device provided lead. Internal pull-down devices provided following leads: MODE1, MODE2, EC1, EC2, EC3, TBS, LOOPA, LOOPB. internal pull-up pull-down devices require input source sink more than Parameter Input Voltage: High Output Voltage: High Input Capacitance Load Capacitance Source Current Sink Current Symbol Isource Isink GNDD GNDD VDDD VDDD Unit
Lucent Technologies Inc.
T7290A DS1/T1/CEPT/E1 Line Interface
Timing Characteristics
duty-cycle timing relationships receive transmit data signals referenced TTL, threshold level. Figure shows this timing. Table Interface Data Timing (See Figure 10.) Symbol tTCLTCL Parameter TCLK Duty Cycle TCLK Clock Period: DS1/T1 CEPT Transmit Data Setup Time Transmit Data Hold Time Clock Rise Time (10%-90%) Clock Fall Time (10%-90%) Receive Data Setup Time Receive Data Hold Time Receive Propagation Delay
647.7
Unit
tTDVTCL tTCLTDX tTCH1TCH2 tTCL2TCL1 tRDVRCH tRCHRDX tRCLRDV
tolerance ±130 ppm. tolerance ppm. tTCLTCL TCLK tTDVTCL tTCLTDX TPDATA TNDATA tRCLRDV RCLK tRDVRCH tRCHRDX RPDATA RNDATA tTCL2TCL1 tTCH1TCH2
5-1156(C)r.8
Figure Interface Data Timing
Lucent Technologies Inc.
T7290A DS1/T1/CEPT/E1 Line Interface
Timing Characteristics (continued)
Table Microprocessor Interface Timing (See Figure 11.) Symbol tSVCSL tCSLCSH tCSHSX tCSH1CSH2 tCSL2CSL1 Parameter Control Signal Setup Time Control Signal Pulse Width Time Control Signal Hold Time Control Signal Rise Time (10%-90%) Control Signal Rise Time (10%-90%)
tCSL2CSL1 MODE1 MODE2 LOOPA LOOPB
tCSH1CSH2
Unit
tCSLCSH
tSVCSL
tCSHSX
5-1165(F)r.4
Figure Microprocessor Interface Timing
Lucent Technologies Inc.
T7290A DS1/T1/CEPT/E1 Line Interface
Applications
Line Termination
following applications (shown Figures 12-15), Lucent 2741 2745 Series transformers recommended. same transformers used T7290 device used T7290A device. tolerance transformer turns ratios maximum ±2%. tolerance resistors transmit path (excluding cable termination) maximum ±1%.
RECEIVE DATA RECEIVE INPUT VDDD GNDD TRANSMIT DATA LOAD TRANSMIT OUTPUT 1.08:1 TPDATA TNDATA TCLK
5-1152(C)r.6
RPDATA RNDATA RCLK
T7290A
VDDA
GNDA
Figure Application Twisted-Pair Interface
RECEIVE DATA LBO/ EQUALIZER WAVEFORM MEETS FIGURE TEMPLATE THIS POINT LINE BUILD-OUT. TRANSMIT DATA 21.5 LOAD 21.5 1.36:1 TRANSMIT OUTPUT TPDATA TNDATA TCLK
5-1153(C)
RPDATA RECEIVE INPUT RNDATA RCLK
VDDD
T7290A
VDDA GNDD GNDA
Figure Application Diagram
Lucent Technologies Inc.
T7290A DS1/T1/CEPT/E1 Line Interface
Applications (continued)
Line Termination (continued)
RECEIVE DATA RECEIVE INPUT VDDD GNDD TRANSMIT DATA 26.1 LOAD 26.1 1.36:1 TRANSMIT OUTPUT TPDATA TNDATA TCLK
5-1154(C)
RPDATA RNDATA RCLK
T7290A
VDDA
GNDA
Figure CEPT Application Twisted-Pair Interface
RECEIVE DATA RECEIVE INPUT VDDD GNDD TRANSMIT DATA 15.4 LOAD 15.4 1.36:1 TRANSMIT OUTPUT TPDATA TNDATA TCLK GNDA RPDATA RNDATA RCLK
T7290A
VDDA
5-1155(C)r.6
Figure CEPT Application Coaxial Interface
Lucent Technologies Inc.
T7290A DS1/T1/CEPT/E1 Line Interface
Outline Diagrams
28-Pin, Plastic
Dimensions millimeters.
IDENTIFIER ZONE
SEATING PLANE 0.10 1.27 0.51 0.79
5-4413(C).r4
Number Pins
Package Dimensions (SOJ) Maximum Length Including Leads 18.03 Maximum Width Without Leads 7.62 Maximum Width Including Leads 8.81 Maximum Height Above Board 3.18
Lucent Technologies Inc.
T7290A DS1/T1/CEPT/E1 Line Interface
Outline Diagrams (continued)
28-Pin, Plastic
Dimensions millimeters.
IDENTIFIER ZONE
SEATING PLANE 0.38 2.54 0.58
5-4410(C).r2
Number Pins
Package Dimensions (DIP) Maximum Length Including Leads 37.34 Maximum Width Without Leads 13.97 Maximum Width Including Leads 15.49 Maximum Height Above Board 5.59
Ordering Information
Device Code 7290A 7290A Package 28-Pin 28-Pin Temperature Comcode (Ordering Number) 106785645 106785637
Lucent Technologies Inc.
T7290A DS1/T1/CEPT/E1 Line Interface
T7290A Migration from T7290
T7290A replacement T7290 family devices that includes T7290-EL, T7290-PL, T7290-EL2, T7290-PL2. following list describes functional changes made T7290 produce T7290A. Modification existing T7290 application required.
input T7290A directly controls function. function T7290 gated chip select (CS). transmitter short circuit (TSC) output alarm been eliminated; however, transmit drivers still powered down under short-circuit conditions. renamed output loss signal (OUT-LOS) indicates when either transmit clock (TCLK) smoothing clock (SCLK) output jitter attenuator absent. Loopback (LP1) been modified route signals through jitter attenuator only. MODE2 must high this loopback operate (jitter attenuator on). digital loss-of-signal (DLOS) functionality compatible systems that must compliant with Bellcore TR-TSY-000009. loss-of-signal (LOS) output indication renamed input loss signal (IN-LOS) ORed function analog loss signal (ALOS) digital loss signal (DLOS) regardless loopback setting. frequency acquisition mode enabled when digital loss-of-signal (DLOS) condition occurs, which case receive clock (RCLK) frequency-locked/phase-locked external clock (EXCLK). Improved ITU-T G.703 interference immunity CEPT mode operation.
DS98-190TIC Replaces DS97-197TIC Incorporate Following Updates
Page Figure Block Diagram, updated. Page 28-Pin, Plastic SOJ, changed dimensions millimeters. Page 28-Pin, Plastic DIP, changed dimensions millimeters. Page corrected Device Code.
Lucent Technologies Inc.
T7290A DS1/T1/CEPT/E1 Line Interface
additional information, contact your Microelectronics Group Account Manager following: INTERNET: http://www.lucent.com/micro E-MAIL: docmaster@micro.lucent.com AMERICA: Microelectronics Group, Lucent Technologies Inc., Union Boulevard, Room 30L-15P-BA, Allentown, 18103 1-800-372-2447, 610-712-4106 CANADA: 1-800-553-2448, 610-712-4106) ASIA PACIFIC: Microelectronics Group, Lucent Technologies Singapore Pte. Ltd., Science Park Drive, #03-18 Cintech III, Singapore 118256 Tel. (65) 8833, (65) 7495 CHINA: Microelectronics Group, Lucent Technologies (China) Co., Ltd., A-F2, 23/F, Fong Universe Building, 1800 Zhong Shan Road, Shanghai 200233 China Tel. (86) 6440 0468, ext. 316, (86) 6440 0652 JAPAN: Microelectronics Group, Lucent Technologies Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan Tel. (81) 5421 1600, (81) 5421 1700 EUROPE: Data Requests: MICROELECTRONICS GROUP DATALINE: Tel. (44) 1189 299, (44) 1189 Technical Inquiries: GERMANY: (49) 95086 (Munich), UNITED KINGDOM: (44) 1344 (Bracknell), FRANCE: (33) (Paris), SWEDEN: (46) 7070 (Stockholm), FINLAND: (358) 4354 2800 (Helsinki), ITALY: (39) 6601 1800 (Milan), SPAIN: (34) 1441 (Madrid)
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Copyright 1998 Lucent Technologies Inc. Rights Reserved Printed U.S.A.
April 1998 DS98-190TIC (Replaces DS97-197TIC)
Printed Recycled Paper

Description Lucent Technologies Microelectronics Group T7290A DS1

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