High Density Programmable Logic Features HIGH DENSITY PROGRAMMABL

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High Density Programmable Logic Features HIGH DENSITY PROGRAMMABL

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ispLSI pLSI 2064
High Density Programmable Logic Features
HIGH DENSITY PROGRAMMABLE LOGIC 2000 Gates Pins, Four Dedicated Inputs Registers High Speed Global Interconnect Wide Input Gating Fast Counters, State Machines, Address Decoders, etc. Small Logic Block Size Random Logic fmax Maximum Operating Frequency Propagation Delay Compatible Inputs Outputs Electrically Erasable Reprogrammable Non-Volatile 100% Tested Time Manufacture Unused Product Term Shutdown Saves Power ispLSI OFFERS FOLLOWING ADDED FEATURES In-System Programmable(ISPTM) 5-Volt Only Increased Manufacturing Yields, Reduced Time-toMarketand Improved Product Quality Reprogram Soldered Devices Faster Prototyping OFFERS EASE FAST SYSTEM SPEED PLDs WITH DENSITY FLEXIBILITY FIELD PROGRAMMABLE GATE ARRAYS Complete Programmable Device Combine Glue Logic Structured Designs Enhanced Locking Capability Three Dedicated Clock Input Pins Synchronous Asynchronous Clocks Programmable Output Slew Rate Control Minimize Switching Noise Flexible Placement Optimized Global Routing Pool Provides Global Interconnectivity ispLSI/pLSI DEVELOPMENT TOOLS pDS® Software Easy WindowsInterface Boolean Logic Compiler Manual Partitioning Automatic Place Route Static Timing Table pDS+Software Industry Standard, Third Party Design Environments Schematic Capture, State Machine, Automatic Partitioning Place Route Comprehensive Logic Timing Simulation Workstation Platforms
Input Input
Functional Block Diagram
Output Routing Pool (ORP)
Output Routing Pool (ORP)
Logic Array
Output Routing Pool (ORP)
Input
0139Bisp/2064
Description
ispLSI pLSI 2064 High-Density Programmable Logic Devices. devices contain Registers, Universal pins, four Dedicated Input pins, three Dedicated Clock Input pins, dedicated Global input pins Global Routing Pool (GRP). provides complete interconnectivity between these elements. ispLSI 2064 features 5-Volt in-system programmability in-system diagnostic capabilities. ispLSI 2064 offers non-volatile "on-the-fly" reprogrammability logic, well interconnect, provide truly reconfigurable systems. architecturally parametrically compatible pLSI 2064 device, multiplexes four input pins control insystem programming. basic unit logic ispLSI pLSI 2064 devices Generic Logic Block (GLB). GLBs labeled A1.B7 (see figure There total GLBs ispLSI pLSI 2064 devices. Each made four macrocells. Each inputs, programmable AND/OR/Exclusive array, four outputs which configured either combinatorial registered. Inputs come from dedicated inputs. outputs brought back into that they connected inputs device.
Functional Block Diagram product names trademarks registered trademarks their respective holders. specifications information herein subject Copyright 1996 Lattice Semiconductor Corp. brand Functional change without notice. Block SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Diagram LATTICE 1996 Data Book
Tel. (503) 681-0118; 1-800-LATTICE; (503) 681-3037; http://www.latticesemi.com
2064_01
Input
HIGH PERFORMANCE E2CMOS® TECHNOLOGY
Output Routing Pool (ORP)
Global Routing Pool (GRP)
Specifications ispLSI pLSI 2064
Functional Block Diagram
Figure ispLSI pLSI 2064 Functional Block Diagram
Input
Generic Logic Blocks (GLBs)
Megablock
Output Routing Pool (ORP)
Output Routing Pool (ORP)
SDI*/IN MODE*/IN
Input
Input
Output Routing Pool (ORP)
SCLK*/IN SDO*/IN
Global Routing Pool (GRP)
ispEN*/NC
Input
0139B(1)isp/2064
RESET
Output Routing Pool (ORP)
*ispLSI 2064 Only
devices also have cells, each which directly connected pin. Each cell individually programmed combinatorial input, output bi-directional with 3-state control. signal levels compatible voltages output drivers source sink Each output programmed independently fast slow output slew rate minimize overall output switching noise. Eight GLBs, cells, dedicated inputs ORPs connected together make Megablock (see figure outputs eight GLBs connected
universal cells ORPs. Each ispLSI pLSI 2064 device contains Megablocks. inputs, outputs from GLBs inputs from bi-directional cells. these signals made available inputs GLBs. Delays through have been equalized minimize timing skew. Clocks ispLSI pLSI 2064 devices selected using dedicated clock pins. Three dedicated clock pins (Y0, asynchronous clock selected basis. asynchronous Product Term clock generated clock.
1996 Data Book
Specifications ispLSI pLSI 2064
Absolute Maximum Ratings
Supply Voltage -0.5 +7.0V Input Voltage Applied. -2.5 +1.0V Off-State Output Voltage Applied .-2.5 +1.0V Storage Temperature 150°C Case Temp. with Power Applied 125°C Max. Junction Temp. (TJ) with Power Applied 150°C
Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage device. Functional operation device these other conditions above those indicated operational sections this specification implied (while programming, follow programming specifications).
Recommended Operating Condition
SYMBOL PARAMETER Supply Voltage Input Voltage Input High Voltage Commercial Industrial 70°C -40°C 85°C MIN. 4.75 MAX. 5.25 Vcc+1 UNITS
Table 0005/2064
Capacitance (TA=25°C, f=1.0 MHz)
SYMBOL PARAMETER Dedicated Input Capacitance Capacitance Clock Capacitance TYPICAL UNITS TEST CONDITIONS 5.0V, 2.0V 5.0V, VI/O 2.0V 5.0V, 2.0V
Table 0006B
Data Retention Specifications
PARAMETER Data Retention ispLSI Erase/Reprogram Cycles pLSI Erase/Reprogram Cycles MINIMUM 10000 MAXIMUM UNITS Years Cycles Cycles
Table 2-0008A-isp
1996 Data Book
Specifications ispLSI pLSI 2064
Switching Test Conditions
Input Pulse Levels Input Rise Fall Time Input Timing Reference Levels Ouput Timing Reference Levels Output Load 3-state levels measured 0.5V from steady-state active level. 3.0V -125 Others 1.5V 1.5V figure
Table 0003/2064
Figure Test Load
Device Output Test Point
Output Load Conditions (see figure
TEST CONDITION Active High Active Active High -0.5V Active +0.5V 35pF 35pF 35pF
Table 0004A
includes Test Fixture Probe Capacitance.
Electrical Characteristics
Over Recommended Operating Conditions
SYMBOL PARAMETER Output Voltage Output High Voltage Input Leakage Current Input High Leakage Current ispEN Input Leakage Current Active Pull-Up Current Output Short Circuit Current Operating Power Supply Current IOL= (Max.) 3.5V VOUT 0.5V 0.0V, 3.0V fCLOCK Commercial Industrial CONDITION MIN. TYP.
MAX. UNITS -150 -150 -200
IIL-isp IIL-PU IOS1 ICC2,
Table 0007Aisp/2064
output time maximum duration second. VOUT 0.5V selected avoid test problems tester ground degradation. Guaranteed 100% tested. Measured using four 16-bit counters. Typical values 25°C. Maximum varies widely with specific device configuration operating frequency. Refer Power Consumption section this data sheet Thermal Management section this Data Book estimate maximum
1996 Data Book
Specifications ispLSI pLSI 2064
External Timing Parameters
Over Recommended Operating Conditions
PARAMETER TEST COND.
DESCRIPTION
-125
-100 10.0 13.0 13.5 15.0 15.0
15.0 18.5 17.0 18.0 18.0 12.0 12.0
MIN. MAX. MIN. MAX. MIN. MAX. 10.0 10.0 12.0 12.0
UNITS
tpd1 tpd2 fmax fmax (Ext.) fmax (Tog.) tsu1 tco1 tsu2 tco2 trw1 tptoeen tptoedis tgoeen tgoedis
Data Propagation Delay, Bypass, Bypass Data Propagation Delay Clock Frequency with Internal Feedback Clock Frequency, Max. Toggle Reg. Setup Time before Clock, Bypass Reg. Clock Output Delay, Bypass Reg. Hold Time after Clock, Bypass Reg. Setup Time before Clock Clock Frequency with External Feedback tsu2 tco1)
11.0 10.0
Reg. Clock Output Delay Reg. Hold Time after Clock Ext. Reset Output Delay Ext. Reset Pulse Duration Product Term Enable Product Term Disable Global Enable Global Disable External Synchronous Clock Pulse Duration, High External Synchronous Clock Pulse Duration,
Unless noted otherwise, parameters GRP, PTXOR path, clock. Refer Timing Model this data sheet further details. Standard 16-bit counter using feedback. Reference Switching Test Conditions section.
Table 0030B/2064-130
1996 Data Book
Specifications ispLSI pLSI 2064
Internal Timing Parameters1
Over Recommended Operating Conditions
PARAMETER
DESCRIPTION
-125
-100
UNITS
MIN. MAX. MIN. MAX. MIN. MAX.
Inputs tdin tgrp t4ptbp t4ptbp t1ptxor t20ptxor txoradj tgbp tgsu tgco tgro tptre tptoe tptck torp
Input Buffer Delay Dedicated Input Delay
Delay
Product Term Bypass Comb. Path Delay Product Term Bypass Reg. Path Delay Product Term/XOR Path Delay Product Term/XOR Path Delay Adjacent Path Delay3
10.2
Register Bypass Delay Register Setup Time before Clock Register Hold Time after Clock Register Clock Output Delay Register Reset Output Delay Product Term Reset Register Delay Product Term Output Enable Cell Delay Product Term Clock Delay
Delay Bypass Delay
torpbp Outputs toen todis tgoe Clocks tgy0 tgy1/2 Global Reset
Output Buffer Delay Output Slew Limited Delay Adder Cell Output Enabled Cell Output Disabled Global Output Enable
10.0
10.0
10.0
Clock Delay, Global Clock Line (Ref. clock) Clock Delay, Global Clock Line
Global Reset
11.4
Internal Timing Parameters tested reference only. Refer Timing Model this data sheet further details. adjacent path only used hard macros.
Table 0036C/2064-130
1996 Data Book
Specifications ispLSI pLSI 2064
ispLSI pLSI 2064 Timing Model
Cell
Feedback
Cell
Ded.
Delay
Comb Bypass Bypass Delays #25, Bypass Delay #29, Bypass Delay #38, (Output)
(Input)
Reset
Control #33, Y0,1,2 #43,
#40,
0491/2064
Derivations tsu, from Product Term Clock
Logic Clock (min) (tio tgrp t20ptxor) (tgsu) (tio tgrp tptck(min)) (#20 #26) (#29) (#20 #35) (0.2 6.0) (0.8) (0.2 3.3) Clock (max) Logic (tio tgrp tptck(max)) (tgh) (tio tgrp t20ptxor) (#20 #35) (#30) (#20 #26) (0.2 5.6) (3.0) (0.2 6.0) Clock (max) Output (tio tgrp tptck(max)) (tgco) (torp tob) (#20 #35) (#31) (#36 #38) (0.2 5.6) (0.2) (0.8 1.2)
Table 0042A-2064
Note: Calculations based upon timing specifications ispLSI pLSI 2064-125L.
1996 Data Book
Specifications ispLSI pLSI 2064
Power Consumption
Power Consumption ispLSI pLSI 2064 device depends primary factors: speed which device operating number Product Terms Figure Typical Device Power Consumption fmax used. Figure shows relationship between power operating speed.
ispLSI pLSI 2064
(mA)
fmax (MHz)
Notes: Configuration Four 16-bit Counters Typical Current
estimated ispLSI pLSI 2064 using following equation: ICC(mA) 0.33) nets freq 0.007) Where: Number Product Terms used design nets Number Signals used device freq Highest Clock Frequency device MHz) estimate based typical conditions (VCC 5.0V, room temperature) assumption loads average exists. These values estimates only. Since value sensitive operating conditions program device, actual should verified.
0127A-64-80isp/2000
1996 Data Book
Specifications ispLSI pLSI 2064
In-System Programmability
ispLSI devices in-system programmable versions Lattice Semiconductor high density programmable Large Scale Integration (pLSI) devices. integrating high voltage programming circuitry onchip, programming accomplished simply shifting data into device. Once function programmed, non-volatile E2CMOS cells will lose pattern even when power turned off. necessary programming done five level logic interface signals. These five signals into on-chip programming circuitry where state machine controls programming. simple signals interface include Enable (ispEN), Serial Data (SDI), Serial Data (SDO), Serial Clock (SCLK) Mode (MODE) control. Figure illustrates block diagram possible scheme programming interface ispLSI devices. details operation internal state machine programming device, please refer Architecture Programming section this Data Book. device identifier ispLSI 2064 0001 0010 hex). This code unique device identifier which generated when read command performed.
Figure Programming Interface
MODE SCLK ispEN
5-wire Programming Interface
ispEN SCLK MODE
SCLK MODE
SCLK MODE
ispEN SCLK MODE
ispLSI
ispGAL
ispGDS
ispLSI
0294B
1996 Data Book
Specifications ispLSI pLSI 2064
ispLSI 2064 Shift Register Layout
Data (SDI)
159.
High Order Shift Register Order Shift Register
E2CMOS Cell Array
Address Shift Register
Note: logic address shift register enables programming verification. logic disables
1996 Data Book
Specifications ispLSI pLSI 2064
Description
NAME
RESET ispEN**/NC
PLCC NUMBERS
DESCRIPTION
Input/Output Pins These general purpose pins used logic array.
Global Output Enable input pins. Dedicated Clock input. This clock input connected clock inputs GLBs device. Active Reset which resets registers device. Input Dedicated in-system programming enable pin. This brought enable programming mode. When low, MODE, SDI, SCLK controls become active. Input This performs functions. When ispEN logic low, functions input load programming data into device. SDI/IN also used control pins state machine. When ispEN high, functions dedicated input. Input This performs functions. When ispEN logic low, functions control operation state machine. When ispEN high, functions dedicated input pin. Output/Input This performs functions. When ispEN logic low, functions output read serial shift register data. When ispEN high, functions dedicated input pin. Input This performs functions. When ispEN logic low, functions clock Serial Shift Register. When ispEN high, functions dedicated input pin.
SDI*/IN
MODE*/IN
SDO*/IN
SCLK*/IN
These pins used. Ground (GND)
Table 0002A-08isp/2064 ispLSI 2064 Only ispEN ispLSI 2064 only; pLSI 2064, must left floating tied Vcc, must grounded tied other signal.
1996 Data Book
Specifications ispLSI pLSI 2064
Description Name
RESET
TQFP Numbers
Description
Input/Output Pins These general purpose pins used logic array.
Global Output Enable input pins. Dedicated Clock input. This clock input connected clock inputs GLBs device. Active Reset which resets registers device.
ispEN**/NC
SDI*/IN
MODE*/IN
SDO*/IN
SCLK*/IN
Input Dedicated in-system programming enable input pin. This brought enable programming mode. MODE, SDI, SCLK controls become active. Input This performs functions. When ispEN logic low, functions input load programming data into device. SDI/IN also used control pins state machine. When ispEN high, functions dedicated input pin. Input This performs functions. When ispEN logic low, functions control operation state machine. When ispEN high, functions dedicated input pin. Output/Input This performs functions. When ispEN logic low, functions output read serial shift register data. When ispEN high, functions dedicated input pin. Input This performs functions. When ispEN logic low, functions clock Serial Shift Register. When ispEN high, functions dedicated input pin. These pins used.
Ground (GND)
ispLSI 2064 Only ispEN ispLSI 2064 only; pLSI 2064, must left floating tied Vcc, must grounded tied other signal.
Table 0002-2064.eps
1996 Data Book
Specifications ispLSI pLSI 2064
Configuration
ispLSI pLSI 2064 84-pin PLCC
*ispEN/NC RESET *SDI/IN
*SDO/IN *MODE/IN
SCLK*/IN
ispLSI 2064 pLSI 2064
View
*Pins have dual function capability ispLSI 2064 only (except which ispEN only).
0123A/2064
1996 Data Book
Specifications ispLSI pLSI 2064
Configuration
ispLSI 2064 100-pin TQFP
ispEN RESET *SDI/IN
ispLSI 2064
View
SCLK*/IN
*MODE/IN *SDO/IN
0766A-2064-isp
*Pins have dual function capability.
1996 Data Book
Specifications ispLSI pLSI 2064
Part Number Description
(is)pLSI
Device Family Device Number Speed fmax fmax fmax
2064
Grade Blank Commercial Industrial Package PLCC TQFP Power
212-80Bisp/2000
ispLSI pLSI 2064 Ordering Information
COMMERCIAL Device Family
fmax (MHz)
(ns)
Ordering Number ispLSI 2064-125LJ ispLSI 2064-125LT ispLSI 2064-100LJ ispLSI 2064-100LT ispLSI 2064-80LJ ispLSI 2064-80LT pLSI 2064-125LJ pLSI 2064-100LJ pLSI 2064-80LJ
Package 84-Pin PLCC 100-Pin TQFP 84-Pin PLCC 100-Pin TQFP 84-Pin PLCC 100-Pin TQFP 84-Pin PLCC 84-Pin PLCC 84-Pin PLCC
Table 0041A-08isp/2000
ispLSI
pLSI
INDUSTRIAL Device Family ispLSI
fmax (MHz)
(ns)
Ordering Number ispLSI 2064-80LJI ispLSI 2064-80LTI
Package 84-Pin PLCC 100-Pin TQFP
Table 0041B-08isp/2000
1996 Data Book
Copyright 1996 Lattice Semiconductor Corporation. E2CMOS, GAL, ispGAL, ispLSI, pLSI, pDS, Silicon Forest, UltraMOS, Lattice Logo, with Lattice Semiconductor Corp. (Stylized) registered trademarks Lattice Semiconductor Corporation (LSC). Logo, Generic Array Logic, InSystem Programmability, In-System Programmable, ISP, ispATE, ispCODE, ispDOWNLOAD, ispGDS, ispStarter, ispSTREAM, ispTEST, ispTURBO, Latch-Lock, pDS+, RFT, Total Twin trademarks Lattice Semiconductor Corporation. service mark Lattice Semiconductor Corporation. brand names product names mentioned trademarks registered trademarks their respective holders. Lattice Semiconductor Corporation (LSC) products made under more following U.S. international patents: 4,761,768 4,766,569 4,833,646 4,852,044 4,855,954 4,879,688 4,887,239 4,896,296 5,130,574 5,138,198 5,162,679 5,191,243 5,204,556 5,231,315 5,231,316 5,237,218 5,245,226 5,251,169 5,272,666 5,281,906 5,295,095 5,329,179 5,331,590 5,336,951 5,353,246 5,357,156 5,359,573 5,394,033 5,394,037 5,404,055 5,418,390 5,493,205 0194091 0196771B1 0267271 0196771 0194091 0196771 P3686070.0-08 does represent that products described herein free from patent infringement from third-party right. specifications information herein subject change without notice. Lattice Semiconductor Corporation (LSC) reserves right discontinue product service without notice assumes obligation correct errors contained herein advise user this document correction such made. recommends customers obtain latest version relevant information establish, before ordering, that information being relied upon current. warrants performance products current applicable specifications accordance with LSC's standard warranty. Testing other quality control procedures performed extent deems necessary. Specific testing parameters each product necessarily performed, unless mandated government requirements. assumes liability applications assistance, customer's product design, software performance, infringements patents services arising from products services described herein. products authorized life-support applications, devices systems. Inclusion products such applications prohibited. LATTICE SEMICONDUCTOR CORPORATION 5555 Northeast Moore Court Hillsboro, Oregon 97124 U.S.A. Tel.: (503) 681-0118 FAX: (503) 681-3037 http://www.latticesemi.com
November 1996

High Density Programmable Logic Features HIGH DENSITY PROGRAMMABL

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