512Kx8 CMOS EEPROM, WE512K8-XCX, 5962-93091 FIG. CONFIGURATION VI
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WE512K8, WE256K8, WE128K8-XCX
512Kx8 CMOS EEPROM, WE512K8-XCX, 5962-93091
FIG. CONFIGURATION VIEW
512KX8 CMOS EEPROM MODULE FEATURES
Read Access Times 150, 200, 250, 300ns JEDEC Standard Pin, Hermetic Ceramic (Package 300) Commercial, Industrial Military Temperature Ranges MIL-STD-883 Compliant Devices Available Write Endurance 10,000 Cycles Data Retention 25°C, Years Power CMOS Operation: Standby Typical/100mA Operating Maximum Automatic Page Write Operation Internal Address Data Latches
DESCRIPTION
A0-18 I/O0- Address Inputs Data Input/Output Chip Select Output Enable Write Enable +5.0V Power Ground
Bytes, Bytes/Row, Four Pages Page Write Cycle Time 10mS Max. Data Polling Write Detection Hardware Software Data Protection Compatible Inputs Outputs
BLOCK DIAGRAM
2000 Rev.1
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
WE512K8, WE256K8, WE128K8-XCX
256Kx8 CMOS EEPROM, WE256K8-XCX, 5962-93155
FIG.2 CONFIGURATION VIEW
256KX8 CMOS EEPROM MODULE FEATURES
Read Access Times 150, 200ns JEDEC Standard Pin, Hermetic Ceramic (Package 302) Commercial, Industrial Military Temperature Ranges MIL-STD-883 Compliant Devices Available Write Endurance 10,000 Cycles Data Retention 25°C, Years Power CMOS Operation: Standby Typical/90mA Operating Maximum Automatic Page Write Operation Internal Address Data Latches
DESCRIPTION
A0-17 I/O0-7 Address Inputs Data Input/Output Chip Select Output Enable Write Enable +5.0V Power Ground
Bytes, Bytes/Row, Eight Pages Page Write Cycle Time 10mS Max. Data Polling Write Detection Hardware Software Data Protection Compatible Inputs Outputs
BLOCK DIAGRAM
White Electronic Designs Corporation Phoenix (602) 437-1520
WE512K8, WE256K8, WE128K8-XCX
128Kx8 CMOS EEPROM, WE128K8-XCX, 5962-93154
FIG. CONFIGURATION VIEW
128KX8 CMOS EEPROM MODULE FEATURES
Read Access Times 150, 200ns JEDEC Standard Pin, Hermetic Ceramic (Package 300) Commercial, Industrial Military Temperature Ranges MIL-STD-883 Compliant Devices Available Write Endurance 10,000 Cycles Data Retention 25°C, Years Power CMOS Operation: Standby Typical/70mA Operating Automatic Page Write Operation Internal Address Data Latches
DESCRIPTION
A0-16 I/O0-7 Address Inputs Data Input/Output Chip Select Output Enable Write Enable +5.0V Power Ground
Bytes, Bytes/Row, Four Pages Page Write Cycle Time 10mS Max. Data Polling Write Detection Hardware Software Data Protection Compatible Inputs Outputs
BLOCK DIAGRAM
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
WE512K8, WE256K8, WE128K8-XCX
BSOLUTE MAXIMUM RATINGS
Parameter Operating Temperature Storage Temperature Signal Voltage Voltage Thermal Resistance junction case Lead Temperature (soldering secs) Symbol TSTG +125 +150 -0.6 6.25 -0.6 +13.5 +300 Unit °C/W
TRUTH TABLE
Mode Standby Read Write Disable Write Inhibit Data High Data Data High Z/Data
NOTE: Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
CAPACITANCE +25°C)
Parameter Input Capacitance Condition 1MHz 512Kx8 256Kx8 128Kx8 Unit
Output Capacitance COUT VI/O 1MHz
RECOMMENDED OPERATING CONDITIONS
Parameter Supply Voltage Input High Voltage Input Voltage Operating Temp. (Mil.) Operating Temp. (Ind.) Symbol -0.3 +0.8 +125 Unit
This parameter guaranteed design tested.
CHARACTERISTICS (VCC 5.0V, -55°C +125°C)
Parameter Input Leakage Current Output Leakage Current Dynamic Supply Current Standby Current Output Voltage Output High Voltage Symbol Conditions 5.5, VIH, VIH, VOUT VIL, VIH, 5MHz, VIL, VIH, 5MHz, 2.1mA, 4.5V -400µA, 4.5V 512K 0.45 256K 0.45 128K Unit 0.45
NOTE: test conditions: -0.3V, 0.3V
FIG. TEST CIRCUIT
TEST CONDITIONS
Parameter Input Pulse Levels Input Rise Fall Input Output Reference Level Output Timing Reference Level Unit
Notes: programmable from +7V. programmable from 16mA. Tester Impedance typically midpoint adjusted simulate typical resistive load circuit. tester includes capacitance.
White Electronic Designs Corporation Phoenix (602) 437-1520
WE512K8, WE256K8, WE128K8-XCX READ
Figure shows Read cycle waveforms. read cycle begins with selection address, chip select output enable. Chip select accomplished placing line low. Output enable done placing line low. memory places selected data byte I/O0 through I/O7 after access time. output memory placed high impedance state shortly after either line line returned high level.
FIG. READ WAVEFORMS
NOTE: delayed tACS-tOE after falling edge without impact tACC -tOE after address change without impact tACC.
READ CHARACTERISTICS (SEE FIGURE WE512K8-XCX (VCC= 5.0V, -55°C +125°C)
Parameter Read Cycle Time Address Access Time Chip Select Access Time Output Hold from Address Change, Output Enable Output Valid Chip Select Output Enable High Output Symbol tACC tACS -150 -200 -250 -300 Unit
WE256K8-XCX WE128K8-XCX
Parameter Read Cycle Time Address Access Time Chip Select Access Time Output Hold from Address Change, Output Enable Output Valid Chip Select Output Enable High Output Symbol tACC tACS
-150
-200
Unit
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
WE512K8, WE256K8, WE128K8-XCX WRITE
Write operations initiated when both high. EEPROM devices support both controlled write cycle. address latched falling edge either whichever occurs last. data latched internally rising edge either whichever occurs first. byte write operation will automatically continue completion.
WRITE CYCLE TIMING
Figures show write cycle timing relationships. write cycle begins with address application, write enable chip select. Chip select accomplished placing line low. Write enable consists setting line low. write cycle begins when last either goes low. line transition from high also initiates internal 150µsec delay timer permit page mode operation. Each subsequent transition from high that occurs before completion 150µsec time will restart timer from zero. operation timer same retriggerable one-shot.
WRITE CHARACTERISTICS (VCC 5.0V, -55°C +125°C)
Parameter Write Cycle Time, Address Set-up Time Write Pulse Width Chip Select Set-up Time Address Hold Time Data Hold Time Chip Select Hold Time Data Set-up Time Output Enable Set-up Time Output Enable Hold Time Write Pulse Width High Symbol tOES tOEH tWPH 512K 256K 128K Unit
NOTES: must remain valid through pulse, 512K A16, must remain valid through pulse, 256K must remain valid through pulse, 128K
White Electronic Designs Corporation Phoenix (602) 437-1520
WE512K8, WE256K8, WE128K8-XCX
FIG. WRITE WAVEFORMS CONTROLLED
NOTE: Decoded Address Lines must valid duration write.
FIG. WRITE WAVEFORMS CONTROLLED
NOTE: Decoded Address Lines must valid duration write.
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
WE512K8, WE256K8, WE128K8-XCX DATA POLLING
Operation with data polling permits faster method writing EEPROM. actual time complete memory programming cycle faster than guaranteed maximum. EEPROM features method determine when internal programming cycle completed. After write cycle initiated, EEPROM will respond read cycles provide microprocessor with status programming cycle. status consists last data byte written being returned with data complemented during programming cycle, I/O7 true after completion. Data polling allows simple test operation determine status EEPROM. During internal programming cycle, read last byte written will produce complement data I/O7. example, data written consisted I/O7 HIGH, then data read back would consist I/O7 LOW. polled byte write sequence would consist following steps: write byte EEPROM store last byte last address written release time slice other tasks read byte from EEPROM last address compare I/O7 stored value different, write cycle completed, step same, write cycle completed, step step
DATA POLLING CHARACTERISTICS (VCC 5.0V, -55°C +125°C)
Parameter Data Hold Time Output Enable Hold Time Output Enable Output Delay Write Recovery Time Symbol tOEH 512Kx8 256Kx8 128Kx8 Unit
FIG. DATA POLLING WAVEFORMS
White Electronic Designs Corporation Phoenix (602) 437-1520
WE512K8, WE256K8, WE128K8-XCX PAGE WRITE OPERATION
These devices have page write operation that allows bytes data (one bytes WE512K8) written into device then simultaneously written during internal programming period. Successive bytes loaded same manner after first data byte been loaded. internal timer begins time operation each write cycle. another write cycle completed within 150µs less, time period begins. Each write cycle restarts delay period. write cycles continued long interval less than time period. usual procedure increment least significant address lines from through through WE512K8) each write cycle. this manner page bytes (128 bytes WE512K8) loaded into EEPROM burst mode before beginning relatively long interval programming cycle. After 150µs time completed, EEPROM begins internal write cycle. During this cycle entire page bytes will written same time. internal programming cycle same regardless number bytes accessed. page address must same each byte load must valid during each high transition CS). block address also must same each byte load must remain valid throughout pulse. page block address lines summarized below:
PAGE MODE CHARACTERISTICS (VCC 5.0V, -55°C +125°C) Parameter Write Cycle Time, Data Set-up Time Data Hold Time Write Pulse Width Byte Load Cycle Time Write Pulse Width High Symbol tBLC tWPH Unit
Device WE512K8-XCX WE256K8-XCX WE128K8-XCX
Block Address A17-A18 A15-A17 A15-A16
Page Address -A16 -A14 -A14
FIG. PAGE WRITE WAVEFORMS
NOTE: Decoded Address Lines must valid duration write.
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
WE512K8, WE256K8, WE128K8-XCX
FIG. SOFTWARE BLOCK DATA PROTECTION ENABLE LGORITHM
LOAD DATA ADDRESS 5555 LOAD DATA ADDRESS 2AAA LOAD DATA ADDRESS 5555 LOAD DATA ADDRESS(4)
WRITES
ENABLED(2)
LOAD LAST BYTE ENTER DATA LAST ADDRESS PROTECT STATE
NOTES: Data Format: I/O7-0 (Hex); Address Format: (Hex). control selection four blocks 512Kx8. A16, control selection pages 256Kx8. control four blocks 128Kx8. Write Protect state will activated write even other data loaded. Write Protect state will deactivated write period even other data loaded. bytes data each blocks loaded 512Kx8. bytes data each blocks loaded 256Kx8 bytes blocks 128Kx8.
White Electronic Designs Corporation Phoenix (602) 437-1520
WE512K8, WE256K8, WE128K8-XCX SOFTWARE DATA PROTECTION
software write protection feature enabled disabled user. When shipped White Microelectronics, devices have feature disabled. Write access device unrestricted. enable software write protection, user writes three access code bytes three special internal locations. Once write protection been enabled, each write EEPROM must same three byte write sequence permit writing. After setting software data protection, attempt write device without three-byte command sequence will start internal write timers. data will written device, however, duration tWC. write protection feature disabled byte write sequence specific data specific locations. Power transitions will reset software write protection. Each byte block (128K bytes WE512K8) EEPROM independent write protection. more blocks enabled rest disabled combination. software write protection guards against inadvertent writes during power transitions unauthorized modification using PROM programmer. block selection controlled upper most address lines (A17 through WE512K8, through WE256K8, WE128K8).
FIG. SOFTWARE BLOCK DATA PROTECTION DISABLE LGORITHM
LOAD DATA ADDRESS 5555 LOAD DATA ADDRESS 2AAA LOAD DATA ADDRESS 5555 LOAD DATA ADDRESS 5555 LOAD DATA ADDRESS 2AAA LOAD DATA ADDRESS 5555 LOAD DATA ADDRESS(4) LOAD LAST BYTE LAST ADDRESS
EXIT DATA PROTECT STATE(3)
HARDWARE DATA PROTECTION
Several methods hardware data protection have been implemented White Microelectronics EEPROM. These included improve reliability during normal operations. power delay climbs past 3.8V typical device will wait 5mSec typical before allowing write cycles. sense While below 3.8V typical write cycles inhibited. Write inhibiting Holding either high inhibits write cycles. Noise filter Pulses <8ns (typ) will initiate write cycle.
NOTES: Data Format: I/O7-0 (Hex); Address Format: (Hex). control selection four blocks 512Kx8. A15, control selection pages 256Kx8. control four blocks 128Kx8. Write Protect state will activated write even other data loaded. Write Protect state will deactivated write period even other data loaded. bytes data each blocks loaded 512Kx8. bytes data each blocks loaded 256Kx8 bytes blocks 128Kx8.
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
WE512K8, WE256K8, WE128K8-XCX
PACKAGE 300: PIN, CERAMIC DIP, SINGLE CAVITY SIDE BRAZED
LINEAR DIMENSIONS MILLIMETERS PARENTHETICALLY INCHES
PACKAGE 302: PIN, CERAMIC DIP, DUAL CAVITY BOTTOM BRAZED
LINEAR DIMENSIONS MILLIMETERS PARENTHETICALLY INCHES
White Electronic Designs Corporation Phoenix (602) 437-1520
WE512K8, WE256K8, WE128K8-XCX
ORDERING INFORMATION
XXXK8
LEAD FINISH: Blank Gold plated leads Solder leads PROCESSING: MIL-STD-883 Compliant Military Screened Industrial Commercial PACKAGE: Ceramic (Package 128Kx8) (Package 256Kx8) (Package 512Kx8) ACCESS TIME (ns) ORGANIZATION, 512Kx8, 256Kx8 128Kx8 EEPROM WHITE ELECTRONIC DESIGNS -55°C +125°C -40°C +85°C +70°C
DEVICE TYPE
512K EEPROM 512K EEPROM 512K EEPROM 512K EEPROM 256K EEPROM 256K EEPROM 128K EEPROM 128K EEPROM
SPEED
150ns 300ns 250ns 200ns 200ns 150ns 200ns 150ns
PACKAGE
PART
WE512K8-150CQ WE512K8-300CQ WE512K8-250CQ WE512K8-200CQ WE256K8-200CQ WE256K8-150CQ WE128K8-200CQ WE128K8-150CQ
5962-93091 01HYX 5962-93091 02HYX 5962-93091 03HYX 5962-93091 04HYX 5962-93155 01HYX 5962-93155 02HYX 5962-93154 01HXX 5962-93154 02HXX
DEVICE TYPE PART
SPEED PACKAGE
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
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