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FEATURES 96-Bit Pixel Port 1600 1280 Screen Resolution MHz, 24-Bit (30-Bit Gamma Corrected) True-Color Triple 10-Bit "Gamma Correcting" Converters (max) Color Matching Triple (256 Color Palette On-Board User Definable Cursor Three Color Overlay Cursor Palette Fully Programmable On-Board RS-343A/RS-170 Compatible Analog Outputs Tri-Level SYNC Functionality Compatible Digital Inputs Standard Interface Programmable Pixel Port: 24-Bit, 16-Bit, 15-Bit 8-Bit (Pseudo) Pixel Data Serializer: Multiplexed Pixel Input Ports; 2:1, 4:1, CMOS Monolithic Construction 160-Lead Plastic Quad Flatpack (QFP): ADV7162 160-Lead "Thermally Enhanced" (PQUAD): ADV7160
registered trademark Analog Devices, Inc.
TRISYNC SYNC BLANK PIXEL DATA (P7-P0) PALETTE SELECTS (PS0, PS1) ODD/EVEN LOADIN COLOR MODE MATRIX
96-Bit, True-Color Video RAM-DAC ADV7160/ADV7162
MODES OPERATION 1600 1200 30/24-Bit Resolution Screen Refresh 1600 1200 16/15-Bit Resolution Screen Refresh 1600 1200 8-Bit Resolution Screen Refresh APPLICATIONS Windows Accelerators High Resolution, True Color Graphics Professional Color Prepress Imaging Digital (HDTV, Digital Video) SPEED GRADES GENERAL DESCRIPTION
ADV7160/ADV7162® 96-bit pixel port Video RAMDAC with color enhanced triple 10-bit DACs. device also includes hardware cursor. ADV7160/ ADV7162 specifically designed graphics subsystem high performance, color graphics workstations windows accelerators. (Continued page
FUNCTIONAL BLOCK DIAGRAM
SYNCOUT BLANK SYNC LOGIC
BYPASS COLOR MODE MATRIX
COLOR PALETTE
PIXEL MASK GREEN BLUE
COLOR OVERLAY PALETTE
FUNCTION DECODE LOGIC CURSOR GENERATOR GREEN BLUE
GREEN
COLOR CURSOR PALETTE
GREEN BLUE
BLUE
ADV7160/ ADV7162
DATA PALETTES REGISTER GREEN REGISTER JTAG TEST ACCESS PORT (8+2) BLUE REGISTER VOLTAGE REFERENCE CIRCUIT VREF RSET COMP
CLOCK CONTROL
LOADOUT PRGCKOUT SCKOUT SCKIN CLOCK DIVIDE SYNCHRONIZATION CIRCUITRY ÷32, ÷16,
CONTROL REGISTERS
CURSOR REGISTERS TEST REGISTERS
PIXEL MASK REGISTER REVISION REGISTER REGISTERS COMMAND REGISTERS (CR1-CR5)
ADDRESS REGISTER (A10-A0)
MODE REGISTER (MR1)
REGISTER STATUS REGISTER
SELECTOR
CLOCK CLOCK CMOS
PORT
PLLREF
D9-D0
REV.
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices. Analog Devices, Inc., 1995 Technology Way, P.O. 9106, Norwood. 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703
ADV7160/ADV7162-SPECIFICATIONS
Parameter STATIC PERFORMANCE Resolution (Each DAC) Accuracy (Each DAC) Integral Nonlinearity Differential Nonlinearity Gray Scale Error Coding DIGITAL INPUTS Input High Voltage, VINH Input Voltage, VINL Input Current, Input Capacitance, CLOCK INPUTS (CLOCK, CLOCK) Input High Voltage, VINH Input Voltage, VINL Input Current, Input Current, (JTAG Inputs) Input Capacitance, DIGITAL OUTPUTS Output High Voltage, Output Voltage, Floating-State Leakage Current Floating-State Output Capacitance ANALOG OUTPUTS Gray Scale Current Range Output Current White Level Relative Blank White Level Relative Black Black Level Relative Blank Blank Level Blank Level Sync Level Tri-Sync Level Relative Blank Size Matching Output Compliance, Output Impedance, ROUT Output Capacitance, COUT VOLTAGE REFERENCE Voltage Reference Range, VREF Input Current, IVREF POWER REQUIREMENTS IAA3 IAA3 Power Supply Rejection Ratio DYNAMIC PERFORMANCE Clock Data Feedthrough4, Glitch Impulse Crosstalk6
(VAA1 VREF +1.235 RSET IOR, IOG, 37.5 pF). specifications TMIN TMAX2 unless otherwise noted.)
Units Bits Gray Scale Binary secs Test Conditions/Comments (DAC Gain Setting 3996)
Guaranteed Monotonic
17.69 16.74 0.95 6.29 6.29 19.05 17.62 1.44 7.62 7.62 17.22 1.14 1.235 1.26 20.40 18.50 1.90 8.96 8.96 +1.4
ISOURCE ISINK
(DAC Gain Setting 3996)
Sync Disabled Sync Enabled
IOUT VREF 1.235 Specified Performance
Operation (ADV7160) Operation (ADV7160) Operation (ADV7160) Operation (ADV7162) Operation (ADV7162) Operation (ADV7162) COMP
NOTES versions. Temperature range TMAX): +70°C. Pixel Port continuously clocked with data corresponding linear ramp. 100oC. Clock data feedthrough function amount overshoot undershoot digital inputs. Glitch impulse includes clock data feedthrough. input values with input rise/fall times measured points. Timing reference points inputs outputs. Crosstalk measured holding high while other making high high transitions. Specifications subject change without notice.
REV.
ADV7160/ADV7162 TIMING CHARACTERISTICS
Parameter fCLOCK fLOADIN Multiplexing Multiplexing Multiplexing Multiplexing Multiplexing Multiplexing Multiplexing Multiplexing Multiplexing Multiplexing Multiplexing Multiplexing -t115 tPD6 Multiplexing Multiplexing Multiplexing
ANALOG OUTPUTS7
(VAA VREF +1.235 RSET IOR, IOG, 37.5 pF).
specifications TMIN TMAX unless otherwise noted.)
CLOCK CONTROL PIXEL PORT
Version
Version 5.88
Version 7.14 2.86 2.86
Units
Conditions/Comments Pixel CLOCK Rate Pixel CLOCK Cycle Time Pixel CLOCK High Time Pixel CLOCK Time Pixel CLOCK LOADOUT Delay LOADIN Clocking Rate
27.5 18.18 36.36
42.5 21.25 11.77 23.53 47.1
17.5 14.29 28.58 57.16
LOADIN Cycle Time LOADIN High Time LOADIN Time Pixel Data Setup Time Pixel Data Hold Time LOADOUT LOADIN Delay LOADOUT LOADIN Delay Pipeline Delay CLOCK Pixel CLOCK PRGCKOUT Delay SCKIN SCKOUT Delay BLANK SCKIN Setup Time BLANK SCKIN Hold Time
CLOCKs CLOCKs CLOCKs
Parameter
Version
Version
Version
Units
Conditions/Comments
Analog Output Delay Analog Output Rise/Fall Time Analog Output Transition Time Analog Output Skew
REV.
ADV7160/ADV7162
PORT
Parameter t238 t249 t259 t269
Version
Version
Version
Units
Conditions/Comments R/W, Setup Time R/W, Hold Time Time High Time Asserted Data-Bus Driven Asserted Data Valid Disabled Data-Bus Three-Stated Disabled Data Invalid Write Data (D0-D9) Setup Time Write Data (D0-D9) Hold Time
NOTES General Notes input values volts, with input rise/fall times measured between points. inputs (CLOCK, CLOCK) VAA-0.8 VAA-1.8 with input rise/fall times measured between points. Timing reference points inputs outputs. Analog output load Data-Bus (D0-D9) loaded shown Figure Digital output load LOADOUT, PRGCKOUT SCKOUT versions Temperature range TMAX); +70°C. Notes PIXEL PORT Pixel Port consists following inputs: Pixel Inputs: GREEN BLUE Palette Selects: PS1[A, Pixel Controls: SYNC, BLANK, TRISYNC, ODD/EVEN Clock Inputs: CLOCK, CLOCK, LOADIN, SCKIN Clock Outputs: LOADOUT, PRGCKOUT, SCKOUT LOADOUT Cycle Time function Pixel CLOCK Rate Multiplexing Mode: multiplexing; CLOCK multiplexing; CLOCK multiplexing; CLOCK These fixed values Pipeline Delay valid under conditions where -t11 met. either -t11 met, part will operate Pipeline Delay increased. Notes ANALOG OUTPUTS Output delay measured from point rising edge CLOCK point full-scale transition. Output rise/fall time measured between points full-scale transition. Transition time measured from point full scale transition output remaining within final output value. (Transition time does include clock data feedthrough). Notes PORT measured with load circuit Figure defined time required output cross derived from measured time taken data outputs change when loaded with circuit Figure measured numbers then extrapolated back remove effects charging capacitor. This means that times t26, quoted Timing Characteristics true values device such independent external loading capacitances. Specifications subject change without notice.
ISINK
OUTPUT
+2.1V 100pF ISOURCE
Figure Load Circuit Databus Access Relinquish Times
REV.
ADV7160/ADV7162 TIMING CHARACTERISTICS (Cont.)
JTAG PORT
(VAA VREF +1.235 3RSET IOR, IOG, 37.5 pF).
specifications TMIN TMAX unless otherwise noted.)
Parameter PERFORMANCE Jitter REFERENCE INPUT PLLREF Frequency PLLREF Period PLLREF Duty Cycle JTAG PERFORMANCE Frequency, High Time, Time, TDI, Setup Time, TDI, Hold Time, Digital Input Setup Time, Digital Input Hold Time, TCLK Drive, TCLK Valid, TCLK Three-State,
Versions 1.67
Units
Conditions/Comments
NOTES input values volts, with input rise/fall times measured between points. Timing reference points inputs outputs. versions. Temperature range TMAX); +70°C. Jitter measured triggering output clock, delayed then measuring time period from trigger edge next edge output clock after delay. This measurement repeated multiple times value determined. Specifications subject change without notice.
TMS,
DIGITAL INPUT
Figure JTAG Timing
REV.
ADV7160/ADV7162 Timing Waveforms
CLOCK
CLOCK
LOADOUT (2:1 MULTIPLEXING)
LOADOUT (4:1 MULTIPLEXING)
LOADOUT (8:1 MULTIPLEXING)
Figure LOADOUT Pixel Clock Input (CLOCK, CLOCK)
LOADIN
PIXEL INPUT DATA VALID DATA
VALID DATA
VALID DATA
Figure LOADIN Pixel Input
REV.
ADV7160/ADV7162
CLOCK
LOADOUT
LOADIN
PIXEL INPUT DATA
AN+1 HN+1
AN+2 HN+2
INPU PIPE LINE
ANALOG OUTPUT DATA (IOR, IOG, IOB, SYNCOUT)
AN-1 HN-1
AN+1 HN+1
AN+2 HN+2
Figure Pixel Input Analog Output Pipeline with Minimum LOADOUT LOADIN Delay (8:1 Multiplex Mode)
CLOCK
-t11
LOADOUT
LOADIN
PIXEL INPUT DATA
AN+1 HN+1
AN+2 HN+2
ANALOG OUTPUT DATA (IOR, IOG, IOB, SYNCOUT)
AN-1 HN-1
AN+1 HN+1
AN+2 HN+2
Figure Pixel Input Analog Output Pipeline with Maximum LOADOUT LOADIN Delay (8:1 Multiplex Mode)
REV.
ADV7160/ADV7162
CLOCK
LOADOUT
LOADIN
PIXEL INPUT DATA
AN+1 DN+1
AN+2 DN+2
DIGIT OUTP INPUT ELINE ALOG
ANALOG OUTPUT DATA (IOR, IOG, IOB, SYNCOUT)
AN-1 DN-1
AN+1 DN+1
AN+2 DN+2
Figure Pixel Input Analog Output Pipeline with Minimum LOADOUT LOADIN Delay (4:1 Multiplex Mode)
CLOCK
-t11
LOADOUT
LOADIN
PIXEL INPUT DATA
AN+1 DN+1
AN+2 DN+2
DIGIT INPUT PIPE ANAL LINE
ANALOG OUTPUT DATA (IOR, IOG, IOB, SYNCOUT)
AN-1 DN-1
AN+1 DN+1
AN+2 DN+2
Figure Pixel Input Analog Output Pipeline with Maximum LOADOUT LOADIN Delay (4:1 Multiplex Mode)
REV.
ADV7160/ADV7162
CLOCK
LOADOUT
LOADIN
PIXEL INPUT DATA
AN+1 BN+1
AN+2 BN+2
DIGITAL
INPUT
ANALOG
OUTPUT
PIPELINE
ANALOG OUTPUT DATA (IOR, IOG, IOB, SYNCOUT)
AN-1
BN-1
AN+1
BN+1
AN+2
BN+2
Figure Pixel Input Analog Output Pipeline with Minimum LOADOUT LOADIN Delay (2:1 Multiplex Mode)
CLOCK
-t10
LOADOUT
LOADIN
PIXEL INPUT DATA
AN+1 BN+1
AN+2 BN+2
DIGITAL
INPUT
ANALOG
OUTPUT
PIPELIN
BN-1 AN+1 BN+1 AN+2 BN+2
ANALOG OUTPUT DATA (IOR, IOG, IOB, SYNCOUT)
AN-1
Figure Pixel Input Analog Output Pipeline with Maximum LOADOUT LOADIN Delay (2:1 Multiplex Mode)
REV.
ADV7160/ADV7162
CLOCK PRGCKOUT (CLOCK/4)
PRGCKOUT (CLOCK/8)
PRGCKOUT (CLOCK/16) PRGCKOUT (CLOCK/32)
Figure Pixel Clock Input Programmable Clock Output (PRGCKOUT)
SCKIN
BLANK
BLANKING PERIOD
SCKOUT
SCAN LINE
START SCAN LINE (N+1)
Figure Video Data Shift Clock Input (SCKIN) BLANK Video Data Shift Clock Output (SCKOUT)
CLOCK
WHITE LEVEL
ANALOG OUTPUTS
SYNCOUT
FULL SCALE TRANSITION
BLACK LEVEL NOTE: THIS DIAGRAM SCALE. PURPOSES CLARITY, ANALOG OUTPUT WAVEFORM MAGNIFIED TIME AMPLLITUDE W.R.T CLOCK WAVEFORM. SYNCOUT DIGITAL VIDEO OUTPUT SIGNAL. ONLY RELEVANT TIMING SPECIFICATION SYNCOUT.
Figure Analog Output Response CLOCK
-10-
REV.
ADV7160/ADV7162
R/W,
VALID CONTROL DATA
D0-D9 (READ MODE)
D0-D9 (WRITE MODE)
Figure Microprocessor Port (MPU) Interface Timing
ABSOLUTE MAXIMUM RATINGS
160-Lead Configuration
Voltage Digital Ambient Operating Temperature (TA) +70°C Storage Temperature (TS) -65°C +150°C Junction Temperature (TJ) +150°C Lead Temperature (Soldering, secs) +260°C Vapor Phase Soldering minute) +220°C Analog Outputs GND2
NOTES Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only functional operation device these other conditions above those listed operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability. Analog Output Short Circuit Power Supply Common indefinite duration.
VIEW (NOT SCALE)
ORDERING INFORMATION
IDENTIFIER
ADV7160KS2203 ADV7162KS2204
Clock Speed ADV7160KS1703 ADV7162KS1704
ADV7160/ADV7162
ADV7160KS1403 ADV7162KS1404
NOTES devices specified +70°C operation. Contact Sales Office latest information package design. ADV7160 packaged 160-pin plastic power quad flatpack, with heatsink embedded. ADV7162 packaged standard 160-pin plastic quad flatpack, QFP.
CAUTION (electrostatic discharge) sensitive device. Electrostatic charges high 4000 readily accumulate human body test equipment discharge without detection. Although ADV7160/ADV7162 features proprietary protection circuitry, permanent damage occur devices subjected high energy electrostatic discharges. Therefore, proper precautions recommended avoid performance degradation loss functionality.
WARNING!
SENSITIVE DEVICE
REV.
-11-
ADV7160/ADV7162
ADV7160/ADV7162 ASSIGNMENTS
Mnemonic PLLREF PS0A PS0B PS0C PS0D PS1A PS1B PS1C PS1D CLOCK
Mnemonic CLOCK SCKIN SCKOUT PRGCKOUT LOADOUT LOADIN
Mnemonic SYNCOUT TRISYNC ODD/EVEN SYNC BLANK VREF COMP RSET
Mnemonic
-12-
REV.
ADV7160/ADV7162
FUNCTION DESCRIPTION
Mnemonic
Function
(R0A R7D), GREEN (G0A G7D), BLUE (B0A B7D): Pixel Port (TTL Compatible Inputs): pixel select inputs, with bits each Red, Green Blue. Each multiplexed [A-D] 2:1. configured 24-Bit True-Color Data, 8-Bit Pseudo-Color Data, 16-Bit True-Color 15-Bit True-Color Data formats. 8-Bit Pseudo-Color Mode, there special case whereby multiplexing also available. will explained more detail later. Pixel Data latched into device rising edge LOADIN. PS0A PS0D, PS1A PS1D Palette Priority Selects (TTL Compatible Inputs): eight inputs provide Bits after input multiplexing. These pixel port select inputs configured three separate functions. Overlay Mode, these inputs provide three color overlay function. With value other than "00" overlay inputs, color displayed comes from overlay palette instead main pixel inputs. ADV7160, Bypass Mode, specifies each pixel whether should pass through Color Matrix Color Palette bypass Matrix Palette. acts overlay input. (This mode available ADV7162.) Palette Select Mode used multiplex outputs number devices. When palette mode inputs match bits mode register, part operates normal. When there mismatch, outputs switched zero, allowing outputs another device drive monitor. LOADIN LOADOUT Pixel Data Load Input (TTL Compatible Input): This input latches multiplexed pixel data, including PS0-PS1, BLANK, TRISYNC, SYNC ODD/EVEN into device. Pixel Data Load Output (TTL Compatible Output): This output control signal runs divided down frequency pixel clock. frequency function multiplex rate. used directly indirectly drive LOADIN. fLOADOUT fCLOCK/M where Multiplex Mode) Multiplex Mode) Multiplex Mode) PRGCKOUT Programmable Clock Output (TTL Compatible Output): This output control signal runs divided down frequency pixel Clock. frequency user programmable determined bits CR30 CR31 Command Register fPRGCKOUT fCLOCK/N where SCKIN Video Shift Clock Input (TTL Compatible Input): signal this input internally gated synchronously with BLANK signal. resultant output, SCKOUT, video clocking signal that stopped during video blanking periods. normally driven divided down version CLOCK frequency. Video Shift Clock Output (TTL Compatible Output): This output synchronously gated version SCKIN BLANK. SCKOUT video clocking signal that stopped during video blanking periods. Clock Inputs (ECL Compatible Inputs): These differential clock inputs designed driven logic levels configured single supply operation. clock rate normally pixel clock rate system. Clock Input (TTL Compatible Input): This clock input designed driven logic levels. then configured output specific frequency depending Registers. section more detail. Composite Blank (TTL Compatible Input): This video control signal drives analog outputs blanking level. Composite-Sync Input (TTL Compatible Input): This video control signal drives analog outputs SYNC level. only asserted during blanking period. CR22 Command Register must SYNC decoded onto analog output, CR41 Command Register must SYNC decoded onto analog output, CR42 Command Register must SYNC decoded onto analog output, otherwise SYNC input ignored.
SCKOUT
CLOCK, CLOCK
PLLREF
BLANK SYNC
REV.
-13-
ADV7160/ADV7162
Mnemonic SYNCOUT TRISYNC Function Composite-Sync Output (TTL Compatible Output). This video output delayed version SYNC. delay corresponds number pipeline stages device. Composite-Sync HDTV Control (TTL Compatible Output). This video input enabled using CR17 Command Register When TRISYNC low, output which Sync enabled, goes tri-sync level. with SYNC input, should only activated while BLANK low. Data (TTL Compatible Input/Output Bus). Data, including color palette values device control information written read from device over this 10-bit, bidirectional databus. 10-bit data 8-bit data used. databus configured either 10-bit parallel data byte data (8+2) well standard 8-bit data. unused bits data should terminated through resistor either digital power plane (VCC) GND. Odd/Even Control (TTL Compatible Input). This input indicates which field frame being displayed. required ensure proper operation ADV7160/ADV7162 cursor when interlaced display mode selected. ignored when noninterlaced display mode selected. This input should change only during vertical blank period. assumed that field will always follow even field vice versa. Chip Enable (TTL Compatible Input). This input must Logic when writing reading from device over data (D0-D9). Internally, data latched rising edge Read/Write Control (TTL Compatible Input). This input determines whether data written read from device's registers color palette RAM. must Logic write data part. must Logic Logic read from device. Command Controls (TTL Compatible Inputs). These inputs determine type read write operation being performed device over data bus, (see Interface Truth Table). Data these inputs latched falling edge Red, Green Blue Current Outputs (High Impedance Current Sources). These video outputs specified directly drive RS-343A RS-170 video levels into doubly terminated loads. Voltage Reference Input (Analog Input): external 1.235 voltage reference required drive this input. AD589 (2-terminal voltage reference) equivalent recommended. (Note: recommended resistor network generate voltage reference.) Output Full Scale Adjust Control (Analog Input). resistor connected between this analog ground controls absolute amplitude output video signal. value RSET nominally with 37.5 termination using CR43 CR44 Command Register Gain shown, required Video Standard achieved. CR44 CR43 Video Standard RS343A, Sync Pedestal RS343A, Sync Pedestal RS343A, Sync Pedestal RS170, Sync Pedestal Gain 3996 4224 4311 5592 Black White 17.62 18.63 19.05 24.67
D9-D0
ODD/EVEN
IOR, IOG, VREF
RSET
Alternatively, RSET calculated following equation:
RSET
COMP GND: TMS, TCK, TDI,
Gain Black White Current
Compensation Pin. capacitor should connected between this VAA. Power Supply 5%). part contains multiple power supply pins, should connected together common filtered analog power supply. Analog Ground. part contains multiple ground pins, should connected together system's ground plane. These four pins control JTAG test access port. Appendix more detail
-14-
REV.
ADV7160/ADV7162
(Continued from page ADV7160/ADV7162 integrates number graphic functions onto device allowing 24-bit direct True-Color (30-bit Corrected-Color) operation maximum screen resolution 1600 1280 refresh rate ADV7160/ ADV7162 integrates Color Palette with three high speed, 10-bit, digital-to analog converters (RGB DACs). also contains user-definable, X-Windows compatible, cursor generator associated RAM. on-board Overlay Palette also included. device's 96-bit Programmable Pixel Port enables various data formats input part. on-board clock synchronization circuit controls clocking functions both part graphics subsystem. There video data paths through ADV7160/ADV7162. routes data from pixel port through DACs, other bypasses routes data direct from pixel port DACs. Either path selected pixel pixel basis. This allows overlay active video window graphics background. on-board palette priority select inputs enable multiple palette devices connected together multipalette window applications. part controlled programmed through microprocessor (MPU) port. bits resolution, associated with color look-up table triple 10-bit DAC, realizes 24-bit True-Color resolution, while also allowing on-board implementation linearization algorithms, such Gamma-Correction Monitor Callibration. This allows effective 30-bit True-Color operation. on-chip video clock controller circuit generates internal clocking some additional external clocking signals. high accuracy, jitter board eliminates need external high speed clock generator. programmed produce pixel clock that multiple reference clock. ADV7162 packaged standard plastic 160-pin quad flatpack (QFP). ADV7160 packaged plastic 160-pin power quad flatpack (PQUAD). Superior thermal distribution achieved inclusion copper heatslug, within standard package outline, which attached. This part ideally suited high performance applications where external environmental conditions unpredictable uncontrollable.
CIRCUIT DETAILS OPERATION
OVERVIEW
Digital video pixel data latched into ADV7160/ADV7162 over devices Pixel Port. This data acts pointer onboard Color Palette RAM. data address pointed latched digital-to-analog converters (DACs) output analog video signal. purposes clarity description, ADV7160/ADV7162 broken down into three separate functional blocks. These are: Pixel Port Clock Control Circuit Port, Registers Color Palette Digital-to-Analog Converters Video Outputs
Pixel Port Clock Control Circuit
input signal PLLREF required part operational. additional signals external glue logic required Pixel Port Clock Control Circuit part operational.
GREEN BLUE
MULTIPLEXER
Pixel Port ADV7160/ADV7162 directly interfaced video/graphics pipeline computer graphics subsystem. connected directly through gate array video systems Frame-Buffer (video memory). pixel port device consists Color Data Pixel Controls Palette Selects Clock Inputs Clock Outputs RED, GREEN, BLUE SYNC, BLANK, TRISYNC PS0A-D, PS1A-D CLOCK, CLOCK, PLLREF, LOADIN, SCKIN LOADOUT, PRGCKOUT, SCKOUT
Figure Multiplexed Color Inputs ADV7160/ADV7162
Pixel Port (Color Data)
associated clocking signals pixel port include:
ADV7160/ADV7162 color data inputs. part four (for multiplexing) 24-bit wide direct color data inputs. These user programmed support number color data formats including 24-bit True-Color, 16-bit True-Color, 15-bit True-Color multiplex modes, 8-bit Pseudo-Color (see "Multiplexing" section) 8:1, multiplex modes. Color data latched into parts pixel port every rising edge LOADIN (see Timing Waveform, Figure required frequency LOADIN determined multiplex rate, where multiplex mode fLOADIN fCLOCK/8 multiplex mode fLOADIN fCLOCK/4 multiplex mode fLOADIN fCLOCK/2
These on-board clock control signals included simplify interfacing between part frame buffer. Either control input signals CLOCK CLOCK (ECL Levels) REV.
-15-
ADV7160/ADV7162
Other pixel data signals latched into device LOADIN include SYNC, BLANK, TRISYNC PS0A-D PS1A-D. Internally, data pipelined through part differential pixel clock inputs, CLOCK CLOCK internal pixel clock generated on-board. LOADIN control signal need only have frequency synchronous relationship pixel CLOCK (see "Pipeline Delay On-Board Calibration" section). completely phase independent LOADIN signal used with ADV7160/ADV7162, allowing CLOCK occur anywhere during LOADIN cycle. Alternatively, LOADOUT signal ADV7160/ADV7162 used. LOADOUT connected either directly indirectly LOADIN. frequency automatically correct LOADIN requirement.
SYNC, BLANK
However, Mode, 8-Bit Pseudo Color, unused Blue Pixel Inputs used provide extra inputs. bypass mode unavailable this case.
Palette Select Mode
These pixel port select inputs effectively determine whether devices analog outputs turned-on shut down. When analog outputs shut down, IOR, forced regardless state pixel control data inputs. This state determined pixel pixel basis PS0-PS1 inputs multiplexed exactly same format pixel port color data. These controls allow switching between multiple palette devices. values match values programmed into bits MR16 MR17 Mode Register, then device selected, there match device effectively shut down.
Bypass Mode Control (ADV7160 Only)
BLANK SYNC video control signals drive analog outputs Blank Sync levels respectively. These signals latched into part rising edge LOADIN. SYNC information encoded onto analog signal when CR22 Command Register "1," analog signal when CR41 Command Register analog signal when CR42 Command Register "1." SYNC input ignored CR22, CR41 CR42 logic "0."
SYNCOUT
this mode used switch between color modes through Color Palette Palette Bypass modes pixel pixel basis. color mode through palette selected using Bits CR27-CR24 Command Register Bypass Color Mode selected using Bits CR17 CR16 Command Register then switches between Palette Color Mode, Bypass Color Mode. input continues overlay input, allowing Overlay Color displayed. Color Mode Palette Color Mode (CR27-CR24) Bypass Color Mode (CR17-CR16) Overlay Color
some applications where permissible encode SYNC green (IOG), blue (IOB), (IOR), SYNCOUT used separate digital SYNC output. This advantage over independent ADV7160/ADV7162) SYNC that does necessitate knowing absolute pipeline delay part. This allows complete independence between LOADIN/Pixel Data CLOCK. SYNC input connected device normal with CR22 Command Register CR41 Command Register CR42 Command Register thereby preventing SYNC from being encoded onto IOG, IOB. output signal generates SYNCOUT with correct pipeline delay which capable directly driving composite SYNC signal computer monitor.
TRISYNC
This mode available using ADV7162.
Overlay Color Mode
this mode, inputs provide control three color overlay. Whenever value other than "00" placed overlay inputs, corresponding overlay color displayed. When overlay inputs contain "00" color specified main pixel inputs.
CLOCK CONTROL CIRCUIT
This input used generate HDTV Sync outputs. CR17 Command Register "1", enabling TRISYNC. When TRISYNC low, analog output which Sync enabled goes tri-sync level.
PS0A-D-PS1A-D (Palette Priority Select Inputs)
ADV7160/ADV7162 integrated Clock Control Circuit (Figure 16). This circuit capable both generating ADV7160/ADV7162's internal clocking signals well external graphics subsystem clocking signals. Total system synchronization attained using parts output clocking signals drive controlling graphics processor's master clock well video frame buffers shift clock signals.
CLOCK, CLOCK Inputs
These multifunctional compatible inputs configured three separate functions. eight inputs multiplexed provide bits which used provide three different functions. function selected CR14 CR15 Command Register CR15 CR14 Color Mode Palette Select Mode Bypass Mode Control (ADV7160 Only) Overlay Color Mode Ignore Inputs
Clock Control Circuit driven pixel clock inputs, CLOCK CLOCK. These inputs driven differential oscillator running from supply.
-16-
REV.
ADV7160/ADV7162
LOADOUT(1) LOADOUT PLLREF
LOADOUT VIDEO FRAME BUFFER
VIDEO FRAME BUFFER
ADV7160/ ADV7162
LOADIN PIXEL DATA
ADV7160/ ADV7162
LOADOUT(2) LOADIN PIXEL DATA
CLOCK CLOCK PRGCKOUT LOADOUT
DIVIDE (÷N)
DIVIDE (÷M) LOADOUT LOADOUT(1) DELAY
SCKOUT TRISYNC BLANK SYNC SCKIN
LATCH
LOADIN
LOADOUT(2)
Figure LOADOOUT Pixel Clock
Pipeline Delay Onboard Calibration
LOADIN
ADV7160/ ADV7162
COLOR DATA MULTIPLEXER
FUNCTION MULTIPLEX RATE MULTIPLEX MODE MULTIPLEX MODE MULTIPLEX MODE INDEPENDENTLY PROGRAMMABLE
Figure Clock Control Circuit ADV7160/ADV7162
CLOCK CONTROL SIGNALS LOADOUT
ADV7160/ADV7162 fixed number pipeline delays (tPD), long timings -t11 met. However, fixed number pipeline delays requirement, timings -t11 ignored, calibration cycle must there restriction LOADIN LOADOUT timing. timings -t11 met, part will function correctly though with increased number pipeline delays. ADV7160/ADV7162 on-board calibration circuitry which synchronizes pixel data LOADIN with internal ADV7160/ADV7162 clocking signals. Calibration performed ways. During device's initialization sequence toggling bits Mode Register, MR10 followed MR15 writing CR10 Command Register MR15 which executes calibration every Vertical Sync.
PRGCKOUT
ADV7160/ADV7162 generates LOADOUT control signal which runs divided down frequency pixel CLOCK. frequency automatically programmed multiplex rate, controlled CR37 CR36 Command Register fLOADOUT fCLOCK/8 fLOADOUT fCLOCK/4 fLOADOUT fCLOCK/2 multiplex mode multiplex mode multiplex mode
PRGCKOUT control signal outputs user programmable clock frequency. divided down frequency pixel CLOCK (see Figure 11). rising edge PRGCKOUT synchronous rising edge LOADOUT. fPRGCKOUT fCLOCK/N where application PRGCKOUT master clock frequency graphics subsystems processor controller.
SCKIN, SCKOUT
LOADOUT signal used directly drive LOADIN pixel latch signal ADV7160/ADV7162. This most simply achieved tying LOADOUT LOADIN pins together. Alternatively, LOADOUT signal used drive frame buffer's shift clock signals, returning LOADIN input delayed with respect LOADOUT. necessary have known fixed number pipeline delays, then there limitation delay between LOADOUT LOADIN (LOADOUT(1) LOADOUT(2)). LOADIN Pixel Data must conform setup hold times t9). however, required that ADV7160/ADV7162 fixed number pipeline delays (tPD) LOADOUT LOADIN must conform timing specifications -t11 illustrated Figures
These video memory signals used minimize external support chips. Figure illustrates function that provided. input signal applied SCKIN synchronously AND-ed with video blanking signal (BLANK). resulting signal output SCKOUT. Figure Timing Waveform section shows relationship between SCKOUT, SCKIN BLANK.
SCKOUT LATCH BLANK SYNC SCKIN ENABLE
Figure SCKOUT Generation Circuit
REV.
-17-
ADV7160/ADV7162
SCKOUT signal essentially video memory shift control signal. stopped during screen retrace. Figure shows suggested frame buffer ADV7160/ADV7162 interface. This minimum chip solution allows ADV7160/ADV7162 control overall graphics system clocking synchronization.
LOADOUT LOADIN VIDEO FRAME BUFFER SCKIN BLANK SCKOUT
ADV7160/ ADV7162
Register from 7FH. should 00H. this register contains 00H, then stops. Therefore feedback divider from steps one, from 1038 steps setting VSEL bit. VSEL accessed changing PCR2 Control Register. counter divides output from oscillator determined PSEL1 PSEL0 which bits PCR5 PCR4 Control Register. This post-scaler useful generation lower frequencies been optimized high frequency operation.
VCO/2 FVCO VCO/4 VCO/8 FOUT
PIXEL DATA
PLLREF
VSEL)(4(V+2) RSEL)(R+2)
Figure ADV7160/ADV7162 Interface Using SCKIN SCKOUT
FOUT FVCO FVCO/2 FVCO/4 FVCO/8
PSEL1 PSEL0 PSEL1 PSEL0
on-board used alternative clock source. This eliminates need external high speed clock generator such crystal oscillator. With PLL, possible generate internal clock whose frequency multiple reference frequency (PLLREF). Internal operation selected setting CR56 Command Register Logic "1." registers programmed frequency required. block diagram Phase Locked Loop shown Figure blocks consist phase frequency detector, charge pump, loop filter, voltage controlled oscillator programmable divider.
PLLREF REFERENCE DIVIDER PHASE DETECTOR FVCO FEEDBACK DIVIDER DIVIDER FOUT CHARGE PUMP VOLTAGE CONTROLLED OSCILLATOR
Figure Transfer Function
transfer function summarized block diagram shown Figure optimize performance on-board PLL, following criteria should followed: PLLREF FVCO
FVCO MHz, VSEL should programmed logic "0." lower frequency output achieved using output divider. jitter performance graph function both FVCO illustrated Figure seen that jitter decreases with increasing FVCO also that jitter decreases with increasing FPD. each FOUT, user should firstly maximize FVCO using output divider then pick PLLREF reference divide maximize FPD. When generating multiple output frequencies from PLLREF value, iterative process should used find PLLREF value that gives best trade between jitter performance FOUT accuracy.
JITTER MEASURED 15µs
0.3MHz 0.42MHz
Figure Block Diagram
phase frequency detector drives voltage controlled oscillator (VCO), frequency that will cause inputs phase frequency detector matched frequency phase. corresponding output calculated PLLREF Feedback Divider Reference Divider Reference Divider combination contents Register RSEL bit. Register resolution bits. programmed setting Register located Control Register address 00CH Register from 7FH. should 00H. this register contains 00H, then stops. Therefore, Reference Divider from steps one, from steps setting RSEL bit. RSEL accessed changing PCR1 Control Register. Feedback Divider combination contents Register, VSEL value. value PCR7 PCR6 Command Register. This value allows better resolution when setting Feedback Divider value. Register resolution bits. programmed setting Register located Control Register address 00FH .The
0.57MHz
JITTER
0.8MHz 1.0MHz 1.5MHz 2.0MHz
2.7MHz 4.0MHz 5.3MHz
FREQUENCY
Figure Jitter
-18-
REV.
ADV7160/ADV7162
COLOR VIDEO MODES
ADV7160/ADV7162 supports number color video modes maximum video rate. Command bits CR27-CR24 Command Register along with MR11 Mode Register determine color mode. Seven color modes Color Palette, three them bypass palette control DACs directly.
24-Bit True Color (CR27, CR26, CR25, CR24
DACs with 30-bit data, allowing display 15-bit GammaCorrected True-Color Images. With MR11 Logic "0," Look-Up Table configured location bits deep bits each Red, Green Blue) output drives DACs with 24-bit data, allowing display 15-bit True-Color Images.
15-BIT COLOR DATA 15-BIT 24-BIT LOOK-UP TABLE 24-BIT COLOR DATA 8-BIT 8-BIT GREEN 8-BIT BLUE ANALOG VIDEO OUTPUTS
part 24-bit/30-bit "Gamma" True-Color operation with MR11 Logic direct 24-bit True-Color operation with MR11 Logic "0." pixel port accepts bits color data which directly mapped Look-Up Table RAM. With MR11 Logic "1," Look-Up Table configured location bits deep bits each Red, Green Blue), preloaded with user determined, nonlinear function, such gamma correction curve output drives DACs with 30-bit data. With MR11 Logic "0," Look-Up Table configured location bits deep bits each Red, Green Blue), preloaded with linear function output drives DACs with 24bit data.
24-BIT COLOR DATA 24-BIT 30-BIT LOOK-UP TABLE 30-BIT COLOR DATA 10-BIT 10-BIT GREEN 10-BIT BLUE ANALOG VIDEO OUTPUTS
BLUE GREEN
GREEN BLUE
Figure 15-Bit 24-Bit True-Color Configuration
8-Bit Pseudo Color (CR27, CR26, CR25, CR24
GREEN BLUE
GREEN
BLUE
This mode sets part into 8-bit Pseudo-Color operation. pixel port accepts bits pixel data, from either red, blue green channel. With MR11 Logic "1," 30-bit word indexed Look-Up Table RAM. Look-Up Table configured location bits deep bits each Red, Green Blue). output drives DACs with 30-bit data. With MR11 Logic "0," 24-Bit word indexed Look-Up Table RAM. Look-Up Table configured location bits deep bits each Red, Green Blue). output drives DACs with 24-bit data. This mode allows display simultaneous colors total palette millions addressable colors.
8-BIT PIXEL DATA 8-BIT 30-BIT LOOK-UP TABLE 30-BIT COLOR DATA 10-BIT 10-BIT GREEN 10-BIT BLUE ANALOG VIDEO OUTPUTS
Figure 24-Bit 30-Bit True-Color Configuration
16-Bit True Color (CR27, CR26, CR25, CR24
GREEN BLUE
part 16-bit True-Color operation. pixel port accepts bits color data which mapped LSBs each blue palettes Look-Up-Table RAM, LSBs green palette Look-Up-Table RAM. With MR11 Logic "1," Look-Up Table configured location bits deep bits each Red, Green Blue) output drives DACs with 30-Bit data, allowing display 16-bit GammaCorrected True-Color Images. With MR11 Logic "0," Look-Up Table configured location bits deep bits each Red, Green Blue); output drives DACs with 24-bit data, allowing display 16-bit True-Color Images.
15-Bit True Color (CR27, CR26, CR25, CR24
GREEN
BLUE
Figure 8-Bit 30-Bit Pseudo-Color Configuration
PIXEL PORT MAPPING
pixel data ADV7160/ADV7162 automatically mapped parts pixel port determined pixel data mode programmed (Bits CR27-CR24 Command Register Pixel data 24-bit True-Color modes directly mapped color inputs R7-R0, G7-G0 B7-B0. There mode operation 16-bit True Color. Data input device over green color ports (R7-R0 G7-G0) internally mapped Locations 0-63 according Figure (Note: Data unused pixel inputs ignored.)
part 15-bit True-Color operation. pixel port accepts bits color data which mapped LSBs each red, green blue palettes Look-Up Table RAM. With MR11 Logic "1," Look-Up Table configured location bits deep bits each Red, Green Blue) output drives REV.
-19-
ADV7160/ADV7162
LOCATION "31" LOCATION (RED LUT)
LOCATION "31" LOCATION (RED LUT)
LOCATION "63" LOCATION GREEN (GREEN LUT)
LOCATION "31" LOCATION GREEN (GREEN LUT)
LOCATION "31" LOCATION DATA LATCHES FIRST LOCATIONS BLUE (BLUE LUT)
DATA INTERNALLY SHIFTED LSBs LOCATION "31" LOCATION DATA LATCHES FIRST LOCATIONS BLUE (BLUE LUT)
DATA DATA PIXEL INPUT ASSIGN- LATCHED INTERNALLY SHIFTED DATA MENTS PIXEL LSBs PORT
DATA PIXEL INPUT ASSIGN- LATCHED DATA MENTS PIXEL PORT
Figure 16-Bit True-Color Mapping using R7-R0 G7-G0
LOCATION "31" LOCATION (RED LUT)
Figure 15-Bit True-Color Mapping using R6-R0 G7-G0
part modes operation 15-bit True Color. first mode, data input device over red, green blue channel (R7-R3, G7-G3 B7-B3) internally mapped Locations Look-Up Table (LUT) according Figure second mode, data input device over just color ports, green (R7-R0 G7-G0) internally mapped Locations according Figure (Note: Data unused pixel inputs ignored.) There three modes operation 8-bit Pseudo Color. Each mode maps input pixel data differently. Data input into three color channels, R7-R0 G7-G0 B7-B0. 24-bit Palette Bypass Mode, red, blue green color channels bypass Pixel Mask Color Palette. Each 8bit color channel mapped onto MSBs corresponding 10-bit input. LSBs each zeros. Bypass Mode selected ways, using CR27- CR24 Command Register pixel pixel basis using inputs (ADV7160 only). 16-bit Palette Bypass Mode, color channels bypass Pixel Mask Color Palette. 8-bits pixel data 8-bits green pixel data mapped onto MSBs blue input MSBs green input shown Figure remaining LSBs each zeros. Bypass Mode selected ways, using CR27-CR24 Command Register pixel pixel basis using inputs (ADV7160 only).
LOCATION "31" LOCATION GREEN (GREEN LUT)
DATA INTERNALLY SHIFTED LSBs LOCATION "31" LOCATION DATA LATCHES FIRST LOCATIONS BLUE (BLUE LUT)
DATA PIXEL INPUT ASSIGN- LATCHED DATA MENTS PIXEL PORT
Figure 15-Bit True Color Mapping using R7-R3, G7-G3 B7-B3
-20-
REV.
ADV7160/ADV7162
PIXEL INPUT DATA ASSIGNMENTS DATA LATCHED PIXEL PORT DATA LATCHED INPUTS BLUE GREEN
15-bit Palette Bypass Mode, color channels bypass Pixel Mask Color Palette. bits pixel data bits green pixel data mapped onto MSBs red, green blue input shown Figure remaining LSBs each zeros. Bypass Mode selected ways, using CR27-CR24 Command Register pixel pixel basis using inputs (ADV7160 only).
Multiplexing
on-board multiplexers ADV7160/ADV7162 eliminate need external data serializer circuits. Multiple video memory devices connected, parallel, directly device. Figure shows four memory banks memory connected ADV7160, running multiplex mode, giving resultant pixel clock rate MHz. Instead having provide pixel input every four pixels provided together every input multiplexer takes four pixels latched parallel, selects them time produce pixel stream pixel clock rate. mode, pixels selected sequence cycling continuously. mode, pixels selected. mode only available 8-bit Pseudo-Color Mode. BLANK, SYNC, ODD/EVEN TRISYNC multiplexed only change pixel boundary depending multiplex mode. rising edge LOADIN, pixel port inputs latched into ADV7160/ADV7162. LOADIN frequency must divided down frequency pixel clock frequency. This achieved using LOADOUT directly drive LOADIN LOADOUT provides correct frequency required, drive LOADIN after delay through some external circuitry.
VIDEO MEMORY/ FRAME BUFFER ADV7160/ADV7162
Figure 16-Bit True-Color Bypass Mode using R7-R0 G7-G0
PIXEL INPUT DATA ASSIGNMENTS DATA LATCHED PIXEL PORT DATA LATCHED INPUTS BLUE GREEN
VRAM (BANK 50MHz 50MHz 50MHz 50MHz 50MHz 50MHz MULTIPLEXER VRAM (BANK 50MHz 50MHz 50MHz 50MHz 50MHz 50MHz 200MHz 50MHz)
VRAM (BANK
VRAM (BANK
Figure Direct Interfacing Video Memory ADV7160/ADV7162
8-Bit Pseudo Color Multiplexing Mode
Fiigure 15-Bit True-Color Bypass Mode using R6-R0 G7-G0
When Multiplexing Mode selected setting CR37 Command Register Logic CR36 Command Register Logic "0," ADV7160/ADV7162 goes into 8Bit Pseudo-Color Mode irrespective Color Mode selected Bits CR27 CR24 Command Register Hence LOADOUT operates fCLOCK/8. Eight 8-bit pixels latched parallel rising edge LOADIN. These 8-bit pixels then selected, time, produce 8-bit pixel stream which passes through Pixel Mask address LUT. order eight 8-bit pixels displayed
REV.
-21-
ADV7160/ADV7162
unused Blue pixel inputs used, this mode, provide extra inputs. These inputs provide bits after multiplexing. inputs used Overlay Palette Select inputs. 24-BIT 30-BIT
G7-G0 R7-R0 G7-G0 R7-R0 G7-G0 R7-R0 G7-G0 R7-R0 PS1-PS0 B1-B0 PS1-PS0 B1-B0 PS1-PS0 B1-B0 PS1-PS0 B1-B0 8-BIT COLOR DATA LOOK-UP-TABLE 30-BIT COLOR DATA 10-BIT 10-BIT GREEN 10-BIT BLUE
ANALOG VIDEO OUTPUTS
GREEN BLUE
GREEN
BLUE
Figure 8-Bit Pseudo Color Multiplexing Mode
MICROPROCESSOR (MPU PORT)
ADV7160/ADV7162 supports standard Interface. functions part controlled this port. Direct access gained Address Register, Mode Register Control Registers well Color Palette. following sections describe setup reading writing devices registers.
Interface
Register Mapping
ADV7160/ADV7162 contains number on-board registers including Mode Register (MR17-MR10), Address Register (A10-A0) many Control Registers well Color Palette Registers. These registers control entire operation part. Figure shows internal register configuration. Control lines determine which register accessing. also determine whether Address Register pointing color registers Look-Up Table control registers. access whatever control register pointed Address Register (A10-A0). access LookUp Table (Color Palette) Overlay Palette through associated color registers. input latches data from part. control input determines between read write accesses. truth tables show modes access various registers color palette both 8-bit wide databus configuration 10-bit wide data configuration. should noted that after power-up, devices port automatically 10-bit wide operation (see Power-On Reset section).
interface (Figure consists bidirectional, 10bit wide databus interface control signals R/W. 10-bit wide databus user configurable illustrated.
Table Data-Bus Width
Data-Bus Width 10-Bit 10-Bit 8-Bit 8-Bit
RAM/DAC Resolution 10-Bit 8-Bit 10-Bit 8-Bit
Read/Write Mode 10-Bit Parallel 8-Bit Parallel Byte 8-Bit Parallel
CONTROL REGISTERS STATUS REGISTER
CURSOR REGISTERS
PIXEL MASK REGISTER
COMMAND REGISTERS (CR1-CR5)
DATA PALETTES
ADDRESS REGISTER ADDR (A10-A0)
MODE REGISTER (MRI)
TEST REGISTERS REGISTER REVISION REGISTER REGISTERS
COLOR REGISTERS GREEN REGISTER BLUE REGISTER
REGISTER
PORT
(8+2) D9-D0
Figure Port Register Configuration
-22-
REV.
ADV7160/ADV7162
MODE REGISTER (MR17-MR10) ADDRESS REGISTER (A10-A0)
ADDRESS REGISTER (A10-A0)
7FFH 400H 3FFH 305H 304H 303H 302H 205H 204H 203H 202H 201H 200H 1FFH 016H 015H 014H 013H 012H 011H 010H 00FH 00EH 00DH 00CH 00BH 00AH 009H 008H 007H 006H 005H 004H 003H 002H 000H
CONTROL REGISTERS
CURSOR IMAGE RESERVED CURSOR COLOR CURSOR COLOR RESERVED CURSOR CONTROL CURSOR Y-HI CURSOR Y-LO CURSOR X-HI CURSOR X-LO RESERVED TEST REGISTER SIGNATURE MISC SIGNATURE BLUE SIGNATURE GREEN SIGNATURE TEST COMMAND REVISION 001H STATUS COMMAND COMMAND COMMAND COMMAND COMMAND PIXEL MASK TEST REGISTERS
REGISTER (R9-R0)
GREEN REGISTER (G9-G0)
BLUE REGISTER (B9-B0)
POINTS LOCATION CORRESPONDING ADDRESS REGISTER (A10-A0)
ADDRESS REGISTER (A10-A0)
7FFH 104H 103H 101H 100H 0FFH 000H
COLOR PALETTE
RESERVED OVERLAY COLOR RESERVED LOOK-UP TABLE (256 ADDRESS ADDRESS
Figure Internal Register Configuration Address Decoding
REV.
-23-
ADV7160/ADV7162
Power-On Reset
power-up, ADV7160/ADV7162 executes power-on reset operation. This initializes pixel port such that pixel sequence ABCD starts Mode Register (MR17-MR10), Command Register (CR27-CR20), Command Register (CR37-CR30) have bits Logic Address Register, Command Register (CR17-CR10), Command Register (CR47-CR40) Command Register (CR57-CR50) have bits Logic "0." output clocking signals also during this reset period. PRGCKOUT CLOCK/32 LOADOUT CLOCK/4: power-on reset activated when goes from This reset active ADV7160/ADV7162 should accessed during this reset period. pixel clock should applied power-up.
Color Palette Accesses
blue concatenated into single 30-bit/24-bit word written location specified address register (A10-A0). address register then automatically increments point next location similar red, green blue palette write sequence performed. address register resets 000H following blue write cycle color palette location 0FFH. three color overlay palette located address space above main color palette. access Overlay Palette, Address Register must first written with address 101H. From then colors accessed same main Color Palette, with Address Register incrementing after each blue access. Data read from Color Palette firstly writing address register color palette location read. performs three successive read cycles from each red, green blue locations (10-bit 8-bit) RAM. Figures illustrate read operations 10-bit databus using DACs 8-bit 10-bit mode read operations 8-bit databus using DACs 8-bit 10-bit mode. internal pointer moves from green blue after each read completed. This pointer reset after blue read whenever address register written. address register then automatically increments point next location similar red, green blue palette read sequence performed. address register resets 000H following blue read cycle color palette location 0FFH. Similarly Overlay Palette, Address Register must first written with address 101H. From then colors read same main Color Palette, with Address Register incrementing after each blue access.
Color Palette consists locations, each location containing bits color information. Data written color palette firstly writing address register color palette location modified. performs three successive write cycles each red, green blue registers (10-bit 8-bit). Figures illustrate write operations 10-bit databus using DACs 8-bit 10-bit mode write operations 8-bit databus using DACs 8-bit 10-bit mode. internal pointer moves from green blue after each write completed. This pointer reset after blue write whenever address register written. During blue write cycle, three bytes red, green
First Write Operation Palette
Palette Write Write Address Register (Lo- Byte) Write Address Register (Hi- Byte) Write Data (R9-R2) Write Data (R1-R0) Write Green Data (G9-G2) Write Green Data (G1-G0) Write Blue Data (B9-B2) Write Blue Data (B1-B0) Write Data (R9-R2)
Databus
Second Write Operation Palette
Databus
First Read Operation Palette
Palette Read Write Address Register (Lo- Byte) Write Address Register (Hi- Byte) Read Data (R9-R2) Read Data (R1-R0) Read Green Data (G9-G2) Read Green Data (G1-G0) Read Blue Data (B9-B2) Read Blue Data (B1-B0) Read Data (R9-R2)
Databus
Second Read Operation Palette
Databus
Figure 8-Bit Data Using 10-Bit DACs
-24-
REV.
ADV7160/ADV7162
Register Accesses
write read from ADV7160/ ADV7162's registers. determine whether Mode Register Address Register being accessed. Access these
Write Operation Palette
registers direct. Control Registers accessed indirectly. Address Register must point desired Control Register. Figure Figures illustrate structure protocol device communication over port.
Palette Write Write Address Register (Lo-Byte) Write Address Register (Hi-Byte) Write Data (R9-R0) Write Green Data (G9-G0) Write Blue Data (B9-B0) Write Data (R9-R0)
Databus
Read Operation Palette Databus
Palette Read Write Address Register (Lo-Byte) Write Address Register (Hi-Byte) Read Data (R9-R0) Read Green Data (G9-G0) Read Blue Data (B9-B0) Read Data (R9-R0)
Figure 8-Bit Databus Using 8-Bit DACs
Write Operation Palette Write Address Register (Lo-Byte) Write Address Register (Hi-Byte) Write Data (R9-R0) Write Green Data (G9-G0) Write Blue Data (B9-B0) Write Data (R9-R0) Palette Write
Databus
Read Operation Palette Databus
Palette Read Write Address Register (Lo-Byte) Write Address Register (Hi-Byte) Read Data (R9-R0) Read Green Data (G9-G0) Read Blue Data (B9-B0) Read Data (R9-R0)
Figure 10-Bit Databus Using 10-Bit DACs
Write Operation Palette Palette Write Write Address Register (Lo-Byte) Write Address Register (Hi-Byte) Write Data (R9-R0) Write Green Data (G9-G0) Write Blue Data (B9-B0) Write Data (R9-R0)
Databus Palette
Read Operation
Palette Read Write Address Registe (Lo-Byte) Write Address Register (Hi-Byte) Read Data (R9-R0) Read Green Data (G9-G0) Read Blue Data (B9-B0) Read Data (R9-R0)
Databus
Figure 10-Bit Databus Using 8-Bit DACS
REV.
-25-
ADV7160/ADV7162
REGISTER PROGRAMMING RAM-DAC Resolution Control (MR11)
following section describes each register, including Address Register, Mode Register each Control Registers terms configuration.
Address Register (A10-A0)
illustrated previous tables, control inputs, conjunction with this address register specify which control register, color palette location accessed port. Address Register bits wide read from well written access Address Register, consecutive accesses with Logic required. first accesses byte; when second access same type performed, i.e., consecutive reads consecutive writes, high byte accessed. type access changed, access different register inserted between first second, then second access will access byte again. When writing reading from color palette sequential basis, only start address needs written. After red, green blue write sequence, address register automatically incremented.
Mode Register (MR1)
When this programmed with "1," bits deep bits each red, green blue), each three DACs configured 10-bit resolution. When MR11 programmed with "0," bits deep bits each red, green blue), DACs configured 8-bit resolution. LSBs 10-bit DACs pulled down zero 8-bit RAM-DAC mode.
Data Width (MR12)
This determines width port. configured either 10-bit wide (D9-D0) 8-bit wide (D7-D0) bus. Ten-bit data written device when configured 8-bit wide mode. MSBs first written D7-D0, then LSBs written over D1-D0. Bits D9-D8 zeros 8bit mode.
Operational Mode Control (MR14-MR13)
When MR14 MR13 part operates normal mode.
Calibrate LOADIN (MR15)
mode register 10-bit wide register. However programming purposes, considered 8-bit wide register (MR19 MR18 both reserved). denoted MR17-MR10 simplification purposes. Figure shows various operations under control mode register. This register read from well written read mode, MR19 MR18 read back, they both returned zeros.
MODE REGISTER DESCRIPTION Reset Control (MR10)
This automatically calibrates on-board LOADIN/ LOADOUT synchronization circuit. transition initiates calibration. This normal operation. "Pipeline Delay Calibration" section. This must this cycle during initialization sequence.
Palette Select Match Bits Control (MR17-MR16)
These bits allow multiple palette devices work together. When bits match MR17 MR16 respectively, device selected. these bits match, device selected analog video outputs drive "Palette Priority Select Inputs" section.
CONTROL REGISTERS
This used reset pixel port sampling sequence. This ensures that pixel sequence ABCD starts reset writing followed followed "1." This must this cycle during initialization sequence.
large bank registers plus cursor image accessed through Control Register. Access made first writing Address Register with appropriate address point particular Control Register (see Figure 34),
MR19
MR18
MR17
MR16
MR15
PCR4 MR14
MR13
MR12
MR11
MR10
RESERVED* CALIBRATE LOADIN PALETTE SELECT MATCH BITS CONTROL MR16 MR17 MR15
DATA WIDTH MR12 8-BIT (D7-D0) 10-BIT (D9-D0)
RAM-DAC RESOLUTION CONTROL MR11 OPERATIONAL MODE CONTROL MR14 MR13 NORMAL OPERATION RESERVED RESERVED RESERVED RESET CONTROL MR10 8-BIT 10-BIT
*THESE BITS READ-ONLY
RESERVED BITS. READ CYCLE WILL RETURN ZEROS "00."
Figure Mode Register (MR1) (MR19-MR10)
-26-
REV.
ADV7160/ADV7162
then performing access Control Register. When accessing Control Registers range 200H 204H, when accessing cursor image, Address Register autoincrements after each register access. accessing last cursor image location address 7FFH, address register reverts address 000H. Address Register also auto-increments after blue access, when accessing color registers address range 303H 304H.
Register (Address (A10-A0) 003H) Hi-Byte Control (CR13)
This enables access Byte Address Register. When CR13 Logic "0", part compatible ADV7150. access hi-byte address register, this Logic "1."
Function Control (CR15-CR14)
This 8-bit wide "Identification" read-only register. ADV7160 will always return hexadecimal value 76H. ADV7162 will always return hexadecimal value 79H.
Pixel Mask Register (Address (A10-A0) 004H)
contents pixel mask register individually bit-wise logically ANDed with Red, Green Blue pixel input stream data. 8-bit read/write register with corresponding normal operation, this register with FFH.
COMMAND REGISTER (CR1) (Address (A10-A0) 005H)
This register contains number control bits shown diagram. 10-bit wide register. However programming purposes, considered 8-bit wide register (CR19 CR18 reserved). Figure shows various operations under control CR1. This register read from well written write mode zero should written CR12. read mode, CR19 CR18 returned zeros.
COMMAND REGISTER 1-BIT DESCRIPTION Calibration Control (CR10)
These bits control functions inputs. They used enable Overlay Mode, Bypass Mode Palette Select Mode. Palette Select Mode (CR15 CR14 "0"), these inputs used multiplex outputs number devices. pixel pixel basis, compared against match bits, MR17 MR16. they match, then part behaves normally. they don't match, then analog output currents switched zero that clock cycle, thus allowing another device, whose match bits match during this time, drive monitor. Bypass Mode (CR15 "0," CR14 "1"), used switch between color modes through Color Palette Palette Bypass Modes, pixel pixel basis. color mode through palette selected using CR17 CR16. illegal program CR27 CR24 select bypass modes when using bits select bypass mode pixel rate. This switching pixel pixel basis only allowed when using ADV7160 device. Therefore, ADV7162, this mode (CR15 "0," CR14 "1"), reserved should used. Overlay Mode (CR15 "1," CR14 "0"), inputs provide control three color overlay. Whenever value other than "00" placed overlay inputs, corresponding overlay color displayed. When overlay inputs contain "00," color specified pixel inputs. When CR15 CR14 "1," inputs completely ignored. There overlay, bypass switching outputs enabled.
Bypass Color Mode Control (CR17-CR16)
This automatically calibrates on-board LOADIN/ LOADOUT synchronization circuit every vertical Sync. MR15 Mode Register must "0."
These bits control mode during bypass switching. There three different modes: 24-bit Bypass, 16-bit Bypass 15-bit Bypass Mode.
CR14 CR13 CR12 CR11 CR10
CR19
CR18
CR17
CR16
CR15
RESERVED* *THESE BITS READ-ONLY
RESERVED BITS. READ CYCLE WILL RETURN ZEROS "00."
FUNCTION CONTROL CR15 CR14 PALETTE SELECTS BYPASS MODE** OVERLAYS IGNORE INPUTS
CR12 THIS SHOULD ZERO
**THIS MODE ONLY AVAILABLE ADV7160. RESERVED ADV7162. BYPASS COLOR MODE CR17 CR16 15-BIT BYPASS 16-BIT BYPASS 24-BIT BYPASS RESERVED CR13 ACCESS HI-BYTE (ADV7150 COMPATIBLE) ACCESS HI-BYTE
TEST MODE CONTROL CR11 DISABLE ENABLE TEST MODE CALIBRATION CONTROL CR10 DISABLE CALIBRATES EVERY VERTICAL SYNC (MR15=0)
ADDRESS REGISTER HI-BYTE CONTROL
Figure Command Register (CR1) (CR19-CR10)
REV.
-27-
ADV7160/ADV7162
CR29 CR28 CR27 CR26 CR25 CR24 CR23 CR22 CR21 CR20
RESERVED* TRUE COLOR/PSEUDO COLOR MODE CONTROL CR27 CR26 CR25 CR24 COLOR MODE 8-BIT PSEUDO COLOR R7-R0 8-BIT PSEUDO COLOR G7-G0 8-BIT PSEUDO COLOR B7-0 16-BIT BYPASS MODE USING R7-R0, G7-G0 15-BIT BYPASS MODE USING R6-R0, G7-G0 16-BIT TRUE COLOR R7-R0, G7-G0 15-BIT TRUE COLOR R7-R3, G7-G3, B7-B3 15-BIT TRUE COLOR R6-R0, G7-G0 24-BIT TRUE COLOR 24-BIT BYPASS MODE
SYNC RECOGNITION CONTROL (GREEN) CR22 IGNORE DECODE
CR21-CR20 (00) PEDESTAL ENABLE CONTROL CR23 ZERO SHOULD WRITTEN THESE BITS
*THESE BITS READ-ONLY RESERVED BITS.
READ CYCLE WILL RETURN ZEROS "00."
Figure Command Register (CR2) (CR29-CR20)
COMMAND REGISTER (CR2) (Address (A10-A0) 006H)
COMMAND REGISTER (CR3) (Address (A10-A0) 007H)
This register contains number control bits shown diagram. 10-bit wide register. However programming purposes, considered 8-bit wide register (CR29 CR28 both reserved). Figure shows various operations under control CR2. This register read from well written write mode zero should written CR21 CR20. read mode, CR29 CR28 returned zeros.
COMMAND REGISTER 2-BIT DESCRIPTION SYNC Recognition Control Green (CR22)
This register contains number control bits shown diagram. 10-bit wide register. However programming purposes, considered 8-bit wide register (CR39 CR38 both reserved). Figure shows various operations under control CR3. This register read from well written write mode zero should written CR35. read mode, CR39 CR38 returned zeros.
COMMAND REGISTER DESCRIPTION PRGCKOUT Frequency Control (CR31-CR30)
This specifies whether video SYNC Input encoded onto analog output ignored.
Pedestal Enable Control (CR23)
These bits specify output frequency PRGCKOUT output. PRGCKOUT divided down version pixel CLOCK.
BLANK Pipeline Delay Control (CR34-CR32)
This specifies whether blanking pedestal generated video outputs.
True-Color/Bypass/Pseudo-Color Mode Control (CR27-CR24)
These bits specify various color modes. These include 24-bit true-color bypass mode, 16-bit true-color bypass mode, 15-bit true-color modes, 15-bit bypass mode three 8-bit pseudo color modes.
These bits specify additional pipeline delay that added BLANK function, relative overall device pipeline delay (tPD). BLANK control normally enters Video from shorter pipeline than video pixel data, this control useful de-skewing pipeline differential.
Pixel Multiplex Control (CR37-CR36)
These bits specify device's multiplex mode. therefore also determines frequency LOADOUT signal. LOADOUT divided down version pixel CLOCK.
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ADV7160/ADV7162
CR39 CR38 CR37 CR36 CR35 CR34 CR33 CR32 CR37 CR36
RESERVED* *THESE BITS READ-ONLY
RESERVED BITS. READ CYCLE WILL RETURN ZEROS "00."
EXTRA BLANK PIPELINE DELAY CONTROL (ADDS PIXEL PIPELINE DELAY; tPD) CR35 ZERO SHOULD WRITTEN THIS CR34 CR33 CR32 BLANK PIPELINE DELAY LOADOUT LOADOUT
LOADOUT
Pixel Multiplex Control CR37 CR36 MUXING: LOADOUT CLOCK MUXING: LOADOUT CLOCK MUXING: LOADOUT CLOCK (PSEUDO COLOR ONLY) MUXING: LOADOUT CLOCK
PRGCKOUT FREQUENCY CONTROL CR31 CR30 CLOCK CLOCK CLOCK CLOCK
Figure Command Register (CR3) (CR39-CR30)
COMMAND REGISTER (CR4) (ADDRESS (A10-A0) 008H) SYNC Recognition Control (CR41)
This register contains number control bits shown diagram. 10-bit wide register. However programming purposes, considered 8-bit wide register (CR49 CR48 both reserved). Figure shows various operations under control CR4. This register read from well written read mode, CR49 CR48 both returned zeros.
COMMAND REGISTER 4-BIT DESCRIPTION HDTV SYNC Enable (CR40)
This specifies whether video SYNC Input encoded onto analog output ignored.
SYNC Recognition Control Blue (CR42)
This specifies whether video SYNC Input encoded onto analog output ignored.
Gain Control (CR44-CR43)
These bits specifies amount gain depending standard required. "DAC Video Outputs" section more detail. gain settings that have pedestal, pedestal automatically disabled independently CR23.
Signature Clock Control (CR45)
This specifies whether video TRISYNC Input encoded, enabling outputs generate Tri-Level Sync.
CR49 CR48 CR47 CR46 CR45
This enables disables clock signature analyzer.
CR44
CR43
CR42
CR41
CR40
Reserved* RESERVED* GAIN *THESE BITS READ-ONLY
RESERVED BITS. READ CYCLE WILL RETURN ZEROS "00."
SIGNATURE RESET CR46 ENABLE DISABLE
CR44 CR43 3996 4224 4311 5592
SYNC RECOGNITION CONTROL (RED) CR41 IGNORE DECODE
SIGNATURE ACQUIRE CR47 DISABLE ENABLE SIGNATURE CLOCK CONTROL CR45 DISABLE CLOCK ENABLE CLOCK
SYNC RECOGNITION CONTROL (BLUE) CR42 IGNORE DECODE HDTV SYNC CONTROL CR40 DISABLE TRI-SYNC ENABLE TRI-SYNC
Figure Command Register (CR4) (CRF49-CR40)
REV.
-29-
ADV7160/ADV7162
Signature Reset Control (CR46) Output Divide Control (PCR5-PCR4)
Taking CR46 then high resets signature analyzer. This done give known starting point before acquiring signature.
Signature Acquire Control (CR47)
These bits control output divider. This post-scaler used generation lower frequencies.
Control (PCR7-PCR6)
This should Logic normal operation. "Test Diagnostic" section more information.
COMMAND REGISTER (CR5) (Address (A10-A0) 00DH)
These bits value transfer function. This extra value provides extra control setting feedback divider value PLL.
Status Register (Address (A10-A0) 00AH)
This register contains control CR56. 10-bit wide register. However programming purposes, considered 8-bit wide register (CR59 CR58 both reserved). This register read from well written Control CR56 selects either external clock internal operation. internal used, Logic should written CR56.This should immediately after power write mode, zero should written CR57 CR55-CR50. read mode, CR59 CR58 both returned zeros.
COMMAND REGISTER (PCR) (Address (A10-A0) 009H)
This register contains number control bits shown diagram. 10-bit wide register. However, programming purposes, considered 8-bit wide register (PCR9 PCR8 both reserved). Figure shows various operations under control PCR. This register read from well written write mode zero should written PCR3. read mode PCR9 PCR8 returned zeros.
Control (PCR0)
This register read only 10-bit register. However SR9- reserved bits, containing zeros SR7-SR1 undefined bits should masked software read back. Therefore, only relevant Status Register contains Logic one, more IOR, IOG, outputs exceed internal voltage SENSE comparator circuit used determine presence monitor. With some diagnostic code, presence loading individual lines determined. reference generated voltage divider from external voltage reference VREF pin. proper operation, following levels should applied comparator IOR, outputs: Voltage High Voltage
Revision Register (Address (A10-A0) 01BH)
This register read only register containing revision silicon.
Register (Address (A10-A0) 00CH)
This enables disables PLL.
RSEL Control (PCR1)
This enables disables RSEL, which together with contents Register affect reference divider value PLL. Reference Divider RSEL) (R+2).
VSEL Control (PCR2)
This enables disables VSEL, which together with contents Register value affect feedback divider value PLL. Feedback Divider VSEL) (4(V 2)+S).
PCR9 PCR8 PCR7 PCR6 PCR5
This register read only 10-bit register. However, R9-R8 reserved bits, containing zeros. read only bit. This should masked software readback value indeterminate. Therefore, Register treated 7-bit wide register. This register, together with RSEL Control Register, controls reference divider on-board PLL.
PCR4
PCR3
PCR2
PCR1
PCR0
VALUE RESERVED* *THESE BITS READ-ONLY
RESERVED BITS. READ CYCLE WILL RETURN ZEROS "00."
PCR7 PCR6 FOUT PCR5 PCR4 (PSEL1 PSEL0) VCO/1 VCO/2 VCO/4 VCO/8
PCR5 ZERO SHOULD WRITTEN THIS
RSEL ENABLE PCR1 DISABLE ENABLE
VSEL ENABLE PCR2 DISABLE ENABLE
CONTROL PCR0 DISABLE ENABLE
Figure Command Register (PCR) (PCR9-PCR0)
-30-
REV.
ADV7160/ADV7162
Register (Address (A10-A0) 00FH)
This register read only 10-bit register. However V9-V8 reserved bits, containing zeros. read only bit. This should masked software readback value indeterminate. Therefore, Register treated 7-bit wide register. This register, together with VSEL Control Register, controls feedback divider on-board PLL. ADV7160/ADV7162 cursor generator board. Several control registers control cursor. These will described detail. Cursor-X Cursor-Y registers specify position cursor placed screen. origin cursor left. position cursor taken relative this point, allowing CursorX Cursor-Y registers programmed with negative numbers thus allow cursor partially completely screen. cursor work X-11 cursor, controlled Bits CCR0 CCR1 Cursor Control Register. screen coordinates measured from rising edge BLANK. first pixel after rising edge BLANK corresponds origin Vertical retrace time extracted from composite SYNC BLANK inputs. start Vertical Retrace recognized counting second rising edge SYNC while BLANK remains low. next rising edge BLANK start line
Cursor X-Lo Cursor X-Hi Register (Address (A10-A0) 200H 201H) Cursor
bits stored each address. With bits cursor pixel, four horizontally adjacent pixels stored each address. each address location Cursor Image filled, progression from left right until line filled bottom until lines filled. cursor displayed both interlaced noninterlaced system, controlled CCR3 Cursor Control Register. interlaced system, only cursor displayed field. ODD/EVEN input indicates which field frame being displayed.
Cursor Coordinate Even
Even field starts with line cursor image line frame. Subsequent even lines cursor image displayed subsequent lines Even field. Even field, frame line counter starts increments every Even field line. field starts with line cursor image line frame. Subsequent lines cursor image displayed subsequent lines field. field, frame line counter starts increments every field line.
Cursor Coordinate
Even field starts with line cursor image line frame. Subsequent even lines cursor image displayed subsequent lines Even field. Even field, frame line counter starts increments every Even field line. field starts with line cursor image line frame. Subsequent lines cursor image displayed subsequent lines field. field, frame line counter starts increments every field line.
Cursor Control Register (Address (A10-A0) 204H)
These 8-bit registers together form 16-bit complement representation cursor x-coordinate screen. valid range cursor x-coordinate FFFH. negative number representation allows part cursor displayed left-hand edge screen
Cursor Y-Lo Cursor Y-Hi Register (Address (A10-A0) 202H 203H)
This register contains number control bits. 10-bit wide register. However programming purposes, considered 8-bit wide register (CCR8 CCR9 both reserved). write mode zero should written CCR4 CCR7. read mode, CCR8 CCR9 returned zeros. Figure shows various operations under control CCR.
CURSOR CONTROL REGISTER DESCRIPTION CURSOR MODE CONTROL (CCR1-CCR0)
These 8-bit registers together form 16-bit complement representation cursor x-coordinate screen. valid range cursor x-coordinate FFFH. negative number representation allows part cursor displayed top/left screen. When accessing cursor registers, Address Register auto-increments after each access. There restrictions updating cursor coordinate registers other than they must written order X-Low, X-Hi, Y-Low, Y-Hi update coordinates. Only cursor displayed frame, last coordinates written. Access these registers independent databus being configured 10-bit operation.
Cursor Color Cursor Color Register (Address (A10-A0) 304H 303H)
These bits specify which type cursor being used. Each cursor pixel value controls color differently each mode.
Table
X-11 Cursor Transparent Transparent Color Color
Cursor Color Color Transparent Bit-Wise Complement
Each these color registers bits wide, made bits Red, bits Green bits Blue. Access these registers behaves same access Color Palette with respect different combinations 10/8-bit databus 10/8-bit resolution.
Cursor Image (Address (A10-A0) 400H-7FFH)
Cursor Enable Control (CCR2)
This turns cursor off.
Interlace Control (CCR3)
This determines whether cursor being used interlaced noninterlaced mode.
This region contains 2-bit Cursor Image. Eight REV. -31-
ADV7160/ADV7162
CCR9 CCR8 CCR7 CCR6 CCR5 CCR4 CCR3 CCR2 CCR1 CCR0
RESERVED* *THESE BITS READ-ONLY
RESERVED BITS. READ CYCLE WILL RETURN ZEROS "00."
CURSOR ENABLE CCR2 CCR7-CCR4 (0000) ZERO SHOULD WRITTEN THESE BITS CURSOR CONTROL CCR3 NONINTERLACED INTERLACED DISABLE ENABLE
CURSOR MODE Control CCR1 CCR0 RESERVED CURSOR CURSOR RESERVED
Figure Cursor Control Register (CCR) (CCR9-CCR0)
DIGITAL-TO-ANALOG CONVERTER (DACS) VIDEO OUTPUTS
ADV7160/ADV7162 contains three high speed video DACs. outputs represented three primary analog color signals (red video), (green video) (blue video).
DACs Analog Outputs
IOR, IOG, DACs (SOURCE TERMINATION)
(CABLE)
(MONITOR)
part contains three matched 10-bit digital-to-analog converters. DACs designed using advanced, high speed, segmented architecture. currents corresponding each digital input routed either IOR, IOG, (bit "1") GND. analog video outputs high impedance current sources. Each these three current outputs specified directly drive 37.5 load (doubly terminated
Reference Input
Figure Output Termination (Doubly Terminated Load)
OUTPUT WITHOUT OUTPUT WITH SYNC ENCODED SYNC ENCODED 19.05 0.714 26.67 1.000 WHITE LEVEL
external 1.23 voltage reference required analog outputs ADV7160/ADV7162. reference voltage connected VREF input. resistor RSET connected between RSET input part ground. specified performance, RSET value This corresponds generation RS-343A video levels (with SYNC Pedestal IRE) into doubly terminated load. this example Gain value 3996 using CR43 CR44 Command Register Figure illustrates resulting video waveform Video Output Truth Table illustrates corresponding control input stimuli. ADV7160/ADV7162 SYNC encoded analog signals, however practice, SYNC generally encoded either output video outputs.
92.5
1.44
0.054
9.05
0.340
BLACK LEVEL BLANK LEVEL
7.62
0.286
SYNC LEVEL
Figure Composite Video Waveform SYNC Decoded; Pedestal IRE; Gain 3996
-32-
REV.
ADV7160/ADV7162
Table III. Video Output Truth Table
Description WHITE LEVEL VIDEO VIDEO BLANK BLACK LEVEL BLACK BLANK BLANK LEVEL SYNC LEVEL
with Sync Enabled (mA) 26.67 Video 9.05 Video 1.44 9.05 1.44 7.62
with Sync Disabled (mA) 19.05 Video 1.44 Video 1.44 1.44 1.44
SYNC
BLANK
Input Data 3FFH Data Data 000H 000H xxxH xxxH
Variations RS-343A
Various other video output configurations implemented ADV7160/ADV7162, including RS-170. table shows calculated values Gain some most common variants RS-343A standard. associated waveforms shown diagrams. Gain 4224 4311 5592 Video Signal
OUTPUT WITHOUT SYNC ENCODED 19.05 0.714 WHITE LEVEL
RS343A, SYNC decoded output; Pedestal RS343A, SYNC decoded; Pedestal RS170, SYNC decoded; Pedestal
BLANK/BLACK LEVEL
OUTPUT WITHOUT OUTPUT WITH SYNC ENCODED SYNC ENCODED 18.62 0.698 26.67 1.000 WHITE LEVEL
Figure Composite Video Waveform Pedestal IRE; Gain 4311
Output Currents
8.05
0.302
BLANK/ BLACK LEVEL
various output currents VREF, RSET gain. programming Command Register Bits choosing correct Gain value, video waveforms conforming common variations RS-170 RS-343A, well HDTV standards generated. currents generated summarized
IOUT IDAC IBLANK ISYNC ITRISYNC
SYNC LEVEL
IDAC (mA)
GAIN RSET
Figure Composite Video Waveform SYNC Decoded; Pedestal IRE; Gain 4224
OUTPUT WITH OUTPUT WITHOUT SYNC ENCODED SYNC ENCODED 26.67 1.00 WHITE LEVEL
BLANK (mA) 0.0817 IDAC SYNC (mA) 0.4322 IDAC TRISYNC (mA) 0.4322 IDAC
37.33 1.400
92.5
21.24 0.800 2.00 0.075 12.67 0.475 10.67 0.400
TRISYNC LEVEL BLACK LEVEL BLANK LEVEL
SYNC LEVEL
Figure Composite Video Waveform SYNC TRISYNC decoded; Pedestal IRE; Gain 5592
REV.
-33-
ADV7160/ADV7162
APPENDIX BOARD DESIGN LAYOUT CONSIDERATIONS
ADV7160/ADV7162 highly integrated circuit containing both precision analog high speed digital circuitry. been designed minimize interference effects integrity analog circuitry high speed digital circuitry. imperative that these same design layout techniques applied system level design such that high speed, accurate performance achieved. "Recommended Analog Circuit Layout" shows analog interface between device monitor. layout should optimized lowest noise ADV7160/ADV7162 power ground lines shielding digital inputs providing good decoupling. lead length between groups pins should minimized minimize inductive ringing.
Ground Planes
operation, reduce lead inductance. Best performance obtained with ceramic capacitor decoupling. Each group pins ADV7160/ADV7162 must have least decoupling capacitor GND. These capacitors should placed close possible device. important note that while ADV7160/ADV7162 contains circuitry reject power supply noise, this rejection decreases with frequency. high frequency switching power supply used, designer should close attention reducing power supply noise consider using three terminal voltage regulator supplying power analog power plane.
Digital Signal Interconnect
ground plane should encompass ADV7160/ADV7162 ground pins, voltage reference circuitry, power supply bypass circuitry ADV7160/ADV7162, analog output traces, digital signal traces leading ADV7160/ ADV7162. ground plane graphics board's common ground plane.
Power Planes
digital inputs ADV7160/ADV7162 should isolated much possible from analog outputs other analog circuitry. Also, these input signals should overlay analog power plane. high clock rates involved, long clock lines ADV7160/ADV7162 should avoided reduce noise pickup. active termination resistors digital inputs should connected regular power plane (VCC), analog power plane.
Analog Signal Interconnect
ADV7160/ADV7162 associated analog circuitry should have it's power plane, referred analog power plane (VAA). This power plane should connected regular power plane (VCC) single point through ferrite bead. This bead should located within three inches ADV7160/ADV7162. power plane should provide power digital logic board, analog power plane should provide power ADV7160/ADV7162 power pins voltage reference circuitry. Plane-to-plane noise coupling reduced ensuring that portions regular power ground planes overlay portions analog power plane, unless they arranged such that plane-to-plane noise common mode.
Supply Decoupling
ADV7160/ADV7162 should located close possible output connectors minimize noise pickup reflections impedance mismatch. video output signals should overlay ground plane, analog power plane, maximize high frequency power supply rejection. Digital Inputs, especially Pixel Data Inputs clocking signals (CLOCK, LOADOUT, LOADIN, etc.) should never overlay analog signal circuitry should kept away possible. best performance, analog outputs (IOR, IOG, IOB) should each have load resistor connected GND. These resistors should placed close possible ADV7160/ADV7162 minimize reflections.
optimum performance, bypass capacitors should installed using shortest leads possible, consistent with reliable
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REV.
ADV7160/ADV7162
POWER SUPPLY DECOUPLING (0.1µF CAPACITOR EACH GROUP) 0.1µF 0.01µF 0.1µF 0.01µF 0.1µF 0.01µF 0.1µF 0.01µF
(VAA) ANALOG POWER PLANE (VAA) 0.1µF COMP VREF RSET (VAA) METAL) RSET 0.1µF AD589 (1.2V REF) COAXIAL CABLE (75) 33µF
(FERRITE BEAD)
(VCC) 0.1µF
MONITOR (CRT)
ADV7160
CONNECTORS
NOTES: RESISTERS METAL FILM 0.1µF 0.01µF CAPACITORS CERAMIC ADDITIONAL DIGITAL CIRCUITRY OMITTED CLARITY
Recommended Analog Circuit Layout
REV.
-35-
ADV7160/ADV7162
APPENDIX TYPICAL FRAME BUFFER INTERFACE
PLLREF
CLOCK CLOCK
PRGCKOUT
DIVIDE (÷N)
DIVIDE (÷M)
LOADOUT
CLOCK
SCKOUT
LATCH
GRAPHICS PROCESSOR/ CONTROLLER
BLANK BLANK SYNC TRISYNC ENABLE
SYNC TRISYNC SCKIN
FRAME BUFFER/ VIDEO MEMORY
LOADIN
ADV7160/ ADV7162
VRAM (BANK VRAM (BANK VRAM (BANK
MULTIPLEXER PALETTE/RAM
VRAM (BANK
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REV.
ADV7160/ADV7162
APPENDIX 10-BIT DACs GAMMA CORRECTION 10-Bit DACs
10-Bit RAM-DAC resolution allows nonlinear video correction, particular Gamma Correction. ADV7160/ADV7162 allows increase color resolution from 24-bit 30-bit effective color without necessity 30-bit deep frame buffer. true-color mode, example, part effectively operates 24-bit 30-bit color look-up table. have assumed that there exists linear relationship between actual values input monitor intensity produced screen. This, however, case. Half scale digital input (1000 0000) might correspond only output intensity (Cathode Tube). intensity (ICRT) produced input value given ICRT (IIN)c where ranges from 2.8. individual values red, green blue known, then called "Gamma Correction" applied each three video input signals (IIN); therefore: IIN(corrected) k(IIN)1/c Traditionally, there been trade-off between implementing nonlinear graphics function, such gamma correction, color dynamic range. ADV7160/ADV7162 overcomes this increasing individual color resolution each red, green blue primary colors from bits color channel bits channel bits bits). table highlights loss resolution when 8-bit data gamma-corrected value quantized traditional 8-bit system. Note that there change 8-bit quantized data linear changes input data over much transfer function. other hand, when quantized bits 10-bit RAMs 10-bit DACs ADV7160/ ADV7162, changes input 8-bit data reflected corresponding changes 10-bit data. graph shows typical gamma curve corresponding gamma value 2.7. This programmed red, green blue RAMs color look-up table instead more traditional linear function. Different curves corresponding particular gamma value independently programmed each red, green blue RAMs. Other applications 10-bit RAM-DAC include closed-loop monitor color calibration.
GAMMA CORRECTION Bits Bits
8-Bit Data
1.00 0.90
OUTPUT NORMALISED
Gamma Corrected (2.7) 0.977797 0.979304 0.980807 0.982306 0.983801 0.985292 0.986780 0.988264 0.989744 0.991220 0.992693 0.994161 0.995626 0.997088 0.998546 1.000000
Quantized Bits
Quantized Bits 1001 1002 1004 1005 1007 1008 1010 1011 1013 1015 1016 1018 1019 1021 1022 1023
0.80 0.70 0.60 0.50 0.40 0.30 0.20 0.10 0.00
INPUT CODE DECIMAL
Gamma Correction Curve (Gamma Value 2.7)
REV.
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ADV7160/ADV7162
APPENDIX INITIALIZATION PROGRAMMING
ADV7160/ADV7162 INITIALIZATION
After power been supplied, ADV7160/ADV7162 must initialized. Mode Register Control Registers must then values written various registers will determined desired operating mode part, i.e., True-Color/ Pseudo-Color, Muxing/2:1 Muxing, on/off, Bypass Mode on/off etc. following section gives recommended initialization ADV7160/ADV7162 example ADV7162 operating specific mode.
ADV7160/ADV7162 Initialization Comment
Write (xx000xx1)* Mode Register (MR1) Write (xx000xx0)* Mode Register (MR1) Write (xx000xx1)* Mode Register (MR1) Write Address Register (A7-A0) Write (xxxx100x)* Command Register (CR1) Write Address Register (A7-A0) Write Address Register (A10-A8) Write (xxxxxx00)* Command (CR2) Write Address Register (A7-A0) Write Address Register (A10-A8) Write (xx0xxxxx)* Command (CR3) Write Address Register (A7-A0) Write Address Register (A10-A8) Write (xxxxxxxx)* Command (CR4) Write Address Register (A7-A0) Write Address Register (A10-A8) Write (0x000000)* Command (CR5) Write Address Register (A7-A0) Write Address Register (A10-A8) Write (xxxxxxxx)* Pixel Mask Register Write Address Register (A7-A0) Write Address Register (A10-A8) Write (xxxxxxxx)* Cursor Control Register Write Address Register (A7-A0) Write Address Register (A10-A8) Write (xxxxxxxx)* Register Write Address Register (A7-A0) Write Address Register (A10-A8) Write (xxxx0xxx)* Register Write Address Register (A7-A0) Write Address Register (A10-A8) Write (xxxxxxxx)* PLLCommand Register Write (xx0xxxxx)* Mode Register (MR1) Write (xx1xxxxx)* Mode Register (MR1) Write (xx0xxxxx)* Mode Register (MR1)
Resets ADV7160/62
Address points Command Register (CR1) Address points high byte access Address points Command Register (CR2) Setup required Address points Command Register (CR3) Setup required Address points Command Register (CR4) Setup required Address points Command Register (CR5) Setup required Address points Pixel Mask Register Pixel Mask required Necessary only used Address points Cursor Control Register (CCR) required Necessary only used Address points Register required Necessary only used Address points Register required Necessary only used Address points Command Register (PCR) required Necessary only manual claibration required Toggles MR15
represents either value that should depending desired operating mode ADV7160/ADV7162.
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REV.
ADV7160/ADV7162
Example
Color Mode: 24-Bit Gamma Corrected True Color (30-Bits) through Color Palette Multiplexing: 2:1, Databus: 10-Bit, RAM-DAC Resolution: 10-Bit, SYNC: Green, Pedestal: IRE, Calibration: Every Vertical Sync, Internal PLL: (Reference MHz)
Register Initialization Comment
Write Mode Register (MR1) Write Mode Register (MR1) Write Mode Register (MR1) Write Address Register (A7-A0) Write Command Register (CR1) Write Address Register (A7-A0) Write Address Register (A10-A8) Write Command (CR2) Write Address Register (A7-A0) Write Address Register (A10-A8) Write Command (CR3) Write Address Register (A7-A0) Write Address Register (A10-A8) Write Command (CR4) Write Address Register (A7-A0) Write Address Register (A10-A8) Write Command (CR5) Write Address Register (A7-A0) Write Address Register (A10-A8) Write Pixel Mask Register Write Address Register (A7-A0) Write Address Register (A10-A8) Write Register Write Address Register (A7-A0) Write Address Register (A10-A8) Write Register Write Address Register (A7-A0) Write Address Register (A10-A8) Write Command Register
Color Palette Initialization
Resets ADV7162* 10-Bit Data Bus, 10-Bit Resolution Address points Command Register (CR1) High byte access, Calibrate every Vertical Sync Address points Command Register (CR2) 24-Bit True Color, IRE, Sync Green Address points Command Register (CR3) Muxing, PRGCKOUT CLOCK Address points Command Register (CR4) GAIN 3996 Address points Command Register (CR5) Internal used Address points Pixel Mask Register Pixel Mask Address points Register value Address points Register value Address points Command Register (PCR) required
Comment
Write Write Write Write Write Write Write Write
Address Register (A7-A0) Address Register (A10-A8) (red data) location (00H) (green data) location (00H) (blue data) location (00H) (red data) location (01H) (green data) location (01H) (blue data) location (01H)
Points Color Palette (Initializes Palette Linear Ramp** Initialization Complete
Write (red data) location (FFH) Write (green data) location (FFH) Write (blue data) location (FFH)
**These command lines reset ADV7162. pipelines each Red, Green Blue pixel inputs synchronously reset Multiplexer's input. Mode Register MR10 written followed followed "1." **This sequence instructions would, course, normally coded using some form loop instruction.
REV.
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ADV7160/ADV7162
APPENDIX SIGNATURE ANALYZER
SIGNATURE REGISTER SIGNATURE CELL
CR42
CR42
Signature Register
ADV7160/ADV7162 contains onboard circuitry that enables both device system level test diagnostics. ADV7160/ ADV7162 signature analyzer pixel datapath, just before decoders. signature analyzer consists 33-bit linear feedback shift register. 30-bit pixel value parallel input into analyzer. signature analyzer only accumulates signature during active display time when BLANK high. CR45 CR47 Command Register control signature analyzer. When CR45 Command Register Logic "1," clock signature analyzer enabled. Toggling CR46 then high resets signature analyzer. This done give known starting point before acquiring signature. CR47 Command Register controls feedback inputs analyzer. When CR47 Command Register Logic "0," feedback disabled each clock cycle, 30-bit pixel value latched directly into analyzer. acquire signature analyzer clocked, CR47 Command Register Logic "1." acquire signature following procedure must followed: CR45 CR47 Command Register Logic during vertical retrace CR46 Command Register toggled reset analyzer. signature acquired during following active screen.
CR45 Command Register Logic during following vertical retrace acquired signature read. least clock cycles should allowed final pixels frame travel down pipeline ADV7160/ ADV7162 before signature clock disabled. signature analyzer read from control registers 010H 013H. These read only 10-bit registers. access these registers depends whether part 8-bit 10-bit data mode operates same accessing color palette.
Address Register CONTROL (A10-A0) REGISTERS 0013H 0012H 0011H 0010H CONTENTS
Signature Misc Register Signature Blue Register
Signature Green Register Signature Register
-40-
REV.
ADV7160/ADV7162
APPENDIX JTAG TEST PORT (IEEE1149.1)
THREE-STATE CONTROL LOADIN SCKIN SCKOUT CLOCK CLOCK LOADOUT PRGCKOUT PS0A PS0B PS0C PS0D PS1A PS1B PS1C PS1D TRISYNC ODD/EVEN SYNC BLANK SYNCOUT
JTAG Boundary Scan Chain
JTAG Test Port
JTAG Test Port 4-pin interface consisting TCK: Test Clock TMS: Test Mode Select TDI: Test Data Input TDO: Test Data Output ADV7160/ADV7162 into required mode, Instruction Register must loaded.
INSTRUCTION EXTEST SAMPLE/PRELOAD IDCODE PRIVATE BYPASS BYPASS BYPASS BYPASS INSTRUCTION REGISTER CODE
Private1 instruction internal production test only. IDCode 32-bit number which scanned through TDO. contents defined below:
VERSION BITS) ADV7160 ADV7162 PART NUMBER BITS) 2776H 2779H MANUFACTURER BITS) 0E5H 0E5H
ADV7160 implementation mandatory instructions: Bypass, Sample/Preload Extest, optional instruction: IDCode. There also private instruction: Private1. REV.
Boundary Scan Chain fundamental feature JTAG Test Port. allows digital input output pins part connected into shift register between pins. digital pins sampled, controlled over JTAG port carry testing. boundary scan cell PLLREF pin. Three-State Control cell controls three-state status microport databus. There cells total Boundary Scan Chain.
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ADV7160/ADV7162
APPENDIX THERMAL ENVIRONMENTAL CONSIDERATIONS
ADV7160/ADV7162 very highly integrated monolithic silicon device. This high level integration, such small package, inevitably leads consideration thermal environmental conditions which ADV7160/ADV7162 must operate Reliability device enhanced keeping cool possible. order avoid destructive damage device, absolute maximum junction temperature 150°C must never exceeded. Certain applications, depending ambient temperature pixel data rates require forced cooling external heatsinks. following data intended guide evaluating operating conditions particular application that optimum device system performance achieved. should noted that information package characteristics published herein most date time reading this. Advances package compounds manufacture will inevitably lead improvements thermal data. Please contact your local sales office most up-to-date information.
Power Dissipation
Heatsinks
maximum silicon junction temperature should limited 100°C. Temperatures greater than this will reduce long-term device reliability. ensure that silicon junction temperature stays within prescribed limits, addition external heatsink necessary. Heatsinks will reduce shown Thermal Characteristics Airflow table.
Table Thermal Characteristics Airflow-ADV7160*
Velocity (Linear Feet/min °C/W Heatsink EG&G D10100-28 Heatsink Thermalloy 2290 Heatsink
(Still Air) 25.5
diagrams show graphs power dissipation watts versus pixel clock frequency ADV7160 ADV7162. When using ADV7162 Bypass Mode, Pixel Mask Register should programmed reduce power further.
2.25
*These figures include thermal conduction through package leads into PCB. Thermal conduction through leads provide 10oC/W reduction
Table Thermal Characteristics Airflow-ADV7162*
Velocity (Linear Feet/min) °C/W Heatsink EG&G D10850-40 Heatsink EG&G D10851-36 Heatsink
(Still Air)
2.00 POWER DISSIPATION Watts 1.75
VREF +1.2V +25°C ADV7160 ADV7162
1.50 1.25 1.00
*These figures include thermal conduction through package leads into PCB. Thermal conduction through leads provide 5oC/W reduction
Thermal Model
0.75 0.50
junction temperature device specific application given
PIXEL CLOCK FREQUENCY
(JA) where: Junction Temperature Silicon (°C) Ambient Temperature (°C) Power Dissipation Junction Case Thermal Resistance (°C/W) Case Ambient Thermal Resistance (°C/W) Junction Ambient Thermal Resistance (°C/W)
Package Enhancements ADV7160
Note: "Worst Case On-Screen Pattern" corresponds full-scale transition each pixel value every CLOCK edge (00H, FFH, 00H, "Typical On-Screen Pattern" corresponds linear changes pixel input (i.e., Black White Ramp). general, color images tend approximate this characteristic.
Typical Power Dissipation Pixel Rate
Package Characteristics
tables thermal characteristics show typical information ADV7160 (160-Lead Plastic Power QFP) AD7162 (160-Lead Plastic QFP) using various values Airflow. Junction-to-Case (JC) Thermal Resistance this particular part (AD7160) 0.4°C/W (AD7162) 6.7°C/W (Note: independent airflow.)
standard PQFP package been enhanced PowerQuad2 package. This supports improved thermal performance compared standard PQFP. this case, attached heat slug that power that dissipated conducted external surface package. This provides highly efficient path transfer heat package surface. package configuration also provides efficient thermal path from ADV7160 Printed Circuit Board. -42- REV.
ADV7160/ADV7162
PAGE INDEX Topic Page FEATURES GENERAL DESCRIPTION ADV7160/ADV7162 BLOCK DIAGRAM ADV7160/ADV7162 SPECIFICATIONS ADV7160/ADV7162 TIMING CHARACTERISTICS TIMING WAVEFORMS 5-11 ORDERING GUIDE ABSOLUTE MAXIMUM RATINGS CONFIGURATIONS FUNCTION DESCRIPTION 13-14 CIRCUIT DETAILS OPERATION PIXEL PORT 15-16 CLOCK CONTROL CIRCUIT 16-17 CLOCK CONTROL SIGNALS 17-18 COLOR VIDEO MODES PIXEL PORT MAPPING 19-21 MULTIPLEXING 21-22 PORT INTERNAL REGISTER CONFIGURATION COLOR PALETTE ACCESS 24-25 ON-CHIP REGISTERS Address Register Mode Register Register Pixel Mask Register Command Register Command Register Command Register 28-29 Command Register 29-30 Command Register Command Register Register Register Status Register Revision Register CURSOR DESCRIPTION 31-32 Cursor X-Low X-High Register Cursor Y-Low Y-High Register Cursor Image Cursor Coordinate Even Cursor Coordinate Cursor Control Register 31-32 DACS VIDEO OUTPUTS 32-33 APPENDIX Board Design Layout Considerations 34-35 APPENDIX Typical Frame Buffer Interface APPENDIX 10-Bit DACs Gamma Correction APPENDIX Initialization Programming 38-39 APPENDIX Signature Analyzer APPENDIX JTAG Test Port APPENDIX Thermal Environmental Considerations INDEX OUTLINE DIMENSIONS FIGURE INDEX Figure Title Load Circuit Data-Bus Access &Relinquish Times JTAG Port Timing LOADOUT Pixel Clock Input LOADIN Pixel Input Data Pixel Input Analog Output Pipeline with Minimum LOADOUT LOADIN Delay (8:1 Mode) Pixel Input Analog Output Pipeline with Maximum LOADOUT LOADIN Delay (8:1 Mode) Pixel Input Analog Output Pipeline with Minimum LOADOUT LOADIN Delay (4:1 Mode) Pixel Input Analog Output Pipeline with Maximum LOADOUT LOADIN Delay (4:1 Mode) Pixel Input Analog Output Pipeline with Minimum LOADOUT LOADIN Delay (2:1 Mode) Pixel Input Analog Output Pipeline with Maximum LOADOUT LOADIN Delay (2:1 Mode) Pixel Clock Input Programmable Clock Output SCKIN SCKOUT Analog Output Response Pixel Clock Timing Multiplexed Color Inputs Clock Control Circuit LOADOUT Pixel Clock SCKOUT Generation Circuit Interface Using SCKIN SCKOUT Block Diagram Transfer Function Jitter 24-Bit 30-Bit True Color Configuration 15-Bit 24-Bit True Color Configuration 8-Bit 30-Bit Pseudo Color Configuration 16-Bit Color Mapping Using R7-R0 G7-G0 15-Bit True Color Mapping Using R7-R3, G7-G3 B7-B3 15-Bit True Color Mapping Using R6-R0 G7-G0 16-Bit True Color (Bypass) Using R7-R0 G7-G0 15-Bit True Color (Bypass) Using R6-R0 G7-G0 Direct Interfacing Video Memory 8-Bit Pseudo Color Multiplexing Mode Port Register Configuration Internal Register Configuration Address Decoding 8-Bit Databus Using 10-Bit DACs 8-Bit Databus Using 8-Bit DACs 10-Bit Databus Using 10-Bit DACs 10-Bit Databus Using 8-Bit DACs Mode Register Command Register Command Register Command Register Command Register Command Register Cursor Control Register Output Termination Composite Video Waveform, SYNC decoded; Pedestal IRE; Gain 3996 Composite Video Waveform, SYNC decoded; Pedestal IRE; Gain 4224 Composite Video Waveform, SYNC TRISYNC decoded; Pedestal IRE; Gain 5592 Composite Video Waveform, Pedestal IRE; Gain 4311
REV.
-43-
ADV7160/ADV7162
OUTLINE DIMENSIONS
Dimensions shown inches (mm).
S-160 160-Lead Plastic Quad Flatpack
1.239 (31.45) 1.219 (30.95) 1.107 (28.10) 1.100 (27.90) 6°±4°
0.160 (4.07) 0.037 (0.95) 0.026 (0.65) 4°±4°
VIEW
(PINS DOWN)
SEATING PLANE 0.004 (0.10) 0.070 (1.77) 0.062 (1.57)
0.070 (1.77) 0.062 (1.57)
0.026 (0.65)
0.014 (0.35) 0.011 (0.27)
0.145 (3.67) 0.125 (3.17)
-44-
REV.
PRINTED U.S.A.
C2013-6-4/95
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