1.544 Mbit/s VT1.5/TU-11 Async Mapper-Desync TXC-04011 DATA SHEET Prel

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1.544 Mbit/s VT1.5/TU-11 Async Mapper-Desync TXC-04011 DATA SHEET Prel

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ADMA-T1P Device
1.544 Mbit/s VT1.5/TU-11 Async Mapper-Desync TXC-04011 DATA SHEET Preliminary FEATURES
Add/drop 1.544 Mbit/s signals from STS-1, STS-3/AU-3, STM-1 VC-4 Independent drop timing modes Selectable B8ZS positive/negative rail interface. Performance counter provided illegal coding violations Digital desynchronizer reduces systemic jitter presence multiple pointer movements. register also provided control internal FIFO leak rate Drop buses monitored parity, loss clock, multiframe errors Performance counters provided VT/TU pointer movements, BIP-2 errors Block Errors (FEBEs) VT/TUs monitored Loss Pointer, Data Flags (NDFs), AIS, Remote Defect Indication (RDI), size errors (S-bits) byte Signal Label Mismatch Unequipped detection Loopback, generate BIP-2 errors, send capability Intel microprocessor interface 120-pin plastic quad flat package
ADMA-T1P device designed add/drop multiplexer, terminal multiplexer, dual single unidirectional ring applications. 1.544 Mbit/s signals mapped from asynchronous Virtual Tributaries (VT1.5s) Tributary Unit (TU11s). ADMA-T1P interfaces multiple-segment, byte-parallel SONET/SDH-formatted 19.44 Mbit/s byte rate STM-1/STS-3 operation 6.48 Mbit/s byte rate STS-1 operation. 1.544 Mbit/s signals either AMI/B8ZS positive/negative rail- NRZ-formatted signals. ADMA-T1P provides performance counters, alarm detection, ability generate errors Alarm Indication Signals (AIS). port loopback capability also provided. dual timing mode Plus feature increases signal count from ADMA-T1 device level that ADMA-T1P 120-pin package. ADMA-T1P interface used connect other TranSwitch devices such STM-1/STS-3/ STS-3c Overhead Terminator (SOT-3), TXC-03003, form STS-3/STM-1 add/drop terminal system. STS-1/STS-3/STM-1 1.544 Mbit/s add/drop mux/demux Unidirectional bidirectional ring applications STS-1/STS-3/STM-1 termination terminal mode multiplexer STS-1/STS-3/STM-1 test equipment
PRELIMINARY information documents contain information products sampling, pre-production early production phases product life cycle. Characteristic data other specifications subject change. Contact TranSwitch Applications Engineering current information this product.
APPLICATIONS
STS-1/STS-3/S- LINE SIDE side drop side side drop side
1.544 Mbit/s TERMINAL SIDE
ADMA-T1P 1.544 Mbit/s VT1.5/TU-11 Async Mapper Desync TXC-04011
Port receive clock Port transmit clock Port receive clock Port transmit clock
Microprocessor Timing Mode interface Select
U.S. Patents No.: 4,967,405; 5,033,064; 5,040,170; 5,265,096; 5,289,057 U.S. and/or foreign patents issued pending Copyright 1995 TranSwitch Corporation TranSwitch registered trademarks TranSwitch Corporation
External Clock
Document Number: TXC-04011-MB September 1995
TranSwitch Corporation
Progress Drive Shelton, 06484 Tel: 203-929-8810 Fax: 203-926-9453
PRELIMINARY
TABLE CONTENTS
SECTION
ADMA-T1P TXC-04011
PAGE
Block Diagram Block Diagram Description Diagram Descriptions Absolute Maximum Ratings Thermal Characteristics Power Requirements Input, Output Parameters Timing Characteristics Memory Memory Descriptions Multiplex Format Mapping Information Package Information Ordering Information Related Products Standards Documentation Sources Documentation Update Registration Form
LIST FIGURES
PAGE Figure Figure Figure Figure Figure Figure Figure Figure Figure ADMA-T1P TXC-04011 Block Diagram 1.544 Mbit/s Mapping ADMA-T1P TXC-04011 Diagram Ports Transmit Timing Ports Receive Timing STS-1 Drop Signals, Timing Derived from Drop STS-3/STM-1 Drop Signals, Timing Derived from Drop STS-1 Signals, Timing Derived from STS-3/STM-1 Signals, Timing Derived from
Figure Microprocessor Read Cycle Intel Timing Figure Microprocessor Write Cycle Intel Timing Figure ADMA-T1P TXC-04011 120-Pin Plastic Quad Flat Package
TXC-04011-MB September 1995
PRELIMINARY
BLOCK DIAGRAM
LINE SIDE
Receive VT/TU Terminate Destuff Transmit VT/TU Terminate Desync
ADMA-T1P TXC-04011
Repeated (Ports
TERMINAL SIDE
AMI/B8ZS Coder
RPOn RNOn RCOn
Control VT/TU Select
RESET Microprocessor ABUST EXTCK
Receive VT/TU Build
Drop Drop
Stuff/ Sync Stuff/ Sync
Transmit
VT/TU Build
AMI/B8ZS Decoder
TPIn TNIn TCIn Note: n=1-2
Repeated (Ports
Figure ADMA-T1P TXC-04011 Block Diagram
BLOCK DIAGRAM block diagram ADMA-T1P shown Figure ADMA-T1P interfaces four buses, designated Drop, Add, Drop Add. four buses STS-3/STM-1 rate 19.44 Mbytes/s, STS-1 rate 6.48 Mbytes/s. North American applications, asynchronous signals carried floating Virtual Tributary 1.5s (VT1.5s) Synchronous Transport Signal (STS-1), STS-1s that carried Synchronous Transport Signal (STS-3). ITU-T applications, signals carried floating mode Tributary Unit (TU-11s) STM-1 Virtual Container structure (VC-4) using Tributary Unit Group (TUG-3), STM-1 Virtual Container structure (VC-3) using Tributary Unit Group (TUG-2) mapping schemes. signals connected (dropped) from Drop Drop), both drop buses lines. asynchronous signals formatted into VT1.5s connected (added) either buses both, depending upon mode operation). When ABUST input high configure ADMA-T1P drop timing mode, buses are, definition, byte, frame, multiframe synchronous with their like-named drop buses, delayed because internal processing. example, byte from VT1.5 TU-11 added bus, time placement derived from Drop timing, from software instructions specifying which VT/TU number dropped. When device configured timing mode (ABUST low), data, parity indicator signals derived from clock, C1J1V1 signals. There will delay either clock cycles output signals relative C1J1V1 signals.
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ADMA-T1P TXC-04011
Receive Block identical Receive Block. VT/TU Terminate, Destuff, Desync, AMI/ B8ZS Line Coder Blocks also repeated both ports. Twelve leads connected between drop ADMA-T1P Drop interface. interface consists byte clock, byte-wide data, C1J1 indicator signal, payload identification signal (SPE) parity. Parity selectable even parity, data only. Depending upon application, buffers latches used between system buses ADMAT1P. Each interface monitored parity, loss clock, multiframe errors. Under microprocessor control, receive blocks extract VT1.5 TU-11 from STS-3 VC-4 VT/TU Terminate Blocks. Each Terminate Block performs pointer processing V2), overhead byte (V5) processing, provides status eight receive overhead communications bits located control bytes VT/TU (see Figure pointer bytes monitored indication, AIS, Loss Pointer alarms. addition, size (S-bits) pointer bytes monitored correct value. Overhead byte (V5) processing includes BIP-2 parity check, along with count detected errors, counting number received Block Errors (FEBE), states receive signal label, mismatch receive signal label against microprocessor written value, unequipped status detection, status Remote Defect Indication (RDI) bit, Remote Failure Indication (RFI) bit. Depending drop selected, VT/TU destuffed using majority rule sets three justification control bits (Cn) which determines whether S-bits data bits justification bits. Desync Block removes effects output systemic jitter that might occur signal mappings pointer movements. Desync Block contains parts, pointer leak buffer loop buffer. function pointer leak buffer accept five consecutive positive negative pointer adjustments ramp effect over specified period time. Loop Buffer consists digital loop filter, which designed track frequency received signal remove both transmission stuffing jitter. option each port provides either data clock AMI/B8ZS-coded positive negative rail signals line interface. Transmit data (towards line) clocked ADMA-T1P rising edges clock. Towards SONET/SDH buses, ADMA-T1P accepts either AMI/B8ZS-coded positive negative rail signals data. 16-bit performance counter provided that counts illegal B8ZS coding violations. line monitored AIS, loss clock signal. Stuff/Sync Block time buffers signal frequency justification Stuff Block. Stuff/Sync Block contains FIFO uses threshold modulation VT/TU justification process. This Block also permits tracking incoming signal having average frequency offset high ppm, peak-to-peak jitter. interface between this Block VT/TU Build Block bidirectional. VT/TU Build Block request bits from FIFO based VT/TU phase. justification algorithm fixes first S-bit (S1) pattern 1110 every four multiframes. second S-bit contains either data justification based length measurement. Since ADMA-T1P supports ring system architecture, sets Blocks provided each port. VT/TU Block formats VT/TU into STS-1, STS-3 STM-1 structure asynchronous 1.544 Mbit/s signals, shown Figure pointer value bytes) fixed value Access provided determining states overhead communications channel (O-bits) located justification control bytes VT/TU format. Access also provided transmitting signal label Remote Defect Indication (RDI) bit, both which located overhead byte. Block Error (FEBE) state determined BIP-2 detector drop side. addition, control provided generating VT/TU (all ones).
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Figure 1.544 Mbit/s Mapping VT1.5 (Pointer Byte)
ADMA-T1P TXC-04011
RRRRRRIR bytes (1.544 Mbit/s Data) bytes (1.544 Mbit/s Data)
bytes
(Pointer Byte)
bytes
Information Overhead communications Justification control Justification opportunity Fixed stuff (set
bytes (1.544 Mbit/s Data)
(Action)
bytes
bytes (1.544 Mbit/s Data) Bytes
(Reserved)
bytes Path Overhead (V5) Byte
BIP-2 BIP-2 Interleaved Parity bits) FEBE Block Error Indication Remote Failure Indication L1L2L3 Signal Label Remote Defect Indication FEBE Signal Label
Data Flag Normal 0110 1001
Size S1S2
Positive Justification Invert five I-bits Negative Justification Invert five D-bits Pointer Range decimal
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DIAGRAM
TCI2 TNI2 TLOS2 TPI2 RCO2 RNO2 BASPE RPO2 BADD BDC1J1 BAC1J1V1 BDCLK BACLK BDPAR
ADMA-T1P TXC-04011
DESCRIPTIONS
POWER SUPPLY GROUND Symbol 107, 109, 101, 104, I/O/P Type Name/Function VDD: +5-volt supply voltage, ±5%. Ground: volts reference
Note: Input; Output; Power
RCO1 RNO1 RPO1 TCI1 TNI1 TLOS1 AASPE TPI1 AADD ADC1J1 AAC1J1V1 ADCLK AACLK ADPAR
Figure ADMA-T1P TXC-04011 Diagram
BDSPE UPAD0/D0 UPAD1/D1 UPAD2/D2 UPAD3/D3 UPAD4/D4 UPAD5/D5 UPAD6/D6 UPAD7/D7 HIGHZ TEST EXTCK RESET ADSPE
ADMA-T1P Diagram
(Top View)
TXC-04011
BAPAR ABUST AAPAR
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Symbol 103, 106, 108, I/O/P -Type
ADMA-T1P TXC-04011
Name/Function
Connect: pins connected, even another pin, must left floating. Connection pins impair performance cause damage device.
DROP Symbol ADCLK I/O/P Type Name/Function Drop Clock: This clock operates 19.44 STS-3/STM-1 operation, 6.48 STS-1 operation. Drop byte-wide data (AD7-AD0), parity (ADPAR), indication (ADSPE), C1J1 byte indicator (ADC1J1) inputs detected falling edges this clock. drop timing mode (lead ABUST high) this clock also used timing deriving like-named byte-wide data (AA7AA0), indicator (AADD), parity (AAPAR). These signals clocked rising edges this clock during time slots that correspond selected VT/TU. Drop Parity Bit: parity input signal representing parity calculation each data byte (AD7AD0), indication (ADSPE), C1J1 byte indicator (ADC1J1) from drop bus. Control register bits provided which allow choice even parity instead, and/or restrict parity detection data byte only. Drop Data Byte: Byte-wide data corresponding STS-1/STS-3/STM-1 signal from bus. first received (dropped) from corresponds (pin 21). Drop Indicator: signal that active high during each byte STS-1/STS-3/STM-1 payload. Drop C1/J1 Indications: active high timing signal that carries STS-1/STS-3/STM-1 frame information. pulse identifies location first byte STS-3/STM-1 signal byte STS-1 signal. pulse, clock cycle wide, identifies location byte STM-1 VC-4 signal. Three pulses provided identify byte locations STM-1 AU-3s STS-3/STS-1 SPEs. pulse provided identify location pulse STS-1 operation. more pulses present signal, they ignored.
ADPAR
AD(7-0)
ADSPE ADC1J1
*See Input, Output Parameters section below Type definitions.
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Symbol AACLK I/O/P Type Name/Function
ADMA-T1P TXC-04011
Clock: When ABUST lead low, this clock must provided timing. This clock operates 19.44 STS-3/STM-1 operation, 6.48 STS-1 operation. indication C1J1 indicators input into ADMAT1P falling edges this clock. bytewide data, indicator, parity bits clocked rising edges clock during time slots that correspond selected (TU). When ABUST high, this input disabled.
AAPAR
CMOS Parity Bit: parity output signal cal(tristate) culated over byte-wide data. This 3-state lead only active when there data being added bus. control provided that allows even parity calculated. CMOS Data Byte: 3-state byte-wide data that cor(tristate) responds selected (TU). first transmitted (added) corresponds Indicator: When ABUST lead low, this signal must provided timing. This signal active high during each byte STS-1/STS-3/STM-1 payload. C1J1V1 Indication: When ABUST lead low, this signal must provided timing. This signal carries STS-1/STS-3/STM-1 frame information. pulse identifies first byte time STS-3/STM-1 signal byte time STS-1 signal. pulse, clock cycle wide, identifies location byte STM-1 VC-4 signal. Three pulses provided identify locations STM-1 AU-3s STS-3 SPEs. pulse provided identify location pulse STS-1 operation. pulses used multiframe indications.
AA(7-0)
AASPE
AAC1J1V1
AADD
CMOS Data Present Indicator: This normally active signal present when output data valid. identifies location (TU) time slots being selected. control provided that allows this active high instead active low.
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DROP Symbol BDCLK I/O/P Type Name/Function
ADMA-T1P TXC-04011
Drop Clock: This clock operates 19.44 STS-3/STM-1 operation, 6.48 STS-1 operation. Drop byte-wide data (BD7-BD0), parity (BDPAR), indication (BDSPE), C1J1 byte indicator (BDC1J1) inputs detected falling edges this clock. drop timing mode (lead ABUST high) this clock also used timing deriving like-named byte-wide data (BA7BA0), indicator (BADD), parity (BAPAR). These signals clocked rising edges this clock during time slots that correspond selected VT/TU. Drop Parity Bit: parity input signal representing parity calculation each data byte (BD7BD0), indication (BDSPE), C1J1 byte indicator (BDC1J1) from drop bus. Control register bits provided which allow choice even parity instead, and/or restrict parity detection data byte only. Drop Data Byte: Byte-wide data corresponding STS-1/STS-3/STM-1 signal from bus. first received (dropped) from corresponds (pin 70). Drop Indicator: signal that active high during each byte STS-1/STS-3/STM-1 payload. Drop C1/J1 Byte Indicators: active high timing signal that carries STS-1/STS-3/STM-1 frame information. pulse identifies location first byte STS-3/STM-1 signal byte STS-1 signal. pulse, clock cycle wide, identifies location byte STM-1 VC-4 signal. Three pulses provided identify byte locations STM-1 AU-3s STS-3/STS-1 SPEs. pulse provided identify location pulse STS-1 operation. more pulses present this signal, they ignored. Clock: When ABUST lead low, this clock must provided timing. This clock operates 19.44 STS-3/STM-1 operation, 6.48 STS-1 operation. indication C1J1 indicators input into ADMAT1P falling edges this clock. bytewide data, indicator, parity bits clocked rising edges clock during time slots that correspond selected (TU). When ABUST high, this input disabled.
BDPAR
BD(7-0)
BDSPE BDC1J1
BACLK
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Symbol BAPAR I/O/P Type Name/Function
ADMA-T1P TXC-04011
CMOS Parity Bit: parity output signal cal(tristate) culated over byte-wide data. This 3-state lead only active when there data being added bus. control provided that allows even parity calculated. CMOS Data Byte: 3-state byte-wide data that cor(tristate) responds selected (TU). first transmitted (added) corresponds Indicator: When ABUST lead low, this signal must provided timing. This signal active high during each byte STS-1/STS-3/STM-1 payload. C1J1 Indications: When ABUST lead low, this signal must provided timing. This signal carries STS-1/STS-3/STM-1 frame information. pulse identifies first byte time STS-3/STM-1 signal byte time STS-1 signal. pulse, clock cycle wide, identifies location byte STM-1 VC-4 signal. Three pulses provided identify locations STM-1 AU-3s STS-3 SPEs. pulse provided identify location pulse STS-1 operation. pulses used multiframe indications.
BA(7-0)
BASPE
BAC1J1V1
BADD
CMOS Data Present Indicator: This normally active signal present when output data valid. identifies location (TU) time slots being selected. control provided that allows this active high instead active low.
PORT INTERFACE Symbol RCO1 I/O/P Type Name/Function
CMOS Receive Output Clock, Port 1.544 clock (tristate) output. Data clocked ADMA-T1P rising edges this clock. Control bits provided inverting this clock forcing this lead 3-state. CMOS Receive Data Positive Rail NRZ, Port When (tristate) ADMA-T1P operating with rail interface, positive rail data provided this lead. When operating bypass mode, signal provided this lead. control provided forcing this lead 3state. CMOS Receive Data Negative Rail, Port When (tristate) ADMA-T1P operating with rail interface, negative rail data provided this lead. control provided forcing this lead 3-state. mode, this lead forced high impedance state. TXC-04011-MB September 1995
RPO1
RNO1
PRELIMINARY
Symbol TCI1 I/O/P Type TTLs Name/Function
ADMA-T1P TXC-04011
Transmit Input Clock, Port 1.544 clock input. Data clocked into ADMA-T1P falling edges this clock. control provided inverting this clock. Transmit Data Positive Rail NRZ, Port When ADMA-T1P operating with rail interface, positive rail input data provided this lead. When operating bypass mode, signal provided this lead. Transmit Data Negative Rail, Port 1/External Transmit Loss Signal, Port When ADMA-T1P operating with rail interface, negative rail input data provided this lead. When interface selected, this lead used provide input active external transmit loss signal indication. this used indicating loss signal then must held high.
TPI1
TNI1/ TLOS1
PORT INTERFACE Symbol RCO2 I/O/P Type Name/Function
CMOS Receive Output Clock, Port 1.544 clock (tristate) output. Data clocked ADMA-T1P rising edges this clock. Control bits provided inverting this clock forcing this lead 3-state. CMOS Receive Data Positive Rail NRZ, Port When (tristate) ADMA-T1P operating with rail interface, positive rail data provided this lead. When operating bypass mode, signal provided this lead. control provided forcing this lead 3state. CMOS Receive Data Negative Rail, Port When (tristate) ADMA-T1P operating with rail interface, negative rail data provided this lead. control provided forcing this lead 3-state. mode, this lead forced high impedance state. TTLs Transmit Input Clock, Port 1.544 clock input. Data clocked into ADMA-T1P falling edges this clock. control provided inverting this clock. Transmit Data Positive Rail NRZ, Port When ADMA-T1P operating with rail interface, positive rail input data provided this lead. When operating bypass mode, signal provided this lead.
RPO2
RNO2
TCI2
TPI2
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Symbol TNI2/ TLOS2 I/O/P Type Name/Function
ADMA-T1P TXC-04011
Transmit Data Negative Rail, Port 2/External Transmit Loss Signal, Port When ADMAT1P operating with rail interface, negative rail input data provided this lead. When interface selected, this lead used provide input active external transmit loss signal indication. this used indicating loss signal then must held high.
MICROPROCESSOR INTERFACE Symbol UPAD(7-0) D(7-0) 102, 100, I/O/P Type Name/Function Address/Data Bus: These leads constitute time multiplexed address data accessing registers which reside ADMA-T1P. UPAD7/D7 most significant bit. High logic Select: enables microprocessor access memory registers control, status, alarm information. Read: active signal generated microprocessor reading registers which reside memory map. Write: active signal generated microprocessor writing registers which reside memory map. Address Latch Enable: active high signal generated microprocessor. Used processor holding address stable during read/write cycle.
TTLs
TTLs
TTLs
TTLs
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CONTROLS Symbol TEST EXTCK I/O/P Type TTLs CMOS Name/Function TranSwitch Test Bit: Must held high.
ADMA-T1P TXC-04011
External Reference Clock: 48.6360 (+/- over life) clock that duty cycle must applied this operating desynchronizer, generating line AIS, driving other internal circuitry. Hardware Reset: active pulse that must applied this minimum nanoseconds after power first applied. reset clears performance counters alarms, resets control bits, initializes internal FIFO. microprocessor must initialize control bits normal operation. High Impedance Select: sets output pins high impedance state testing purposes. Otherwise, this must held high. Timing Select: selects timing mode. clock (AACLK, BACLK), (AASPE, BASPE) C1J1V1 (AAC1J1V1, BAC1J1V1) input signals used deriving data, parity indicator signals buses. high selects drop timing mode. data, parity indicator signals derived from drop timing signals.
RESET
TTLs
HIGHZ
TTLs
ABUST
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ABSOLUTE MAXIMUM RATINGS
Parameter Supply voltage input voltage Ambient operating temperature Operating junction temperature Storage temperature range Symbol -0.5 -0.5 +6.0
ADMA-T1P TXC-04011
Unit
*Note: Operating conditions exceeding those listed Absolute Maximum Ratings cause permanent failure. Exposure absolute maximum ratings extended periods impair device reliability.
THERMAL CHARACTERISTICS
Parameter Thermal resistance: junction ambient -Typ -Unit
oC/W
Test Conditions ft/min linear airflow
POWER REQUIREMENTS
Parameter 4.75 5.25 Unit STS-1 STS-1 STS-3 STM-1 STS-3 STM-1 Test Conditions
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INPUT, OUTPUT PARAMETERS
ADMA-T1P TXC-04011
INPUT PARAMETERS CMOS Parameter Input leakage current Input capacitance 3.15 1.65 Unit Test Conditions 4.75 5.25 4.75 5.25 5.25
INPUT PARAMETERS Parameter Input leakage current Input capacitance +1.0 Unit Test Conditions 4.75 5.25 4.75 5.25 5.25
INPUT PARAMETERS TTLs Parameter Negative going, threshold voltage Positive going, threshold voltage Input leakage current Input capacitance Vhys Hysteresis (VT+ VT-) Unit 5.25 Test Conditions
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OUTPUT PARAMETERS CMOS Parameter (HIGHZ output current) -4.0 +10.0 Unit
ADMA-T1P TXC-04011
Test Conditions 4.75; -4.0 4.75;
INPUT/OUTPUT PARAMETERS Parameter Input leakage current Input capacitance -8.0 +1.0 Unit 4.75; -8.0 4.75; Test Conditions 4.75 5.25 4.75 5.25 5.25
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TIMING CHARACTERISTICS
ADMA-T1P TXC-04011
Detailed timing diagrams ADMA-T1P device illustrated Figures through with values timing intervals tabulated below each timing diagram. output times measured with maximum load capacitance. Timing parameters measured voltage levels (VIH VIL)/2 input signals (VOH VOL)/2 output signals. Figure Ports Transmit Timing
tCYC tPWL TCIn (INPUT) TPIn/TNIn (INPUT)
Note:
tPWH
Note: TCIn shown TCLKI where data clocked falling edges. Data clocked rising edges when TCLKI operation, TNIn used input external loss signal indication. Otherwise, this must held high.
Parameter TCIn clock period TCIn clock time TCIn clock high time TPIn/TNIn data set-up time before TCIn TPIn/TNIn data hold time after TCIn
Symbol tCYC tPWL tPWH
560.0 280.0 280.0 10.0
647.7
Unit
TXC-04011-MB September 1995
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Figure Ports Receive Timing
ADMA-T1P TXC-04011
tCYC tPWH RCOn (OUTPUT) RPOn/RNOn (OUTPUT)
Note:
tPWL
Note: RCOn shown RCLKI=0, where data clocked rising edges. Data clocked falling edges when RCLKI=1.
Parameter RCOn clock period RCOn clock time RCOn clock high time RPOn/RNOn data delay from RCOn
Symbol tCYC tPWL tPWH
Unit
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ADMA-T1P TXC-04011
Figure STS-1 Drop Signals, Timing Derived from Drop
tCYC
A/BDCLK (INPUT)
tSU(1) tH(1) tSU(2)
tPWH
A/BD(7-0) (INPUT) A/BDSPE (INPUT)
tH(2)
tSU(1)
tH(1) tOD(2) tOD(1) tOD(3)
A/BDC1J1 (INPUT) A/BA(7-0) (OUTPUT) A/BADD (OUTPUT)
Note: output A/BA(7-0) shown above corresponds state control ABD, when there data byte clock cycle) delay between drop buses. This delay increased data bytes when control
Parameter A/BDCLK drop clock period A/BDCLK drop clock duty cycle, tPWH/tCYC A/BD(7-0) drop data A/BDC1J1 set-up time before A/BDCLK A/BD(7-0) drop data A/BDC1J1 hold time after A/BDCLK A/BDSPE set-up time before A/BDCLK A/BDSPE hold time after A/BDCLK A/BA(7-0) data (from tri-state) delay from A/BDCLK A/BA(7-0) data tri-state) delay from A/BDCLK A/BADD indicator delay from A/BDCLK
Symbol tCYC
154.32
Unit
tSU(1) tH(1) tSU(2) tH(2) tOD(2) tOD(3) tOD(1)
18.5 20.0 19.0
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ADMA-T1P TXC-04011
Figure STS-3/STM-1 Drop Signals, Timing Derived from Drop
tCYC
A/BDCLK (INPUT) A/BD(7-0) (INPUT) A/BDSPE (INPUT) A/BDC1J1 tSU(1) (INPUT) A/BA(7-0) (OUTPUT)
tPWH tSU(1) tH(1)
C1(1)
C1(2)
C1(3) tSU(2)
FIXED STUFF FIXED STUFF
tH(2)
tH(1) C1(1) tOD(2) tOD(3)
A/BADD (OUTPUT)
tOD(1)
Note: output A/BA(7-0) shown above corresponds state control ABD, when there data byte clock cycle) delay between drop buses. This delay increased data bytes when control
Parameter A/BDCLK drop clock period A/BDCLK drop clock duty cycle, tPWH/tCYC A/BD(7-0) drop data A/BDC1J1 set-up time before A/BDCLK A/BD(7-0) drop data A/BDC1J1 hold time after A/BDCLK A/BDSPE set-up time before A/BDCLK A/BDSPE hold time after A/BDCLK A/BA(7-0) data (from tri-state) delay from A/BDCLK A/BA(7-0) data tri-state) delay from A/BDCLK A/BADD indicator delay from A/BDCLK
Symbol tCYC tSU(1) tH(1) tSU(2) tH(2) tOD(2) tOD(3) tOD(1)
51.44
Unit
18.3 19.8 18.8
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Figure STS-1 Signals, Timing Derived from
tCYC
ADMA-T1P TXC-04011
A/BACLK (INPUT)
tPWH
A/BASPE (INPUT)
tSU(1) tH(1)
tSU(2) tH(2)
A/BAC1J1V1 (INPUT)
tOD(3)
A/BA(7-0) (OUTPUT) A/BADD (OUTPUT)
tOD(2)
tOD(1)
Note: output A/BA(7-0) shown above corresponds state control ABD, when there data byte clock cycle) delay between drop buses. This delay increased data bytes when control
Parameter A/BACLK drop clock period A/BACLK duty cycle, tPWH/tCYC A/BAC1J1V1 set-up time A/BACLK A/BAC1J1V1 hold time after A/BACLK A/BASPE set-up time A/BACLK A/BASPE hold time after A/BACLK A/BA(7-0) data (from tristate) delay from A/BACLK A/BA(7-0) data tristate delay from A/BACLK A/BADD indicator delay from A/BACLK
Symbol tCYC
154.32
Unit
tSU(1) tH(1) tSU(2) tH(2) tOD(2) tOD(3) tOD(1)
18.5 20.0 19.0
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Figure STS-3/STM-1 Signals, Timing Derived from
tCYC
ADMA-T1P TXC-04011
A/BACLK (INPUT)
tSU(2)
tPWH
A/BASPE (INPUT)
tSU(1) tH(1) C1(1)
tH(2)
A/BAC1J1V1 (INPUT)
tOD(3)
A/BA(7-0) (OUTPUT) A/BADD (OUTPUT)
tOD(2)
tOD(1)
Note: output A/BA(7-0) shown above corresponds state control ABD, when there data byte clock cycle) delay between drop buses. This delay increased data bytes when control
Parameter A/BACLK drop clock period A/BACLK duty cycle, tPWH/tCYC A/BAC1J1V1 set-up time A/BACLK A/BAC1J1V1 hold time after A/BACLK A/BASPE set-up time A/BACLK A/BASPE hold time after A/BACLK A/BA(7-0) data (from tristate) delay from A/BACLK A/BA(7-0) data tristate delay from A/BACLK A/BADD indicator delay from A/BACLK
Symbol tCYC
51.44
Unit
tSU(1) tH(1) tSU(2) tH(2) tOD(2) tOD(3) tOD(1)
18.5 20.0 19.0
TXC-04011-MB September 1995
PRELIMINARY
Figure Microprocessor Read Cycle Intel Timing tPW(1) tSU(1) UPAD/D (0-7) tH(1) Address tOD(2) tSU(2) tH(3) tH(2) Data tOD(1) tW(1)
ADMA-T1P TXC-04011
tW(2)
tPW(2)
Parameter pulse width UPAD(0-7) address set-up time before UPAD(0-7) address hold time after UPAD(0-7) address hold time after D(0-7) data available delay time after D(0-7) data delay time tri-state after wait after set-up time before hold time after wait after pulse width
Symbol tPW(1) tSU(1) tH(1) tH(2) tOD(2) tOD(1) tW(1) tSU(2) tH(3) tW(2) tPW(2)
20.0
Unit
20.0 45.0 17.0
TXC-04011-MB September 1995
PRELIMINARY
Figure Microprocessor Write Cycle Intel Timing tPW(1) tSU(1) UPAD/D (0-7) tH(1) Address tSU(3) tW(2) tPW(2) Data tH(3) tH(2) tW(1)
ADMA-T1P TXC-04011
Parameter pulse width wait after UPAD(0-7) address set-up time before UPAD(0-7) address hold time after D(0-7) data input hold time after set-up time before hold time after wait after pulse width
Symbol tPW(1) tW(1) tSU(1) tH(1) tH(2) tSU(3) tH(3) tW(2) tPW(2)
20.0 16.0 20.0 45.0
Unit
TXC-04011-MB September 1995
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MEMORY
ADMA-T1P TXC-04011
ADMA-T1P memory consists counters register positions which accessed microprocessor. Addresses which shown TranSwitch test registers wholly `Unused' bytes memory must accessed microprocessor. value specified content read from `Unused' position when address which contains selected read cycle, position should written when address selected write cycle address). COMMON CONTROL Address Status* (Hex)
RESET T1SEL1 MOD1 TAISE AAHZE
RESETS T1SEL0 MOD0 UQAE BAHZE NPIA
RESETC BYPAS1 T1B8ZS R1AIS ADDI NPIB
Unused
BYPAS2 T2B8ZS R2AIS NPIC
T1LOOP T1AIS RDIEN E1AISD
T2LOOP T2AIS T2SEL1
R1EN Unused T2SEL0
R2EN TCLKI RCLKI PTALTE Unused
Unused PDDO
TranSwitch Test Register TranSwitch Test Register TranSwitch Test Register
R=Read Only; R(L)=Read Only (Latched); R/W=Read/Write; W=Write only.
A-SIDE DROP STATUS REGISTERS Address Status* (Hex)
R(L)
ADLOC
Unused
AALOC
A2DH4E
A1DH4E
ADPAR
Unused Unused Unused Unused
PORT STATUS/TRANSMIT REGISTERS Address Status* (Hex)
R(L) R1SEL T1VTAIS T1FB2 T1FFB
Port Pointer Leak Rate Port B8ZS/AMI Coding Errors (low order byte) Unused R1FFE T1LOCS T1AIS
Port B8ZS/AMI Coding Errors (high order byte) Unused T1RDI T1RFI Label
Port O-Bits VTN1 (VT#)
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PORT A-SIDE DROP RECEIVE REGISTERS Address Status* (Hex)
R(L) R(L) Unused TranSwitch Test Register A1UNEQ A1AIS A1SLER A1LOP
ADMA-T1P TXC-04011
A1BIP2 Error Count A1FEBE Count Unused A1SIZE A1RDI A1NDF A1RFI Unused Label A1NJ Counter O-Bits A1UPSL TA1FE
A1PJ Counter
PORT B-SIDE DROP RECEIVE REGISTERS Address Status* (Hex)
R(L) R(L) Unused TranSwitch Test Register B1UNEQ B1AIS B1SLER B1LOP
B1BIP2 Error Count B1FEBE Count Unused B1SIZE B1RDI B1NDF B1RFI Unused Label B1NJ Counter O-Bits B1UPSL TB1FE
B1PJ Counter
B-SIDE DROP STATUS REGISTERS Address Status* (Hex)
R(L)
BDLOC
Unused
BALOC
B2DH4E
B1DH4E
BDPAR
Unused Unused Unused Unused
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PORT STATUS/TRANSMIT REGISTERS Address Status* (Hex)
R2SEL T2VTAIS T2FB2 T2FFB R(L)
ADMA-T1P TXC-04011
Port Pointer Leak Rate Port B8ZS/AMI Coding Errors (low order byte) Unused R2FFE T2LOCS T2AIS
Port B8ZS/AMI Coding Errors (high order byte) Unused T2RDI T2RFI Label
Port O-Bits VTN2 (VT#)
PORT A-SIDE DROP RECEIVE REGISTERS Address Status* (Hex)
R(L) R(L) Unused TranSwitch Test Register A2UNEQ A2AIS A2SLER A2LOP
A2BIP2 Error Count A2FEBE Count Unused A2SIZE A2RDI A2NDF A2RFI Unused Label A2NJ Counter O-Bits A2UPSL TA2FE
A2PJ Counter
PORT B-SIDE DROP RECEIVE REGISTERS Address Status* (Hex)
R(L) R(L) Unused TranSwitch Test Register B2UNEQ B2AIS B2SLER B2LOP
B2BIP2 Error Count B2FEBE Count Unused B2SIZE B2RDI B2NDF B2RFI Unused Label B2NJ Counter O-Bits B2UPSL TB2FE
B2PJ Counter
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MEMORY DESCRIPTIONS
CONTROL REGISTERS Address Symbol RESET Description
ADMA-T1P TXC-04011
Reset ADMA-T1P: configures controls their power-up states, resets performance counters re-centers internal FIFOs. Afterwards this self-clearing resets Note: Upon power-up control bits, except BPASn, MODn, AAHZE, BAHZE, reset (where represents port Upon powerup, alarms, except AnLOP BnLOP, reset MODn control bits select STS-3 format, while BPASn, AAHZE, BAHZE, AnLOP, BnLOP control bits Reset Selected Functions: resets performance counters alarms re-centers internal FIFOs. control register bits reset, will maintain their existing states. Afterwards this selfclearing resets Note Reset Counters: causes performance counters reset Afterwards this self-clearing resets Note Port Transmit A/B-side Selection: This works conjunction with R1SEL provide following modes operation port Timing VT/TU added derived from either Drop bus. T1SEL1 T1SEL0 R1SEL Mode A-side drop only B-side drop only A-side drop, A-side B-side drop, B-side A-side drop, B-side B-side drop, A-side A-side drop, A-side B-side B-side drop, B-side A-side
RESETS
RESETC T1SEL1 T1SEL0
BYPAS1 BYPAS2 T1LOOP
Bypass CODEC Port arranges B8ZS/AMI CODEC port bypassed operation. enables CODEC port Bypass CODEC Port arranges B8ZS/AMI CODEC port bypassed operation. enables CODEC port Port Loopback: causes loopback port receive output data clock signals looped back transmit input, receive data signals provided output. input signal from line disabled.
SONET Drop Port
Note This position should written after device initialization after mode changes (i.e., after changing T1SEL1, T1SEL0, T2SEL1, T2SEL0, R1SEL, VTN1, R2SEL VTN2 bits) order prevent FIFO error from occurring.
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Address (cont.) Symbol T2LOOP Description
ADMA-T1P TXC-04011
Port Loopback: causes loopback port receive output data clock signals looped back transmit input, receive data signals provided output. input signal from line disabled. Receive Port Enable: enables receive data (NRZ rail) output clock output port forces data clock output leads high impedance state. Receive Port Enable: enables receive data (NRZ rail) output clock output port forces data clock output leads high impedance state. SONET/SDH Format Selection: SONET/SDH format selection according table below: MOD1 MOD0 Format Selected STS-1 format STS-3 format STM-1 format STM-1 TUG-3/VC-4 format
R1EN
R2EN
MOD1 MOD0
T1B8ZS T2B8ZS T1AIS T2AIS TCLKI
Port B8ZS CODEC Enable: selects B8ZS CODEC function port selects CODEC function port Port B8ZS CODEC Enable: selects B8ZS CODEC function port selects CODEC function port Port Transmit AIS: causes (unframed ones signal) generated transmit (add) direction port Port Transmit AIS: causes (unframed ones signal) generated transmit (add) direction port Port Transmit Clock Inversion: causes data ports clocked positive clock edges. causes data clocked negative clock edges. Port Transmit Enable: enables sent when loss signal clock detected port port interface signals. unframed ones data signal. Unequipped Alarm Enable: enables receive sent when unequipped status detected either A-side B-side drop data. unequipped status defined VT/TU signal label.
TAISE
UQAE
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PRELIMINARY
Address (cont.) Symbol R1AIS Description
ADMA-T1P TXC-04011
Generate Receive Port causes generated receive data port independent internal alarm detection. unframed ones data signal. conditions generating port are: When control R1SEL more following: R1AIS=1. Loss Pointer (A1LOP). VT/TU (A1AIS). A-side drop loss clock (ADLOC). A-side Error (A1DH4E). Unequipped signal label (A1UNEQ), UQAE Mismatch signal label (A1SLER). VT/TU selection range equal When control R1SEL more following: R1AIS=1. Loss Pointer (B1LOP). VT/TU (B1AIS). B-side drop loss clock (BDLOC). B-side Error (B1DH4E). Unequipped signal label (B1UNEQ), UQAE Mismatch signal label (B1SLER). VT/TU selection range equal Microprocessor writes R1AIS.
R2AIS
Generate Receive Port causes generated receive data port independent internal alarm detection. unframed ones data signal. conditions generating port are: When control R2SEL more following: R2AIS=1. Loss Pointer (A2LOP). VT/TU (A2AIS). A-side drop loss clock (ADLOC). A-side Error (A2DH4E). Unequipped signal label (A2UNEQ), UQAE Mismatch signal label (A2SLER). VT/TU selection range equal When control R2SEL more following: R2AIS=1. Loss Pointer (B2LOP). VT/TU (B2AIS). B-side drop loss clock (BDLOC). B-side Error (B2DH4E). Unequipped signal label (B2UNEQ), UQAE Mismatch signal label (B2SLER). VT/TU selection range equal Microprocessor writes R2AIS.
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Address (cont.) Symbol RDIEN Description
ADMA-T1P TXC-04011
Transmit Receive Defect Indication Enable: enables ADMA-T1P send when receive alarm occurs. disables automatic insertion, allows microprocessor control both states transmitted status (Bit V5). port alarms causing function R1SEL, T1SEL1 T1SEL0 control bits. port alarms causing function R2SEL, T2SEL1 T2SEL0 control bits. following summary various alarms control bits that cause RDI. represents port When RDIEN Loss Pointer (AnLOP, BnLOP). VT/TU (AnAIS, BnAIS). A/B-side drop Error (AnDH4E, BnDH4E). Unequipped signal label (AnUNEQ, BnUNEQ), UQAE Signal label mismatch (AnSLER, BnSLER). When RDIEN Microprocessor writes TnRDI. Note. microprocessor send anytime writing TnRDI. However, prevent contention between internal alarms causing microprocessor controlling RDI, control RDIEN must written with
T2SEL1 T2SEL0
Port Transmit A/B-side Selection: This works conjunction with R2SEL provide following modes operation port Timing VT/TU added derived from either Drop bus. T2SEL1 T2SEL0 R2SEL Mode A-side drop only B-side drop only A-side drop, A-side B-side drop, B-side A-side drop, B-side B-side drop, A-side A-side drop, A-side B-side side drop, B-side A-side
RCLKI
Port Receive Clock Inversion: causes receive clock clock data negative edge instead positive edge both ports.
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Address Symbol AAHZE BAHZE ADDI Description
ADMA-T1P TXC-04011
A-side High Impedance Enable: forces A-side output signals high impedance state. allows normal operation. B-side High Impedance Enable: forces B-side outputs signals high impedance state. allows normal operation. Indicator Inversion: enables B-side indicator signals active high instead active low. enables B-side indicator signals active instead active high. Delayed: causes data delayed clock cycles with respect drop data. causes data delayed clock cycle with respect drop data. A/B-side Even Parity Generated: enables even parity generated, while enables parity generated. Pointer Tracking Transition Enabled: enables transition pointer tracking state machine, required ITU-T requirements. disables transition required Bellcore standards. Null Pointer Indicator Selection: enables null pointer indicator generated more TUG-3s when STM-1 TUG-3 format selected. null pointer indicator defined 1001 bits 1-4, bits unspecified five bits 7-11, followed five zeros bits 12-16 (two bytes). Those bytes which designated stuff generated, data forced high impedance state during those time slots. Receive Byte Disable: disables add/drop byte from generating ports when byte ones. A/B-side Drop Even Parity Detected: enables even parity detected A/B-side drop buses. enables parity detected. A/B-side Drop Parity Detected Data Only: causes parity detected data byte only. causes parity detected data byte, C1J1 signals.
PTALTE
NPIA NPIB NPIC
E1AISD
PDDO
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A-SIDE DROP STATUS REGISTERS Address Symbol ADLOC Description
ADMA-T1P TXC-04011
A-side Drop Loss Clock: latched position that indicates loss clock A-side drop been detected. loss clock alarm causes receive duration alarm, sets likenamed signals (data signal) high impedance state. AADD indication signal becomes inactive duration alarm. This position cleared microprocessor read cycle. alarm active, this position will re-latch. loss clock alarm occurs when input drop clock (ADCLK) stuck high more clock cycles. Recovery occurs first drop clock transition. Loss Clock: latched position which indicates that detected loss clock, when control lead ABUST low. loss clock alarm causes data parity 3-state, sets indicator duration alarm. This position cleared microprocessor read cycle. alarm active, this position will re-latch. loss clock alarm occurs when input clock (AACLK) stuck high more clock cycles. Recovery occurs first clock transition. A-side Drop Port Loss Indication: latched position that indicates that anticipated received multiframe sequence been received properly. ADMA-T1P will continue operate free running mode, will lock sequence after consecutive sequences have been received properly. This position cleared microprocessor read cycle. alarm active, this position will re-latch. A-side Drop Port Loss Indication: latched position which indicates that anticipated received multiframe sequence been received properly. ADMA-T1P will continue operate free running mode, will lock sequence after consecutive sequences have been received properly. This position cleared microprocessor read cycle. alarm active, this position will re-latch. A-side Drop Parity Error Detected: latched position which indicates that parity error been detected A-side drop signals. Even parity detection enabled writing Drop Parity Even (DPE) control bit. Other than alarm indication, other action taken. This position cleared microprocessor read cycle. alarm active, this position will re-latch.
AALOC
A2DH4E
A1DH4E
ADPAR
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PRELIMINARY
PORT STATUS/TRANSMIT REGISTERS Address Symbol Port Pointer Leak Rate Value Port Coding Error Counter Order Byte R1FFE Description
ADMA-T1P TXC-04011
Port FIFO Leak Rate Register: count written into this location used internal leak buffer, represents average leak rate. count represents frames, multiframes, rate occurrence pointer movements from number counts read from positive/ negative stuff counters. count invalid, selection takes place. Port Transmit Coding Violation Counter: order byte 16-bit saturating counter that counts number coding errors that have occurred B8ZS line codes. During read cycle internal logic holds count until read cycle complete, then updates counter. This counter cleared reset pulse, when written reset counter control (RESETC), read cycle. This location must read first before high order byte. Port Receive FIFO Error: latched position which indicates that receive FIFO port overflowed underflowed. FIFO will reset automatically. Other than alarm indication, other action will taken. This position cleared microprocessor read cycle. alarm active, this position re-latches. Port Transmit Loss Clock Signal: latched position which indicates that Port clock data signal failed. This position cleared microprocessor read cycle, either alarms then active this position re-latches. Loss clock occurs when input clock (TCI1) stuck high more clock cycles. Recovery occurs first input clock transition. Loss signal rail interface occurs when TPI1 signal transitions occur period consecutive pulse positions. Recovery occurs when there average pulse density least 12.5% over period contiguous pulse positions starting with receipt detected pulse. Port Transmit Detected: latched position which indicates that (unframed ones) been detected Port data. This position cleared microprocessor read cycle. alarm active, this position re-latches. Port Transmit Coding Violation Counter: High order byte 16-bit saturating counter which counts number coding errors that have occurred B8ZS line codes. This counter cleared reset pulse, when written reset counter control (RESETC), read cycle.
T1LOCS
T1AIS
Port Coding Error Counter High Order Byte
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Address Symbol T1VTAIS Description
ADMA-T1P TXC-04011
Port Transmit VT/TU AIS: causes VT/TU generated transmitted. VT/TU consists ones entire including bytes through Port Transmit BIP-2 Error Mask (Force BIP-2 Error): causes bits (BIP-2 value) transmitted byte sent inverted from calculated value continuously. Port Transmit Force FEBE Error: causes (FEBE) byte transmitted inverted from normally transmitted value. Port Transmit Remote Defect Indication (Yellow/FERF): causes alarm transmitted (Bit Port Transmit Remote Failure Indication: causes alarm transmitted (Bit Port Transmit Signal Label: three positions written processor correspond bits through byte. corresponds byte. Port 1Transmit Overhead Communication Channel Bits: Bits correspond bits first justification control byte, while bits correspond bits second justification control byte VT/TU format. Port Receive B-side VT/TU Selection: Determines drop VT/TU selection. selects B-side drop bus, selects A-side drop bus. Port VT/TU Selection: Works conjunction with R1SEL control bit. seven binary code written into this location selects that dropped from B-side drop bus. binary value value above range will select example, selection STS-3 format given below: STS-3 Mapping selected, generated STS-1#1, GP#1, VT#1 selected STS-1#2, GP#1, VT#1 selected STS-1#3, GP#1, VT#1 selected STS-1#3, GP#7, VT#4 selected selected, generated selected, generated
T1FB2
T1FFB T1RDI T1RFI Label Port Transmit O-bits R1SEL
VTN1
Note: over-written writing R1EN which will 3-state port data clock output leads.
TXC-04011-MB September 1995
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PORT A-SIDE DROP RECEIVE REGISTERS Address Symbol A1BIP2 Count Description
ADMA-T1P TXC-04011
Port A-side Drop BIP-2 Counter: 8-bit saturating counter which counts number BIP-2 errors detected receive direction. maximum errors detected each frame. During read cycle internal logic holds incoming error count until read cycle complete, then updates counter. This counter cleared reset pulse, when written reset counter control (RESETC), read cycle. Port A-side Drop FEBE Counter: 8-bit saturating counter which counts number FEBE errors received (Bit During read cycle internal logic holds incoming error count until read cycle complete, then updates counter. This counter cleared reset pulse, when written reset counter control (RESETC), read cycle. Port A-side Drop Unequipped Indication: latched position which indicates Unequipped status been detected signal label bits (Bits This position cleared microprocessor read cycle. alarm active, this position will re-latch. Port A-side Drop Signal Label Mismatch Indication: latched position which indicates that receive signal label bits (Bits match microprocessor-written signal label. This position cleared microprocessor read cycle. alarm active, this position re-latches. Port A-side Drop Data Flag Indication: latched position which indicates Data Flag (1001) been detected pointer byte (Bits inverse 0110). This position cleared microprocessor read cycle. alarm active, this position re-latches. Port Transmit A-side FIFO Error: latched position which indicates that A-side FIFO overflowed underflowed. FIFO resets automatically. This position cleared microprocessor read cycle. alarm active, this position re-latches.
A1FEBE Count
A1UNEQ
A1SLER
A1NDF
TA1FE
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Address Symbol A1AIS Description
ADMA-T1P TXC-04011
Port A-side Drop Alarm: latched position which indicates (TU) been detected. This position cleared microprocessor read cycle. alarm active, this position will relatch. Port A-side Drop Loss Pointer Alarm: latched position which indicates loss pointer been detected. This position cleared microprocessor read cycle. alarm active, this position will re-latch. Port A-side Drop Pointer Size Error Indication: latched position which indicates that receive size indicator pointer (Bits pointer byte) does This position cleared microprocessor read cycle. alarm active, this position will relatch. Port A-side Drop Remote Defect Indication (FERF): latched position which indicates (FERF/Yellow) alarm been detected (Bit This position cleared microprocessor read cycle. alarm active, this position will re-latch. Port A-side Drop Remote Failure Indication: latched position which indicates alarm been detected (Bit This position cleared microprocessor read cycle. alarm active, this position will re-latch. Port A-side Drop Received Signal Label: three positions correspond three signal label bits found bits through These bits updated each time. corresponds byte. These bits also compared against microprocessor-written mismatch signal label bits mismatch indication. Port A-side Drop Positive Pointer Justification Counter: four counter that increments positive pointer movement. During read cycle internal logic holds count until read cycle complete, then updates counter. This counter cleared reset pulse, when written reset counter control (RESETC), read cycle. Port A-side Drop Negative Pointer Justification Counter: four counter that increments negative pointer movement. During read cycle internal logic holds count until read cycle complete, then updates counter. This counter cleared reset pulse, when written reset counter control (RESETC), read cycle. Port A-side Drop Receive 0-bits: eight bits indicate states eight overhead communication bits received VT/TU. Bits correspond bits first justification control byte, while bits correspond bits second justification control byte VT/TU format. Port A-side Drop Microprocessor-Written Signal Label: three positions correspond three signal label bits found bits through corresponds byte. These bits written microprocessor, compared against received signal label mismatch signal label alarm.
A1LOP
A1SIZE
A1RDI
A1RFI
Label
A1PJ Count
A1NJ Count
O-bits
A1UPSL
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PORT B-SIDE DROP RECEIVE REGISTERS Address Symbol B1BIP2 Count Description
ADMA-T1P TXC-04011
Port B-side Drop BIP-2 Counter: 8-bit saturating counter which counts number BIP-2 errors detected receive direction. maximum errors detected each frame. During read cycle internal logic holds incoming error count until read cycle complete, then updates counter. This counter cleared reset pulse, when written reset counter control (RESETC), read cycle. Port B-side Drop FEBE Counter: 8-bit saturating counter which counts number FEBE errors received (Bit During read cycle internal logic holds incoming error count until read cycle complete, then updates counter. This counter cleared reset pulse, when written reset counter control (RESETC), read cycle. Port B-side Drop Unequipped Indication: latched position which indicates Unequipped status been detected signal label bits (Bits This position cleared microprocessor read cycle. alarm active, this position will re-latch. Port B-side Drop Signal Label Mismatch Indication: latched position which indicates that receive signal label bits (Bits match microprocessor-written signal label. This position cleared microprocessor read cycle. alarm active, this position re-latches. Port B-side Drop Data Flag Indication: latched position which indicates Data Flag (1001) been detected pointer byte (Bits inverse 0110). This position cleared microprocessor read cycle. alarm active, this position re-latches. Port Transmit B-side FIFO Error: latched position which indicates that B-side FIFO overflowed underflowed. FIFO will reset automatically. This position cleared microprocessor read cycle. alarm active, this position re-latches. Port B-side Drop Alarm: latched position which indicates (TU) been detected. This position cleared microprocessor read cycle. alarm active, this position will relatch. Port B-side Drop Loss Pointer Alarm: latched position which indicates loss pointer been detected. This position cleared microprocessor read cycle. alarm active, this position will re-latch. Port B-side Drop Pointer Size Error Indication: latched position which indicates that receive size indicator pointer (Bits pointer byte) does This position cleared microprocessor read cycle. alarm active, this position will relatch.
B1FEBE Count
B1UNEQ
B1SLER
B1NDF
TB1FE
B1AIS
B1LOP
B1SIZE
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Address (cont.) Symbol B1RDI Description
ADMA-T1P TXC-04011
Port B-side Drop Remote Defect Indication (FERF): latched position which indicates (FERF/Yellow) alarm been detected (Bit This position cleared microprocessor read cycle. alarm active, this position will re-latch. Port B-side Drop Remote Failure Indication: latched position which indicates alarm been detected (Bit This position cleared microprocessor read cycle. alarm active, this position will re-latch. Port B-side Drop Received Signal Label: three positions correspond three signal label bits found bits through These bits updated each time. corresponds byte. These bits also compared against microprocessor-written mismatch signal label bits mismatch indication. Port B-side Drop Positive Pointer Justification Counter: four counter that increments positive pointer movement. During read cycle internal logic holds incoming count until read cycle complete, then updates counter. This counter cleared reset pulse, when written reset counter control (RESETC), read cycle. Port B-side Drop Negative Pointer Justification Counter: four counter that increments negative pointer movement. During read cycle internal logic holds incoming count until read cycle complete, then updates counter. This counter cleared reset pulse, when written reset counter control (RESETC), read cycle. Port B-side Drop Receive 0-bits: eight bits indicate states eight overhead communication bits received Bits correspond bits first justification control byte, while bits correspond bits second justification control byte VT/TU format. Port B-side Drop Microprocessor-Written Signal Label: three positions correspond three signal label bits found bits through corresponds byte. These bits written microprocessor, compared against received signal label mismatch signal label alarm.
B1RFI
Label
B1PJ Count
B1NJ Count
O-bits
B1UPSL
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B-SIDE DROP STATUS REGISTERS Address Symbol BDLOC Description
ADMA-T1P TXC-04011
B-side Drop Loss Clock: latched position that indicates loss clock B-side drop been detected. loss clock alarm causes receive duration alarm, sets likenamed signals (data signal) high impedance state. BADD indication signal becomes inactive duration alarm. This position cleared microprocessor read cycle. alarm active, this position will re-latch. loss clock alarm occurs when input drop clock (BDCLK) stuck high more clock cycles. Recovery occurs first drop clock transition. Loss Clock: latched position which indicates that detected loss clock, when control lead ABUST low. loss clock alarm causes data parity 3-state, sets indicator duration alarm. This position cleared microprocessor read cycle. alarm active, this position will re-latch. loss clock alarm occurs when input clock (BACLK) stuck high more clock cycles. Recovery occurs first clock transition. B-side Drop Port Loss Indication: latched position that indicates that anticipated received multiframe sequence been received properly. ADMA-T1P will continue operate free running mode, will lock sequence after consecutive sequences have been received properly. This position cleared microprocessor read cycle. alarm active, this position will re-latch. B-side Drop Port Loss Indication: latched position which indicates that anticipated received multiframe sequence been received properly. ADMA-T1P will continue operate free running mode, will lock sequence after consecutive sequences have been received properly. This position cleared microprocessor read cycle. alarm active, this position will re-latch. B-side Drop Parity Error Detected: latched position which indicates that parity error been detected B-side drop signals. Even parity detection provided writing Drop Parity Even (DPE) control bit. Other than alarm indication, other action taken. This position cleared microprocessor read cycle. alarm active, this position will re-latch.
BALOC
B2DH4E
B1DH4E
BDPAR
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PORT STATUS/TRANSMIT REGISTERS Address Symbol Port Pointer Leak Rate Value Port Coding Error Counter Order Byte R2FFE Description
ADMA-T1P TXC-04011
Port FIFO Leak Rate Register: count written into this location used internal leak buffer, represents average leak rate. count represents frames, multiframes rate occurrence pointer movements from number counts read from positive/ negative stuff counters. count invalid, selection takes place. Port Transmit Coding Violation Counter: order byte 16-bit saturating counter that counts number coding errors that have occurred B8ZS line codes. During read cycle internal logic holds count until read cycle complete, then updates counter. This counter cleared reset pulse, when written reset counter control (RESETC), read cycle. This location must read first before reading high order byte. Port Receive FIFO Error: latched position which indicates that receive FIFO port overflowed underflowed. FIFO will reset automatically. Other than alarm indication, other action will taken. This position cleared microprocessor read cycle. alarm active, this position re-latches. Port Transmit Loss Clock Signal: latched position which indicates that Port clock data signal failed. This position cleared microprocessor read cycle, either alarms then active this position re-latches. Loss clock occurs when input clock (TCI2) stuck high more clock cycles. Recovery occurs first input clock transition. Loss signal rail interface occurs when TPI2 signal transitions occur period consecutive pulse positions. Recovery occurs when there average pulse density least 12.5% over period contiguous pulse positions starting with receipt detected pulse. Port Transmit Detected: latched position which indicates that (unframed ones) been detected Port data. This position cleared microprocessor read cycle. alarm active, this position re-latches. Port Transmit Coding Violation Counter: High order byte 16-bit saturating counter which counts number coding errors that have occurred B8ZS line codes. This counter cleared reset pulse, when written reset counter control (RESETC), read cycle.
T2LOCS
T2AIS
Port Coding Error Counter High Order Byte
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Address Symbol T2VTAIS Description
ADMA-T1P TXC-04011
Port Transmit VT/TU AIS: causes VT/TU generated transmitted. VT/TU consists ones entire including bytes through Port Transmit BIP-2 Error Mask (Force BIP-2 Error): causes bits (BIP-2 value) transmitted byte sent inverted from calculated value continuously. Port Transmit Force FEBE Error: causes (FEBE) byte transmitted inverted from normally transmitted value. Port Transmit Remote Defect Indication (Yellow/FERF): causes alarm transmitted (Bit Port Transmit Remote Failure Indication: causes alarm transmitted (Bit Port Transmit Signal Label: three positions written processor correspond bits through byte. corresponds byte. Port Transmit Overhead Communication Channel Bits: Bits correspond bits first justification control byte, while bits correspond bits second justification control byte VT/TU format. Port Receive B-side VT/TU Selection: Determines drop VT/TU selection. selects B-side drop bus, selects A-side drop bus. Port VT/TU Selection: Works conjunction with R2SEL control bit. seven binary code written into this location selects that dropped from B-side drop bus. binary value value above range will select example, selection STS-3 format given below: STS-3 Mapping selected, generated STS-1#1, GP#1, VT#1 selected STS-1#2, GP#1, VT#1 selected STS-1#3, GP#1, VT#1 selected STS-1#3, GP#7, VT#4 selected selected, generated selected, generated
T2FB2
T2FFB T2RDI T2RFI Label Port Transmit O-bits R2SEL
VTN2
Note: over-written writing R2EN which will 3-state port data clock output leads.
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PORT A-SIDE DROP RECEIVE REGISTERS Address Symbol A2BIP2 Count Description
ADMA-T1P TXC-04011
Port A-side Drop BIP-2 Counter: 8-bit saturating counter which counts number BIP-2 errors detected receive direction. maximum errors detected each frame. During read cycle internal logic holds incoming error count until read cycle complete, then updates counter. This counter cleared reset pulse, when written reset counter control (RESETC), read cycle. Port A-side Drop FEBE Counter: 8-bit saturating counter which counts number FEBE errors received (Bit During read cycle internal logic holds incoming error count until read cycle complete, then updates counter. This counter cleared reset pulse, when written reset counter control (RESETC), read cycle. Port A-side Drop Unequipped Indication: latched position which indicates Unequipped status been detected signal label bits (Bits This position cleared microprocessor read cycle. alarm active, this position will re-latch. Port A-side Drop Signal Label Mismatch Indication: latched position which indicates that receive signal label bits (Bits match microprocessor-written signal label. This position cleared microprocessor read cycle. alarm active, this position re-latches. Port A-side Drop Data Flag Indication: latched position which indicates Data Flag (1001) been detected pointer byte (Bits inverse 0110). This position cleared microprocessor read cycle. alarm active, this position re-latches. Port Transmit A-side FIFO Error: latched position which indicates that A-side FIFO overflowed underflowed. FIFO will reset automatically. This position cleared microprocessor read cycle. alarm active, this position re-latches. Port A-side Drop Alarm: latched position which indicates (TU) been detected. This position cleared microprocessor read cycle. alarm active, this position will relatch. Port A-side Drop Loss Pointer Alarm: latched position which indicates loss pointer been detected. This position cleared microprocessor read cycle. alarm active, this position will re-latch. Port A-side Drop Pointer Size Error Indication: latched position which indicates that receive size indicator pointer (Bits pointer byte) does This position cleared microprocessor read cycle. alarm active, this position will relatch.
A2FEBE Count
A2UNEQ
A2SLER
A2NDF
TA2FE
A2AIS
A2LOP
A2SIZE
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Address (cont.) Symbol A2RDI Description
ADMA-T1P TXC-04011
Port A-side Drop Remote Defect Indication (FERF): latched position which indicates (FERF/Yellow) alarm been detected (Bit This position cleared microprocessor read cycle. alarm active, this position will re-latch. Port A-side Drop Remote Failure Indication: latched position which indicates alarm been detected (Bit This position cleared microprocessor read cycle. alarm active, this position will re-latch. Port A-side Drop Received Signal Label: three positions correspond three signal label bits found bits through These bits updated each time. corresponds byte. These bits also compared against microprocessor written mismatch signal label bits mismatch indication. Port A-side Drop Positive Pointer Justification Counter: four counter that increments positive pointer movement. During read cycle internal logic holds incoming count until read cycle complete, then updates counter. This counter cleared reset pulse, when written reset counter control (RESETC), read cycle. Port A-side Drop Negative Pointer Justification Counter: four counter that increments negative pointer movement. During read cycle internal logic holds incoming count until read cycle complete, then updates counter. This counter cleared reset pulse, when written reset counter control (RESETC), read cycle. Port A-side Drop Receive 0-bits: eight bits indicate states eight overhead communication bits received VT/TU. Bits correspond bits first justification control byte, while bits correspond bits second justification control byte VT/TU format. Port A-side Drop Microprocessor-Written Signal Label: three positions correspond three signal label bits found bits through corresponds byte. These bits written microprocessor, compared against received signal label mismatch signal label alarm.
A2RFI
Label
Port A2PJ Count
Port A2NJ Count
O-bits
A2UPSL
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PORT B-SIDE DROP RECEIVE REGISTERS Address Symbol B2BIP2 Count Description
ADMA-T1P TXC-04011
Port B-side Drop BIP-2 Counter: 8-bit saturating counter which counts number BIP-2 errors detected receive direction. maximum errors detected each frame. During read cycle internal logic holds incoming error count until read cycle complete, then updates counter. This counter cleared reset pulse, when written reset counter control (RESETC), read cycle. Port B-side Drop FEBE Counter: 8-bit saturating counter which counts number FEBE errors received (Bit During read cycle internal logic holds incoming error count until read cycle complete, then updates counter. This counter cleared reset pulse, when written reset counter control (RESETC), read cycle. Port B-side Drop Unequipped Indication: latched position which indicates Unequipped status been detected signal label bits (Bits This position cleared microprocessor read cycle. alarm active, this position will re-latch. Port B-side Drop Signal Label Mismatch Indication: latched position which indicates that receive signal label bits (Bits match microprocessor-written signal label. This position cleared microprocessor read cycle. alarm active, this position re-latches. Port B-side Drop Data Flag Indication: latched position which indicates Data Flag (1001) been detected pointer byte (Bits inverse 0110). This position cleared microprocessor read cycle. alarm active, this position re-latches. Port Transmit B-side FIFO Error: latched position which indicates that B-side FIFO overflowed underflowed. FIFO will reset automatically. This position cleared microprocessor read cycle. alarm active, this position re-latches. Port B-side Drop Alarm: latched position which indicates (TU) been detected. This position cleared microprocessor read cycle. alarm active, this position will relatch. Port B-side Drop Loss Pointer Alarm: latched position which indicates loss pointer been detected. This position cleared microprocessor read cycle. alarm active, this position will re-latch. Port B-side Drop Pointer Size Error Indication: latched position which indicates that receive size indicator pointer (Bits pointer byte) does This position cleared microprocessor read cycle. alarm active, this position will relatch.
B2FEBE Count
B2UNEQ
B2SLER
B2NDF
TB2FE
B2AIS
B2LOP
B2SIZE
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Address (cont.) Symbol B2RDI Description
ADMA-T1P TXC-04011
Port B-side Drop Remote Defect Indication (FERF): latched position which indicates (FERF/Yellow) alarm been detected (Bit This position cleared microprocessor read cycle. alarm active, this position will re-latch. Port B-side Drop Remote Failure Indication: latched position which indicates alarm been detected (Bit This position cleared microprocessor read cycle. alarm active, this position will re-latch. Port B-side Drop Received Signal Label: three positions correspond three signal label bits found bits through These bits updated each time. corresponds byte. These bits also compared against microprocessor-written mismatch signal label bits mismatch indication. Port B-side Drop Positive Pointer Justification Counter: four counter that increments positive pointer movement. During read cycle internal logic holds incoming count until read cycle complete, then updates counter. This counter cleared reset pulse, when written reset counter control (RESETC), read cycle. Port B-side Drop Negative Pointer Justification Counter: four counter that increments negative pointer movement. During read cycle internal logic holds incoming count until read cycle complete, then updates counter. This counter cleared reset pulse, when written reset counter control (RESETC), read cycle. Port B-side Drop Receive 0-bits: eight bits indicate states eight overhead communication bits received Bits correspond bits first justification control byte, while bits correspond bits second justification control byte VT/TU format. Port B-side Drop Microprocessor-Written Signal Label: three positions correspond three signal label bits found bits through corresponds byte. These bits written microprocessor, compared against received signal label mismatch signal label alarm.
B2RFI
Label
B2PJ Count
B2NJ Count
O-bits
B2UPSL
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MULTIPLEX FORMAT MAPPING INFORMATION
STS-1 VT1.5 (1.544 Mbit/s) Multiplex Format
ADMA-T1P TXC-04011
following diagram table illustrate mapping VT1.5s into STS-1 SPE. Column assigned carry path overhead bytes.
VT1.5
COLUMNS
STS-1
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STS-1 Mapping Registers
ADMA-T1P TXC-04011
VT1.5 Column Numbers* Selected
Note: Columns carry fixed Stuff bytes. Column assigned bytes.
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STS-3/AU-3 VT1.5/TU-11 (1.544 Mbit/s) Multiplex Format Mapping
ADMA-T1P TXC-04011
following diagram table illustrate mapping VT1.5/TU-11s into STS-3/AU-3 SPE. Each STS-3 carries three STS-1s. Column each STS-1/AU-3 assigned carry path overhead bytes.
VT1.5
COLUMNS
STS-1
STS-3/AU-3
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STS-3 AU-3 Mapping Registers VT/TU Column Numbers Registers VT/TU Column Numbers Registers
ADMA-T1P TXC-04011
VT/TU Column Numbers*
STS-1 AU-3
Selected STS-1 AU-3
STS-1 AU-3
Note: Columns 175, 176, fixed stuff.
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TU-11 VC-4 Multiplex Format Mapping
ADMA-T1P TXC-04011
following diagram table illustrate mapping TU-11s into VC-4. ADMA-T1P provides control bits enabling Null Pointer Indicators (NPIs) columns indicated.
COLUMNS
TU-11
TUG-2
TUG-3
VC-4
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TU-11 VC-4 Multiplex Format Mapping Registers VC-4 Column Numbers Registers VC-4 Column Numbers Registers
ADMA-T1P TXC-04011
VC-4 Column Numbers
TUG-3
Selected TUG-3
TUG-3
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PACKAGE INFORMATION
ADMA-T1P TXC-04011
ADMA-T1P available 120-pin plastic quad flat package suitable surface mounting, illustrated Figure
Details
TRANSWITCH
0.80
Detail
0.35 INDEX Detail
23.20 28.00 31.20
0.16 4.07 DETAIL 0.25 DEGREES DETAIL 3.42
0.80
Note: dimensions shown millimeters nominal unless otherwise indicated.
Figure ADMA-T1P TXC-04011 120-Pin Plastic Quad Flat Package
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ORDERING INFORMATION
Part Number: TXC-04011-BIPQ
ADMA-T1P TXC-04011
120-pin Plastic Quad Flat Package (PQFP)
RELATED PRODUCTS
TXC-02201, VLSI Device (SONET STS-3/STS-1 Mux/Demux). This device multiplexes/ demultiplexes three STS-1s into/from STS-3 signal, interfaces with SOT-1 device STS-1 signals. TXC-02301B, SYN155 VLSI Device (155-Mbit/s Synchronizer, Data Output). Provides complete STS-3/STM-1 frame synchronization incoming Mbit/s signals single power CMOS unit. TXC-02302B, SYN155C VLSI Device (155-Mbit/s Synchronizer, Clock Data Output). This device similar SYN155. both clock data outputs line side. TXC-03001, SOT-1 VLSI Device (SONET STS-1 Overhead Terminator). single chip, provides SONET interface payload. Provides access transport path overhead defined STS-1/STS-N SONET signal. TXC-03003, SOT-3 VLSI Device (STM-1/STS-3/STS-3c Overhead Terminator). This device performs section, line, path overhead processing STS-3/STS-3c/STM-1 signal. Compliant with ANSI ITU-T standards. TXC-04001B, ADMA-T1 VLSI Device (Dual 1.544 Mbit/s VT1.5 TU-11 Async MapperDesync). Interconnects signals with asynchronous mode VT1.5 TU-11 tributaries carried SONET STS-1 AU-3 rate payload interface. Similar ADMA-T1P device lacks timing mode packaged 84-pin PLCC.
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STANDARDS DOCUMENTATION SOURCES
ADMA-T1P TXC-04011
Telecommunication technical standards reference documentation obtained from following organizations:
ANSI (U.S.A.): American National Standards Institute (ANSI) West 42nd Street York, York 10036 Tel: 212-642-4900 Fax: 212-302-1286 Bellcore (U.S.A.): Bellcore Attention Customer Service Corporate Place Piscataway, 08854 Tel: 800-521-CORE U.S.A.) Tel: 908-699-5800 Fax: 908-336-2559 IEEE (U.S.A.) Institute Electrical Electronics Engineers, Inc. Customer Service Department Hoes Lane 1331 Piscataway, 08855-1331 Tel: 800-7014333 U.S.A.) Tel: 908-981-0060 Fax: 908-981-9667 ITU-TSS (International): Publication Services International Telecommunication Union (ITU) Telecommunication Standardization Sector (TSS) Place Nations 1211 Geneve Switzerland Tel: 41-22-730-5285 Fax: 41-22-730-5991 (Japan): Standard Publishing Group Telecommunications Technology Committee Floor, Hamamatsucho Suzuki Building, 2-11, Hamamatsu-cho, Minato-ku, Tokyo Tel: 81-3-3432-1551 Fax: 81-3-3432-1553
TXC-04011-MB September 1995
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ADMA-T1P TXC-04011
NOTES
TXC-04011-MB September 1995
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ADMA-T1P TXC-04011
NOTES
TranSwitch reserves right make changes product(s) circuit(s) described herein without notice. liability assumed result their application. TranSwitch assumes liability TranSwitch applications assistance, customer product design, software performance, infringement patents services described herein. does TranSwitch warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right TranSwitch covering relating combination, machine, process which such semiconductor products services might used.
PRELIMINARY information documents contain information products sampling, preproduction early production phases product life cycle. Characteristic data other specifications subject change. Contact TranSwitch Applications Engineering current information this product. TXC-04011-MB September 1995
TranSwitch VLSI: Powering Communication Innovation
TranSwitch Corporation Progress Drive Shelton, 06484 Tel: 203-929-8810 Fax: 203-926-9453
PRELIMINARY
DOCUMENTATION UPDATE REGISTRATION FORM
ADMA-T1P TXC-04011
would like added database customers have registered receive updated documentation this device becomes available, please provide your name address below, mail this page Mary Koch TranSwitch. Mary will ensure that relevant Product Information Sheets, Data Sheets, Application Notes Technical Bulletins sent you. Please print type information requested below, attach business card. Name: Title: Company: Dept./Mailstop: Street: City/State/Zip: located outside U.S.A., please Postal Code: Country:
Telephone:_ Ext.: Fax: E-Mail: Purchasing Dept. Location:
Please describe briefly your intended application this device, indicate whether would care have TranSwitch applications engineer contact provide assistance:
also interested receiving updated documentation other TranSwitch device types, please list them below rather than submitting separate registration forms:
Please this page Mary Koch (203) 926-9453 fold, tape mail (see other side)
TXC-04011-MB September 1995
TranSwitch VLSI: Powering Communication Innovation
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First Class Postage Required
TranSwitch Corporation Attention: Mary Koch Progress Drive Shelton, 06484 U.S.A.
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Please complete registration form this back cover sheet, mail wish receive updated documentation this TranSwitch product becomes available.
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1.544 Mbit/s VT1.5/TU-11 Async Mapper-Desync TXC-04011 DATA SHEET Prel

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