Data Sheet 08.97 7274 Revision History: Current Version: 08.

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Data Sheet 08.97 7274 Revision History: Current Version: 08.

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Channel ADPCM Controller Quad ADPCM 7274 Version 7274 Version
Data Sheet 08.97
7274 Revision History:
Current Version: 08.97
Previous Version: Preliminary Data Sheet 01.97 Page Page previous Version) Version) Subjects (major changes since last revision)
List figures (new) Note added (The last bits Input leakage current (Values added neg. temperature range, XTAL1) Input/Output voltage (addapted levels, test conditions added) Frame strobe delay tFSD (new) clock delay tBCd (changed) DSYNC delay tDSYNC (new)
Edition 08.97 This edition realized using software system FrameMaker®. Published Siemens 81541 Siemens 08.97. Rights Reserved. Attention please! patents other rights third parties concerned, liability only assumed components, applications, processes circuits implemented within components assemblies. information describes type component shall considered assured characteristics. Terms delivery rights change design reserved. questions technology, delivery prices please contact Semiconductor Group Offices Germany Siemens Companies Representatives worldwide (see address list). technical requirements components contain dangerous substances. information types question please contact your nearest Siemens Office, Semiconductor Group. Siemens approved CECC manufacturer. Packing Please recycling operators known you. also help touch with your nearest sales office. agreement will take packing material back, sorted. must bear costs transport. packing material that returned unsorted which obliged accept, shall have invoice costs incurred. Components used life-support devices systems must expressly authorized such purpose! Critical components1 Semiconductor Group Siemens only used life-support devices systems2 with express written approval Semiconductor Group Siemens critical component component used life-support device system whose failure reasonably expected cause failure that life-support device system, affect safety effectiveness that device system. Life support devices systems intended implanted human body, support and/or maintain sustain human life. they fail, reasonable assume that health user endan-
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1.6.1 1.6.2 1.6.3 1.6.4 2.4.1 2.4.2 2.4.2.1 2.4.2.2 2.10 2.10.1 3.10 3.11 3.12 3.13 3.14
Overview Features Logic Symbol Configuration Definitions Functions Functional Block Diagram System Integration PCM-4 System PCM-4 System using Standard Codec Filters PCM-8 System DECT Linecard Functional Description ADPCM Coder Interface Propagation Delay Echosuppression Speech Detection Echosuppression Speech Detector Noise Monitor Speech Detection Preprocessing Fax/Modem Detection Artificial Echo Loss Congestion Tone Generator Frame Strobe Outputs Serial Microcontroller Interface Boundary Scan Test Controller Controller Register Location Description Configuration Register (CR) Compression Rate Register (CRR) Uncompressed Time slot Registers (UT0 UT3) Decoder Position Register (DPP) Time Slots Register (MSB) Echo Suppressor Enable Register (ESE) Additional Feature Register (ADF) Additional Feature Register (ADF2) Fax/Modem Detection Enable Register (FDE) Modem Detection Status Register (FDS) Status Register (DST) Command Register (COM) Address Register (ADR) Data High Byte Register (DATAH)
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3.15 3.16 3.16.1 3.16.2 3.16.3 3.16.4 3.16.5 3.16.6 3.16.7 4.4.1 4.4.2 4.4.3 4.4.4 6.3.1 6.3.2
Data Byte Register (DATAL) Loactions Programming Cells Extended Features Congestion Tone Generator Tone Filter Artificial Echo Loss Gain (AEL_GAIN) Speech Detector Noise Monitor Echo Suppressor Fax/Modem Detection Electrical Characteristics Absolute Maximum Ratings Characteristics Capacitances Characteristics Interface Timing Serial Microcontroller Interface Timing Boundary Scan Timing Timing Package Outlines Appendix Proposed Default Values Locations Working Sheet Register Programming Development Tools STSI 4000 PCM-4 Userboard SIPB 7274 Quad ADPCM
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Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure
Logic Symbol Configuration (top view) Block Diagram Integration PCM-4 System Integration PCM-4 System with Automatic Modem Handling Integration PCM-4 Systems using Standard Codec Filters Integration PCM-8 Systems Integration DECT Linecard Encoder Block Diagram Decoder Block Diagram Allocation Data Slots within Slots Decoder Encoder Timing PCM-4 System Decoder Encoder Timing PCM-8 System Echo Sources DECT System Echosuppressor Functionality Echosuppression Compressed Side (DECT System) Echosuppresion Uncompressed Side (PCM-4/8 System). Speech Detector Mechanism Speech Detector Parameters Speech Detection Principle Fax/Modem Tone Detection Frame Strobe Output: Short Frame Timing, Single Clock Mode Frame Strobe Output: Short Frame Timing, Double Clock Mode. Frame Strobe Output: Long Frame Timing, Single Clock Mode. Frame Strobe Output: Long Frame Timing, Double Clock Mode Microcontroller Interface Timing: Write Access Microcontroller Interface Timing: Read Access Waveforms Tests. Interface Timing Double Clocking Model Serial Interface Timing Boundary Scan Timing Clock Timing Working Sheet Register Programming STSI 4000 PCM4 Userboard (Euroset included Kit) SIPB 7274 Quad ADPCM
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Overview Overview
four channel ADPCM Controller 7274 (Quad ADPCM) features four independent full duplex Adaptive Differential Pulse Code Modulation voice coders with individually selectable compression down kbit/s specified CCITT Recommendation G.726. A-law, µ-law 16-bit linear operation provided. optional echosupression algorithm included well Artificial Echo loss insertion programmable tone generation. device optimized operation PCM-4 PCM-8 systems together with 2466 SICOFI-4-µC 2091 IEC-Q V5.x. internal FAX/Modem recognition allows simple allocation data rate needed modem transmission connection modems/data rate convertors 7110 ISAR. Quad ADPCM provides interfaces allowing free selection input output time slots register setting. bypass mode facilitates data over voice applications. Flexible applications supported connecting cost microcontroller serial processor interface. Indirect access provided controller interface. Additional frame synchronization signals each channel with selectable timing conditions allow direct connection standard codec filters. Quad ADPCM power consuming CMOS device. comes P-MQFP-44 package.
Semiconductor Group
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Channel ADPCM Controller Quad ADPCM
7274 7274
Version Features
CMOS
full duplex ADPCM Voice Coders 16/24/32/40 kbit/s compression rate CCITT G.726, G.721 compliant Compression rate individually programmable during operation Cascadable PCM-8 Systems Parameterizable Echosupression P-MQFP-44 Programmable tone generation A-Law, µ-Law linear operation Pprogrammable FAX/Modem-tone detection, compliant G.164 Optional Artificial Echo Loss compliant ETSI Stand-alone operation PCM-4 Systems without microcontroller A-law µ-law default strapping PCM-Interfaces 1.536, 2.048 4.096 providing time slots Frame Strobe Signals standard codec filters, long frame short frame timing Serial Microcontroller Interface DECT synchronization clock JTAG Boundary Scan compliant IEEE 1149.1 Sub-micron CMOS Technology P-MQFP-44 Package
Type 7274 7274
Semiconductor Group
Ordering Code Q67101-H6678 Q67101-H6893
Package P-MQFP-44 P-MQFP-44
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Overview Logic Symbol
Figure
Logic Symbol
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Overview (top view) Configuration
Figure
Configuration (top view)
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Overview Definitions Functions
Symbol Input Function Output Open Drain (OD) Power Supply Pins Supply Voltage +/-5 Ground
JTAG Boundary Scan Test Clock Test Mode Select, internal pullup Test Data Input, internal pullup Test Data Output
Interface DINC DINU (OD) (OD) Data Compressed. Input ADPCM data synchronous clock Data Compressed. Output ADPCM data synchronous clock. Open drain. Data Uncompressed. Input data synchronous clock Data Uncompressed. Output data synchronous clock. Open drain. Frame synchronization clock. start time slot marked. Data clock. Clock range 1.536 4.096 MHz. clock. Half clock output this pin.
Note: This included boundary scan path.
Transmit Control Compressed, active. during slots data transmitted DOC. Transmit Control Uncompressed, active. during slots data transmitted DOU.
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Overview
Symbol Input Function Output Open Drain (OD) Microcontroller Interface CCLK CDIN Chip Select enable read write data, active low. Connect used. Controller data clock. Shifts data from device. Connect used. Controller Data CCLK determines data rate. Connect used. Controller Data Out. CCLK determines data rate. CDOUT "high data transmitted. Interrupt. active, open drain.
CDOUT (OD)
Miscellaneous Function Pins Master Clock. crystal clock output master clock another Quad ADPCM. signal enabled setting ADF2:MCE.
Note: This included boundary scan path.
Frame Sync High during time uncompressed data channel active bus. Frame Sync High during time uncompressed data channel active bus. Frame Sync High during time uncompressed data channel active bus. Frame Sync High during time uncompressed data channel active bus. Select A-law (ALAW high) µ-law (ALAW low) default setting after reset.
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ALAW
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Overview Miscellaneous Function Pins (cont'd) XTAL1 XTAL2 Master Reset, active. Crystal 20.48 crystal 20.48 clock signal connected. Crystal Out. 20.48 crystal connected. Leave open, crystal connected. DECT Sync. Output Input DECT master clock. Power Down disables holds operation channels Also disables data input output compressed side well DECT-sync generation. Power down disables holds operation channels Disables Congestion tone generator. Test pins. Used production testing only. connect.
DSYNC
TEST0. TEST7
TMEN
Test pin. Used production testing only. Active low. Internal pullup. connect.
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Overview Functional Block Diagram
Figure
Block Diagram
cores contain ADPCM coders each. compressed data handled tone generator resides Hence, disabled (pin high), input/output compressed data four channels possible. disabled, tone generator provided.
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Overview 1.6.1 System Integration PCM-4 System
Figure gives general overview integration PCM-4 system. register Quad ADPCM default configuration. connection microcontroller necessary. interface working with double data clock 1.536 coming from IEC-Q V5.x. This corresponds number time slots IOMchannels respectively. DINU DINC pins tied together well pins. This way, busses using same physical lines. IEC-Q NT-TE-1536 mode side COT-1536 mode side. uses slots There, Quad ADPCM reads writes compressed data. takes uncompressed data from time slots (see figure below, most left timeslot being slot SICOFI-4-µC programmed read/write these time slots. Note that IEC-Q uses IOM-2 interface where control information such C/Icommands Monitor messages exchanged time slots These time slots should consequently used exchange compressed uncompressed data.
Figure
Integration PCM-4 System
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Overview SICOFI-4-µC uses 1.536 clock internally generate masterclock. IEC-Q also issues 7.68 clock. This clock used microcontroller clock. IEC-Q V5.x allows program this clock rate between 0.92 7.68 MHz. automatic modem detection enables 7274 Quad ADPCM monitor compressed uncompressed side highway four channels parallel. This allows dynamically allocate data rate needed transmission high speed modem signals hand over control 7110 ISAR. Quad ADPCM detects fax/modem tone. microcontroller then sets compressed output according channel highly impedant state. 7110 ISAR takes over uncompressed receive data, performs modem operation data rate adaptation passes output data onto timeslot left open Quad ADPCM.
Figure
Integration PCM-4 System with Automatic Modem Handling
7110 ISAR provide 14.4 kbit/s modem transmission four channels. ISAR occupies leaving direct 14.4 kbit/s modem transmission. ISAR used operation expected four channels simultaneously.
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Overview 1.6.2 PCM-4 System using Standard Codec Filters
Quad ADPCM provides additional frame sync signals each channel. case data clock rate 1.536 MHz, generated with additional PLL. microcontroller selects appropriate timing conditions frame sync pulses. Short frame long frame mode provided. additional clock (BCL) allows easily connect single clock mode devices (e.g. CODECs) double clock mode devices (e.g. IEC-Q V5.x) well.
Figure
Integration PCM-4 Systems using Standard Codec Filters
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Overview 1.6.3 PCM-8 System
Figure
Integration PCM-8 Systems
Figure depicts integration PCM-8 system. interface working with double data clock 1.536 coming from IEC-Q V5.x. This corresponds number time slots IOM-channels respectively. IEC-Q NTTE-1536 mode side COT-1536 mode side. uses slots There, Quad ADPCM read write compressed data. They take uncompressed data from time slots (time slots count 11). SICOFI-4-µC programmed read/write these time slots. DINU DINC pins both Quad ADPCM tied together well pins. This way, busses Quad ADPCM using same physical lines. This possible proper time slot assignment. Note that IEC-Q uses IOM-2 interface where control information such C/Icommands Monitor messages exchanged time slots These slots should used compressed uncompressed data transfer. additional clock generator data clock necessary because 1.536 clock issued IEC-Q. IEC-Q also issues 7.68 clock which used microcontroller clock.
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Overview 1.6.4 DECT Linecard
Figure
Integration DECT Linecard
Figure presents integration linecard featuring DECT basestations. Quad ADPCM features flexible access arbitrary time slots highway it's interfaces. Quad ADPCM provides DECT synchronization clock either period. other Quad ADPCM receive this clock synchronized reprogramming e.g. data rates other registers. Together with 2096 OCTAT-P 24902/PEB 24911 Quad IEC-Q layer-1 transceivers, seamless handover possible linecard.
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Functional Description Functional Description ADPCM Coder
Quad ADPCM contains cores each implementing algorithms channels. supports full duplex ADPCM coding encoding specified CCITT recommendation G.726. A-law, µ-law linear operation selectable separately each channel setting UTi-register corresponding channel synchronous coding adjustment (SCA) unit decoder (see fig. prevents cumulative distortion occurring tandem operation, e.g. ADPCM ADPCM. optionally disabled improve signal/noise ratio when going from analog coding. Figure shows structure encoder given CCITT rec. G.726.
Figure
Encoder Block Diagram
Figure illustrates structure decoder.
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Functional Description
Figure Decoder Block Diagram Interface
Quad ADPCM allows most flexible interface. select time slots four uncompressed data streams well beginning compressed data stream register programming. There data-in line uncompressed data (pin DINU) data-in line compressed data (pin DINC) well dataout lines uncompressed data compressed data respectively (pins DOC). time slots both data streams overlap, both outputs both inputs electrically connected. Four time slots assigned four uncompressed data streams. They select input well output uncompressed data. uncompressed channel assignments controlled registers being channel number 0.3). case single clock mode MSB:UTMi used extend programming range maximum time slots. compressed data start bit. four compressed data streams tied together. compressed data channel comes first, then compressed data channel etc. register, number first compressed data selected. Depending compression rate, two, three, four five compressed bits will placed positions n+1, etc. first compressed second channel directly follows last first channel. first third channel directly follows last second channel etc. compression rate changed positions higher channels change well. case bitwise bypassing combination compression bypassing same principle applies. Figure illustrates relation frame sync signal pin, numbering bits frame beginning slots. Double data clock mode
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Functional Description assumed. user take care 'overlap' data multiple allocation channels same timeslots.
Figure Allocation Data Slots within Slots rising edge marks start frame. Each slot consists bits. beginning compressed data every frame given figure compressed channel assignment programmed register DPP. case single clock mode 4.096 only first bits selected start position. Care taken proper programming registers overlap data interfaces shall work highway. Input data output data always allocated same time slots. Start execution time programs such that coding decoding performed single frame slot assignment properly chosen. That default time slot assignment given figure well PCM-8 system shown figure propagation delay through ADPCM channels system (coding side, decoding other side) single frame. Propagation Delay
begin decoder encoder program tied frame clock FSC. optimized provide frame group delay complete encoding/decoding operation four channels time slots uncompressed data compressed data assigned properly. Figure gives location decoder start time encoder start time frame. uncompressed input data read time slots before encoder starts, available compressed output immediately after encoder stops. compressed input data read before decoder starts, uncompressed data available uncompressed output immediately after decoder stops. example figure uncompressed data read time slots before encoder starts. compressed during time slot time slots next frame.
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Functional Description compressed data read time slots before decoder starts. decoded during time slots during time slots same frame been read. Note that decoding takes longer than encoding. Hence, with default time slot assignment described section1.6.1, delay compress data frame uncompressed data available same frame.
Figure Decoder Encoder Timing PCM-4 System Quad ADPCM devices together PCM-8 system clock 1.536 MHz, there enough time slots uncompressed data left before start encoder. Therefore, encoder start position shifted begin frame setting ADF2:ENS '1'. this done Quad ADPCM, timing given figure results.
Figure Decoder Encoder Timing PCM-8 System
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Functional Description uncompressed data slots processed during time slot encoder device passed slot next frame. uncompressed data slots processed during slot next frame slot Again, channels have frame delay complete encoding/decoding operation. time slots assigned proposed above, delay more channels frames. clock rate higher than 1.536 more than time slots available. this case, there several ways assign time slots appropriately minimum delay. Note however that encoding time then longer than time slot decoding takes more than time slots. exact start decoder encoder different clock rates given tables below: Decoder start after slot number ADF2:DCLK ADF2:ENS= ADF2:ENS= ADF2:DCLK
Decoder after slot number 1536 ADF2:ENS= ADF2:ENS= 2048 ADF2:ENS= ADF2:ENS= 4096 ADF2:ENS= ADF2:ENS= ADF2:DCLK ADF2:DCLK ADF2:DCLK ADF2:DCLK ADF2:DCLK ADF2:DCLK
Encoder start after slot number 1536 ADF2:ENS= ADF2:ENS=
Semiconductor Group
ADF2:DCLK
ADF2:DCLK
start next frame start next frame
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Functional Description 2048 ADF2:ENS= ADF2:ENS= 4096 ADF2:ENS= ADF2:ENS= ADF2:DCLK ADF2:DCLK ADF2:DCLK ADF2:DCLK
Encoder after slot number 1536 ADF2:ENS= ADF2:ENS= 2048 ADF2:ENS= ADF2:ENS= 4096 ADF2:ENS= ADF2:ENS= ADF2:DCLK next frame ADF2:DCLK start next frame next frame ADF2:DCLK ADF2:DCLK next frame ADF2:DCLK next frame ADF2:DCLK
start next frame start next frame
Note: ADF2:ENS '0', issued DOC. ADF2:ENS '1', only issued DOC.
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Functional Description Echosuppression Speech Detection
7274 Quad ADPCM very flexible echosuppressor integrated. addition direction echosuppressor (attenuation compressed uncompressed side) parameters required optimize speech detection signal suppression also fully programmable. parameters part need reprogrammed after every reset. reset settings exist parameters. Refer section 3.16.1 procedure programming cells. 2.4.1 Echosuppression
account echos from side with delay echosuppressor implemented algorithms 7274. Echos mainly result when converting digital speech/data information (e.g. from interface, interface DECT interface) into analog tip/ring signals. Depending origin echo delay echo varies. Figure shows typical sources echos DECT system connected public exchange with analog digital trunk lines.
delay
Central Office
Near Echo delay
Central Office
analog subscriber
Figure Echo Sources DECT System echos unpredictable with respect duration delaytime because these parameters change with each communication connection established. Unlike near echos where these parameters only vary within limited bandwidth echos cancelled. suppression implemented instead consists gain stage which adds additional attenuation receive path (typically while speech recognized transmit path receive power level does exceed specified limit. receive power level limit guarantees that despite echosuppression participant other side line switch echosuppression speaking loud.
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Functional Description signal flow path with programmable echosuppression parameters illustrated figure programming parameters echosuppression described section 3.16.6.
Power Level
Power Level
ES_RxPL
Time
Power Estimator Speech Detection Suppression on/off
tPLdly
Power Level been exceeded
Attenuation
ES_ATT tdly
Time
Figure Echosuppressor Functionality echosuppressor switched with time constant without delay when estimated receive power level above value programmed ES_RxPL during time constant tPLdly. figures show 7274 allows also select direction suppression. DECT systems typically suppression would performed compressed side (figure 16). This ensures that local echos which would noticed speaker side (handy) delay attenuated.
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Functional Description
Basestation
Linecard
64kbps
32kbps
32kbps
ADPCM
64kbps
CODEC
Figure Echosuppression Compressed Side (DECT System) non-DECT systems like PCM-4 applications (i.e. without delay order milliseconds) echo from side must attenuated. this reason uncompressed 7274 output side receive signal containing echo) will suppressed soon speech detected transmit path uncompressed input 7274). This guarantees improved speech quality side Refer figure details.
64kbps
32kbps
CODEC
64kbps
ADPCM
32kbps
Figure Echosuppresion Uncompressed Side (PCM-4/8 System)
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Functional Description Echosuppressor Related Parameters parameters used conjunction with echsuppressor located RAM. summery given table below. detailed description please refer section 3.16.6. Parameter ES_ATT Description Echosuppressor Attenuation Determines level attenuation receive path speech detected transmit path estimation receive power below specified limit. Echosuppressor Delay Specifies delay time tdly between disappearance speech (speechdetector: speech) start rise time echosuppressor. Echosuppressor Rise Time Specifies time which attenuation increased from programmed value Echosuppressor Fall Time Specifies time which attenuation decreased from programmed value speech detected transmit path. Echosuppressor Receive Power Level Delay This coefficient time constant tPLdly power estimator receive signal. Echosuppressor Receive Power Level This parameter specifies power level threshold receive direction. signal receive path exceeds programmed value attenuation added echsuppressor will switched after tPLdly elapsed. This guarantees that despite echosuppression subscriber other line switch echosuppression speaking loud.
ES_DLY
ES_RISE
ES_FALL
ES_PLdly
ES_RxPL
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Functional Description 2.4.2 Speech Detector
Basically speech detector makes burst characteristic speech. That means, every fast change signal amplitude compared average signal level recognized speech. This done averaging input signal with lowpass filter (noise monitor lowpass) comparing output this lowpass with input signal itself. shown figure speech detector mechanism composed three seperate blocks: Power estimator receive path Speech detection preprocessing transmit path Noise monitor transmit path
Speech Detector
Noise monitor
Noise Monitor Offset
Power estimate
ES_RxPL ES_PLdly
Speech Detector Preprocessing Logarithmic amplifier
SD_LIM
NM_OFF
Lowpass filter
SD_LP
SD_LP
Peak detector
SD_PDS SD_PDN
Noise Monitor Lowpass filter NM_LP
NM_LPlim NM_LPfade NM_LPrise
Speech/ speech
ON/OFF Echosuppressor
Figure Speech Detector Mechanism speech detection performed components which offer programmable parameters. These components logarithmic amplifier, speech detection lowpass filter, peak detector noise monitor. They have following functions: Logarithmic Amplifier Compression signal area incoming transmit signal. Speech Detection Lowpass Filter Spike reduction incoming signal.
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Functional Description Peak Detector Improvement speech detection offering different time constants detected non-detected speech. Noise Monitor Discriminates between speech noise. noise monitor comprises lowpass filter programmable offset. detailed description refer section 2.4.2.1. Figure gives illustration speech detector parameters.
3.14
Speech
NM_OFF Adaptive range controlled noise monitor
NM_LPlim
SD_LIM
speech
Figure Speech Detector Parameters 2.4.2.1 Noise Monitor
tasks noise monitor differentiate voice signals from background noise, even exceeds voice level, recognize voice signals without delay. Therefore Noise Monitor consists Noise Monitor Lowpass Filter (NM_LP) Noise Monitor Offset (NM_OFF) separate branches. Basically works burst-characteristic speech: voice signals consist short peaks with high power (bursts). contrast, background noise regarded approximately stationary from average power.
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Functional Description noise monitor able discriminate between speech noise. consists noise monitor lowpass filter NM_LP offset NM_OFF. Basically works burst-characteristic speech: Voice signals consist short peaks with high power (bursts). Background noise regarded approximately stationary from averaged power. task noise monitor recognize voice signals without delay recognize background noise. Since only difference between average signal level instant signal leads speech recognition, influence noise decision cancelled, even noise level exceeds voice level. figure illustration programmable parameters Noise Monitor. Noise Monitor Lowpass Filter noise monitor lowpass filter NM_LP provides different time constants noise (nondetected speech) speech. determines average noise reference level. case background noise level output lowpass filter approximately level input. offset NM_OFF comparator remains initial state. case speech difference signal level between offset branch lowpass branch comparator increases comparator output changes state. speech bursts digital signals arriving comparator offset branch change faster than those lowpass branch that comparator output changes polarity. Hence logical levels generated speech noise. small fade constant NM_LPfade enables fast discharging lowpass after speech recognition. recommended choose large rising constant NM_LPrise that speech itself charges lowpass very slowly. Generally recommended program infinite rise time NM_LPrise because that case noise approximation disabled. maximum value lowpass limited programmable value NM_LPlim detect continuous tones speech activate echosuppressor. Offset offset stage NM_OFF represents level threshold between signal averaged noise. this parameter reference level programmed percentage full speech signal.
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Functional Description Noise Monitor Related Parameters parameters used conjunction with noise monitor located RAM. summery given table below. detailed description please refer section 3.16.5. Parameter NM_LPlim Description Noise Monitor Lowpass Limit This value limits charging lowpass filter. continous input signal, that detected speech, above this limit. Noise Monitor Lowpass Fade Constant Enables fast discharge noise monitor lowpass after speech recognition. Noise Monitor Lowpass Rise Time Determines time noise monitor lowpass charged after speech recognized. Noise Monitor Offset Specifies level threshold between signal noise. Speech bursts NM_OFF above average signal recognized. Speech Detection Preprocessing
NM_LPfade
NM_LPrise
NM_OFF
2.4.2.2
described preceding chapter, Noise Monitor able discriminate between speech noise. very short speech pauses e.g. between words, however, changes immediately non-speech, which equal noise. Therefore peak detection required front Noise Monitor. Peak detector peak detector bridges very short speech pauses during monologue that respective time constant long. Furthermore, speech bursts stored that sure speech detection guaranteed. speech recognized noise monitor lowpass must charged very fast averaged noise level. Additionally noise edges smoothed. Therefore time constants necessary have programmed separately: SD_PDS speech SD_PDN noise (background) signals. Hence 'speech mode' detected faster kept longer than speech mode' that smaller breaks cause switching. Also noise smoothened.
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Functional Description Speech Detection Lowpass Filter peak detector very sensitive spikes. lowpass SD_LP filters receive signal containing noise that main spikes eliminated. programmable time constant SD_LP possible defuse high-energy sibilants noise edges. Logarithmic Amplifier compress speech signals their amplitudes ease detection speech, signals have companded logarithmically. Hereby, speech detector should influenced system noise which always present should discriminate between speech background noise. limitation logarithmic amplifier programmed parameter SD_LIM. SD_LIM related maximum level. signal exceeding limitation defined SD_LIM getting amplified logarithmically, while very smooth system noise below neglected. should level minimum system noise which always existing. Principle Speech Detection diagrams figure graphically describe inputs outputs speech detector blocks. result completely identical implementation Quad ADPCM echosupressor helps understand function speech detector.
input signal
peak detector
speech speech (noise)
Figure Speech Detection Principle
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Functional Description first diagram shows analog representation input signal, since this signal form more convenient readers understanding signal processing. ADPCM circuits signal delivered speech detector digitally. peak detector output envelope input signal, where short pauses bridged. next diagram explains function noise monitor with branches (noise monitor offset input noise monitor lowpass filter). lower diagram result signal processing speech detector shown. Speech Detector Related Parameters parameters used conjunction with speech detection located RAM. summery given table below. detailed description please refer section 3.16.5. Parameter SD_LIM Description Speech Detection Limit Input signals below level determined SD_LIM processed speech detector. Usually SD_LIM programmed threshold that above noise floor system. Speech Detection Lowpass This time constant determines main spikes being eliminated. Note that SD_LP large response time speechdetector long. Speech Detection Peak Detector 'Speech' This coefficient specifies time constant speech signals. large value should programmed avoid quick charging during speech. Speech Detection Peak Detector 'Noise' This coefficient specifies time constant noise signals. Small time constants allow quick adaptation changes noise level.
SD_LP
SD_PDS
SP_PDN
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Functional Description Fax/Modem Detection
fax/modem tone detection implemented each channel Quad ADPCM. Typically tone used indicate remote side that modem requesting connection. guarantee reliable detection this tone fully programmable parameters provided. These parameters allow adjustment individual requirements. soon tone which fullfills programmed conditions detected, interrupt will generated (provided interrupt generation enabled with register). register source interrupt read. Quad ADPCM indicates successfull detection seperately compressed uncompressed side with '1'. Reading register will automatically reset interrupt line (INT high). Every transition bits register generates interrupt. transition will however occure only after device detected that information sent more (power monitoring). stopping tone will cause transition. Optionally each channel register individually reset '0'. This reset performed programming corresponding FDE:EMi (resets detection bits channel uncompressed compressed side '0'). After reprogramming FDE:EMi next interrupt will generated soon fax/modem tone criterias fullfilled again.
Note: default values available after reset. parameters need programmed after reset.
operation fax/modem detection illustrated figure reliable tone detection combination frequency criteria time criteria must met.
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Functional Description
Bandpass filter
MD_BW
Level detection
Power estimate
Level detection
MD_FREQ
MD_LIM
MD_LP
MD_LEV
Timer
MD_FREQ
MD_BW
Level detection
Power estimate
Level detection
MD_DIFF
MD_Thold
(modem detected)
MD_LIM
MD_LP
Notch filter
Bandpass filter
MD_BW
Level detection
Power estimate
Level detection
MD_FREQ
MD_LIM
MD_LP
MD_LEV
Timer MD_Thold
MD_FREQ
MD_BW
Level detection
Power estimate
Level detection
MD_DIFF
MD_LIM
MD_LP
Notch filter
Figure Fax/Modem Tone Detection upper branches Tx-path contain bandpass filter detect modem tones. lower branches contain notch filter filter modem signal that output signals these branches represent power remaining band. speech signals output signal lower branch will large compared output upper path vice versa modem signals. center frequency bandwidth modem filters programmed using parameters MD_FREQ MD_BW (bandpass notch filter). filter outputs averaged using lowpass filter with parameter MD_LP that power estimate signals obtained. minimum modem level which detected specified CCITT standard G.164. respective limit value programmed using parameter MD_LIM. difference value MD_DIFF implemented modem signal detection transmit path. difference signal energy modem frequency band modem frequency band larger than MD_DIFF modem signal detected.
Semiconductor Group 08.97
7274 7274
Functional Description large values MD_DIFF erraneous fax/modem detection speech input signals avoided. other hand modem signals with small frequency deviations additional noise detected anymore. Smaller values MD_DIFF allow fax/modem detection noisy environment. Protection against erraneous fax/modem detection speech input signals however reduced. timer (MD_Thold)has been implemented eliminate influence transients. Adjustment should such that modem tones minimum duration duration detected required CCITT specification G.164. Fax/Modem Detection Related Parameters parameters used conjunction with fax/modem detection located RAM. summery given table below. detailed description please refer section 3.16.7. Parameter MD_FREQ Description Fax/Modem Detection Center Frequency Should adjusted frequency modem signal detected (2.1 tones). Fax/Modem Detection Bandwidth Determines bandwidth modem filter. Fax/Modem Detection Lowpass Specifies time constant power estimator. Fax/Modem Detection Break Time Tone breaks less than specified time ignored. Fax/Modem Detection Hold Time Specifies time detection conditions have valid fax/modem detection. Fax/Modem Detection Difference This parameter specifies difference outputs bandpass notch filter have exceed. difference signal energy modem frequency band modem frequency band larger than MD_DIFF modem signal detected. Fax/Modem Detection Level Determines threshold below which noise signals ignored. Fax/Modem Detection Limit level programmed MD_LIM compared with output modem filter. level modem signal above MD_LIM modem detection activated.
08.97
MD_BW MD_LP MD_Tbreak MD_Thold
MD_DIFF
MD_LEV
MD_LIM
Semiconductor Group
7274 7274
Functional Description MD_LEVE MD_TIME parameter specifies level fax/modem detection. parameter specifies timing conditions fax/modem detection. Artificial Echo Loss
Artificial Echo Loss (AEL) added receive path. gain programmed from direction opposite direction echo suppression register. enabled each channel independently setting register bits '1'. Artificial Echo Loss Related Parameters parameter used conjunction with located RAM. summery given table below. detailed description please refer section 3.16.4 Parameter AEL_GAIN Description Artificial Echo Loss Gain Determines level added receive path.
Semiconductor Group
08.97
7274 7274
Functional Description Congestion Tone Generator
programmable tone with amplitude between frequency between uncompressed data output instead data. ADPCM data evaluated congestion tone generator enabled. tone used create 'line occupied' signal already terminal side wireless local loop system case interface occupied. tone enabled each channel independently setting register bits '1'. It's modulation done enabling disabling appropriate rate. enabled tone generation. Congestion Tone Generator Related Parameters parameters used conjunction with congestion tone generator located RAM. summery given table below. detailed description please refer section 3.16.2. Parameter CT_FREQ CT_LEV CT_GAIN Description Congestion Tone Frequency Determines level Congestion Tone Specifies frequency gain Frame Strobe Outputs
application pair gain systems together with standard codec filters supported with Frame Strobe output channel pins being channel number). There different timings available, referred short frame long frame, respectively. selection done with configuration register CR:FST selects short frame timing. CR:FST selects long frame timing. CR:FSEN '0', four outputs tied VSS. Figures give timings short framing. Figure illustrate long frame timings.
Semiconductor Group
08.97
7274 7274
Functional Description short frame timings first starts with falling edge FSi. frame strobe signal high during period single clock mode (ADF2:DCLK '1') well double clock mode (ADF2:DCLK '0').
DOUT
shofr_si
Figure Frame Strobe Output: Short Frame Timing, Single Clock Mode
DOUT
shofr_db
Figure Frame Strobe Output: Short Frame Timing, Double Clock Mode double clock mode, signal used recieving device determine when data shifted
Semiconductor Group
08.97
7274 7274
Functional Description long frame timing time slots nominally coincident with rising edge FSi. frame strobe signal high during (single clock mode), (double clock mode) respectively, periods marking complete time slot.
DOUT
lonfr_si
Figure Frame Strobe Output: Long Frame Timing, Single Clock Mode
Figure Frame Strobe Output: Long Frame Timing, Double Clock Mode double clock mode, signal used recieving device determine when data shifted
Semiconductor Group
08.97
7274 7274
Functional Description Serial Microcontroller Interface
serial microcontroller interface consists four lines: CCLK, CDIN CDOUT. used start serial access registers. Following falling edge first eight bits received CDIN specify command. following data byte stored selected register with rising edge first received specifies read (bit '0') command write command (bit '1'). following five bits give register address (MSB first).
CCLK CDIN CDOUT
Control
Data Byte High
Figure Microcontroller Interface Timing: Write Access
CCLK CDIN CDOUT
ontrol igh"Z" IdentificationC ataB
Figure Microcontroller Interface Timing: Read Access read access ID-Byte (COH) issued before data byte shown figure maximum data clock frequency applied CCLK 7.68 MHz. CCLK pause between control read/write byte(s). These breaks arbitrarly long missing all.
Semiconductor Group
08.97
7274 7274
Functional Description Data bits CDIN latched device with rising edge CCLK. bits CDOUT line with falling edge CCLK, they therfore latched with rising edge. Indirect Access provided register, register, DATA registers register. DATA registers used either read data from write data RAM. read access other registers only used control register contents. Data into registers arbitrary time valid with next rising edge frame clock FSC. DSYNC input, data valid next rising edge frame after next falling edge clock DSYNC. 2.10 Boundary Scan Test Controller
Quad ADPCM provides boundary scan support cost effective board testing. consists -Complete boundary scan signals (pins) according IEEE Std. 1149.1 specification -Test access port controller (TAP) -Four dedicated pins (TCK, TMS, TDI, TDO) -One 32-bit IDCODE register pins except power supply pins, 'not connected' pins BCL, MCL, TDI, TDO, TCK, TMS, XTAL1 XTAL2 included boundary scan. When controller appropriate mode data shifted into boundary scan pins TDI/TDO using clock TCK. clock rate MHz. Depending functionality one, three boundary scan cells provided.
Note: There several pins, which chip test used pins. Please refer section whether these pins inputs outputs. However, they included boundary scan pins with three scan cells.
Type Input Output Number Boundary Scan Cells Usage input output, enable input, output, enable
Semiconductor Group
08.97
7274 7274
Functional Description pins included following sequence boundary scan: Boundary Scan Number Number Name Type Number Scan Cells
DSYNC DINU ALAW CDOUT CDIN CCLK DINC
Semiconductor Group
08.97
7274 7274
Functional Description 2.10.1 Controller
Test Access Port (TAP) controller implements state machine defined JTAG standard IEEE Std. 1149.1. Transitions cause controller perform state change. Following standard definition instructions executable. controller instructions: Code Instruction EXTEST INTEST SAMPLE/PRELOAD IDCODE CLAMP HIGHZQ BYPASS Function External testing Internal testing Snap-shot testing Reading code Reading outputs Z-State boundary scan output pins Bypass operation
EXTEST used examine board interconnections. When controller state "update DR", output pins updated with falling edge TCK. When entered state "capture levels input pins latched with rising edge TCK. in/out shifting scan vectors typically done using instruction SAMPLE/PRELOAD. INTEST supports internal chip testing. When controller state "update DR", inputs updated internally with falling edge TCK. When entered state "capture levels outputs latched with rising edge TCK. in/out shifting scan vectors typically done using instruction SAMPLE/PRELOAD. Note: (INTEST) default value instruction register. SAMPLE/PRELOAD provides snap-shot level during normal operation used preload (TDI) shift (TDO) boundary scan with test vector. Both activities transparent system functionality. BYPASS, entering shifted after clock cycle, e.g. skip testing selected printed circuit board. HIGHZQ sets pins included boundary scan path into high impedance state. this state, in-circuit test system drive signals onto these pins.
Semiconductor Group
08.97
7274 7274
Register Location Description CLAMP allows state signals included boundary scan driven from Quad ADPCM determined from boundary scan register while bypass register selected serial path between TDO. These signals will change while CLAMP selected. IDCODE serially reads 32-bit identification register TDO. contains version number bits), device code bits) manufacturer code bits). fixed "1". Version 0001 Device Code 0000 0000 0011 0011 Manufacturer Code 0000 1000 Output
Note: state 'test logic reset' code '011' loaded into instruction code register.
Register Location Description
Operational modes register programming. default state registers after reset such that operation PCM-4 system possible without access microcontroller Quad ADPCM. A-law µ-law operation then strapping. registers except register read write type. These used control register contents read data DATAL DATAH registers. address register summary given following table. Registers with addresses accessible user. They used test purposes only.
Note: Defaults registers with default values given depend setting ALAW pin. ALAW low: left reset value valid. ALAW high: right rest value valid.
Semiconductor Group
08.97
7274 7274
Register Location Description Table Register Summary Reset value (hex)
Description Refer page
Addres Register (hex) Name
ADF2 DATAH DATAL
Uncompressed Timeslot channel Uncompressed Timeslot channel
Uncompressed Timeslot channel Uncompressed Timeslot channel time slots
Compression Rate Register1) Decoding Position1) Additional Features Register Additional Features Register Configuration Register2) Echosuppressor enable Detection Enable Register Detection Status Register Status Register3) Command Register Address block Data Register, high byte Data Register, byte
change this register becomes effective only after frames change this register becomes effective next frame write access user
Semiconductor Group
08.97
7274 7274
Register Location Description Configuration Register (CR)
Configuration Register selects general setting valid four channels.
FSEN MCLK1 MCLK0
FSEN
Frame Strobe Enable enable frame strobes pins FS3.FS0 pins Frame Synchronization Type selects long frame selects short frame Master Clock selection frequency must disclosed device proper operation given table below:
MCLK1
MCLK1, MCLK0
MCLK0
Clock
1536 2048 4096 reserved
Oscillator Bypass bypasses internal oscillator crystal connected XTAL1 XTAL2 when crystal connected XTAL1 XTAL2 DECT Sync Mode Quad ADPCM provides DECT Synchronization clock either period period DSYNC pin. clock also into Quad ADPCM DSYNC programmed input. settings programmed given table below:
DS1,
Clock period DSYNC
DSYNC tied input
Semiconductor Group
08.97
7274 7274
Register Location Description DSYNC output, generates signal with time 62.5 falling edge this signal rising edge FSC. DSYNC input, contents registers with addresses stored with first rising edge after falling edge DSYNC pin. This allows synchronous adaption compression rate disabling/ enabling outputs devices system. DSYNC input, ADF2:SBE 'don't care'. signal starts frame enabled during frame Reset resets device it's default state. effect same applying 'low' clock cycles. Reset after cycles. Compression Rate Register (CRR)
Compression Rate Register selects compression rate each channel separately.
CR31 CR30 CR21 CR20 CR11 CR10 CR01 CR00
CR31, CR30 CR21, CR20 CR11, CR10 CR01, CR00
Compression Rate channel Compression Rate channel Compression Rate channel Compression Rate channel compression rates each channel according table below:
CRi1
CRi0
compression rate channel
kb/s kb/s kb/s kb/s
Semiconductor Group
08.97
7274 7274
Register Location Description UTi:M1 (bypass-mode, section 3.3), number bypassed most significant bits register given table below. MSBs un-compressed data passed compressed location.
CRi1
CRi0
number bypassed bits, channel UTi:M0
µ-Law
number bypassed bits, channel UTi:M0
a-law
CRi1 CRi0 internally encodes decodes data. Hence, features like echosuppression, etc. available.
Note:Due conversion given µ-Law, only a-law operation exact bypass operation possible.
Uncompressed Time slot Registers (UT0 UT3)
Uncompressed Time slot registers select operation mode channel together with time slot where uncompressed data taken from DINU DOU, respectively.
Time slot select time slot interface selected where uncompressed data taken from written respectively. maximum data rate 4.096 MHz, there single clock mode maximum time slots. slots given table below. setting registers must take into account available number time slots. part register: MSB:UTMi channel
Semiconductor Group
08.97
7274 7274
Register Location Description
MSB: UTMi
slot number
Compression Mode Selection A-law, µ-law, linear operation complete disable corresponding channel selected given below. linear case uncompressed data occupies time slots. Data taken from written slot defined next one. synchronous coding adjustment (SCA, figure disabled.
description
channel disabled Encoder 16-bit lin. ADPCM Decoder ADPCM 16-bit lin. disabled bypass register bypass register Encoder µ-law ADPCM Decoder ADPCM µ-law disabled Encoder A-law ADPCM Decoder ADPCM A-law; disabled Encoder µ-law ADPCM Decoder ADPCM µ-law enabled Encoder A-law ADPCM Decoder ADPCM A-law; enabled
mode
Powerdown Linear
Bypass, Dataover-voice Bypass, Dataover-voice without without
These modes ADPCM algorithm Powerdown Reset specified CCITT Rec. G.726 Bypass bits causes encoding decoding providing features AEL, echosuppression etc. Real bypass only with less than bit.
Semiconductor Group
08.97
7274 7274
Register Location Description
default after reset given table below. default time slots fixed while default compression depends state ALAW pin.
register
ALAW-pin
default after reset
Decoder Position Register (DPP)
Decoder PCM-position register selects frame where compressed data taken from DINC DOC, respectively. double clock mode, each frame consists more than bits, depending clock rate. binary content register gives number frame, where compressed data begins. clock mode there bits each frame. that case, assignment compressed data restricted first bits frame. compressed data tied together. register give location compressed data channel compressed data channel directly follows channel channel follows channel etc.
Note: lower frequency than 4.096 applied pin, setting register must take into account available number bits. Note: last bits frame must used start position compressed data.
Semiconductor Group
08.97
7274 7274
Register Location Description Time Slots Register (MSB)
register contains most significant bits time slots assignment uncompressed data. This register only necessary when single clock mode enabled (ADF2:DCLK '1'). this case, there time slots available. ADF2:DCLK '0', there only time slots available MSB:UTMi bits taken into account. also contains disable bits compressed uncompressed output. long '1', corresponding output time slot pins 'Z'-state allowing 7110 ISAR pass data onto this time slot.
UTM3 UTM2 UTM1 UTM0
UTM3
Uncompressed Time slot most corresponding channel
significant
(MSB)
Enable Output corresponding channel Disable Output corresponding channel resets ADPCM algorithm Echo Suppressor Enable Register (ESE)
register contains enable bits four echo suppressor algorithms direction suppressed echo. other echo suppressor parameters reside RAM. They indirectly programmed COM, DATA registers.
Disable Echosuppressor corresponding channel Enable Echosuppressor corresponding channel Direction suppressed echo corresponding channel echo from transmit path receive path uncompressed side suppressed echo from transmit path receive path compressed side suppressed.
Note:The direction opposite direction echosuppression.
Semiconductor Group
08.97
7274 7274
Register Location Description Additional Feature Register (ADF)
Additional Features register contains enable bits congestion tone generator.
Disables Artificial echo loss corresponding channel Enable Artificial echo loss corresponding channel Disable Congestion tone corresponding channel Enable Congestion tone corresponding channel Additional Feature Register (ADF2)
Additional Features register contains select double single clock mode clock select start time encoder algorithm.
Note: should changed during operation avoid cracking.
DCLK
DCLK
Data Clock Mode clock rate either equal data rate (single clock) twice data rate (double clock). selects double clock selects single clock ENcoder Start time when encoder algorithm starts according tables section 2.3.
Note:If ADF2:ENS '0', issued DOC. ADF2:ENS '1', only issued DOC.
Semiconductor Group
08.97
7274 7274
Register Location Description Synchronous Buffer enable DSYNC output (CR:DS1 contents registers with addresses stored with first rising edge after falling edge DSYNC pin. DSYNC output (CR:DS1 =1), contents registers with addresses stored with next rising edge pin. DSYNC input, don't care. contents registers with addresses stored with first rising edge after falling edge DSYNC pin. Master Clock Enable Enables output 20.48 crystal clock MCL. This clock used clocking other Quad ADPCMs. Disable master clock output MCL. Fax/Modem Detection Enable Register (FDE)
Fax/Modem Detection Enable Register contains enable bits fax/modem detection. enable low, corresponding bits (compressed uncompressed input) Fax/Modem Detection Status register will reset.
EAD3 EAD2 EAD1 EAD0
Enable Modem detection corresponding channel Disable Modem detection corresponding channel
EAD3
Enable Automatic Disable echosuppressor corresponding channel given G.164. Disables fax/modem detected. Disable automatic deactivation echosuppressor fax/modem detected.
Semiconductor Group
08.97
7274 7274
Register Location Description 3.10 Modem Detection Status Register (FDS)
FAX/Modem Detection Status register contains status FAX/Modem tone detection. tone detected, corresponding '1'. transition register causes interrupt pin. This interrupt reset after read register. reset register, corresponding register reset. then register again, detection mechanism ready next fax/modem detection. fax/modem transmission also resets corresponding creates interrupt.
Detection Uncompressed input corresponding channel Detection Compressed input corresponding channel Status Register (DST)
3.11
Status Register controls access DATAH DATAL registers microcontroller.
RDY2 RDY1
RDY2
completed processing current command from microcontroller. indicates that command from microcontroller completely processed completed processing current command from microcontroller. indicates that command from microcontroller completely processed
RDY1
Semiconductor Group
08.97
7274 7274
Register Location Description 3.12 Command Register (COM)
register provides access RAM. access both DSPs simultaneously possible with status bits command bits. selects read write access. status bits allows access RAM. command releases content DATA register DSP.
CMD2 CMD1
Read/Write read access write access deactivated activated frames later deactivated activated frames later indicates read write access microcontroller This automatically reset when read register. indicates read write access microcontroller This automatically reset when read register.
CMD2
CMD1
Note: only taken into account corresponding low. Setting high forces powerdown state. Note: Read access both RAMs simultaneously permitted. data would lost there only data register high byte byte respectively.
Semiconductor Group
08.97
7274 7274
Register Location Description 3.13 Address Register (ADR)
register contains address. range FFH.
3.14
Data High Byte Register (DATAH)
DATAH register contains high byte data for/from RAM.
3.15
Data Byte Register (DATAL)
DATAL register contains byte data for/from RAM.
Semiconductor Group
08.97
7274 7274
Register Location Description 3.16 Loactions
Access provided register, register, register together with DATAH DATAL registers. sections 3.12 3.15 register description. This section lists parameters addresses. Each adress points word. related DATAH register, related DATAL register. table below summarizes location parameters gives reference following sections with detailed parameter description. Table
Adress (hex)
MD_LP MD_Tbreak MD_DIFF MD_LEVE ES_PLdly CT_LEV TF_BW TF_ATT NM_LPlim SD_LP NM_LPfade NM_LPrise ES_ATT ES_RISE -MD_FREQ MD_BW MD_LIM MD_Thold MD_LEV MD_TIME
Summary Parameter Locations
High Byte Nib. Nib.
CT_FREQ CT_GAIN TF_RES TF_SAT AEL_GAIN SD_LIM NM_OFF SP_PDN SD_PDS ES_DLY ES_FALL ES_RxPL modem detection echo suppressor artificial echo loss speech detector noise monitor
Byte Nib. Nib.
Function
refer page
congestion tone generator tone filter
Applies only
Semiconductor Group
08.97
7274 7274
Register Location Description 3.16.1 Programming Cells Extended Features
make 7274 features echosuppression, fax/modem tone detection, tone generation artificial echo loss special parameters located must programmed. typical programming sequence write parameters cell read programmed values back confirmation described below.
Note: cells loaded with default values after reset.
Example: Load value bandwidth fax/modem detection with 100Hz Write with following parameters: Adress: High Byte 100Hz: Byte 100Hz:
Write Data High Register (DATAH) Write Data Register (DATAL) Write address parameter bandwidth (ADR) Write simultaneously (COM) Read write operation completed (DST)
Read back bandwidth cell (ADR still 0DH): Read DSP1 bandwidth cells (COM) Read read operation completed(DST) Read Data High Register (DATAH) Read Data Register (DATAL) Read DSP2 bandwidth cells (COM) Read read operation completed(DST) Read Data High Register (DATAH) Read Data Register (DATAL) DATAH DATAL DATAH DATAL
Note: parameters given tables show complete coding possibilities space limitation. values required that listed below, complete tables available disk.
Semiconductor Group
08.97
7274 7274
Register Location Description 3.16.2 Congestion Tone Generator
Congestion Tone Frequency (CT_FREQ) This parameter specifies frequency congestion tone that output uncompressed side instead data. Range: range: Coding: 0000H 2000H freq [kHz] (CT_FREQ 65536)
Congestion Tone Level (CT_LEV) level congestion tone programmed using this parameter. Range: Coding: Table Value refer table Values Congestion Tone Level Level 0.00 1.16 2.50 5.00 Value Level 10.10 14.54 18.06 22.14 Value Level 24.64 28.16 31.26 36.06 Value Level 40.21 44.64 -10E9
Congestion Tone Frequency Gain (CT_GAIN) CT_GAIN determines frequency gain. Range: Coding: Table Value refer table Values Congestion Tone Frequency Gain Gain 0.00 3.25 5.00 6.02 Value Gain 7.50 10.10 12.04 14.54 Value Gain 18.06 24.08 30.10 36.12 Value Gain 42.14 48.16 10E9
Semiconductor Group
08.97
7274 7274
Register Location Description 3.16.3 Tone Filter
Tone Filter Bandwidth (TF_BW) Determines bandwidth tone filter. Range: Coding: Table refer table Values Tone Filter Bandwidth Value 0.0000000 0.2500000 0.3750000 0.4375000 0.5000000 0.6250000 0.7187500 0.8125000 Value 0.9062500 0.9980469
Value
Tone Filter Resonance Frequency (TF_RES) Range: Coding: Table Value refer table Values Tone Filter Resonance Frequency Freq. 2000.00 1678.28 1510.57 1321.82 Value Freq. 1034.83 858.33 721.37 601.07 Value Freq. 480.31 423.03 357.05 298.43 Value Freq. 210.78 125.87 79.59
Semiconductor Group
08.97
7274 7274
Register Location Description Tone Filter Attenuation Factor (TF_ATT) Determines out-of-frequency attenuation. Range: Coding: Table Value refer table Tone Filter Attenuation Atten. 48.16 42.14 36.12 Value Atten. 30.10 24.08 Value Atten. 18.06 12.04 Value Atten. 6.02 0.00
Tone Filter Saturation Amplification (TF_SAT) Range: Coding: Table Value 3.16.4 Range: Coding: refer table Values Tone Filter Saturation Amplification Ampl. 12.041 9.542 7.959 7.044 6.088 5.460 Value Ampl. 4.048 2.961 2.006 1.023 0.462 0.000 Value Ampl. -0.493 -1.025 -1.972 -3.059 -5.494 -6.089 Value Ampl. -7.180 -8.519 -12.041 -10E9
Artificial Echo Loss Gain (AEL_GAIN) refer table (CT_LEV)
Determines level added receive path.
Semiconductor Group
08.97
7274 7274
Register Location Description 3.16.5 Speech Detector Noise Monitor
Speech Detection Limit (SD_LIM) This parameter determines maximum limit signal speech detection. Range: range: Coding: limit [dB] -96.32 SD_LIM 0.7525
Speech Detection Lowpass (SD_LP) This parameter specifies main spikes signal being eliminated. Range: Coding: Table Value refer table Values Time Constant time 0.94 2.00 4.00 7.05 Value time 15.00 21.27 30.06 42.60 Value time 60.17 73.08 85.27 102.34 Value time 120.41 132.07 146.22 170.60
Peak Detector Noise (SD_PDN) This time constant specifies Range: Coding: refer table (SD_LP)
Peak Detector Speech (SD_PDS) This time constant specifies Range: Coding: refer table (SD_LP)
Semiconductor Group
08.97
7274 7274
Register Location Description Noise Monitor Lowpass Limit (NM_LPlim) This parameter determines maximum value lowpass detect continous tones speech activate echosuppressor. Range: range: Coding: limit [dB] NM_LPlim 0.7525
Noise Monitor Offset (NM_OFF) Specifies level threshold between signal noise. Range: range: Coding: limit [dB] NM_OFF 0.7525
Noise Monitor Lowpass Fade Constant (NM_LPfade) fade constant enables fast discharge noise monitor lowpass after speech recognition. Range: Coding: refer table (SD_LP)
Noise Monitor Lowpass Rise Time (NM_LPrise) This time constant determines time noise monitor charged after speech recognized Range: Coding: Table Value refer table Values Time Constant Noise Monitor Lowpass time 4.10 5.46 6.55 7.71 Value time 8.46 10.92 13.11 14.56 Value time 17.48 21.85 26.21 30.84 Value time 34.95 43.69 52.43 58.25
Semiconductor Group
08.97
7274 7274
Register Location Description 3.16.6 Echo Suppressor
Echosuppressor Attenuation (ES_ATT) parameter ES_ATT determines level attenuation (refer figure receive path speech been detected transmit path estimation receive power below specified limit. Range: range: Coding: suppressor attenuation [dB] (ES_ATT 128)
Echosuppressor Delay (ES_DLY) ES_DLY specifies delay time tdly between disappearance speech transmit path (speechdetector speech) start fall time echosuppressor. Range: range: Coding: 1020 tdly [ms] ES_DLY
Echosuppressor Rise Time (ES_RISE) ES_TR specifies rate which attenuation increased from programmed value speech detected speech detector. This rate determines rise time Range: Coding: Table Value 0.025 dB/ms dB/ms refer table Values rate determing rise time rate db/ms 0.025 0.101 0.152 0.203 Value rate db/ms 0.306 0.510 0.819 1.025 Value rate db/ms 1.370 1.647 2.066 2.768 Value rate db/ms 3.336 4.520 5.066 5.652
Semiconductor Group
08.97
7274 7274
Register Location Description Echosuppressor Fall Time (ES_FALL) This parameter determines rate which attenuation decreased from programmed value speech transmit path disappeared power level receive path exceeded specified value. This rate determines fall time Range: Coding: Table Value 0.01 dB/ms 2.13 dB/ms refer table Values rate determing fall time rate db/ms 0.010 0.029 0.101 0.203 Value rate db/ms 0.304 0.405 0.507 0.608 Value rate db/ms 0.675 0.809 1.010 1.110 Value rate db/ms 1.210 1.344 1.609 2.138
Echosuppressor Reveice Power Level Delay (ES_PLdly) This coefficient specifies time constant power estimator receive signal. Range: range: Coding: (only MSBs used) tPLdly [ms] -0.125 (1-2-ES_PLdly)
Echosuppressor Reveice Power Level (ES_RxPL) ES_RxPL parameter specifies power level threshold receive direction. signal receive path exceeds programmed value attenuation added echosuppressor will switched after tPLdly elapsed. This guarantees that despite echosuppression participant other side line switch echosuppression speaking loud. Range: range: Coding: threshold [dB] (ES_RxPL 256)
Semiconductor Group
08.97
7274 7274
Register Location Description 3.16.7 Fax/Modem Detection
Fax/Modem Detection Center Frequency (MD_FREQ) parameter MD_FREQ specifies center frequency fax/modem tone that detected. Range: Coding: Table Value refer table Values Fax/Modem Detection Center Frequency Freq. 1500 1600 1700 Value Freq. 1800 1900 2000 Value Freq. 2100 2200 2300 Value Freq. 2400 2500
Fax/Modem Detection Bandwidth (MD_BW) parameter MD_BW specifies range around center frequency within fax/ modem tone detection allowed. Range: Coding: Table Value refer table Values Fax/Modem Detection Bandwidth Freq. 1.09 10.06 20.01 Value Freq. 50.03 100.10 150.02 Value Freq. 200.83 250.19 300.39 Value Freq. 350.04 400.17 500.37
Fax/Modem Detection Lowpass (MD_LP) This parameter specifies time constant power estimators fax/modem detection. Range: Coding: refer table
Semiconductor Group
08.97
7274 7274
Register Location Description Fax/Modem Detection Limit (MD_LIM) level programmed MD_LIM compared with output modem filter. level modem signal above MD_LIM fax/modem detection activated. Range: range: Coding: limit [dB] -96.32 SD_LIM 0.7525
Fax/Modem Detection Break Time (MD_Tbreak) Tone breaks less than specified time ignored. Range: Resolution: Coding: 127.5 time [ms] MD_Tbreak
Fax/Modem Detection Hold Time (MD_Thold) MD_Thold specifies time detection conditions have valid fax/modem detection. Range: Resolution: Coding: time [ms] MD_Thold
Fax/Modem Detection Difference (MD_DIFF) This parameter specifies difference outputs bandpass notch filter have exceed. difference signal energy modem frequency band modem frequency band larger than MD_DIFF modem signal detected. Range: range Coding: delta [dB] sign (MD_DIFF) MD_DIFF 0.7525 MD_DIFF LSBs location.
Fax/Modem Detection Level (MD_LEV) MD_LEV determines threshold below which noise signals ignored. Range: Resolution: Coding: level [dB] MD_LEV 0.7525
Semiconductor Group
08.97
7274 7274
Register Location Description Fax/Modem Detection Level (MD_LEVe) parameter specifies level fax/modem detection. Range: Resolution: Coding: level [dB] MD_LEV 0.7525
Fax/Modem Detection Time (MD_TIMe) parameter specifies timing conditions fax/modem detection. Range: Resolution: Coding: time [ms] MD_TIME
Semiconductor Group
08.97
7274 7274
Electrical Characteristics Parameter Ambient temperature under bias: Storage temperature Voltage with respect ground Maximum voltage Electrical Characteristics Absolute Maximum Ratings Symbol Limit Values Unit
Tstg Vmax
Note: Stresses above those listed here cause permanent damage device. Exposure absolute maximum rating conditions extended periods affect device reliability.
Semiconductor Group
08.97
7274 7274
Electrical Characteristics Characteristics
PEB: PEF: Parameter High level input voltage level input voltage level input leakage current Symbol min. Limit Values typ. max. Unit Test Condition
pins except XTAL1 pins except XTAL1 pins except XTAL1 pins except XTAL1 whole temperature range (pins DOC, DOU, INT) (all other pins) operational both DSPs power down mode
High level input leakage current
XTAL1 leakage current
High level output voltage level output voltage
0.45
Power supply current
Note: listed characteristics ensured over operating range integrated circuit. Typical characteristics specify mean values expected over production spread. otherwise specified, typical characteristics apply given supply voltage.
Semiconductor Group
08.97
7274 7274
Electrical Characteristics Parameter Input capacitance Output capacitance capacitance Characteristics Capacitances Symbol min. COUT CI/O Limit Values max. Unit
Ambient temperature under bias range, Inputs driven logical logical '0'. Timing measurements made logical logical '0'. testing input/output waveforms shown below.
Figure Waveforms Tests
Semiconductor Group
08.97
7274 7274
Electrical Characteristics 4.4.1 Interface Timing
DINC DINU
Figure Interface Timing Double Clocking Model Parameter clock period pulse width setup time hold time Data delay Data setup time Data hold time Tristate Control delay Frame Strobe delay Symbol min. tDCL tWL, tDOd tDIs tDIh tTCd tFSd Limit Values max. Unit
Semiconductor Group
08.97
7274 7274
Electrical Characteristics 4.4.2 Serial Microcontroller Interface Timing
CCLK
CDIN
CDINs
CDINh
CDOUT
CDOUTd
uC_tim
Figure Serial Interface Timing
Parameter Clock period Chip Select setup time Chip Select hold time CDIN setup time CDIN hold time CDOUT data delay
Symbol min. tCSs tCSh tCDINs tCDINh tCDOUTd
Limit Values max.
Unit
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Electrical Characteristics 4.4.3 Parameter Test clock period Test clock period Test clock period high set-up time hold time from set-up time hold time from valid delay from Boundary Scan Timing Symbol min. tTCP tTCPL tTCPH tMSS tMSH tDIS tDIH tDOD Limit Values max. Unit
Figure Boundary Scan Timing
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Electrical Characteristics 4.4.4 Timing
DSYNC
DSYNC
Figure Clock Timing
Parameter Clock delay DSYNC delay
Symbol min. tBCd tDSYNC
Limit Values max.
Unit
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Package Outlines Package Outlines
Plastic Package, P-MQFP-44 (Plastic Metric Quad Flat Package)
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Appendix Appendix Proposed Default Values Locations
Adress (hex)
Function
proposed value (hex)
effect
tone generator tone filter artificial echo loss speech detector
CT_FREQ CT_LEV CT_GAIN TF_BW -0.99, TF_RES TF_ATT TF_SAT AEL_GAIN -24.64 NM_LPlim SD_LIM SD_LP NM_OFF NM_LPfade SD_PDN NM_LPrise SD_PDS ES_ATT ES_DLY ES_RISE -3.3 dB/ms ES_FALL dB/ms ES_PLdly ES_RxPL MD_FREQ 2100 MD_BW MD_LP MD_LIM MD_Tbreak MD_Thold =0.4 MD_DIFF MD_LEV =-44 MD_LEVE MD_TIME
echo suppressor
modem detection
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Appendix Working Sheet Register Programming
Figure Working Sheet Register Programming
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Appendix 6.3.1 Development Tools STSI 4000 PCM-4 Userboard Part Number STSI 4000 Ordering Code Q67100-H6865
Description PCM-4 Userboard
STSI 4000 consists Remote Terminal (RT) board Central Office Terminal (COT) board fully operational PCM-4 demonstration. These boards combined with standard analog telephones standard analog have complete system. principle STSI 4000 shown figure
STSI 4000
SLIC SLIC 7274 SLIC SLIC 2466 C165 C165 2466 2091
Tel.
2091
7274
Euroset
Line
Figure STSI 4000 PCM4 Userboard (Euroset included Kit) V.24 connection possible read write 7274 2091 V5.x registers. Addtional commands allow control monitor 2466 specific functions like hook on/off detection, channel allocation etc. This allows program very efficiently different configurations test device functionality. Alternatively user download C165 program test realtime behavior. From 1997 onwards additionally software package including sourcecode will available which provides basic modules operate STSI 4000 PCM-4 system without need external V.24 interfaces. STSI 4000 boards contains hardware required typical PCM-4 system with exception phantom power-supply feeding ringing generation.
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Appendix 6.3.2 SIPB 7274 Quad ADPCM Part Number SIPB 7274 Ordering Code Q67100-H6866
Description Quad ADPCM
SIPB 7274 Quad ADPCM consists SIPB 7274 board containing Quad ADPCM controllers operating back-to-back, EVC50 microcontroller board based C513 processor EVC50 connect optionally (not included SIPB 7274 kit) 2465/6 evaluation board (e.g. SIPS 2466). This configuration allows fast testing 7274 features.
EVC50
SIPS2466
SIPB7274
AAAAAAAAA AAAAAAAA AAAAAAAAA AAAAAAAA AAAAAAAAA AAAAAAAA SLIC AAAAAAAAA AAAAAAAA AAAAAAAAA AAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAA 7274 7274 AAAAAAAAA AAAAAAAA SLIC AAAAAAAAA AAAAAAAA AAAAAAAAA AAAAAAAA AAAAAAAAA AAAAAAAA AAAAAAAAA AAAAAAAA AAAAA AAAAAAAAA AAAA AAAAAAAAA AAAAAAAAA AAAAA AAAAAAAAA AAAA
AAAAAAAAAA AAAAAAAA AAAAAAAAAA AAAAAAAA AAAAAAAAAA AAAAAAAA SLIC AAAAAAAAAA AAAAAAAA AAAAAAAAAA AAAAAAAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA AAAAAAAA AAAAAAAAAA AAAAAAAA SLIC AAAAAAAAAA AAAAAAAA AAAAAAAAAA AAAAAAAA AAAAAAAAAA AAAAAAAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA
EVC50-bus
PCM4
Figure SIPB 7274 Quad ADPCM coded (uncompressed) data extracted/inserted connector compressed 7274 (A). Optionally compressed outputs 7274 directly connected those 7274 provide back-to back operation device device 'B'. uncompressed data 7274 extracted/ inserted connector Numerous access points board allow easy monitoring 7274 signals.
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Index Boundary scan Congestion tone
DECT Echosuppression direction Fax/Modem Tone Detection Frame Strobe ID-Byte ISAR Noise monitor
Peak detector Propagation delay Receive power level Serial interface Synchronous coding adjustment
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Data Sheet 08.97 7274 Revision History: Current Version: 08.

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