IMAGE SIGNAL PROCESSING SUB-SYSTEM 1-D/2-D SOFTWARE CONFIGURABLE
|
|
|
Top Searches for this datasheet
IMSA110
IMAGE SIGNAL PROCESSING SUB-SYSTEM
1-D/2-D SOFTWARE CONFIGURABLE CONVOLVER/FILTER ON-CHIP PROGRAMMABLE LINE DELAYS 1120 STAGES) 8-BIT DATA 8.5-BIT COEFFICIENT SLICE MULTIPLY-AND-ACCUMULATE STAGES (21) CONVOLUTION WINDOW ON-CHIP POST PROCESSOR DATA TRANSFORMATION FULLY CASCADABLE WINDOW SIZE ACCURACY DATA THROUGHPUT (420 MOPS) SIGNED/UNSIGNED DATA COEFFICIENTS MICROPROCESSOR INTERFACE HIGH SPEED CMOS IMPLEMENTATION COMPATIBLE SINGLE SUPPLY POWER DISSIPATION WATTS CERAMIC
PGA100 (Ceramic Grid Array Package)
APPLICATIONS digital convolution correlation Real time image processing enhancement Edge feature detection Data transformation histogram equalisation Computer vision robotics Template matching Pulse compression interpolation
July 1992
ORDERING INFORMATION
Part Number IMSA110-G20S Package PGA100
A110-01.TBL
Clock Speed 20MHz
Military/ commercial commercial
1/26
IMSA110
CONNECTIONS
Index PSRIN PSRIN PSRIN PSRIN COUT COUT COUT
PSROUT PSROUT PSROUT
PSRIN
PSRIN
PSROUT
PSROUT
COUT
COUT
PSRIN
PSROUT PSROUT
COUT
COUT
PSRIN
PSROUT
COUT
COUT
COUT [10]
COUT
COUT [11]
COUT [12]
COUT [13]
COUT [14]
[10]
[11]
[12]
D[6]
COUT [16]
COUT [15]
[13]
[15]
[17]
COUT [19]
COUT [18]
COUT [17]
[14]
[19]
[21]
COUT [20]
[16]
[20]
RESET
D[2]
D[5]
D[7]
COUT [21]
[18]
D[0]
D[1]
D[3]
D[4]
Notes pins must connected Volt power supply. pins must connected ground.
INTRODUCTION IMSA110 single-chip reconfigurable cascadable subsystem suitable many high speed image signal processing applications. Apart from powerful multiply-accumulate capability (420 MOPs), strength IMSA110 lies extensive programmable support data conditioning transformation.
DESCRIPTION IMSA110 consists configurable array multiply-accumulators, three programmable length 1120 stage shift registers, versatile post-processing unit microprocessor interface configuration control purposes. comprehensive on-chip facilities make single device capable dealing with many image processing operations.
2/26
A110-01.EPS
IMSA110
Figure IMSA110 Users Model
ENABLE ENABLE WRITE 8-bit Update coefficient registers DATA Decode logic 8-bit Current coefficient registers Backend look table 8-bit data transformation look Asynchronous Functions Configuration control registers PCR0 PCR1 PCR2
ADDRESS
Control logic
CLOCK RESET
PSRIN
1120 stage Programmable shift register (PSRC)
7-stage multiply-accumulate array
1120 stage Programmable shift register (PSRB)
7-stage multiply-accumulate array
PSROUT CASCADE INPUT
1120 stage Programmable shift register (PSRA)
7-stage multiply-accumulate array Backend post-processing unit (normalization, saturation, data transformation)
CASCADE OUTPUT
A110-02.EPS
Synchronous Functions
IMSA110 five interfaces through which data transferred, Figure microprocessor interface allows access coefficient registers, configuration status registers, data transformation tables. remaining four interfaces allow high speed data input output IMSA110and cascading several devices. typical IMSA110 system shown Figure devices used cascade, they configured, entirely under software control, stage transversal filter window, where integers satisfying example cascaded devices software configured 84-stage filter, window, window, window. final output chip bits wide twos complement format.
Figure shows distribution delays inside part. latency between PSRin COUT dependent upon length PSRc. example, with PSRc coefficients zero except CR0c[6] data passes through stages), COUT will correspond PSRin delayed clock cycles. latency betweenPSRin PSRoutis cycles PLUS lengths PSRc, PSRb PSRa. shift registers bypassed setting SCR[1] then PSRout will PSRin delayed clock cycles. Latency between cascade input (CIN) cascade output (COUT) cycles. This shown lumped cascade input cascade output pads Figure Figure gives details data pipelining through backend datapath.
3/26
IMSA110
Figure Synchronous Functions IMSA110
PSRIN Programmable PSRC shift register 1120 stages
CR1c coefficient registers bits CR0c coefficient registers bits
CR1b coefficient registers bits CR0b coefficient registers bits Programmable PSRB shift register 1120 stages
CR1a coefficient registers bits CR0a coefficient registers bits Programmable PSRA shift register 1120 stages
Backend processing unit including cascade data path, normalization, saturation units data transformation look tables
(see Figure detail)
4/26
A110-03.EPS
PSROUT
cascade input
COUT cascade output
IMSA110
Figure Typical IMSA110 Based System
General purpose microprocessor
Input
PSRIN
PSROUT
PSRIN
PSROUT
PSRIN
PSROUT
Clock
PROGRAMMABLE SHIFT REGISTERS three shift registers bits wide each programmable from 1120 clock cycles length. lengths programmed into control registers microprocessor interface. Data clocked into device PSRin (Programmable Shift Register maximum rate 20MHz. On-chip, input data then through pipeline three shift registers. output first shift register passes first 7-stage array also input second shift register. Having passed through three shift registers data output PSRout used cascading. Alternatively, shown Figure shift registers bypassed input data transferred PSRout after delay stages. This mode controlled on-chip control registers significantly simplifies software configuration cascade arrangement. ARRAY shown Figure processing core device consists configurable array multiplyaccumulators (macs). array consists three 7-stage transversal filters which configured either 21-stage linear pipeline two-dimensional window. input data bits wide array three programmable shift registers. output each shift register supplied input three 7-stage transversal filters. each three transversal filters associated input data simultaneously stages. each stage input sample multiplied coefficient stored memory, added output previous stage delayed clock cycle. output each 7-stage fed, delay stage, first stage next transversal
filter. coefficient word width array bits wide. banks coefficients provided. instant coefficients within array. defined state `Current Bank' bit, ACR[0]. other altered microprocessor interface. Once coefficients been loaded, activities coefficient banks interchanged without interrupting flow data. Alternatively, setting `continous bank swap' SCR[0], coefficient banks swapped automatically after each data input. this case `Current Bank' only determines which bank used first. Both data input coefficients programmed independently support twos complement positive unsigned formats allowing multiple devices used `slice' higher accuracy systems. Within array truncation rounding performed partial products. array output backend post-processing unit which responsible data transformation normalisation cascading function. BACKEND POST-PROCESSOR hardware description Backend Post-Processor consists four major blocks input block (shifter, cascade adder rectifier unit),a statistics monitor,the data conditioning unit which itself consists data transformation unit data normaliser, output block (output adder multiplexers). detailed diagram Backend Post-Processor given Figure operations performed backend twos complement signed numbers unless otherwise stated.
5/26
A110-04.EPS
IMSA110 Cascade Cascade
IMSA110 Cascade Cascade
IMSA110 Cascade Cascade
Output
IMSA110
Shifter, Cascade Adder Rectifier Data from array enters datapath programmable shifter. shifter capable arithmetic right shifts (divides) bits with rounding, left shifts bits. size this shift controlled status bits BCR0[5-1]. output shifter passes into cascade adder where added, along with rounding generated shifter, either cascade input (BCR0[0] zero value (BCR[0] result this 22-bit signed addition greater than (209715110) then adder will generate positive overflow. Likewise, less than -221, (-209715210) negative overflow will generated. other words, positive overflow generated result adding positive numbers (both MSBs negative (resulting Conversely, negative overflow generated result adding negative numbers (both MSBs positive (MSB Adding numbers different signs cannot cause adder overflow. output cascade adder optionally full-wave half wave rectified under control BCR0[7,6]. output rectifier passes onto bus. Overflows signalled both statistics monitor data conditioner. Statistics Monitor statistics monitor allows user watch dogs dynamics data bus. cannot affect data bus. statistics gathered provide information system behaviour which used ensure correct data scaling normalisation. information also useful control overall system's analogue frontend. Hardware/Functions statistics monitor consists Min/Max register (MMR), Min/Max Buffer (MMB), Over/UnderShoot Counter (OUC), Over/UnderShoot Buffer (OUB) twos complement comparator. perform four functions REGISTER Capture maximum value data store MMR. REGISTER Capture minimum value data store MMR. OVERSHOOT COUNTER Increment each time data value exceeds preset value MMR. UNDERSHOOT COUNTER Increment each time data value less than preset value MMR. mode operation determined Max/Min switch BCR1[0], Static Threshold switch BCR1[1]. Operation Each sample compared against threshold stored MMR. unit configured overshoot counter data exceeds threshold MMR, then counter (OUC) incremented. data less than equal threshold, then action will occur. unsigned will wrap around. Thus behaves saturating counter with maximum value (3FFFFF16, 419430310). there positive overflow bus, then counter will increment since correct value must exceed threshold. Similarly negative overflow will increment counter since correct value cannot exceed preset threshold. unit configured undershoot counter then counter will incremented whenever sample less than preset threshold. this case negative overflow will cause counter increment. unit configured register exceeds current threshold MMR, then value Xbus loaded into becomes threshold counter incremented. threshold exceeded then action occurs. Thus value maximum value that appeared bus, value been incremented number times that threshold been updated. unit configured register then threshold updated counter incremented whenever less than current threshold. When operating min/max register, overflows never cause threshold updated this would load erroneous value into MMR.
6/26
IMSA110
Figure Detailed Block Diagram Backend Post-processing Unit
Clock cycle Cascade input pads From array Shifter [8:0] Rounding
negative overflow positive overflow
Cascade Adder
Rectifier DATA TRANSFORMATION UNIT Prescaler Over/under select (Isbs) Over/undershoot buffer Min/max register STATISTICS MONITOR Min/max buffer
Comparator GT/LT Over/undershoot count
Control
[26:22] [21:0]
DATA NORMALIZER Shifter Zero data
Byte select
from Output Adder Rounding
[21:14] [21:14] Cascade output pads [13:8] [7:0]
A110-05.EPS
[7:0]
7/26
IMSA110
Overflows records history positive overflows bus. Similarly records history negative overflows. These bits zero writing copy location active independently whether Static Threshold set. When read, then bits interpreted follows:
condition overflow occured more positive overflows have occured more negative overflows have occured Both postive negative overflows have occured
amount right shift programmed BCR2[4-0] have value from Over/under select detector With PosLUTAddr (SCR[6]) zero, this unit monitors whether amount right shift performed prescalar sufficient include significant bits maintain sign selected field (i.e. over under select generated most significant selected field differs from subsequent right including most significant right shifted bus). This will overselect positive (Bit underselect negative (Bit other words address always deemed signed with address range -128 127. however control PosLUTAddr (SCR[6]) one, unit monitors whether amount right shift performed prescaler sufficient include significant bits selected field that unselected bits zero (i.e. over under select generated first selected (bit zero differs from subsequent right including most significant rightshifted bus). This will anoverselect Xbus positive underselect WHENEVER Xbus negative. Thus, this mode, address range 255. Prescalar under/over selects positive/negative overflows passed along with selected address field. Look table (LUT) byte select consists words, bits wide plus special locations called upper lower saturation registers (USR respectively). Thus actually words bits. output called bus. most significant bits address field used address words LUT. least significant pair bits field used control byte select output. Thus addition operating 64+2 word look table words, used bit, 256+2 byte providing 8bit 8bit transformations. Positive overflows bus, over selects prescalar cause access overriding address given prescalar. Likewise negative overflows under selects cause access LSR. sort overflow prescalar will cause byte select control overridden most significant byte (byte appropriate Saturation Register will appear byte wide output data transformation unit.
Detailed block diagram Backend Post-processing Unit Access registers accessed, through memory interface, only their associated buffers (MMB respectively) accessible directly. order load with value, host must first write value then transfer data from performing WRITE copy location, 0B416. read host must first perform READ cycle from location 0B416 (which transfers contents into MMB) then read MMB. accessed same except that dummy writes reads done from location 0BC16. Copies from (reads) performed time giving snapshot contents respectively. Copies from (writes) also performed time allowing threshold counter updated dynamically. Data transformation unit data transformation unit consists prescalar, under/over select detector, look table byte selector. used isolation perform abitrary data mappings, conjunction with data normaliser implement sophisticated dynamic range compression functions. Prescalar This allows 8-bit field anywhere within 22-bit selected address LUT. This performed right shifting that required bits least significant end.
8/26
IMSA110
there simultaneous overflows prescalar then overflow from takes priority. thus used model saturating behaviour analogue circuits instead usual `wrap around' encountered digital systems. Alternatively could signal error conditions within backend directly output pins output multiplexers. loaded memory interface. addressing corresponds field, assuming that byte selector being used. order access look table, from microprocessor interface, Access control ACR[1] must zero. This will force zero normaliser controlled BCR3[7-3] regardless setting dynamic normalisation bit, BCR3[2]. LUT, then loaded with arbitrary value microprocessor interface. Setting access control will then allow used data transformation unit. Data normaliser This unit consists shifter capable right shifts bits left shifts bits, followed zero data unit adder. shifter controllable from sources control bits BCR3[7-3] bits bus. Enable Dynamic Normalisation (BCR3[2]) determines which source control normaliser. this zero normaliser controlled BCR3[7-3]. five field twos complement number between This indicates amount right shift (negative meaning left shift). value outside this range causes output shifter forced zero. output shifter, with rounding generated shifter, goes into output adder. Output adder This adder with inputs coming from data normaliser. other input either bits Ybus from data transformation unit, zero under control BCR3[1]. Note that overflow occuring left shifting normaliser subsequent addition output adder detected IMSA110. Output multiplexers These multiplexers allow currently selected byte from optionally selected drive either most significant byte and/or least significant byte Cascade Output pins. This controlled state BCR2[5] BCR2[6]. Enabling either these multiplexers overrides state Cascade Output pins only relavent pins. remaining pins will continue represent output output adder. BACKEND POST-PROCESSOR Modes Operation backend post-processing unit capable performing many functions including data scaling, transformation, dynamic range compression histogram equalisation. Default mode (after Reset) power after reset state backend post-processor such that data from array cascade input added pass straight through datapath unaffected. default mode statistics monitor register although values OUB, OUC, will undefined. Likewise contents LUT, will undefined, Access control will zero forcing zero allowing microprocessor interface access LUT, LSR. Note that cascade output pins output pins tristated. Cascade adder data scalar These units allow cascading A110s where output array scaled before added cascade input data. shifter also used combining devices obtain extended precision input data, coefficient word length both. ability zero cascade input provides simple means controlling number `active' devices cascaded well means debugging large systems. Rectification Rectification, removal negative results, needed several image processing functions. example, edge detection using Sobel operator usually requires full wave rectification different signs obtained differing edge transitions. Edge detection using Laplacian operator produces change sign edge. this case, removing negative numbers using half wave rectification produce better results full wave rectification lead some blurring edge transition.
9/26
IMSA110
Static scaling This performed using units: array output shifter above), data normaliser. second case data undergoes simple scaling operation (with rounding) within normaliser.The normalisercan used scale (multiply) data factors 1/16384 1/8192, 1/4096 1/2, controlling normaliser from control bits BCR3[7-3], this provides means simple scaling data before output. Setting BCR3[1] BCR2[6,7] zero ensures that data transformation unit takes part operation output normaliser passed unchanged output pins. Dynamic scaling this mode scaling controlled data itself. i.e. scalar controlled from (Ybus bits 26-22) setting BCR3[2] one, Ybus input output adder being zero either setting BCR3[1] zero programming accordingly. This mode provide discontinuous non-linear transformation. Simple transformation This mode allows user apply arbitrary transformations data before output. Here treated addressed either -128 PosLUTAddr zero PosLUTAddr one. field selected prescalar used address byte which passed directly output pins output multiplexers. Ybus control data normaliser disabled, BCR3[7-3] range zero normaliser output Ybus input output adder zero BCR3[1]. both) output multiplexers enabled addressed byte from passes straight cascade output pads. Only most significant byte applicable this mode overflows override byte select control force select most significant byte. Dynamic normalisation this mode normaliser transformation units output conditioner used together perform sophisticated non-linear dynamic range compression transformations. simple transformation case prescalar selects field anywhere within bus. most significant bits, overflows, address LUT. this case look table treated 64+2 Bits used control normaliser block that input normaliser dynamically scaled. output normaliser then added output adder least significant bits (Note that only bits actually used). Thus data scaled, rounded, then anoffset added scaled result. Each operation viewed
output input scale offset
Where scale offset both programmable functions input. view this operation consider that original data range divided into equal sized levels each level different scale offset applied. scale offset stored would chosen give desired behaviour under overflow conditions. Note that case cascade adder overflows, data invalid, scale here would usually range zero normaliser output. offsets would then provide cascade output directly. Note also that scale field programmed that normaliser always zeros data, then output will correspond offset field LUT. This viewed coarse transformation with wide dynamic range which useful applications such image contour emphasis equalisation.
Figure Format Data Stored LUT,
BYTE BYTE BYTE BYTE
offset BCR3
10/26
A110-06.EPS
scale BCR3
IMSA110
GLOSSARY This section defines meaning terms used elsewhere this data sheet. Arithmetic Shift right shift, most significant always copied into most significant result. example shifting right
01000101 11000101 00010001 11110001 two's complement 10000000 10000001 11111111 00000000 00000001 01111111 decimal -128 -127
left shift, least significant will become zero. Note that left shifting cause overflows these detected output scalar data normaliser. Rounding rounding done within A110is equivalent truncating after adding LSB. (Rounding always applied positive direction). example twos complement numbers undergoing right shift:
00000011 00000010 11111110 00000001 11111101 00000000 00000001 (rounded 00000000 00000001 (rounded 11111111 00000000 (rounded 00000000 rounding) 11111111 rounding)
Rectification Rectification method removing negative numbers. There methods: Full wave Half wave. either case positive numbers zero unaffected. Full wave rectification, negative numbers negated(i.e. multiplied that they become positive. Half wave rectification, negative numbers replaced zero. Dynamic Range Compression When Dynamic used this context, indicate change behaviour each data point. example, dynamic shift where size shift change each successive clock cycle. Dynamic range compression range compression making offset shift, which change depending each data point. This allows essential non-linear transformations required image processing implemented A110. Fields Bits, words addresses this data sheet little-endian; lowest order byte multiple byte word referred byte addressed same way. Similarly, least significant field that with lowest number. example, `bits 26-22' refers field where treated least significant, most significant. Latency Within IMSA110 latency number clock cycles from input corresponding output. instance, with programmable shift registers bypassed setting SCR[1] latency from PSRin PSRout will shown Figure
Left shifts generate rounding. Transversal Filter transversal filter calculation consisting products successive points input data. input data xi+1, coefficients, c6,c5, result,
x6-i
Two's Complement Two's complement numbers allow both positive negative numbers. example numbers most positive number 127, most negative -128:
11/26
IMSA110
Figure
PSRIN
PSROUT PSRIN latched
DESIGNATIONS System services
VCC, RESET In/out Function Power supply return Input clock System reset
mise inductance within package. supply pins must connected. supply must decoupled close chip least 100nF inductance (e.g. ceramic) capacitor between GND. clock signal controls timing input output four dedicatedinterfaces,and controls progress data through shift registers, multiply-accumulate array post-processing unit. A110 fully static clock slowed down stopped either state without corrupting data. RESET this taken least clock cycles, control logic within A110 will reset control configuration registers will initialised their default values. other register, memory locations, datapath registers shift registers will reset this signal. reset initiated automatically when power first applied device. This reset will completed once four cycles have occured after valid. Synchronous services PSRin[7-0] This 8-bit wide supplies input data device. input data enters first three shift registers chain. timing this input controlled signal. data PSRin port sampled rising edge clock. cascade arrangement, this will connected PSRout port previous device. such arrangement PSRin port first device will input overall cascaded system.
Synchronous input/output
PSRin[7-0] PSRout[7-0] Cin[21-0] Cout[21-0] In/out Function Programmable shift register input Programmable shift register output Cascade input port Cascade output port
Asynchronous input/output
ADR[8-0] D[7-0]
Note
In/out in/out
Function Memory interface enable signals Memory interface write enable Memory interface adress Memory interface data
Signal names shown with overbar they active low, otherwise they active high.
System services System services include necessary logic start maintain A110. Power Power supplied device pins. Several each provided mini12/26
A110-07.EPS
IMSA110
PSRout[7-0] This outputs data from last programmable shift register chain. data this synchronouslyclocked rising edge CLK. cascade arrangement this port will connected PSRin port next device. power after reset, PSRout pins tristated. They enabled SCR[5]. Cin[21-0] Cascade Input port allows IMSA110s cascaded. also used combining external signal (e.g. reference image offset) with processed result. cascade arrangement, this will connected Cascade Output previous device. data sampled rising edge CLK. Cout[21-0] This outputs processed result from IMSA110 also used cascading. 22-bit result synchronously clocked rising edge CLK. typical cascaded system this will connected Cascade Input port next device. last device cascade, this will output overall system. power after reset, Cout pins tristated. They enabled SCR[4]. Asynchronous input/output both these signals low, then microprocessor interface enabled. operation these enable signals very similar those found static RAMs. When either these signals high Write Enable address inputs ignored microprocessor interface Data signals high impedance. When both Enable signals read write access made registers RAMs within IMSA110. Access microprocessor interface occur asynchronously synchronous pins (PSRin, PSRout, Cin, Cout) device. Write Enable indicates whether access A110 memory interface read write. write access indicated. ADR[8-0] nine binary value applied address inputs IMSA110 indicates which register location within device accessed. D[7-0] During write microprocessor interface 8-bit word applied Data pins which written appropriate location. During read cycle contents location accessed placed Data pins. When either Enables high Data pins high impedance. REGISTER DESCRIPTION Memory Within IMSA110 addresses fully decoded. Reading from locations defined memory will produce zero data. Data written such locations ignored. This allows part fully programmed using with address incremeter. this case, future compatibility, zero should written undefined locations.
13/26
IMSA110
Register CR0a CR0b CR0c CR1a CR1b CR1c PCRA PCRB PCRC Address decimal 16-22 32-38 64-70 80-86 96-102 128-129 130-131 132-133 160-163 176-178 184-186 248-251 252-255 256-511 Address 000-006 010-016 020-026 040-046 050-056 060-066 080-081 082-083 084-085 0A0-0A3 0B0-0B2 0B8-0BA 0F8-0FB 0FC-0FF 100-1FF Function Coefficient Registers Bank Coefficient Registers Bank Coefficient Registers Bank Coefficient Registers Bank Coefficient Registers Bank Coefficient Registers Bank PSRA Control Register PSRB Control Register PSRC Control Register Static Control Register Active Control Register Backend Configuration Register Maximum/Minimum Buffer Copy Overshoot/Undershoot Buffer Copy Test Control Register Upper Saturation Register Lower Saturation Register Look Table
Registers CR0a Coefficient registers bank These seven 8-bit locations contain coefficients which used third, three, 7-stage arrays. CR0a(0) (address #000) corresponds coefficient register this array nearest output. Similarly CR0a(6) (address #006) corresponds coefficient register this nearest input. These Coefficient registers written provided that other register bank use. Whether coefficient written signed unsigned determined `Unsigned Coefficient' SCR[3]. Once value written coefficient register, value read back from
internal duplicate register. These registers will used array, when ACR[0], `Current Bank' zero. Writing these Coefficient Registers while will result undefined operation array. CR0b Coefficient registers bank These seven 8-bit locations contain coefficients which used second, three, 7-stage arrays chain. CR0b(0) (address #010) corresponds coefficient register this array nearest output. Similarly CR0b(6) (address #016) corresponds coefficient register this nearest input. Their behaviour otherwise identical CR0a.
14/26
IMSA110
Figure IMSA110 Memory
Address (Hex) 0FC-0FF 0F8-0FB 0B8-0BA 0B0-0B2 BCR3 Normaliser Control output byte Half Wave PosLUT Addr Enable
Name
Look Table Lower Saturation Register Upper Saturation Register Copy Over/UnderShoot Buffer Over/UnderShoot Buffer Copy Min/Max Buffer Min/Max Buffer Dynamic normalisation output adder
BCR2 BCR1 BCR0
Full Wave
output byte
Look Prescaler Static threshold Greater Than Zero Cascade Unsigned Data Backend Access Bypass PSRs Current Bank Cont Swap
Output Scaler Cascade Enable Unsigned Coef Load
PCRC PCRC PCRB PCRB PCRA PCRA CR1c
Shift Length (Upper Bits) Shift Length (Upper Bits) Shift Length (Upper Bits)
Shift Length (Lower Bits) Shift Length (Lower Bits) Shift Length (Lower Bits) Bank Coefficient Register
CR1b
Bank Coefficient Register
CR1a
Bank Coefficient Register
CR0c
Bank Coefficient Register
CR0b
Bank Coefficient Register
CR0a
Bank Coefficient Register
15/26
IMSA110
CR0c Coefficient registers bank These seven 8-bit locations contain coefficients which used first, three, 7-stage arrays chain. CR0c(0) (address #020) corresponds coefficient register this array nearest output. Similarly CR0c(6) (address #026) corresponds coefficient register this nearest input. Their behaviour otherwise identical CR0a. CR1a Coefficient registers bank These seven 8-bit locations contain coefficients which used third, three, 7-stage arrays chain. CR1a(0) (address #040) corresponds coefficient register this array nearest output. Similarly CR1a(6) (address #046) corresponds coefficient register this nearest input. These registers will used provided that ACR[0], `Current Bank'is one, continuous bank swap mode operation (SCR[0] one). CR1b Coefficient registers bank These seven 8-bit locations contain coefficients which used second, three, 7-stage arrays chain. CR1b(0) (address #050) corresponds coefficient register this array nearest output. Similarly CR1b(6) (address #056) corresponds coefficient register this nearest input. Their behaviour otherwise identical CR1a. CR1c Coefficient registers bank These seven 8-bit locations contain coefficients which used second, three, 7-stage arrays chain. CR1c(0) (address #060) corresponds coefficient register this array nearest output. Similarly CR1c(6) (address #066) corresponds coefficient register this nearest input. Their behaviour otherwise identical CR1a. PCRA PSRA Control register This 16-bit register, with least significant byte location #080, used length last shift register chain. Programmed lengths outside range 1120 will cause undefined behaviour shift register. PCRB PSRB Control register This 16-bit register, with least significant byte location #082, used length second shift register chain. Programmed lengths outside range 1120 will cause undefined behaviour shift register.
16/26
PCRC PSRC Control register This 16-bit register, with least significant byte location #084, used length first shift register chain. Programmed lengths outside range 1120 will cause undefined behaviour shift register. Static control register Static Control Register contains control bits which parts A110 which likely need reconfiguration during processing. contents this register affected A110 read time. Modifying Static Control register during processing will result undefined behaviour. Normal operation will start occur between clock cycles after completion write cycle. Active control register Active Control Register contains status control bits which likely accessed during normal operation A110. Backend configuration register Backend Configuration Registers consist four byte-wide registers BCR0, BCR1, BCR2, BCR3 which located addresses #0A0, #0A1, #0A2, #0A3 respectively. These four registers used control backend post-processing unit. None control bits these registers modified A110. Modification values these registers during processing result undefinedbehaviour.Normal operation will start occur between clock cycles after completion write cycle. Maximum/minimum buffer These three locations hold 24-bit wide word, with least significant byte lowest address, buffer between microprocessor interface. transactions between host processor must take place through this register. When use, value this buffer undefined. Copy This location used enable data transfer between MMR. write this location causes contents copied into bits (the cascade adder overflow flags) zero. read from this location causes reverse, contents copied into MMB. value written this location ignored, value read back undefined.
IMSA110
Overshoot/undershoot buffer These three memory locations hold 22-bit word, with least significant byte lowest address, buffer between microprocessor interface. transactions between host processor must take place through this register. When use, value this buffer undefined. Copy This location memory used enable data transfer between OUC. write this location causes contents copied into OUC. read from this location causes reverse, contents copied into OUB. value written this location ignored, value read back will undefined. Test control register This register used testing, should loaded with zero normal operation. Upper saturation register This 32-bit value with least significant byte lowest address. contents used replace output positive overflow(s) occur look prescaler cascade adder.Accesses from microprocessor interface only made while ACR[1] zero. Lower saturation register This 32-bit value with least significant byte lowest address. contents used replace output negativeoverflow(s) occur look prescaler cascade adder.Accesses from microprocessor interface only made while ACR[1] zero. Look table These locations 256-byte look table which used data mapping transformation operations. From microprocessor interface, these locations addressed same that seen 8-bit output look prescaler. When used mode, locations treated same other registers: Word most significant byte #103, least significant byte #100, Word most significant byte #133, least significant byte #130. Accesses from microprocessor interface only made while ACR[1] zero. REGISTERS ALLOCATION This section describes register details bit. Each section commences with name register with number(s) followed default value, general format:
Name REGISTER [MSB-LSB] Default MSB.LSB
least significant register tables indicates default state register bit(s). 10.1 control registers (PCR)
PSRA control PCRA[10-0] Default:
These eleven least significant bits PCRA used specify length last Programmable Shift Register (PSRA). length shift register will numerically equal binary value loaded these bits. value loaded must range 1120 decimal. value outside this range written these bits behaviour shift register will undefined. After updating this register, behaviourof delay undefined clock cycles. Hence changing length from 1000 1001 delays, will result correct output only after 1023 cycles. This will also have propagate through backend before cascade output values will correct.
Reserved PCRA[15-11] Default: 00000
These most significant bits PCRA reserved. user should write zero these locations maintain compatibility with future products. value read from these locations will zero.
17/26
IMSA110
PSRB control PCRB[10-0] Default: Cascade Enable SCR[4] Default:
These eleven least significant bits PCRB used specify length second Programmable Shift Register (PSRB). length shift register will numerically equal binary value loaded these bits. value loaded must range 1120 decimal. value outside this range written these bits behaviour shift register will undefined. After updating this register will also have propagate through PSRA backend before cascade output values will correct
Reserved PCRB[15-11] Default: 00000
zero this location will force Cascade Output pins into tristate mode.
Unsigned coefficient load SCR[3] Default:
These most significant bits PCRB reserved. user should write zero these locations maintain compatibility with future products. value read from these locations will zero.
PSRC control PCRC[10-0] Default:
this one, format subsequently loaded coefficients become unsigned, with coefficient value assuming range between decimal. 8-bit coefficient with bits will represent +255 decimal. When this zero format subsequentlyloaded coefficients will twos complement corresponding numerical value will have range between -128 +127. changing this whilst coefficients being loaded, coefficients between -128 +255 used. unsigned format coefficients suitable when A110s combined obtain wider coefficients extended precision.
SCR[3] Coefficient type Signed coefficients Unsigned coefficients SCR[2] Default:
These eleven least significant bits PCRC used specify length first Programmable Shift Register (PSRC). length shift register will numerically equal binary value loaded these bits. value loaded must range 1120 decimal. value outside this range written these bits behaviour shift register will undefined. After updating this register will also have propagate through PSRB, PSRA backend before cascade output values will correct
Reserved PCRC[15-11] Default: 00000
Unsigned data
These most significant bits PCRC reserved. user should write zero these locations maintain compatibility with future products. value read from these locations will zero. 10.2 Static control register (SCR)
Reserved SCR[7] Default:
this one, A110 input data format will become unsigned, with input data value assuming range between decimal. 8-bit value with bits will represent +255 decimal. When this zero input data format will twos complement corresponding numerical value will have range between -128 +127.Unlike SCR[3], this cannot used dynamically alter data format. unsigned format suitable when A110s combined obtain wider input data extended precision.
SCR[2] Signed data Unsigned data Default: Data type
This location reserved. user should write zero this location maintain compatibility with future products. value read from this location will zero.
Positive Look table address SCR[6] Default:
Bypass shift registers SCR[1]
This affects which over/under select detector checks address. determines whether address range signed (-128 127) positive 255). this location indicates positive address.
Enable SCR[5] Default:
zero this location will force Outputpins into tristate mode.
18/26
This used program path between PSRin PSRout ports. zero this location will cause output from last programmable shift register sent PSRout port. Writing this will cause three programmable shift registers bypassed, data entering port PSRin directly, delay clock cycles, port PSRout. This allows full programmability cascade arrangement that same hardware operated variety ways.
IMSA110
Continous bank swap SCR[0] Default:
continuous bank Swap selects whether banks coefficient registers used alternately after each data input this controlled solely state `Current Bank' Active Control Register ACR[0].
SCR[0] Swap mode Swap asserting ACR[0] Swap after each input cycle
full-wave rectified (absolute value operation) before remainder backend. This will override function BCR0[6].
Enable half-wave rectification BCR0[6] Default:
Writing this will cause negative values from cascade adder replaced with zero. Note that writing into BCR0[7] will override function this control bit.
BCD0[7-6] Rectifier mode Straight through Half wave rectification Full wave rectification Full wave rectification BCR0[5-1] Default: 00000
10.3 Active control register (ACR)
Reserved ACR[7-2] Default: 00000
These most significant bits reserved. user should write zero these locations maintain compatibility with future products. value read from these locations will zero.
Enable look table ACR[1] Default:
array output scaler
Writing zero into this control allows memory interface access Look table; output data transformation unit will zero. normaliser will controlled BCR3[7-3], regardless state BCR3[2]. Writing ACR[1] allows A110 Look Table. After changing this bit, clock cycles must occur before Look Table accessed.
ACR[1] Current bank mode Memory interface access Data transformation unit ACR[0] Default:
contents these five bits control amount right left shift applied data output array. This field interpreted two's complement number. positive number represents right shift (divide). shift range (11000) (01000) legal. Values outside this range will result undefined behaviour output scaler.
Zero cascade input BCR0[0] Default:
This controls Cascade Input Multiplexer. Writing this will cause zero, instead cascade input data, cascade adder.
BCR[0] Cascade input mode Cascade data Zero
When `Continuous Bank Swap' zero, writing zero into this control instructs A110 coefficient registers addresses #X26. Setting this instructs A110 coefficient registers addresses #X66. `Continuous Bank Swap' one, then this only indicates bank selected first cycle continuous swap mode. Writing this whilst continuous bank swap mode (SCR[0]=1) will result undefined behaviour array.
ACR[0] Coefficient bank coefficient registers #X26 coefficient registers #X66
10.5 Backend control register (BCR1)
Reserved BCR1[7-2] Default: 00000
These locations reserved. user should write zero these locations maintain compatibility with future products. values read from these locations will zero.
Static threshold BCR1[1] Default:
10.4 Backend control register (BCR0)
Enable full-wave rectification BCR0[7] Default:
this output cascade adder
this one, signals from comparator will used increment Over Undershoot Counter only. this zero, signals from comparator will used latch output Cascade Adder into Maximum Minimum Register (MMR), increment counter. this case counter will have been incremented number times that threshold been updated.
19/26
IMSA110
Enable greater than BCR1[0] Default:
This control determines whether comparator statistics monitor behaves `greater than', `less than' comparator. signal from this comparator used drive Over Undershoot Counter Register. this location selects `greater than'.
BCR1[1-0] Statistics monitor mode Min. register Max. register Undershoot counter Overshoot counter
(arithmetic) right shift applied data, Look Prescaler. Writing numerical value between (binary 10000) into these bits, will cause data right-shifted corresponding number places. example, pattern 00101 written these five positions, right shift places will occur. Writing value outside range will result undefinedbehaviour look Prescaler. 10.7 Backend control register (BCR3)
Normalizer control BCR3[7-3] Default: 00000
10.6 Backend control register (BCR2)
Reserved BCR2[7] Default:
This location reserved. user should write zero this location maintain compatibility with future products. value read from this location will zero.
Pass data least significant output BCR2[6] Default:
These five bits control number places, that normaliser shifts data right left. This field interpreted twos complement number. positive number taken right shift. shift range (11110)to (01110) legal. other value will cause number zero output from normaliser.
Enable dynamic normalization BCR3[2] Default:
this one, normaliser will controlled bits from output look table, instead BCR3[7-3].
Feed data output adder BCR3[1] Default:
This controls output multiplexer. this one, selected byte from output least significant byte (bits Cascade Output pins.
Pass data most significant output BCR2[5] Default:
This controls output multiplexer. this one, selected byte from output most significant byte (bits Cascade Output pins.
Look prescaler BCR2[4-0] Default: 00000
inputs Output Adder either supplied Look Table forced zero. Setting this control zero selects zero. Setting this control selects bits Look Table.
Reserved BCR3[0] Default:
contents these five bits control amount
This location reserved. user should write zero this location maintain compatibility with future products. value read from this location will zero.
20/26
IMSA110
ELECTRICAL SPECIFICATION 11.1 electrical characteristics ABSOLUTE MAXIMUM RATINGS
Symbol Tstg PDmax Parameter supply voltage Voltage other Temperature under bias Storage temperature Power dissipation Min. -1.0 Typ. Max. VCC+0.5 Units Notes (1,2)
Notes voltages with respect GND. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Stresses greater than those listed cause permanent damage device. Exposure absolute maximum rating conditions extended periods affect reliability. This device contains circuitry protect inputs against damage caused high static voltages electrical fields. However, advised that normal precautions taken avoid application voltage higher than absolute maximum rated voltages this high impedence circuit. Unused inputs should tied appropriate logic level such GND.
OPERATING CONDITIONS
Symbol Parameter Supply Voltage Input Logic Voltage Input Logic Voltage other pins Input Logic Voltage Input Logic Voltage other pins Ambient Operating Temperature Min. -0.5 -0.5 Typ. Max. VCC+0.5 VCC+0.5 Units Notes
Notes voltages with respect GND. Input signal transients, 10ns wide, permitted voltage ranges (GND 0.5V) (GND 1.0V) 0.5V 1.0V. linear ft/min transverse flow.
CHARACTERISTICS
Symbol
Notes
Parameter Output Logic Voltage Output Logic Voltage Input leakage current(any input current) state output leakage current Average power supply current
Min.
Typ.
Max.
Units
Notes (1,2)
voltages with respect GND. Parameters measured over full voltage temperature operating range. VCC(max), IOut -4.4 IOut
CAPACITANCE
other pins
Notes This parameter supplied engineering guidance guaranteed. 25°C MHz.
Min.
Typ.
Max.
Units
Notes
21/26
IMSA110
11.2 Thermal Characteristics GRID ARRAY THERMAL CHARACTERISTICS
Symbol Parameter Junction ambient thermal resistance Units °C/W Notes
Notes Measured linear ft/min transverse flow. This parameter sampled 100% tested.
11.3 timing characteristics test conditions OUTPUT LOADS (except output turn-off tests) 30pF outputs. Figure Output Load (output turn-off tests)
30pF
1.5V
TIMING REFERENCE LEVELS
INPUTS OUTPUTS OUTPUTS
Notes
Reference levels 0.8V, 2.0V 0.5V, 4.0V 0.4V, 2.4V ±100mV change from previous steady output voltage
Notes
Except CLK. Output continously driven. Timings tested using VOL=0.8V with suitable allowance time taken output fall from 0.8V 0.4V. Output turn-off tests.
11.4 Timing diagrams CLOCK REQUIREMENTS
Symbol tCHCL tCLCH tCHCH Parameter Clock Pulse High Width Clock Pulse Width Clock Period Clock rise time Clock fall time Typ. Units Notes
Notes Clock input transitions should monotonic between input thresholds Rev.A parts tCHCL, tCLCH tCHCH have maximum values 000ns, 000ns 000ns respectively. minimum clock frequency 10kHz.)
22/26
A110-08.EPS
sink
source
IMSA110
Figure
CHCL
4.0V 0.5V CLCH CHCH
A110-09.EPS
MICROPROCESSOR INTERFACE READ CYCLE
Symbol tAVEL tEHAX tWHEL tEHWX tELQX tELQV tEHQX tEHQZ Address setup Address hold Read Command Setup Read Command Hold Output turn-on Read data access Read data hold Output turn Parameter Units Notes
Figure
AVEL ADDRESS
WHEL
ELQV DATA ELQX
EHQX
EHQZ
23/26
A110-10.EPS
IMSA110
MICROPROCESSOR INTERFACE WRITE CYCLE
Symbol tELEH tAVEL tEHAX tWLEL tEHWX tDVEH tEHDX Enable Width Address setup Address hold Write Command Setup Write Command Hold Write data Write data hold Parameter Units Notes
Figure
ELEH
AVEL ADDRESS
EHAX
WHEL DVEH
EHWX
EHDX
A110-11.EPS
DATA
24/26
IMSA110
SYNCHRONOUS INPUT OUTPUT
Symbol tCHQV tCHQX tDVCH tCHDX high Output Valid Output hold time after Input setup time high Input hold time high Parameter Units Notes
Figure
INPUT DVCH CHDX
CHQV CHQX
A110-12.EPS
OUTPUT
25/26
IMSA110
PACKAGE MECHANICAL DATA PINS GRID ARRAY PACKAGE
index
PMPGA100.EPS
Millimetres 26.924 17.019 18.796 2.456 4.572 3.302 0.457 1.143 22.860 2.540 0.508 0.254 0.127 0.127 0.278 0.127 0.127 0.051 0.127 0.127 0.127 1.060 0.670 0.740 0.097 0.180 0.130 0.018 0.045 0.900 0.100 0.020
Inches 0.010 0.005 0.005 0.011 0.005 0.005 0.002 0.005 0.005 0.005
Notes
diameter Flange diameter
PGA100.TBL
Chamfer
Information furnished believed accurate reliable. However, SGS-THOMSON Microelectronics assumes responsibility consequences such information infringement patents other rights third parties which result from use. licence granted implication otherwise under patent patent rights SGS-THOMSON Microelectronics. Specifications mentioned this publication subject change without notice. This publication supersedes replaces information previously supplied. SGS-THOMSON Microelectronics products authorized critical components life support devices systems without express written approval SGS-THOMSON Microelectronics. 1994 SGS-THOMSON Microelectronics Rights Reserved Purchase Components SGS-THOMSON Microelectronics, conveys license under Philips Patent. Rights these components system, granted provided that system conforms Standard Specifications defined Philips. SGS-THOMSON Microelectronics GROUP COMPANIES Australia Brazil China France Germany Hong Kong Italy Japan Korea Malaysia Malta Morocco Netherlands Singapore Spain Sweden Switzerland Taiwan Thailand United Kingdom U.S.A.
26/26
Other recent searches
TPS54310 - TPS54310 TPS54310 Datasheet
NTE2960 - NTE2960 NTE2960 Datasheet
MS-156NB - MS-156NB MS-156NB Datasheet
MHW2727 - MHW2727 MHW2727 Datasheet
HUF75852G3 - HUF75852G3 HUF75852G3 Datasheet
BC546 - BC546 BC546 Datasheet
BC549 - BC549 BC549 Datasheet
BC550 - BC550 BC550 Datasheet
BC556 - BC556 BC556 Datasheet
BC560 - BC560 BC560 Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
