µPD98411 AQUAD SONET FRAMER µPD98411 NEASCOT-P40 ATM-LAN LSI

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µPD98411 AQUAD SONET FRAMER µPD98411 NEASCOT-P40 ATM-LAN LSI

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INTEGRATED CIRCUIT
µPD98411
AQUAD SONET FRAMER
µPD98411 NEASCOT-P40 ATM-LAN LSIs provides functions sublayer SONET/SDH-base physical layer Aprotocol specified AForum. main functions include transmission function Acell passed from Alayer payload 155M-bps SONET STS3c/SDH STM-1 frame transmit cell (Physical Media Dependent) sublayer physical layer, reception function separate overhead Acell from data string received from device transmit Acell Alayer. µPD98411 NEASCOT-P40 combines these transmission This ideally suited /reception functions into port function that realized single 4-port chip.
Ahubs, Aswitches, other equipment used configure Anetwork. addition, µPD98411 also clock recovery function each port extract synchronous clock reception receive data from stream, clock synthesis function generate clock transmission. details functional description, refer following user's manual.
µPD98411 User's Manual S12736E
FEATURES
Incorporates Auser network interface sublayer function four channels. Conforms AFORUM v3.1. Incorporates four clock recovery PLLs clock synthesizer PLL. Conforms AFORUM UTOPIA Level v1.0.
Alayers selected from multi-PHY interface Mbps) several different modes.
Single 16-bit Single 8-bit Dual 8-bit 1TCLAV/1RCLAV (Cell Available signal mode) Direct Status Indication mode Multiplexed Status Polling mode
management interface either modes.
RD-WR-RDY style (Intel-compatible mode) DS-R/W-ACK style (Motorola-compatible mode)
line-side interface accepts P-ECL level input. Supports loopback function. Supports pseudo error generation frame transmission function. Incorporates general input port channel three output ports (each able drive LED) channel. Supports JTAG boundary scan test (IEEE 1149.1).
information this document subject change without notice. Before using this document, please confirm that this latest version.
devices/types available every country. Please check with local representative availability additional information.
Document S12953EJ4V0DS00 (4th edition) Date Published January 1999 CP(K) Printed Japan ©NEC Corporation 1997,1999
µPD98411
Incorporates wide range operation, administration, maintenance (OAM) functions. Transmission
Alarm Condition Failure Detection Line AIS/Path Line RDI/Path Line Quality Monitoring Insertion B1-byte computation Insertion B2-byte computation Insertion B3-byte computation Automatic transmission Line Automatic transmission Path
Reception
Alarm Condition Failure Detection External input signal change Line AIS/Path Line RDI/Path Notification Degraded Line Quality error error error Line Path Frequency justification FIFO overflow Line Quality Monitor Counter error counter error counter error counter Line counter Path counter Frequency justification counter processing dropped cell counter FIFO overflow dropped cell counter Received idle cell counter Valid cell counter
0.35-µm CMOS process power consumption; +3.3 single-voltage power supply
ORDERING INFORMATION
Part Number Package 240-pin plastic (fine pitch)
µPD98411GN-MMU
Data Sheet S12953EJ4V0DS00
µPD98411
APPLICATIONS
following examples application using µPD98411.
ASwitches
µPD98411
AInterface
OC-12 SONET Framer
µPD98411
SWITCH
Backbone Network
µPD98411
µPD98411
UTOPIA Level2
Data Sheet S12953EJ4V0DS00
µPD98411
SYSTEM CONFIGURATION
µPD98411 System Application
(PECL)
Status
(19.44M)
Optical Module
Multimode Fiber
PD98411
ALayer Device UTOPIA
Optical Module
(NEASCOT-P40)
Equalizer Components Magnetics RJ-45 Connector Shielded Twist Pair
UTOPIA Management
Equalizer Components
Magnetics
RJ-45 Connector
Processor
Connection transceiver/receiver following show example connecting µPD98411 optical transceiver. Since
µPD98411 operates coupling circuit should added connected device.
µPD98411
Port0
3.3V 0.1µF
RDIT0 RDIC0 TDOT0 TDOC0
optical transceiver
RSDT RSDC TXDT TXDC
1.1k 1.1k
0.1µF PECL->TTL translator MC10H350 Motorola, etc.
VCCR VCCT VEER VEET
Data Sheet S12953EJ4V0DS00
µPD98411
UTOPIA Interface UTOPIA interface transfers transmit/receive cell data device upper Alayer. version June '95" standard.
Mode Dual eight-bit bus. this mode, 8-bit data used ports. Ports transfer signals using eight-bit bus, while ports transfer signals using another eight-bit bus. ports operate independently. indicate Cell Available state TCLAV RCLAV signal mode TCLAV RCLAV signal mode outputs TCLAV RCLAV signal status information four ports µPD98411 multiplexing them into single signal.
µPD98411
Port0 TCLAV RCLAV Port1
interface
between µPD98411 Alayer conforms "MPHY Data Path Operation" "UTOPIA Level
µPD98411
Port0
UTOPIA 8-bit
Alayer device
Port1
Alayer Device
Port2
8-bit
Port3
Alayer device
Port2
16-bit
Port3
TADD RADD
Single eight-bit bus. this mode, cell data four ports transferred through eight-bit bus. maximum transfer rate Mbps bits MHz).
Direct Status Indication Mode
µPD98411 four TXCLAV RXCLAV status signals, pair TXCLAV RXCLAV each port. Status signals cell transfers independent each other. address information needed obtain status information.
µPD98411
Port0 Port1
UTOPIA
Port0 TCLAV3-TCLAV0
Port1
8-bit
Port2 Port3
Alayer device
µPD98411
Port2
RCLAV3-RCLAV0 16-bit
Alayer Device
Port3
TADD RADD
Single sixteen-bit bus. this mode, cell data four ports transferred through sixteen-bit bus. maximum transfer rate Mbps bits MHz).
Multiplexed Status Polling Mode When more µPD98411s connected Alayer, Alayer obtain status information connected ports clock cycles which transmits receives
µPD98411
Port0 Port1
single data cell. Because minimum clock cycles
UTOPIA
required obtain TCLAV/RCLAV signal status port Alayer polling. Therefore every port address allocated fixed manner four status signals eight
16-bit
Port2 Port3
Alayer device
port groups.
Data Sheet S12953EJ4V0DS00
155.52 PECL serial interface
Conforms UTOPIA level multi-PHY interface Mbps Clock Recovery
BLOCK DIAGRAM
framer block timing generation Descramble generation Overhead extraction framer block Scramble timing generation generation Overhead setup
Acell processor block Cell descramble Cell synchronization Idle cell drop
compare/control
Port0
Alayer interface
Data Sheet S12953EJ4V0DS00
interface (PECL IN/OUT)
Port1
interface (PECL IN/OUT)
FIFO cells)
Acell processor block generation Cell scramble Cell mapping Idle cell insertion
FIFO cells)
Clock Recovery interface (PECL IN/OUT)
framer block S/PTX Framer Block block framer
Clock recovery
Acell processor block
FIFO
Clock recovery interface (PECL IN/OUT)
ACells Operate Block Acell processor block
FIFO Cells
FIFO
S/PTX Framer Block framer block framer block
ACells Operate Block Acell processor block
FIFO Cells
FIFO
Port2
Acell processor block
FIFO
Port3
Clock Synthesizer
sequencer Mode registers Test registers Performance registers
Interrupt cause registers
JTAG
Tx/Rx overhead registers
Management interface
µPD98411
Interface Address: bits Data: bits
µPD98411
FUNCTIONAL GROUPS
JRSTB JTAG boundary scan interface +3.3 RCLK1 RCLK2 RENBL1_B RENBL2_B RCLAV0 RCLAV1 RCLAV2 RCLAV3 RADD1[4:0] RADD2[4:0] RSOC1 RSOC2 RDO[15:0] RPR1 RPR2 RDIT0/RDIC0 (differential input) TDOT0/TDOC0 (differential input) RDIT1/RDIC1 (differential input) TDOT1/TDOC1 (differential input) interface RDIT2/RDIC2 (differential input) TDOT2/TDOC2 (differential input) RDIT3/RDIC3 (differential input) TDOT3/TDOC3 (differential input) TFKT/TFKC (differential input) REFCLK REFCLK-2nd CSSEL RXFP TXFP TFSS XLFC MADD[8:0] MDATA[7:0] CS_B DS/RD_B Management interface RW/WR_B ACK/RDY_B BMODE RESET_B PHINT0_B PHINT1_B PHINT2_B PHINT3_B PALM0[2:0] PALM1[2:0] PALM2[2:0] PALM3[2:0] Alarm signal output CMD0 CMD1 CMD2 CMD3 External alarm signal input TCLK1 TCLK2 TENBL1_B TENBL2_B TCLAV0 TCLAV1 TCLAV2 TCLAV3 TADD1[4:0] TADD2[4:0] TSOC1 TSOC2 TDI[15:0] TPR1 TPR2
UTOPIA interface (Rx)
UTOPIA interface (Tx)
signal input
Data Sheet S12953EJ4V0DS00
µPD98411
CONFIGURATION
240-pin plastic (fine pitch) (Top View)
Remark1.
internal connect pin.
Leave pins open.
this document, xxx_B stands active pin.
Data Sheet S12953EJ4V0DS00
µPD98411
ARRANGEMENT TABLE
(1/2)
Number Name RDO[11] RDO[12] RDO[13] RDO[14] RDO[15] RCLAV1 RCLAV0 RCLK1 RENBL1_B RADD1[0] RADD1[1] RADD1[2] RADD1[3] RADD1[4] ACK/RDY_B RW/WR_B DS/RD_B CS_B MADD[8] MADD[7] MADD[6] MADD[5] MADD[4] MADD[3] MADD[2] MADD[1] MADD[0] MD[7] MD[6] MD[5] MD[4] Number Name MD[3] MD[2] MD[1] MD[0] BMODE VDD-PEC TFKC TFKT GND-PEC CSSEL GND-CS VDD-CS REFCLK REFCLK-2nd JRST_B VDD-PE0 TDOT0 TDOC0 GND-PE0 GND-PE0 RDIC0 RDIT0 VDD-PE0 XLFC VDD-PE1 TDOT1 Number Name TDOC1 GND-PE1 GND-PE1 RDIC1 RDIT1 VDD-PE1 VDD-PE2 TDOT2 TDOC2 GND-PE2 GND-PE2 RDIC2 RDIT2 VDD-PE2 VDD-PE3 TDOT3 TDOC3 GND-PE3 GND-PE3 RDIC3 RDIT3 VDD-PE3 Number Name TXFP RXFP TFSS CMD3 CMD2 CMD1 CMD0 PALM3[2] PALM3[1] PALM3[0] PALM2[2] PALM2[1] PALM2[0] PALM1[2] PALM1[1] PALM1[0] PALM0[2] PALM0[1] PALM0[0] PHINT3_B PHINT2_B PHINT1_B PHINT0_B RESET_B TADD2[0] TADD2[1]
Data Sheet S12953EJ4V0DS00
µPD98411
(2/2)
Number Name TADD2[2] TADD2[3] TADD2[4] TENBL2_B TCLK2 TCLAV3 TCLAV2 TDI[0] TDI[1] TDI[2] TDI[3] TDI[4] TDI[5] TDI[6] TDI[7] TPR2 TSOC2 Number Name TADD1[0] TADD1[1] TADD1[2] TADD1[3] TADD1[4] TENBL1_B TCLK1 TCLAV1 TCLAV0 TDI[8] TDI[9] TDI[10] TDI[11] TDI[12] Number Name TDI[13] TDI[14] TDI[15] TPR1 TSOC1 RSOC2 RPR2 RDO[0] RDO[1] RDO[2] RDO[3] RDO[4] RDO[5] RDO[6] RDO[7] RCLAV3 Number Name RCLAV2 RCLK2 RENBL2_B RADD2[0] RADD2[1] RADD2[2] RADD2[3] RADD2[4] RSOC1 RPR1 RDO[8] RDO[9] RDO[10]
Data Sheet S12953EJ4V0DS00
µPD98411
NAME
ACK/RDY_B BMODE CMD3-CMD0 CS_B CSSEL DS/RD_B GND-CS GND-PE3, GND-PE2, GND-PE1, GND-PE0 GND-PEC JRST_B MADD[8:0] MD[7:0] PALM3[2:0], PALM2[2:0], PALM1[2:0], PALM0[2:0] PHINT3_B, PHINT2_B, PHINT1_B, PHINT0_B, RADD2[4:0], RADD1[4:0] Internal Receive System Clock Receive Address Physical Interrupt Ground TFKT/C PECL Block JTAG Clock JTAG Data Input JTAG Data Output JTAG Mode Select JTAG Reset Management Interface Address Management Interface Data Physical Alarm Output Signals TDOC3-TDOC0 TDOT3-TDOT0 TENBL2_B, TENBL1_B TFKC TFKT TFSS TPR2,TPR1 TSOC2,TSOC1 TxFP VDD-CS VDD-PE3, VDD-PE2, VDD-PE1, VDD-PE0 VDD-PEC Supply Voltage TFKT/C PECL Block XLFC Loop Filter Capacity Transmit Reference Clock Complement Transmit Reference Clock True Transmit Frame Signal Transmit Data Path Parity Transmit Start Cell Transmit Frame Pulse Supply Voltage Supply Voltage Analog Block Supply Voltage PECL Block Acknowledge/Ready Mode Command Signal Chip Select Clock Source Select Data Strobe/Read Ground Ground Analog Block Ground PECL Block REFCLK REFCLK-2nd RENBL2_B, RENBL1_B RESET_B RPR2, RPR1 System Reset Receive Data Path Parity System Clock Reference Cock Receive Data Enable
RSOC2, RSOC1 Receive Start Cell RW/WR_B RxFP SD3-SD0 TADD2[4:0], TADD1[4:0] Internal Transmit System Clock Management Interface Read/Write Receive Frame Pulse Signal Detect Transmit Address
TCLAV3-TCLAV0 Transmit Cell Available Signals TCLK2, TCLK1 TDI15-TDI0 Transmit DATA transferring Clock Transmit Data Input from ALayer Transmit Data Output Complement Transmit Data Output True Transmit Data Enable
RCLAV3-RCLAV0 Receive Cell Available Signals RCLK2, RCLK1 RDIC3-RDIC0 RDIT3-RDIT0 RDO[15:0] Receive Data Transferring Clock Receive Data Input Complement Receive Data Input True Receive Data Output
Data Sheet S12953EJ4V0DS00
µPD98411
CONTENTS
FUNCTIONS
1.10 Interface UTOPIA Interface Management Interface Alarm Signal Input/output JTAG Boundary Scan Power Supply Ground Others Disipation Unused Pins Initial State Pins Correspondence between UTOPIA Interface Modes Pins Used
ELECTRICAL CHARACTERISTICS PACKAGE DRAWING RECOMMENDED SOLDERING CONDITIONS
Data Sheet S12953EJ4V0DS00
µPD98411
FUNCTIONS
Interface
Name RDIT3RDIT0 RDIC3RDIC0 TDOT3TDOT0 TDOC3TDOC0 SD3-SD0 105, 104, 119-116 Level P-ECL True(+) P-ECL Complement(-) P-ECL True(+) P-ECL Complement(-) CMOS Line signal detection signal input. Refers pins inputting (Signal Detect) signal line transceivers (such optical modules). this signal goes low, this port detects LOS. High: Normal REFCLK CMOS System clock (19.44MHz) input. Used source clock internal synthesizer PLL/clock recovery register operation. REFCLK-2nd CMOS Second system clock (19.44MHz) input. Refers inputting second source clock internal synthesizer PLL. This used unnecessary switch source clock synthesizer PLL. CSSC register (address 076H) specifies which REFCLK REFCLK-2nd clocks source block. REFCLK input selected default. Even when REFCLK-2nd used source clock synthesizer PLL, REFCLK used register operation well; therefore, necessary input clock. Low: state Transmit serial data output. Refers differential output P-ECL level. transmit clock. Receive serial data input. Refers differential input P-ECL level. Function
(1/3)
REFCLK REFCLK_2nd
Transmit synthesizer clock
155.52MHz transmit clock
Register REF_cnt
RXFP
CMOS
Receive frame pulse output (8kHz). pulse signal output synchronously with start receiving frame. pulse signal cycle clock length. internal FPMSK register (address: 07CH) used select which four ports will output pulse synchronous receiving frame. port selected default; therefore, using default will result output.
Data Sheet S12953EJ4V0DS00
µPD98411
(2/3)
Name XLFC Level Analog Function Loop filter capacity connection pin. Refers connecting loop filter synthesizer PLL. Leave open. TXFP CMOS Transmitting frame pulse signal output (8KHz). Outputs pulse signal synchronous with start transmission frame equivalent cycle clock length. setting internal FPMSK register (address: 07CH) selects which four ports should output pulse synchronous with transmitting frame. port selected default value; therefore, using default will result output. TFSS CMOS Frame transmission disable signal input. High input this pin, output data strings ports fixed either frame transmission stops. input, transmission restarts from start (the byte) frame. Transmission starts with output transmission synchronously with rising edge clock cycles after last rising edge clock which TFSS detected being high. CMOS Receive system clock output (19.44MHz). Each port uses 155.52MHz receive clock divided eight internal receive processing; this outputs this clock. Which port's system clock output selected setting relevant value RCMSK register (address: 07BH). using default value, clock port selected. During resetting when port selected, output. Also, this output REFCLK-2nd clock.
Data Sheet S12953EJ4V0DS00
µPD98411
(3/3)
Name Level CMOS Function Transmission system clock output (19.44 MHz). Each port uses 155.52MHz transmit clock divided eight internal transmit processing; this outputs this clock. Which port's system clock output selected setting relevant value TCMSK register (address: 07AH). During resetting when port selected, output. TFKT P-ECL True(+) TFKC P-ECL Complement(-) CSSEL CMOS Externally generated 155.52MHz transmit clock input. Refers inputting externally generated transmit clock (155.52MHz) when using internally mounted synthesizer PLL. This enabled setting CSSEL High. TFKT/TFKC enable signal input. This inputs enable signal TFKT/TFKC when inputting 155.52MHz clock from outside chip TFKT/TFKC pin. High: TFKT/TFKC enable Low: TFKT/TFKC disable
UTOPIA Interface
used each UTOPIA interface signal varies with mode selected internal MltUt register address 079H). Please refer table "Correspondence between UTOPIA Interface Modes Pins Used". (1/4) Name RDO[15:8] RDO[7:0] 239-237 219-215 213-211 Level CMOS 3-state Receive data buses. These 16-bit data pins transfer receive data Alayer device. Output made synchronous with startup RCLK clock. pins used varies depending UTOPIA interface mode selected MltUt register (address: 079H). Single 8-bit bus: RDO[7:0] Single 16-bit bus: RDO[15:0] Dual 8-bit bus: RDO[15:8]/RDO[7:0] RCLK2 RCLK1 CMOS Receive clock input. These pins accept receive data transfer clocks 50MHz. used varies depending UTOPIA interface mode selected MltUt register (address: 079H). Single 8-bit bus: RCLK2 Single 16-bit bus: RCLK1 Dual 8-bit bus: RCLK1/RCLK2 Function
Data Sheet S12953EJ4V0DS00
µPD98411
(2/4)
Name RSOC2 RSOC1 Level CMOS 3-state Function Receive cell starting location signal output. These pins output signal which indicates location first byte with regard Alayer device. used varies depending UTOPIA interface mode selected MltUt register (address: 079H). Single 8-bit bus: RSOC2 Single 16-bit bus: RSOC2 Dual 8-bit bus: RSOC1/RSOC2 RENBL2_B RENBL1_B CMOS Receive enable signal input. These pins input signal which indicates that corresponding Alayer device capable accepting receive data. used varies depending UTOPIA interface mode selected MltUt register (address: 079H). Single 8-bit bus: RENBL2_B Single 16-bit bus: RENBL1_B Dual 8-bit bus: RENBL1_B/RENBL2_B RCLAV3 RCLAV2 RCLAV1 RCLAV0 CMOS 3-state Receive cell transferable signal output. This signal informs Alayer device that cell more data exists receive FIFO. 1TCLAV&1RCLAV mode, RCLAV signal each port internally multiplexed output signal. four signals RCLAV0 RCLAV3, operation signal which used vary depending UTOPIA interface mode selected MltUt register (address: 079H). Single 8-bit bus: RCLAV2 Single 16-bit bus: RCLAV1 Dual 8-bit bus: RCLAV1/RCLAV2 Direct Status Indication (DSI) mode, four signals RCLAV0 RCLAV3 allocated each ports identify their FIFO statuses. RCLAV0 corresponds Port RCLAV3 Port RADD2[4:0] RADD1[4:0] 232-228 19-15 CMOS Receiving address input. These pins input address which selects port. Different pins used depending UTOPIA interface mode selected MltUt register (address: 079H). Single 8-bit bus: RADD2[4:0] Single 16-bit bus: RADD1[4:0] Dual 8-bit bus: RADD1[4:0]/RADD2[4:0]
Data Sheet S12953EJ4V0DS00
µPD98411
(3/4)
Name RPR2 RPR1 Level CMOS Parity output pins. parity bits generated output from these pins with respect data output from RDO15-RDO0. used varies depending UTOPIA interface mode selected MltUt register (address: 079H). Single 8-bit bus: RPR2 Single 16-bit bus: RPR2 Dual 8-bit bus: RPR1/RPR2 TDI[15:8] TDI[7:0] 204-202 199-195 176-174 172-168 CMOS Transmit data buses. These data buses input transmit data from Alayer device rising edge TCLK clock. used varies depending UTOPIA interface mode selected MltUt register (address: 079H). Single 8-bit bus: TDI[15:8] Single 16-bit bus: TDI[15:0] Dual 8-bit bus: TDI[15:8]/TDI[7:0] TCLK2 TCLK1 CMOS Transmit clock input. These pins input clocks 50MHz transmit data transfer. used varies depending UTOPIA interface mode selected internal MltUt register (address: 079H). Single 8-bit bus: TCLK1 Single 16-bit bus: TCLK2 Dual 8-bit bus: TCLK1/TCLK2 TSOC2 TSOC1 CMOS Transmit cell starting location signal input. These pins input signal which indicates location first byte transmit cell. used varies depending UTOPIA interface mode selected MltUt register (address: 079H). Single 8-bit bus: TSOC1 Single 16-bit bus: TSOC1 Dual 8-bit bus: TSOC1/TSOC2 TENBL2_B TENBL1_B CMOS Transmit enable signal input. These pins input signal which indicates that Alayer device outputting valid transmit data TDI[15]-TDI[0]. used varies depending UTOPIA interface mode selected internal MltUt register (address: 079H). Single 8-bit bus: TENBL1_B Single 16-bit bus: TENBL2_B Dual 8-bit bus: TENBL1_B/TENBL2_B Function
Data Sheet S12953EJ4V0DS00
µPD98411
(4/4)
Name TCLAV3 TCLAV2 TCLAV1 TCLAV0 Level CMOS 3-state Function Transmit cell acceptable signal output. signal informs Alayer device that unused storage space least cell available transmit FIFO. 1TCLAV&1RCLAV mode, TCLAV signal each port internally multiplexed output signal. four signals TCLAV0 TCLAV3, used varies depending UTOPIA interface mode selected MltUt register (address: 079H). Single 8-bit bus: TCLAV1 Single 16-bit bus: TCLAV2 Dual 8-bit bus: TCLAV1/TCLAV2 Direct Status Indication (DSI) mode, four pins TCLAV0 TCLAV3 allocated each ports signal signal, indicate FIFO statuses each port. TCLAV0 corresponds Port TCLAV3 Port TADD2[4:0] TADD1[4:0] 159-155 186-182 CMOS Transmission address input. These pins input address port selected. pins used vary depending UTOPIA interface mode selected MltUt register (address: 079H). Single 8-bit bus: TADD1[4:0] Single 16-bit bus: TADD2[4:0] Dual 8-bit bus: TADD1[4:0]/TADD2[4:0] TPR2 TPR1 CMOS Parity input pins. These pins input parity input from TD0[15]-TDO[0]. used varies depending UTOPIA interface mode selected MltUt register (address: 079H). Single 8-bit bus: TPR1 Single 16-bit bus: TPR1 Dual 8-bit bus: TPR1/TPR2
Data Sheet S12953EJ4V0DS00
µPD98411
Management Interface
Name BMODE Level CMOS Mode selection input. This input used select mode management interface. BMODE=: Selects <RD_B, WR_B, RDY_B> function. Selects <DS_B, R/W_B, ACK_B> function. MADD[8:0] 26-34 CMOS Address input. 9-bit addresses inputting internal register addresses. MD[7:0] CS_B 36-39 42-45 CMOS CMOS 3-state Chip select signal input. When level, access internal registers enabled. DS/RD_B CMOS Data strobe signal input read signal input. function this varies depending management interface mode selected BMODE input. BMODE Functions data strobe signal DS_B BMODE Function RD_B selecting read access RW/WR_B CMOS Read/write signal input write signal input. function this varies depending management interface mode selected BMODE input. When BMODE=0, functions Read/Write control signal R/W_B. R/W_B= High: Low: internal registers. ACK/RDY_B CMOS 3-state Data acknowledge signal output ready signal output. Outputs acknowledge ready signals which accept Read/Write cycle internal registers. PHINT3_BPHINT0_B 149-152 CMOS Interrupt signal output. These signals inform host that interrupt factor occurred. modes available this purpose: which indicates interrupt factor four ports using PHINT0_B signal other which uses four pins PHINT0-PHINT3 indicate individual interrupt each port. Port corresponds PHINT0_B pin; Port PHINT3_B. RESET_B CMOS System reset signal input. Initializes µPD98411. This input signal should kept more. Especially, case power abovementioned pulse width must kept after supply voltage reaches equal more than least. When RESET_B signal input, clock must input REFCLK pin. Read cycle Write cycle 8-bit data buses reading/writing internal register data. Function
When BMODE=1, functions WR_B selecting Write
Data Sheet S12953EJ4V0DS00
µPD98411
Alarm Signal Input/output
Name CMD0-CMD3 128-131 Level CMOS Function General-purpose input signal. Refers general-purpose input pins which input status signals, etc. from external peripheral devices. signal level these pins also reflected status bits internal registers, changes these bits used identify interrupt factors. Each port equipped with pin: CMD0 corresponds Port CMD3 Port PALM3[2:0] PALM2[2:0] PALM1[2:0] PALM0[2:0] 133-135 136-138 141-143 144-146 CMOS layer alarm detection signal output. These pins output signal notify that port detected alarm defect (LOS, OOF, LOF, OCD, LCD, Line AIS, Path AIS, Line RDI, Path RDI) that level input changed. Additionary, possible general output ports which reflects state internal register,too. events indicated selected seting AMPR, AMR1, AMR2 registers.
JTAG Boundary Scan
Name Level CMOS Function Refers boundary scan data input. When unused, connect this ground.
CMOS
3-state
Refers boundary scan data output. When unused, leave this open. Refers boundary scan clock input. When unused, connect this ground.
CMOS
CMOS
Refers boundary scan mode select signal input. When unused, connect this ground.
JRST_B
CMOS
Refers boundary scan reset signal input. When unused, connect this ground.
Data Sheet S12953EJ4V0DS00
µPD98411
Power Supply Ground
100, 120, 132, 140, 147, 160, 164, 173, 181, 187, 194, 201, 208, 214, 220, 227, 234, 101, 107, 121, 122, 139, 148, 154, 161, 167, 179, 180, 188, 191, 200, 207, 221, 224, VDD-PEC GND-PEC -TFKT/TFKC input high-speed part power supply (+3.3V±5%) ground. Noise from this power supply affects jitter characteristic. Eliminate noise through countermeasures such filters. VDD-CS GND-CS -Transmit clock synthesizer power supply (+3.3V±5%) ground. Noise from this power supply affects jitter characteristic. Eliminate noise through countermeasures such filters. VDD-PE3 VDD-PE2 VDD-PE1 VDD-PE0 GND-PE3 GND-PE2 GND-PE1 GND-PE0 102, -Each port high-speed section, receive clock recovery section power supply (+3.3V±5%). Noise from this power supply affects jitter characteristic. Eliminate noise through countermeasures such filters. Each port high-speed section, receive clock recovery section ground. Noise from this power supply affects jitter characteristic. Eliminate noise through countermeasures such filters. -I/O -Function Low-speed section logic power supply (+3.3V±5%) ground.
Name
Others
Name 108-115 Level CMOS -Function These refer internal circuit connection test pins. sure leave them open.
Data Sheet S12953EJ4V0DS00
µPD98411
Disipation Unused Pins
Take following actions with pins that unused certain modes.
Name RCLK2, RCLK1 RENBL2_B, RENBL1_B RADD2[4:0], RADD1[4:0] TDI[15:0] TCLK2, TCLK1 TSOC2, TSOC1 TENBL2_B, TENBL1_B TADD2[4:0], TADD1[4:0] TPR2, TPR1 RDO[15:0] RSOC2, RSOC1 RPR2, RPR1 RCLAV3-RCLAV0 TCLAV3-TCLAV0 CMD3-CMD0 SD3-SD0 TFKT/TFKC TFSS XLFC REFCLK-2nd Each output pins Connect them ground. Pull them Pull TFKT connect TFKC ground. Connect ground. Leave open. Connect ground Leave them open. Leave them open. Measure Connect them ground.
Data Sheet S12953EJ4V0DS00
µPD98411
Initial State Pins
Name RDO[15:0] RSOC2, RSOC1 RCLAV3-RCLAV0 TCLAV3-TCLAV0 RPR2, RPR1 PHINT3_B-PHINT0_B PALM3[2:0]-PALM0[2:0] RXFP TXFP MD[7:0] ACK/RDY_B TDOT3-TDOT0 TDOC3-TDOC0 Hi-Z Hi-Z During Resetting Hi-Z After Resetting Hi-Z
Data Sheet S12953EJ4V0DS00
µPD98411
1.10
Dual 8-bit Direct Status Indication Using TCLAV/ RCLAV signals (two-state outputs) 0101
Correspondence between UTOPIA Interface Modes Pins Used
Mode MSL[3:0] 0001 Port Port Port Port Port Port Port Port Pins Used omitted) TCLK1, TDI[15:8], TADD1, TPR1, TENBL1_B, TCLAV1, TSOC1 TCLK2, TDI[7:0], TADD2, TPR2, TENBL2_B, TCLAV2, TSOC2 RCLK1, RDO[15:8], RADD1, RPR1, RENBL1_B, RCLAV1, RSOC1 RCLK2, RDO[7:0], RADD2, RPR2, RENBL2_B, RCLAV2, RSOC2 TCLK1, TDI[15:8], TADD1, TPR1, TENBL1_B, TCLAV0-TCLAV1, TSOC1 TCLK2, TDI[7:0], TADD2, TPR2, TENBL2_B, TCLAV2-TCLAV3, TSOC2 RCLK1, RDO[15:8], RADD1, RPR1, RENBL1_B, RCLAV0-RCLAV1, RSOC1 RCLK2, RDO[7:0], RADD2, RPR2, RENBL2_B, RCLAV2-RCLAV3, RSOC2 TCLK1, TDI[15:8], TADD1, TPR1, TENBL1_B, TCLAV1, TSOC1 TCLK2, TDI[7:0], TADD2, TPR2, TENBL2_B, TCLAV2, TSOC2 RCLK1, RDO[15:8], RADD1, TPR1, RENBL1_B, RCLAV1, RSOC1 RCLK2,RDO[7:0], RADD2, TPR2, RENBL2_B, RCLAV2, RSOC2 TCLK1, TDI[15:8], TADD1, TPR1, TENBL1_B, TCLAV0-TCLAV1, TSOC1 TCLK2, TDI[7:0], TADD2, TPR2, TENBL2_B, TCLAV2-TCLAV3, TSOC2 RCLK1, RDO[15:8], RADD1, RPR1, RENBL1_B, RCLAV0-RCLAV1, RSOC1 RCLK2, RDO[7:0], RADD2, RPR2, RENBL2_B, RCLAV2-RCLAV3, RSOC2
TCLAV/2 RCLAV
Multiplexed Status Polling Using TCLAV/ RCLAV signals (three-state outputs) Multiplexed Status Polling Using TCAV/ RCLAV signals (three-state outputs)
1001
Port Port Port Port Port Port
1101
Port Port
Single 8-bit
TCLAV/1 RCLAV Direct Status Indication Using TCLAV/ RCLAV signals (two-state outputs) Multiplexed Status Polling Using TCLAV/ RCLAV signals (three-state outputs) Multiplexed Status Polling Using TCAV/ RCLAV signals (three-state outputs)
0010 0110
TCLK1, TDI[15:8], TADD1, TPR1, TENBL1_B, TCLAV1, TSOC1 RCLK2, RDO[7:0], RADD2, RPR2, RENBL2_B, RCLAV2, RSOC2 TCLK1, TDI[15:8], TADD1, TPR1, TENBL1_B, TCLAV0-TCLAV3, TSOC1 RCLK2, RDO[7:0], RADD2, RPR2, RENBL2_B, RCLAV0-RCLAV3, RSOC2 TCLK1, TDI[15:8], TADD1, TPR1, TENBL1_B, TCLAV1, TSOC1 RCLK2, RDO[7:0], RADD2, RPR2, RENBL2_B, RCLAV2, RSOC2 TCLK1, TDI[15:8], TADD1, TPR1, TENBL1_B, TCLAV0-TCLAV3, TSOC1 RCLK2, RDO[7:0], RADD2, RPR2, RENBL2_B, RCLAV0-RCLAV3, RSOC2 TCLK2, TDI[15:0], TADD2, TPR1, TENBL2_B, TCLAV2, TSOC1 RCLK1, RDO[15:0], RADD1, RPR2, RENBL1_B, RCLAV1, RSOC2 TCLK2, TDI[15:0], TADD2, TPR1, TENBL2_B, TCLAV0-TCLAV3, TSOC1 RCLK1, RDO[15:0], RADD1, RPR2, RENBL1_B, RCLAV0-RCLAV3, RSOC2 TCLK2, TDI[15:0], TADD2, TPR1, TENBL2_B, TCLAV2, TSOC1 RCLK1, RDO[15:0], RADD1, RPR2, RENBL1_B, RCLAV1, RSOC2 TCLK2, TDI[15:0], TADD2, TPR1, TENBL2_B, TCLAV0-TCLAV3, TSOC1 RCLK1, RDO[15:0], RADD1, RPR2, RENBL1_B, RCLAV0-RCLAV3, RSOC2
1010
1110
Single 16-bit
TCLAV/1 RCLAV Direct Status Indication Using four TCLAV/four RCLAV signals (two-state outputs) Multiplexed Status Polling Using TCLAV/one RCLAV signal (three-state outputs) Multiplexed Status Polling Using four TCLAV/four RCLAV signals (three-state outputs)
0011 0111
1011
1111
Data Sheet S12953EJ4V0DS00
µPD98411
ELECTRICAL CHARACTERISTICS
Note mark shows characteristics which changed from previous version.
Absolute Maximum Ratings Parameter Supply voltage Input/output voltage Symbol VI/VO Topt Tstg Pins except P-ECL VIA/VOA P-ECL pins Conditions Rating -0.5 +4.6 -0.5 +6.6 VDD+3.0 -0.5 +4.6 VDD+0.5 +150 Unit
Operating temperature Storage temperature Caution
even parameters exceeds absolute maximum rating even momentarily, quality product degraded. absolute maximum rating therefore specifies upper lower limit values which product used without physical damage. sure exceed fall below these values when using product.
Capacitance Parameter Input capacitance Output capacitance capacitance Symbol Conditions Frequency 1MHz Frequency 1MHz Frequency 1MHz MIN. MAX. Unit
Recommended Operating Conditions Parameter Symbol VILA High-level input voltage VIHA P-ECL differential input voltage VIDIFF Pins except P-ECL P-ECL pins Pins except P-ECL P-ECL pins P-ECL pins Conditions MIN. 0.95 -2.82 -1.49 MAX. 1.05 -1.50 5.25 -0.4 2.41 Unit
Supply voltage Operating ambient temperature Low-level input voltage
Data Sheet S12953EJ4V0DS00
µPD98411
Characteristics (VDD
Parameter Off-state output current Input leakage current Symbol IILA Conditions Pins except P-ECL P-ECL pins 59,65,66,67 pins P-ECL pins High-level output voltage Low-level output current VOHA P-ECL pins 0.4V, 3.3V Pins except P-ECL High-level output current Supply current 2.4V, 3.3V Pins except P-ECL During normal operation -9.0 -1.14 -0.92 -0.69 56.4 MIN. MAX. Unit
Internal Pull-down resistance Low-level output voltage
VOLA
-2.175 -1.975 -1.755
Characteristics (VDD
propagation delay time defined follows: 0.7VDD Input 0.3VDD 0.5VDD
Output
0.5VDD
Testing Load Circuit Test
Device Under Test CL=30pF Include Capacitance
Remark
case CL=50pF, operating condition changes
Data Sheet S12953EJ4V0DS00
µPD98411
Management Interface Internal Register Read
Parameter CS_B setting time (vs. DS_B[RD_B]) R/W_B[WR_B] setting time (vs. DS_B[RD_B]) Address hold time (vs. DS_B[RD_B]) CS_B hold time (vs. DS_B[RD_B]) R/W_B[WR_B] hold time (vs. DS_B[RD_B]) tHADDS tHCSDS tHRWDS tVAKDS tVDADS tIAKDS tIDADS tDDAAK tWDS tDSINT Load capacitance: Load capacitance: Load capacitance: Load capacitance: Load capacitance: 51.44 51.44 Symbol tSCSDS tSRWDS Conditions MIN. MAX. Unit Address setting time (vs. DS_B[RD_B]) tSADDS
DS_B[RD_B] ACK_B[RDY_B] output delay DS_B[RD_B] data output delay DS_B[RD_B] ACK_B[RDY_B] float delay DS_B[RD_B] data float delay ACK_B data output delay DS_B[RD_B] pulse width DS_B [RD_B] DS_B [RD_B] recovery time
tTCLK cycle TCLK. BMODE="0"
MADD[8:0]
tSADDS tHADDS tHCSDS tVDADS tDDAAK tIDADS tDSINT
CS_B MD[7:0] DS_B /RD_B
tSCSDS
tWDS
RW_B /WR_B
tSRWDS tHRWDS tVAKDS tIAKDS
ACK_B /RDY_B
)BMODE="1"
MADD[8:0] tSADDS CS_B MD[7:0] tVDADS tDDAAK DS_B /RD_B RW_B /WR_B tSRWDS ACK_B /RDY_B tVAKDS tIAKDS tHRWDS tIDADS tDSINT tSCSDS tHADDS tHCSDS
Data Sheet S12953EJ4V0DS00
µPD98411
Internal Register Write
Parameter Symbol Conditions MIN. MAX. Unit
Address setting time (vs. DS_B[RD_B]) CS_B setting time (vs. DS_B[WR_B]) R/W_B[RD_B] setting time (vs. DS_B[WR_B]) Data setting time (vs. DS_B[WR_B]) Address hold time (vs. DS_B[WR_B]) CS_B hold time (vs. DS_B[WR_B]) R/W_B[RD_B] hold time (vs. DS_B[WR_B]) Data hold time (vs. DS_B[WR_B])
tSADDS tSCSDS tSRWDS tSDADS tHADDS tHCSDS tHRWDS tHDADS tVAKDS tIAKDS tWDS tDSINT Load capacitance: Load capacitance:
51.44 51.44
DS_B[RD_B] ACK_B[RDY_B] output delay DS_B[RD_B] ACK_B[RDY_B] float delay DS_B [RD_B] pulse width DS_B [RD_B] DS_B [RD_B] recovery time
tTCLK cycle TCLK. )BMODE="0"
MADD[8:0] tSADDS CS_B tSCSDS MD[7:0] tSDADS DS_B /RD_B tWDS RW_B /WR_B tSRWDS ACK_B /RDY_B tVAKDS tIAKDS tHRWDS tDSINT tHDADS tHADDS tHCSDS
BMODE="1"
MADD[8:0] tSADDS CS_B MD[7:0] tSDADS RW_B/WR_B DS_B/RD_B tSRWDS ACK_B/RDY_B tVAKDS tIAKDS tHRWDS tWDS tDSINT tHDADS tSCSDS tHADDS tHCSDS
Data Sheet S12953EJ4V0DS00
µPD98411
Interface
Parameter Symbol Conditions Load capacitance: MIN. MAX. Unit
REFCLK PALM3[2:0] -PALM0 tDARRL [2:0] delay REFCLK PHINT3- PHINT tDRFINT delay
REFCLK tDARRL PALM3[2:0]PALM0[2:0]
REFCLK tDRFINT PHINT3_B-PHINT0_B tDRFINT
tDARRL
Control Signal Interface
Parameter TFSS setting time (vs. TCL) TFSS hold time (vs. TCL) Symbol tSTFTL tHTFTL tDTFTL tDRFRL tSCMRF tHCMRF tSSDRF tHSDRF Load capacitance: Load capacitance: Conditions MIN. MAX. Unit
TxFP delay RxFP delay setting time (vs. REFCLK) hold time (vs. REFCLK) setting time (vs. REFCLK) hold time (vs. REFCLK)
tDTFTL TFSS tSTFTL TXFP tDRFRL RXFP REFCLK CMD3-CMD0 tSCMRF SD3-SD0 tSSDRF tHSDRF tHCMRF tDRFRL tHTFTL tDTFTL
Data Sheet S12953EJ4V0DS00
µPD98411
UTOPIA Interface (transmission side)
Parameter TCLK cycle time TCLK high-level width TCLK low-level width Symbol tCYTK tWTKH tWTKL tDCATK tVCATK tICATK tSDITK tHDITK tSSOTK tHSOTK tSPRTK tHPRTK tSADTK tHADTK tSENTK tHENTK tCYTK tWTKH TCLK tSADTK TADD2[4:0] TADD1[4:0] TCLAV3-TCLAV0 tVCATK TENBL2_B, TENBL1_B TSOC2,TSOC1 tSDITK TDI[7:0] tSPRTK TPR2,TPR1 tHPRTK tHDITK tSSOTK tSENTK tDCATK tDCATK tHADTK tICATK tWTKL Load capacitance: Load capacitance: Load capacitance: Conditions MIN. 0.4xtCYTK 0.4xtCYTK MAX. 0.6x tCYTK 0.6x tCYTK Unit
TCLK TCLAV delay TCLK TCLAV output delay TCLK TCLAV data float delay TDI[0]-TDI[7] setting time (vs. TCLK) TDI[0]-TDI[7] hold time (vs. TCLK) TSOC setting time (vs. TCLK) TSOC hold time (vs. TCLK) setting time (vs. TCLK) hold time (vs. TCLK) TADD0- TADD setup time (vs. TCLK) TADD0- TADD7 hold time (vs. TCLK) TENBL_B setting time (vs. TCLK) TENBL_B hold time (vs. TCLK)
tHSOTK
tHENTK
Data Sheet S12953EJ4V0DS00
µPD98411
UTOPIA Interface (reception side)
Parameter RCLK cycle time RCLK high-level width RCLK low-level width Symbol tCYRK tWRKH tWRKL tDCARK tVCARK tICARK tDDORK tVDORK tIDORK tDSORK tVSORK tISORK tDPRRK tVPRRK tIPRRK tSADRK tHADRK tSENRK tHENRK Load capacitance: Load capacitance: Load capacitance: Load capacitance: Load capacitance: Load capacitance: Load capacitance: Load capacitance: Load capacitance: Load capacitance: Load capacitance: Load capacitance: Conditions MIN. 0.4xtCYRK 0.4xtCYRK MAX. 0.6xtCYRK 0.6xtCYRK Unit
RCLK RCLAV delay RCLK RCLAV output delay RCLK RCLAV data float delay RCLK delay RCLKRDO output delay RCLKRDO data float delay RCLK RSOC delay RCLK RSOC output delay RCLK RSOC data float delay RCLK delay RCLK output delay RCLK data float delay RADD setting time (vs. RCLK) RADD hold time (vs. RCLK) RENBLB setting time (vs. RCLK) RENBLB hold time (vs. RCLK)
tCYRK tWRKH RCLK RADD2[4:0], RADD1[4:0] RCLAV3-RCLAV0 RENBL2_B, RENBL1_B tSENRK RSOC2,RSOC1 tISORK RDO[15:0] tIDORK RPR2,RPR1 tIPRRK tVPRRK tDPRRK tDPRRK tVDORK tDDORK tDDORK tVSORK tDSORK tDSORK tDCARK tDCARK tICARK tVCARK tWRKL tSADRK tHADRK
tHENRK
Data Sheet S12953EJ4V0DS00
µPD98411
Interface (transmission side)
Parameter REFCLK cycle time
Note
Symbol tCYRF tWRFH tWRFL tCYSF
Conditions
MIN. -20ppm 0.4xtCYRF 0.4xtCYRF -0.005UI
51.4403
MAX. +20ppm 0.6xtCYRF 0.6xtCYRF
Unit
REFCLK high-level width REFCLK low-level width TFKT(C) cycle time Note
6.43
+0.005UI
transmit source clock which jitter below 0.01UI, basis signal which least equal more than 40-ppm precision must inputted.
When using Clock Synthesizer
tCYFR tWRFH REFCLK TDOT3-TADT0 (TDOC3-TDOC0) tWRFL
(ii) When using external serial clock
tCYSF TFKT (TFKC) TDOT3-TDOT0 (TDOC3-TDOC0)
Interface (reception side)
Parameter RDIT(C) setting time (vs. TFKT(C)) RDIT(C) hold time (vs. TFKT(C)) Symbol tSDISC tHDISC Conditions When using external When using external MIN. MAX. Unit
TFKT (TFKC) tSDISC RDIT3-RDIT0 (RDIC3-RDIC0) tHDISC
Data Sheet S12953EJ4V0DS00
µPD98411
PACKAGE DRAWING
240-PIN PLASTIC (FINE PITCH) (32x32)
detail lead
ITEM MILLIMETERS 34.6±0.2 32.0±0.2 32.0±0.2 34.6±0.2 1.25 1.25 0.22 +0.05 -0.04 0.10 (T.P.) 1.3±0.2 0.5±0.2 0.17 +0.03 -0.07 0.10 3.2±0.1 0.4±0.1 MAX.
NOTE Each lead centerline located within 0.10 true position (T.P.) maximum material condition.
P240GN-50-LMU, MMU, SMU-4
Data Sheet S12953EJ4V0DS00
µPD98411
RECOMMENDED SOLDERING CONDITIONS
conditions listed below shall when soldering this product. more details, refer document "Semiconductor Device Mounting Technology Manual (C10535E)". Please consult with sales offices case other soldering process used, case soldering done under different conditions.
Surface-mount devices 240-pin plastic (fine pitch) Soldering process Infrared reflow Soldering conditions Peak package's surface temperature :235° below, Reflow time seconds below (210 higher), Number reflow profess Exposure limit days hours pre-backing required 125C° afterwards) Terminal temperature :300 below, Flow time seconds below (Per side device).
Note
Symbol IR35-363-1
Partial heating method
Note
Exposure limit before soldering after dry-pack package opened. Storage conditions: relative humidity less.
Data Sheet S12953EJ4V0DS00
µPD98411
NOTES CMOS DEVICES
PRECAUTION AGAINST SEMICONDUCTORS
Note: Strong electric field, when exposed device, cause destruction gate oxide ultimately degrade device operation. Steps must taken stop generation static electricity much possible, quickly dissipate once, when occurred. Environmental control must adequate. When dry, humidifier should used. recommended avoid using insulators that easily build static electricity. Semiconductor devices must stored transported anti-static container, static shielding conductive material. test measurement tools including work bench floor should grounded. operator should grounded using wrist strap. Semiconductor devices must touched with bare hands. Similar precautions need taken boards with semiconductor devices
HANDLING UNUSED INPUT PINS CMOS
Note: connection CMOS device inputs cause malfunction. connection provided input pins, possible that internal input level generated noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar NMOS devices. Input levels CMOS devices must fixed high using pull-up pull-down circuitry. Each unused should connected with resistor, considered have possibility being output pin. handling related unused pins must judged device device related specifications governing devices.
STATUS BEFORE INITIALIZATION DEVICES
Note: Power-on does necessarily define initial status device. Production process does define initial operation status device. Immediately after power source turned devices with reset function have been initialized. Hence, power-on does guarantee out-pin levels, settings contents registers. Device initialized until reset signal received. Reset operation must executed immediately after power-on devices having reset function.
Data Sheet S12953EJ4V0DS00
µPD98411
NEASCOT-P40 trademark corporation.
export this product from Japan prohibited without governmental license. export re-export this product from country other than Japan also prohibited without license from that country. Please call sales representative.
information this document subject change without notice. Before using this document, please confirm that this latest version. part this document copied reproduced form means without prior written consent Corporation. Corporation assumes responsibility errors which appear this document. Corporation does assume liability infringement patents, copyrights other intellectual property rights third parties arising from device described herein other liability arising from such device. license, either express, implied otherwise, granted under patents, copyrights other intellectual property rights Corporation others. Descriptions circuits, software, other related information this document provided illustrative purposes semiconductor product operation application examples. incorporation these circuits, software, information design customer's equipment shall done under full responsibility customer. Corporation assumes responsibility losses incurred customer third parties arising from these circuits, software, information. While Corporation been making continuous effort enhance reliability semiconductor devices, possibility defects cannot eliminated entirely. minimize risks damage injury persons property arising from defect semiconductor device, customers must incorporate sufficient safety measures design, such redundancy, fire-containment, anti-failure features. devices classified into following three quality grades: "Standard", "Special", "Specific". Specific quality grade applies only devices developed based customer designated "quality assurance program" specific application. recommended applications device depend quality grade, indicated below. Customers must check quality grade each device before using particular application. Standard: Computers, office equipment, communications equipment, test measurement equipment, audio visual equipment, home electronic appliances, machine tools, personal electronic equipment industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment medical equipment (not specifically designed life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems medical equipment life support, etc. quality grade devices "Standard" unless otherwise specified NEC's Data Sheets Data Books. customers intend devices applications other than those specified Standard quality grade, they should contact sales representative advance.

µPD98411 AQUAD SONET FRAMER µPD98411 NEASCOT-P40 ATM-LAN LSI

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