description These 8-bit latches feature 3-state outputs designed

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description These 8-bit latches feature 3-state outputs designed

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SN54ABT573, SN74ABT573 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
description
These 8-bit latches feature 3-state outputs designed specifically driving highly capacitive relatively low-impedance loads. They particularly suitable implementing buffer registers, ports, bidirectional drivers, working registers. eight latches ABT573 transparent D-type latches. While latch-enable (LE) input high, outputs follow data inputs. When latch enable taken low, outputs latched logic levels inputs.
State-of-the-Art EPIC-B BiCMOS Design Significantly Reduces Power Dissipation Protection Exceeds 2000 MIL-STD-883C, Method 3015; Exceeds Using Machine Model Latch-Up Performance Exceeds JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce) 25°C High-Drive Outputs 32-mA IOH, 64-mA Package Options Include Plastic Small-Outline (DW) Shrink Small-Outline (DB) Packages, Ceramic Chip Carriers (FK), Plastic Ceramic DIPs
SN54ABT573 PACKAGE SN74ABT573 PACKAGE (TOP VIEW)
SN54ABT573 PACKAGE (TOP VIEW)
buffered output-enable (OE) input used place eight outputs either normal logic state (high logic levels) high-impedance state. high-impedance state, outputs neither load drive lines significantly. high-impedance state increased drive provide capability drive lines without need interface pullup components. does affect internal operations latches. data retained data entered while outputs high-impedance state. ensure high-impedance state during power power down, should tied through pullup resistor; minimum value resistor determined current-sinking capability driver. SN74ABT573 available TI's shrink small-outline package (DB), which provides same count functionality standard small-outline packages less than half printed-circuit-board area. SN54ABT573 characterized operation over full military temperature range 55°C 125°C. SN74ABT573 characterized operation from 40°C 85°C.
EPIC-B trademark Texas Instruments Incorporated.
PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters.
Copyright 1994, Texas Instruments Incorporated
POST OFFICE 655303
DALLAS, TEXAS 75265
SN54ABT573, SN74ABT573 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
FUNCTION TABLE (each latch) INPUTS OUTPUT
logic symbol
logic diagram (positive logic)
Seven Other Channels
This symbol accordance with ANSI/IEEE 91-1984 Publication 617-12.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, Input voltage range, (see Note Voltage range applied output high state power-off state, Current into output state, SN54ABT573 SN74ABT573 Input clamp current, Output clamp current, Maximum power dissipation 55°C still air) (see Note package package package Storage temperature range 65°C 150°C
Stresses beyond those listed under "absolute maximum ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated under "recommended operating conditions" implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability. NOTES: input output negative-voltage ratings exceeded input output clamp-current ratings observed. maximum package power dissipation calculated using junction temperature 150°C board trace length mils, except package, which trace length zero. more information, refer Package Thermal Considerations application note 1994 Advanced BiCMOS Technology Data Book, literature number SCBD002B.
POST OFFICE 655303
DALLAS, TEXAS 75265
SN54ABT573, SN74ABT573 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
recommended operating conditions (see Note
SN54ABT573 Supply voltage High-level input voltage Low-level input voltage Input voltage High-level output current Low-level output current Input transition rise fall rate Outputs enabled SN74ABT573 UNIT
Operating free-air temperature NOTE Unused floating inputs must held high low.
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER IOZH IOZL Ioff ICEX TEST CONDITIONS Outputs high Outputs high input Other inputs Outputs Outputs disabled -100 0.55 0.55* ±100 -180 -180 0.55 0.55 ±100 -180 25°C -1.2 SN54ABT573 -1.2 SN74ABT573 -1.2 UNIT
products compliant MIL-STD-883, Class this parameter does apply. typical values more than output should tested time, duration test should exceed second. This increase supply current each input that specified voltage level rather than GND.
POST OFFICE 655303
DALLAS, TEXAS 75265
SN54ABT573, SN74ABT573 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
timing requirements over recommended ranges supply voltage operating free-air temperature (unless otherwise noted) (see Figure
25°C Pulse duration, high High Setup time data before time, Hold time, data after SN54ABT573 SN74ABT573 UNIT
switching characteristics over recommended ranges supply voltage operating free-air temperature, (unless otherwise noted) (see Figure
PARAMETER tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ FROM (INPUT) (OUTPUT) 25°C SN54ABT573 SN74ABT573 UNIT
POST OFFICE 655303
DALLAS, TEXAS 75265
SN54ABT573, SN74ABT573 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
PARAMETER MEASUREMENT INFORMATION
From Output Under Test (see Note Open TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Open
LOAD CIRCUIT OUTPUTS Timing Input Input VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP HOLD TIMES Data Input
Input (see Note tPLH Output
tPHL tPHL tPLH
Output Control tPZL Output Waveform (see Note Output Waveform Open (see Note tPZH
tPLZ tPHZ
Output
VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS ENABLE DISABLE TIMES LOW- HIGH-LEVEL ENABLING
NOTES: includes probe capacitance. input pulses supplied generators having following characteristics: MHz, Waveform output with internal conditions such that output except when disabled output control. Waveform output with internal conditions such that output high except when disabled output control. outputs measured time with transition measurement.
Figure Load Circuit Voltage Waveforms
POST OFFICE 655303
DALLAS, TEXAS 75265
SN54ABT573, SN74ABT573 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
POST OFFICE 655303
DALLAS, TEXAS 75265
IMPORTANT NOTICE Texas Instruments subsidiaries (TI) reserve right make changes their products discontinue product service without notice, advise customers obtain latest version relevant information verify, before placing orders, that information being relied current complete. products sold subject terms conditions sale supplied time order acknowledgement, including those pertaining warranty, patent infringement, limitation liability. warrants performance semiconductor products specifications applicable time sale accordance with TI's standard warranty. Testing other quality control techniques utilized extent deems necessary support this warranty. Specific testing parameters each device necessarily performed, except those mandated government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS INVOLVE POTENTIAL RISKS DEATH, PERSONAL INJURY, SEVERE PROPERTY ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). SEMICONDUCTOR PRODUCTS DESIGNED, AUTHORIZED, WARRANTED SUITABLE LIFE-SUPPORT DEVICES SYSTEMS OTHER CRITICAL APPLICATIONS. INCLUSION PRODUCTS SUCH APPLICATIONS UNDERSTOOD FULLY CUSTOMER'S RISK. order minimize risks associated with customer's applications, adequate design operating safeguards must provided customer minimize inherent procedural hazards. assumes liability applications assistance customer product design. does warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right covering relating combination, machine, process which such semiconductor products services might used. TI's publication information regarding third party's products services does constitute TI's approval, warranty endorsement thereof.
Copyright 1998, Texas Instruments Incorporated

description These 8-bit latches feature 3-state outputs designed

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