PALCE22V10 Flash Erasable, Reprogrammable CMOS PAL® Device p
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22V10
PALCE22V10
Flash Erasable, Reprogrammable CMOS PAL® Device
power max. commercial max. commercial CMOS Flash EPROM technology electrical erasability reprogrammability Variable product terms through product terms User-programmable macrocell Output polarity control Individually selectable registered combinatorial operation input terms outputs DIP, LCC, PLCC available commercial version 181-MHz state machine military industrial versions 110-MHz state machine 15-ns commercial, industrial, military versions 25-ns commercial, industrial, military versions High reliability Proven Flash EPROM technology 100% programming functional testing
Functional Description
Cypress PALCE22V10 CMOS Flash Erasable second-generation programmable array logic device. implemented with familiar sum-of-products (AND-OR) logic structure programmable macrocell.
Logic Block Diagram (PDIP/CDIP)
CP/I
PROGRAMMABLE ARRAY (132
Reset
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Preset
I/O9
I/O8
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
CE22V10-1
Configuration
CP/I I/O0 I/O1
282726 12131415161718 I/O9 I/O8 CE22V10-2
CP/I I/O0 I/O1 2827 CE22V10-3 121314 1516 1718
View
PLCC View
registered trademark Advanced Micro Devices.
Cypress Semiconductor Corporation Document 38-03027 Rev.
3901 North First Street
Jose
I/O9 I/O8
95134 408-943-2600 Revised September 1996
PALCE22V10
Selection Guide
Generic Part Number PALCE22V10-5 PALCE22V10-7 PALCE22V10-10 PALCE22V10-15 PALCE22V10-25 Com'l Mil/Ind Com'l Mil/Ind Com'l Mil/Ind Com'l Mil/Ind
Functional Description (continued)
PALCE22V10 executed 24-pin 300-mil molded DIP, 300-mil cerDIP, 28-lead square ceramic leadless chip carrier, 28-lead square plastic leaded chip carrier, provides inputs outputs. PALCE22V10 electrically erased reprogrammed. programmable macrocell provides capability defining architecture each output individually. Each potential outputs specified "registered" "combinatorial." Polarity each output also individually selected, allowing complete flexibility output configuration. Further configurability provided through "array" configurable "output enable" each potential output. This feature allows outputs reconfigured inputs individual basis, alternately used combination controlled programmable array. PALCE22V10 features variable product term architecture. There pairs product term sums beginning product terms output incrementing product terms output. providing this variable structure, PALCE 22V10 optimized configurations found majority applications without creating devices that burden product term structures with unusable product terms lower performance. Additional features Cypress PALCE22V10 include synchronous preset asynchronous reset product term. These product terms common macrocells, eliminating need dedicate standard product terms initialization functions. device automatically resets upon power-up. PALCE22V10, featuring programmable macrocells variable product terms, provides device with flexibility implement logic functions 500- 800-gate-array complexity. Since each output pins individually configured inputs temporary permanent basis, func-
tions requiring inputs only single output down inputs outputs possible. potential outputs enabled using product terms. output permanently selected output arbitrarily enabled output input through selective individual product terms associated with each output. Each these outputs achieved through individual programmable macrocell. These macrocells programmable provide combinatorial registered inverting non-inverting output. registered mode operation, output register back into array, providing current status information array. This information available establishing next result applications such control state machines. combinatorial configuration, combinatorial output output disabled, signal present made available array. flexibility provided both programmable product term control outputs variable product terms allows significant gain functional density through programmable logic. Along with this increase functional density, Cypress PALCE22V10 provides lower-power operation through CMOS technology, increased testability with Flash reprogrammability.
Configuration Table
Registered/Combinatorial Configuration Registered/Active Registered/Active HIGH Combinatorial/Active Combinatorial/Active HIGH
Document 38-03027 Rev.
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PALCE22V10
Macrocell
OUTPUT SELECT
INPUT/ FEEDBACK MACROCELL
CE22V10-4
Maximum Ratings
(Above which useful life impaired. user guidelines, tested.) Storage Temperature .-65°C +150°C Ambient Temperature with Power Applied.-55°C +125°C Supply Voltage Ground Potential (Pin -0.5V +7.0V Voltage Applied Outputs High State -0.5V +7.0V Input Voltage. -0.5V +7.0V Output Current into Outputs (LOW)
Note: "instant case temperature.
Programming Voltage. 12.5V Latch-Up Current. >200 Static Discharge Voltage (per MIL-STD-883, Method 3015) >2001V
Operating Range
Range Commercial Industrial Military[1] Ambient Temperature +75°C -40°C +85°C -55°C +125°C ±10% ±10%
Document 38-03027 Rev.
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PALCE22V10
Electrical Characteristics Over Operating Range[2]
Parameter VIL[4] ICC1 Description Output HIGH Voltage Output Voltage Input HIGH Level Input Level Input Leakage Current Output Leakage Current Standby Power Supply Current Min., Min., Test Conditions -3.2 Com'l Mil/Ind Com'l Mil/Ind -0.5 Com'l Mil/Ind Com'l Com'l Mil/Ind Mil/Ind -130 Min. Max. Unit
Guaranteed Input Logical HIGH Voltage Inputs[3] Guaranteed Input Logical Voltage Inputs[3] VCC, Max. Max., VOUT Max., GND, Outputs Open Unprogrammed Device Max., Output Open, Device Programmed 10-Bit Counter,
Output Short Circuit Current Max., VOUT 0.5V[5,6]
ICC2[6]
Operating Power Supply Current
Capacitance[6]
Parameter COUT
Description Input Capacitance Output Capacitance
Test Conditions 2.0V VOUT 2.0V
Min.
Max.
Unit
Endurance Characteristics[6]
Parameter Description Minimum Reprogramming Cycles Test Conditions Normal Programming Conditions Min. Max. Unit Cycles
Notes: last page this specification Group subgroup testing information. These absolute values with respect device ground. overshoots system tester noise included. (Min.) equal -3.0V pulse durations less than more than output should tested time. Duration short circuit should more than second. VOUT 0.5V been chosen avoid test problems caused tester ground degradation. Tested initially after design process changes that affect these parameters.
Document 38-03027 Rev.
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PALCE22V10
Test Loads Waveforms
R1238 (319 MIL) R1238 (319 MIL) OUTPUT (1.2K MIL)
OUTPUT
R2170 (236 MIL) OUTPUT
INCLUDING SCOPE
INCLUDING SCOPE
R2170 (236 MIL)
INPUT PULSES 3.0V
CE22V10-5
Equivalent OUTPUT VENIN EQUIVALENT (Commercial) 2.08V=V
CE22V10-6
Equivalent OUTPUT
VENIN EQUIVALENT (Military) 2.13V=V
CE22V10-7
Load Speed 7.5,
Package PDIP, CDIP, PLCC,
Parameter
1.5V 2.6V
Output aveform Measurement Level 0.5V 0.5V 1.5V
0.5V Test Waveforms
Document 38-03027 Rev.
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PALCE22V10
Commercial Switching Characteristics PALCE22V10[2,7]
22V10-5 Parameter fMAX1 fMAX2 fMAX3 tSPR Description Input Output Propagation Delay[8] Input Output Enable Delay[9] Input Output Disable Delay[10] Clock Output Delay[8] Input Feedback Set-Up Time Synchronous Preset Set-Up Time Input Hold Time External Clock Period (tCO Clock Width HIGH Clock Width
22V10-7 Min. Max.
22V10-10 Min. Max. 76.9
22V10-15 Min. Max. 55.5 83.3 68.9
22V10-25 Min. Max. 33.3 35.7 38.5 Unit
Min.
Max.
External Maximum Frequency (1/(tCO tS))[11] Data Path Maximum Frequency (1/(tWH tWL))[6, Internal Feedback Maximum Frequency (1/(tCF tS))[6,13] Register Clock Feedback Input[6,14] Asynchronous Reset Width Asynchronous Reset Recovery Time Asynchronous Reset Registered Output Delay Synchronous Preset Recovery Time Power-Up Reset Time[6,15]
Notes: Part Test Loads Waveforms used parameters except tEA(+). Part Test Loads Waveforms used tER. Part Test Loads Waveforms used tEA(+). Min. times tested initially after design process changes that affect these parameters. test load part Test Loads Waveforms used measuring tEA(-). test load part Test Loads Waveforms used measuring tEA(+) only. Please part Test Loads Waveforms enable disable test waveforms measurement reference levels. This parameter measured time after output disable input that previous output data state remains stable output. This delay measured point which previous HIGH level fallen volts below min. previous level risen volts above max. Please part Test Loads Waveforms enable disable test waveforms measurement reference levels. This specification indicates guaranteed maximum frequency which state machine configuration with external feedback operate. This specification indicates guaranteed maximum frequency which device operate data path mode. This specification indicates guaranteed maximum frequency which state machine configuration with internal only feedback operate. This parameter calculated from clock period fMAX internal (1/fMAX3) measured (see Note above) minus registers PALCE22V10 have been designed with capability reset during system power-up. Following power-up, registers will reset logic state. output state will depend polarity output buffer. This feature useful establishing state machine initialization. insure proper operation, rise must monotonic timing constraints depicted Power-Up Reset Waveform must satisfied
Document 38-03027 Rev.
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PALCE22V10
Military Industrial Switching Characteristics PALCE22V10[2,7]
22V10-10 Parameter fMAX1 fMAX2 fMAX3 tSPR Description Input Output Propagation Delay[8] Input Output Enable Delay[9] Input Output Disable Delay Clock Output Delay[8] Input Feedback Set-Up Time Synchronous Preset Set-Up Time Input Hold Time External Clock Period (tCO Clock Width HIGH Clock Width
[10]
22V10-15 Min. Max. 50.0 83.3 68.9
22V10-25 Min. Max. 30.3 35.7 32.2 Unit
Min.
Max.
76.9
External Maximum Frequency (1/(tCO tS))11] Data Path Maximum Frequency (1/(tWH tWL))[6,12 Internal Feedback Maximum Frequency (1/(tCF tS))[6,13] Register Clock Feedback Input[6,14] Asynchronous Reset Width Asynchronous Reset Recovery Time Asynchronous Reset Registered Output Delay Synchronous Preset Recovery Time Power-Up Reset Time[6,15]
Document 38-03027 Rev.
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PALCE22V10
Switching Waveforms
INPUTS I/O, REGISTERED FEEDBACK SYNCHRONOUS PRESET ASYNCHRONOUS RESET REGISTERED OUTPUTS COMBINATORIAL OUTPUTS
[10]
[10]
CE22V10-8
Power-Up Reset Waveform[15]
POWER SUPPLY VOLTAGE REGISTERED ACTIVE OUTPUTS CLOCK
CE22V10-9
Document 38-03027 Rev.
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PALCE22V10
Functional Logic Diagram PALCE22V10
Macro- cell
Macro- cell
Macro- cell
Macro- cell
Macro- cell
Macro- cell
Macro- cell
Macro- cell
Macro- cell
Macro- cell
CE22V10-10
Document 38-03027 Rev.
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PALCE22V10
Ordering Information
(mA) (ns) (ns) (ns) Ordering Code PALCE22V10-5PC PALCE22V10-5JC PALCE22V10-7JC PALCE22V10-7PC PALCE22V10-10JC PALCE22V10-10PC PALCE22V10-10JI PALCE22V10-10PI PALCE22V10-10DMB PALCE22V10-10KMB PALCE22V10-10LMB PALCE22V10-15JC PALCE22V10-15PC PALCE22V10-15JI PALCE22V10-15PI PALCE22V10-15DMB PALCE22V10-15KMB PALCE22V10-15LMB PALCE22V10-25JC PALCE22V10-25PC PALCE22V10-25JI PALCE22V10-25PI PALCE22V10-25DMB PALCE22V10-25KMB PALCE22V10-25LMB Package Name Package Type 24-Lead (300 MIL) Molded 28-Lead Plastic Leaded Chip Carrier 28-Lead Plastic Leaded Chip Carrier 24-Lead (300-Mil) Molded 28-Lead Plastic Leaded Chip Carrier 24-Lead (300-Mil) Molded 28-Lead Plastic Leaded Chip Carrier 24-Lead (300-Mil) Molded 24-Lead (300-Mil) CerDIP 24-Lead Rectangular Cerpack 28-Square Leadless Chip Carrier 28-Lead Plastic Leaded Chip Carrier 24-Lead (300-Mil) Molded 28-Lead Plastic Leaded Chip Carrier 24-Lead (300-Mil) Molded 24-Lead (300-Mil) CerDIP 24-Lead Rectangular Cerpack 28-Square Leadless Chip Carrier 28-Lead Plastic Leaded Chip Carrier 24-Lead (300-Mil) Molded 28-Lead Plastic Leaded Chip Carrier 24-Lead (300-Mil) Molded 24-Lead (300-Mil) CerDIP 24-Lead Rectangular Cerpack 28-Square Leadless Chip Carrier Military Industrial Commercial Military Industrial Commercial Military Industrial Commercial Commercial Operating Range Commercial
MILITARY SPECIFICATIONS Group Subgroup Testing Characteristics
Parameter Subgroups
Switching Characteristics
Parameter Subgroups
Document 38-03027 Rev.
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PALCE22V10
Package Diagrams
24-Lead (300-Mil) CerDIP
MIL-STD-1835 Config.A
28-Lead Plastic Leaded Chip Carrier
24-Lead Rectangular Cerpack
MIL-STD-1835 Config.A
28-Square Leadless Chip Carrier
MIL-STD-1835
Document 38-03027 Rev.
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PALCE22V10
Package Diagrams (continued)
24-Lead (300-Mil) Molded P13/P13A
Document 38-03027 Rev.
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Cypress Semiconductor Corporation, 1996. information contained herein subject change without notice. Cypress Semiconductor Corporation assumes responsibility circuitry other than circuitry embodied Cypress Semiconductor product. does convey imply license under patent other rights. Cypress Semiconductor does authorize products critical components life-support systems where malfunction failure reasonably expected result significant injury user. inclusion Cypress Semiconductor products life-support systems application implies that manufacturer assumes risk such doing indemnifies Cypress Semiconductor against charges.
PALCE22V10
Document Title: PALCE22V10 Flash Erasable, Reprogrammable CMOS PAL® Device Document Number: 38-03027 REV. 106372 Issue Date 07/11/01 Orig. Change Description Change Change from Spec Number: 38-00447 38-03027
Document 38-03027 Rev.
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