64-Macrocell MAX® EPLD macrocells LABs dedicated inputs, bidirect
|
|
|
Top Searches for this datasheet
CY7C343
64-Macrocell MAX® EPLD
macrocells LABs dedicated inputs, bidirectional pins Programmable interconnect array 0.8-micron double-metal CMOS EPROM technology Available 44-pin HLCC, PLCC Lowest power device CY7C343 contains highly flexible macrocells expander product terms. These resources divided into four Logic Array Blocks (LABs) connected through Programmable Inter-connect Array (PIA). There input pins, that doubles clock when needed. CY7C343 also pins, each connected macrocell LABs LABs remaining macrocells used embedded logic. CY7C343 excellent wide range both synchronous asynchronous applications.
Functional Description
CY7C343 high-performance, high-density erasable programmable logic device, available 44-pin PLCC HLCC packages.
Logic Block Diagram
INPUT INPUT INPUT INPUT DEDICATED INPUTS SYSTEM CLOCK MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELLS 7-16 MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL INPUT INPUT/CLK INPUT INPUT
PINS
PINS
MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELLS 25-32 (10,
MACROCELLS 57-64 MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL
PINS
PINS
MACROCELLS 39-48
C343-1
registered trademark Altera Corporation. Warp, Warp Professional, Warp Enterprise trademarks Cypress Semiconductor.
Cypress Semiconductor Corporation Document 38-03015 Rev.
3901 North First Street
Jose
95134 408-943-2600 Revised July 2000
CY7C343
Selection Guide
7C343-20 Maximum Access Time (ns) Maximum Operating Current (mA) Commercial Military Industrial Maximum Standby Current (mA) Commercial Military Industrial 7C343-25 7C343-30 7C343-35
Configuration
HLCC, PLCC View
INPUT INPUT INPUT INPUT
INPUT INPUT/CLK INPUT INPUT
7C343
C343-2
Maximum Ratings
(Above which useful life impaired. user guidelines, tested.) Storage Temperature -65°C to+150°C Ambient Temperature with Power Applied. to+70°C Maximum Junction Temperature (Under Bias). 150°C Supply Voltage Ground Potential -2.0V +7.0V Maximum Power Dissipation.2500 Current .500
Output Current, .-25 Input Voltage[1] .-3.0V +7.0V Program Voltage 13.0V Static Discharge Voltage >1100V (per MIL-STD-883, method 3015)
Operating Range
Range Commercial Industrial Military Ambient Temperature +70°C -40°C +85°C -55°C +125°C (Case) ±10% ±10%
Note: Minimum input -0.3V. During transitions, inputs undershoot -2.0V periods less than
Document 38-03015 Rev.
Page
CY7C343
Electrical Characteristics Over Operating Range[2]
Parameter ICC1 ICC2 Description Output HIGH Voltage Output Voltage Input HIGH Level Input Level Input Current Output Leakage Current Output Short Circuit Current Power Supply Current (Standby) Power Supply Current
Test Conditions Min., -4.0 Min.,
Min.
Max. 0.45
Unit
-0.3 Max., VOUT 0.5V[3, Load) Load) MHz[4, Commercial Military/Industrial Commercial Military/Industrial
VCC+0.3
Recommended Input Rise Time Recommended Input Fall Time
Capacitance[6]
Parameter COUT Description Input Capacitance Output Capacitance Test Conditions VOUT 2.0V, Max. Unit
Test Loads Waveforms[6]
OUTPUT INCLUDING SCOPE OUTPUT INCLUDING SCOPE 3.0V INPUT PULSES
C343-4
C343-3
Equivalent OUTPUT
EQUIVALENT (commercial/military) 1.75V
Notes: Typical values 25°C more than output should tested time. Duration short circuit should more than second. VOUT 0.5V been chosen avoid test problems caused tester ground degradation. Guaranteed 100% tested. Measured with device programmed 16-bit counter each LAB. This parameter tested periodically sampling production material. Part Test Load Waveforms used parameters except tXZ, which used part Test Load Waveforms. external timing parameters measured referenced external pins device.
Document 38-03015 Rev.
Page
CY7C343
Programmable Interconnect Array
Programmable Interconnect Array (PIA) solves interconnect limitations routing only signals needed each logic array block. inputs outputs every macrocell within device feedback every device. Unlike masked programmable gate arrays, which induce variable delay dependent routing, fixed delay. This eliminates undesired skews among logic signals, which cause glitches internal external logic. fixed delay, regardless programmable interconnect array configuration, simplifies design ensuring that internal signal skews races avoided. result simpler design implementation, often single pass, without multiple internal logic placement routing iterations required programmable gate array achieve design timing objectives.
Timing Considerations
Unless otherwise stated, propagation delays include expanders. When using expanders, maximum expander delay tEXP overall delay. Similarly, there additional tPIA delay input from when compared signal from straight input pin. When calculating synchronous frequencies, inputs input pins. should used data applied pin. greater than tCO1, 1/tS2 becomes limiting frequency data path mode unless 1/(tWH tWL) less than 1/tS2. When expander logic used data path, appropriate maximum expander delay, tEXP tS1. Determine which 1/(tWH tWL), 1/tCO1, 1/(tEXP tS1) lowest frequency. lowest these frequencies maximum data path frequency synchronous configuration. When calculating external asynchronous frequencies, tAS1 inputs dedicated input pins. data applied pin, tAS2 must used required set-up time. (tAS2 tAH) greater than tACO1, 1/(tAS2 tAH) becomes limiting frequency data path mode unless 1/(tAWH tAH) less than 1/(tAS2 tAH). When expander logic used data path, appropriate maximum expander delay, tEXP tAS1. Determine which 1/(tAWH tAWL), 1/tACO1, 1/(tEXP tAS1) lowest frequency. lowest these frequencies maximum data path frequency asynchronous configuration. parameter indicates system compatibility this device when driving other synchronous logic with positive input hold times, which controlled same synchronous clock. greater than minimum required input hold time subsequent synchronous logic, then devices guaranteed function properly with common synchronous clock under worst-case environmental supply voltage conditions. parameter tAOH indicates system compatibility this device when driving subsequent registered logic with positive hold time using same clock CY7C343. general, tAOH greater than minimum required input hold time subsequent logic (synchronous asynchronous), then devices guaranteed function properly under worst-case environmental supply voltage conditions, provided clock signal source same. This also applies expander logic used clock signal path driving device, driven device. This expander logic second device's clock signal path adding additional delay (tEXP), causing output data from preceding device change prior arrival clock signal following device's register.
Timing Delays
Timing delays within CY7C343 easily determined using WarpTM, Warp ProfessionalTM, Warp Enterprisesoftware. CY7C343 fixed internal delays, allowing user determine worst case timing delays design.
Design Recommendations
Operation devices described herein with conditions above those listed under "Maximum Ratings" cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this data sheet implied. Exposure absolute maximum ratings conditions extended periods time affect device reliability. CY7C343 contains circuitry protect device pins from high static voltages electric fields; however, normal precautions should taken avoid applying voltage higher than maximum rated voltages. proper operation, input output pins must constrained range (VIN VOUT) VCC. Unused inputs must always tied appropriate logic level (either GND). Each pins must connected together directly device. Power supply decoupling capacitors least must connected between GND. most effective decoupling, each should separately decoupled GND, directly device. Decoupling capacitors should have good frequency response, such monolithic ceramic types.
Document 38-03015 Rev.
Page
CY7C343
EXPANDER DELAY tEXP
REGISTER OUTPUT DELAY
INPUT INPUT DELAY
LOGIC ARRAY CONTROL DELAY tLAC LOGIC ARRAY DELAY tLAD
tCLR tPRE tRSU
INPUT/ OUTPUT
tCOMB tLATCH
SYSTEM CLOCK DELAY tICS DELAY tPIA CLOCK DELAY
FEEDBACK DELAY
DELAY
C343-5
Figure CY7C343 Internal Timing Model.
Document 38-03015 Rev.
Page
CY7C343
External Synchronous Switching Characteristics[6] Over Operating Range
7C343-20 Parameter tPD1 tPD2 tPD3 tPD4 tCO1 tCO2 Description Dedicated Input Combinatorial Output Delay[7] Input Combinatorial Output Delay[8] Dedicated Input Combinatorial Output Delay with Expander Delay[9] Input Combinatorial Output Delay with Expander Delay[4, Input Output Enable Delay
7C343-25 Min. Max. Page Unit
Min. Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind
Max.
Input Output Disable Delay[4, Synchronous Clock Input Output Delay Synchronous Clock Local Feedback Combinatorial Output[4, Dedicated Input Feedback Set-Up Time Synchronous Clock Input[7] Input Set-Up Time Synchronous Clock Input[7, Input Hold Time from Synchronous Clock Input[7] Synchronous Clock Input HIGH Time Synchronous Clock Input Time Asynchronous Clear Width[4, Asynchronous Clear Recovery Time
Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind
Asynchronous Clear Registered Output Delay[7] Asynchronous Preset Recovery Time
Asynchronous Preset Registered Output Delay[7] Synchronous Clock Local Feedback Input[4, External Synchronous Clock Period (1/fMAX3)[4]
Document 38-03015 Rev.
CY7C343
External Synchronous Switching Characteristics[6] Over Operating Range (continued)
7C343-20 Parameter fMAX1 fMAX2 fMAX3 fMAX4 Description External Maximum Frequency (1/(tCO1 tS1))[4, Com'l/Ind Min. 41.6 41.6 66.6 66.6 83.3 83.3 83.3 83.3 Max. 7C343-25 Min. 62.5 62.5 62.5 62.5 Max. Unit
Internal Local Feedback Maximum Frequen- Com'l/Ind lesser (1/(tS1 tCF)) (1/tCO1)[4, Data Path Maximum Frequency, least 1/(tWL tWH), 1/(tS1 tH), (1/tCO1)[4, Maximum Register Toggle Frequency (1/(tWL+tWH))[4, Output Data Stable Time from Synchronous Clock Input[4, Asynchronous Preset Width
Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind
Notes: This specification measure delay from input signal applied dedicated input (44-pin PLCC input combinatorial output output pin. This delay assumes expander terms used form logic function. When this note applied parameter specification indicates that signal (data, asynchronous clock, asynchronous clear, and/or asynchronous preset) applied dedicated input only signal path (either clock data) employs expander logic. input signal applied pin, additional delay equal tPIA should added comparable delay dedicated input. expanders used, maximum expander delay tEXP overall delay comparable delay without expanders. This specification measure delay from input signal applied macrocell output. This delay assumes expander terms used form logic function. This specification measure delay from input signal applied dedicated input (44-pin PLCC input combinatorial output output pin. This delay assumes expander terms used form logic function includes worst-case expander logic delay pass through expander logic. This parameter tested periodically sampling production material. This specification measure delay from input signal applied macrocell output. This delay assumes expander terms used form logic function includes worst-case expander logic delay pass through expander logic. This parameter tested periodically sampling production material. This specification measure delay from synchronous register clock internal feedback register output signal input logic array then combinatorial output. This delay assumes expanders used, register synchronously clocked feedback within same LAB. This parameter tested periodically sampling production material. data applied input capture macrocell register, set-up time minimums should observed. These parameters synchronous operation tAS2 asynchronous operation. This specification measure delay associated with internal register feedback path. This delay from synchronous clock logic array input. This delay plus register set-up time, tS1, minimum internal period internal synchronous state machine configuration. This delay feedback within same LAB. This parameter tested periodically sampling production material. This specification indicates guaranteed maximum frequency, synchronous mode, which state machine configuration with external feedback operate. assumed that data inputs feedback signals applied dedicated inputs. This specification indicates guaranteed maximum frequency which state machine, with internal-only feedback, operate. register output states must also control external points, this frequency still observed long this frequency less than 1/tCO1. feedback assumed local, originating within same LAB. This frequency indicates maximum frequency which device operate data path mode. This delay assumes data input signals applied dedicated inputs expander logic used. This specification indicates guaranteed maximum frequency, synchronous mode, which individual output buried register cycled. This parameter indicates minimum time after synchronous register clock input that previous register output data maintained output pin.
Document 38-03015 Rev.
Page
CY7C343
External Synchronous Switching Characteristics[6] Over Operating Range (continued)
7C343-30 Parameter tPD1 tPD2 tPD3 tPD4 tCO1 tCO2 Description Dedicated Input Combinatorial Output Delay[7] Input Combinatorial Output Delay[8] Dedicated Input Combinatorial Output Delay with Expander Delay[9] Input Combinatorial Output Delay with Expander Delay[4, Input Output Enable Delay
7C343-35 Min. Max. 12.5 12.5 12.5 12.5 Page Unit
Min. Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind
Max.
Input Output Disable Delay[4, Synchronous Clock Input Output Delay Synchronous Clock Local Feedback Combinatorial Output[4, Dedicated Input Feedback Set-Up Time Synchronous Clock Input[7] Input Set-Up Time Synchronous Clock Input[7, Input Hold Time from Synchronous Clock Input[7] Synchronous Clock Input HIGH Time Synchronous Clock Input Time Asynchronous Clear Width[4, Asynchronous Clear Recovery Time
Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind
Asynchronous Clear Registered Output Delay[7] Asynchronous Preset Recovery Time
Asynchronous Preset Registered Output Delay[7] Synchronous Clock Local Feedback Input[4, External Synchronous Clock Period (1/fMAX3)[4]
Document 38-03015 Rev.
CY7C343
External Synchronous Switching Characteristics[6] Over Operating Range (continued)
7C343-30 Parameter fMAX1 fMAX2 fMAX3 fMAX4 Description External Maximum Frequency (1/(tCO1 tS1))[4, Com'l/Ind Min. Max. 7C343-35 Min. 22.2 22.2 Max. Unit
Internal Local Feedback Maximum Frequen- Com'l/Ind lesser (1/(tS1 tCF)) (1/tCO1)[4, Data Path Maximum Frequency, least 1/(tWL tWH), 1/(tS1 tH), (1/tCO1)[4, Maximum Register Toggle Frequency (1/(tWL+tWH))[4, Output Data Stable Time from Synchronous Clock Input[4, Asynchronous Preset Width
Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind
External Asynchronous Switching Characteristics Over Operating Range[6]
7C343-20 Parameter tACO1 tACO2 tAS1 tAS2 tAWH tAWL tACF fMAXA1 fMAXA2 fMAXA3 Description Asynchronous Clock Input Output Delay
7C343-25 Min. Max. Unit
Min. Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind 41.6 41.6 58.8 58.8
Max.
Asynchronous Clock Input Local Feedback Combinatorial Output[19] Dedicated Input Feedback Set-Up Time Asynchronous Clock Input[7] Input Set-Up Time Asynchronous Clock Input[7] Input Hold Time from Asynchronous Clock Input[7] Asynchronous Clock Input HIGH Time[7] Asynchronous Clock Input Time
Asynchronous Clock Local Feedback Input[4, External Asynchronous Clock Period (1/fMAXA4)[4] External Maximum Frequency Asynchronous Mode 1/(tACO1 tAS1)[4, Maximum Internal Asynchronous Frequency[4,
Data Path Maximum Frequency Asynchro- Com'l/Ind nous Mode[4,
Document 38-03015 Rev.
Page
CY7C343
External Asynchronous Switching Characteristics Over Operating Range[6] (continued)
7C343-20 Parameter fMAXA4 tAOH Description Maximum Asynchronous Register Toggle Frequency 1/(tAWH tAWL)[4, Output Data Stable Time from Asynchronous Clock Input[4, Com'l/Ind Com'l/Ind Min. 62.5 62.5 Max. 7C343-25 Min. Max. Unit
Notes: This specification measure delay from asynchronous register clock input internal feedback register output signal input logic array then combinatorial output. This delay assumes expanders used logic combinatorial output asynchronous clock input. clock signal applied dedicated input feedback within single LAB. This parameter tested periodically sampling production material. This parameter measured with positive-edge triggered clock register. negative edge triggering, tAWH tAWL parameters must swapped. given input used clock multiple registers with both positive negative polarity, tAWH should used both tAWH tAWL. This specification measure delay associated with internal register feedback path asynchronous clock logic array input. This delay plus asynchronous register set-up time, tAS1, minimum internal period internal asynchronously clocked state machine configuration. This delay feedback within same LAB, assumes expander logic clock path, assumes that clock input signal applied dedicated input pin. This parameter tested periodically sampling production material. This specification indicates guaranteed maximum frequency which asynchronously clocked state machine configuration with external feedback operate. assumed that data inputs, clock inputs, feedback signals applied dedicated inputs, that expander logic employed clock signal path data path. This specification indicates guaranteed maximum frequency which asynchronously clocked state machine with internal-only feedback operate. This parameter determined lesser (1/tACF tAS1)) (1/(tAWH +tAWL)). register output states must also control external points, this frequency still observed long this frequency less than 1/tACO1. This frequency maximum frequency which device operate asynchronously clocked data path mode. This specification determined least 1/(tAWH tAWL), 1/(tAS1 tAH) 1/tACO1. assumes data clock input signals applied dedicated input pins expander logic used. This specification indicates guaranteed maximum frequency which individual output buried register cycled asynchronously clocked mode clock signal applied external dedicated input pin. This parameter indicates minimum time that previous register output data maintained output after asynchronous register clock input.
Document 38-03015 Rev.
Page
CY7C343
External Asynchronous Switching Characteristics Over Operating Range[6]
7C343-30 Parameter tACO1 tACO2 tAS1 tAS2 tAWH tAWL tACF fMAXA1 fMAXA2 fMAXA3 fMAXA4 tAOH Description Asynchronous Clock Input Output Delay Asynchronous Clock Input Local Feedback Combinatorial Output[19] Dedicated Input Feedback Set-Up Time Asynchronous Clock Input[7] Input Set-Up Time Asynchronous Clock Input[7] Input Hold Time from Asynchronous Clock Input[7] Asynchronous Clock Input HIGH Time
7C343-35 Min. Max. Unit
Min. Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind
Max.
Asynchronous Clock Input Time[7, Asynchronous Clock Local Feedback Input[4, External Asynchronous Clock Period (1/fMAXA4)[4] External Maximum Frequency Asynchronous Mode 1/(tACO1 tAS1)[4, Maximum Internal Asynchronous Frequency[4, Data Path Maximum Frequency Asynchronous Mode[4, Maximum Asynchronous Register Toggle Frequency 1/(tAWH tAWL)[4, Output Data Stable Time from Asynchronous Clock Input[4,
Internal Switching Characteristics Over Operating Range[6]
7C343-20 Parameter tEXP Description Dedicated Input Buffer Delay Input Buffer Delay Expander Array Delay Com'l/Ind Com'l/Ind Com'l/Ind Min. Max. 7C343-25 Min. Max. Unit
Document 38-03015 Rev.
Page
CY7C343
Internal Switching Characteristics Over Operating Range[6] (continued)
7C343-20 Parameter tLAD tLAC tRSU tLATCH tCOMB tICS tPRE tCLR Logic Array Data Delay Logic Array Control Delay Output Buffer Delay Output Buffer Enable Delay
[27]
7C343-25 Min. Max. Unit
Description Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind Output Buffer Disable Delay Register Set-Up Time Relative Clock Signal Register Register Hold Time Relative Clock Signal Register Flow-Through Latch Delay Register Delay Transparent Mode Delay Clock HIGH Time Clock Time Asynchronous Clock Logic Delay Synchronous Clock Delay Feedback Delay Asynchronous Register Preset Time Asynchronous Register Clear Time
[28]
Min.
Max.
Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind Com'l/ Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind
Document 38-03015 Rev.
Page
CY7C343
Internal Switching Characteristics Over Operating Range[6] (continued)
7C343-20 Parameter tPCW tPCR tPIA Description Asynchronous Preset Clear Pulse Width Com'l /Ind Asynchronous Preset Clear Recovery Time Programmable Interconnect Array Delay Time Com'l/Ind Com'l/Ind Min. Max. 7C343-25 Min. Max. Unit
Internal Switching Characteristics Over Operating Range[6]
7C343-30 Parameter tEXP tLAD tLAC tRSU tLATCH tCOMB Description Dedicated Input Buffer Delay Input Buffer Delay Expander Array Delay Logic Array Data Delay Logic Array Control Delay Output Buffer Delay Output Buffer Enable Delay
[27]
7C343-35 Min. Max. Unit
Min. Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind
Max.
Output Buffer Disable Delay Register Set-Up Time Relative Clock Signal Register Register Hold Time Relative Clock Signal Register Flow-Through Latch Delay Register Delay Transparent Mode Delay
[28]
Com'l/Ind
Notes: Sample tested only output change This specification guarantees maximum combinatorial delay associated with macrocell register bypass when macrocell configured combinatorial operation.
Document 38-03015 Rev.
Page
CY7C343
Internal Switching Characteristics Over Operating Range[6] (continued)
7C343-30 Parameter tICS tPRE tCLR tPCW tPCR tPIA Clock HIGH Time Clock Time Asynchronous Clock Logic Delay Synchronous Clock Delay Feedback Delay Asynchronous Register Preset Time Asynchronous Register Clear Time Description Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind Asynchronous Preset Clear Pulse Width Com'l/Ind Asynchronous Preset Clear Recovery Time Programmable Interconnect Array Delay Time Com'l/Ind Com'l/Ind Min. Max. 7C343-35 Min. 12.5 12.5 12.5 12.5 Max. Unit
Switching Waveforms
External Combinatorial
DEDICATED INPUT/ INPUT /tPD2 COMBINATORIAL OUTPUT COMBINATORIAL REGISTERED OUTPUT HIGH-IMPEDANCE THREE-STATE VALID OUTPUT
C343-6
HIGH-IMPEDANCE THREE-STATE
Document 38-03015 Rev.
Page
CY7C343
Switching Waveforms (continued)
External Synchronous
DEDICATED INPUTS REGISTERED FEEDBACK SYNCHRONOUS CLOCK tCO1 ASYNCHRONOUS CLEAR/PRESET[7] /tPO REGISTERED OUTPUTS tCO2 COMBINATORIAL OUTPUT FROM REGISTERED FEEDBACK [11]
C343-7
/tPW
/tPR
External Asynchronous
DEDICATEDINPUTSOR REGISTERED FEEDBACK ASYNCHRONOUS CLOCK INPUT
tAS1
tAWH
tAWL
tACO1 tAOH
tRW/tPW
tRR/tPR
ASYNCHRONOUS CLEAR/PRESET
tRO/tPO ASYNCHRONOUS REGISTERED OUTPUTS tACO2 COMBINATORIAL OUTPUT FROM ASYNCH. REGISTERED FEEDBACK
C343-8
Document 38-03015 Rev.
Page
CY7C343
Switching Waveforms (continued)
Internal Combinatorial
INPUT tEXP EXPANDER ARRAY DELAY tLAC, tLAD LOGIC ARRAY INPUT tPIA
LOGIC ARRAY OUTPUT
C343-9
Internal Asynchronous
tIOR CLOCK CLOCK INTO LOGIC ARRAY CLOCK FROM LOGIC ARRAY tRSU DATA FROM LOGIC ARRAY tRD,tLATCH REGISTER OUTPUT LOCAL
C343-10
tAWH
tAWL
tCLR,tPRE
Internal Synchronous
SYSTEM CLOCK SYSTEM CLOCK REGISTER tRSU DATA FROM LOGIC ARRAY
C343-12
tICS
Document 38-03015 Rev.
Page
CY7C343
Switching Waveforms (continued)
Output Mode
CLOCK FROM LOGIC ARRAY
DATA FROM LOGIC ARRAY OUTPUT HIGH IMPEDANCE STATE
C343-11
Information
Speed (ns) Ordering Code CY7C343-20JC/JI CY7C343-25HC/HI CY7C343-25JC/JI CY7C343-30HC/HI CY7C343-30JC/JI CY7C343-30HMB CY7C343-35HC/HI CY7C343-35JC CY7C343-35HMB Package Name Package Type 44-Lead Plastic Leaded Chip Carrier 44-Pin Windowed Leaded Chip Carrier 44-Lead Plastic Leaded Chip Carrier 44-Pin Windowed Leaded Chip Carrier 44-Lead Plastic Leaded Chip Carrier 44-Pin Windowed Leaded Chip Carrier 44-Pin Windowed Leaded Chip Carrier 44-Lead Plastic Leaded Chip Carrier 44-Pin Windowed Leaded Chip Carrier Military Military Commercial/Industrial Commercial/Industrial Operating Range Commercial/Industrial Commercial/Industrial
MILITARY SPECIFICATIONS Group Subgroup Testing Characteristics
Parameters ICC1 Subgroups
Switching Characteristics
Parameters tPD1 tPD2 tPD3 tCO1 tACO1 tACO2 Subgroups
Document 38-03015 Rev.
Page
CY7C343
Package Diagrams
44-Pin Windowed Leaded Chip Carrier
51-80079
Document 38-03015 Rev.
Page
CY7C343
Package Diagrams (continued)
44-Lead Plastic Leaded Chip Carrier
51-85003-A
Document 38-03015 Rev.
Page
Cypress Semiconductor Corporation, 2000. information contained herein subject change without notice. Cypress Semiconductor Corporation assumes responsibility circuitry other than circuitry embodied Cypress Semiconductor product. does convey imply license under patent other rights. Cypress Semiconductor does authorize products critical components life-support systems where malfunction failure reasonably expected result significant injury user. inclusion Cypress Semiconductor products life-support systems application implies that manufacturer assumes risk such doing indemnifies Cypress Semiconductor against charges.
CY7C343
Document Title: CY7C343 63-Macrocell MAX® EPLD Document Number: 38-03015 REV. 106315 Issue Date 04/24/01 Orig. Change Description Change Change from Spec number: 38-03015
Document 38-03015 Rev.
Page
Other recent searches
TPS2114A - TPS2114A TPS2114A Datasheet
TPS2115A - TPS2115A TPS2115A Datasheet
THS4509 - THS4509 THS4509 Datasheet
SMD100-2018 - SMD100-2018 SMD100-2018 Datasheet
R5F21256SNFP - R5F21256SNFP R5F21256SNFP Datasheet
ICX086AK - ICX086AK ICX086AK Datasheet
DS04-71113-1Ea - DS04-71113-1Ea DS04-71113-1Ea Datasheet
CCPD-920 - CCPD-920 CCPD-920 Datasheet
AL60A - AL60A AL60A Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
