192-Macrocell MAX® EPLD macrocells LABs dedicated inputs, bidirec

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192-Macrocell MAX® EPLD macrocells LABs dedicated inputs, bidirec

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CY7C3
192-Macrocell MAX® EPLD
macrocells LABs dedicated inputs, bidirectional 0.8-micron double-metal CMOS EPROM technology Programmable interconnect array expander product terms Available 84-pin HLCC, PLCC, packages Externally, CY7C341 provides dedicated inputs, which used system clock. There pins that individually configured input, output, bidirectional data flow.
Programmable Interconnect Array
Programmable Interconnect Array (PIA) solves interconnect limitations routing only signals needed each logic array block. inputs outputs every macrocell within device feedback every device. Unlike masked programmable gate arrays, which induce variable delay dependent routing, fixed delay. This eliminates undesired skews among logic signals, which cause glitches internal external logic. fixed delay, regardless programmable interconnect array configuration, simplifies design assuring that internal signal skews races avoided. result ease design implementation, often single pass, without multiple internal logic placement routing iterations required programmable gate array achieve design timing objectives.
Functional Description
CY7C341 Erasable Programmable Logic Device (EPLD) which CMOS EPROM cells used configure logic functions within device. architecture 100% user-configurable, allowing devices accommodate variety independent logic functions. macrocells CY7C341 divided into Logic Array Blocks (LABs), LAB. There expander product terms, LAB, used shared macrocells within each LAB. Each interconnected with programmable interconnect array, allowing signals routed throughout chip. speed density CY7C341 allows them used wide range applications, from replacement large amounts 7400-series logic, complex controllers multifunction chips. With greater than times functionality 20-pin PLDs, CY7C341 allows replacement over devices. replacing large amounts logic, CY7C341 reduces board space part count, increases system reliability. Each contains macrocells. LABs macrocells connected pins buried, while LABs macrocells connected pins buried. Moreover, addition buried macrocells, there single product term logic expanders each LAB. Their greatly enhances capability macrocells without increasing number product terms each macrocell.
Timing Delays
Timing delays within CY7C341 easily determined using WarpTM, Warp ProfessionalTM, Warp Enterprisesoftware. CY7C341 fixed internal delays, allowing user determine worst case timing delays design.
Design Recommendations
proper operation, input output pins must constrained range (VIN VOUT) VCC. Unused inputs must always tied appropriate logic level (either GND). Each pins must connected together directly device. Power supply decoupling capacitors least must connected between GND. most effective decoupling, each should separately decoupled GND, directly device. Decoupling capacitors should have good frequency response, such monolithic ceramic types.
Logic Array Blocks
There logic array blocks CY7C341. Each consists macrocell array containing macrocells, expander product term array containing expanders, block. programmable interconnect array dedicated input bus. macrocell feedbacks macrocell array, expander array, programmable interconnect array. Expanders feed themselves macrocell array. feedbacks programmable interconnect array that they accessed macrocells other LABs well macrocells which they situated.
Design Security
CY7C341 contains programmable design security feature that controls access data programmed into device. this programmable feature used, proprietary design implemented device cannot copied retrieved. This enables high level design control obtained since programmed data within EPROM cells invisible. that controls this function, along with other program data, reset simply erasing device.
registered trademark Altera Corporation. Warp, Warp Professional, Warp Enterprise trademarks Cypress Semiconductor Corporation.
Cypress Semiconductor Corporation Document 38-03034 Rev.
3901 North First Street
Jose
95134 408-943-2600 Revised July 2000
CY7C3
Selection Guide
7C341-25 Maximum Access Time (ns) Maximum Operating Current (mA) Commercial Industrial Military Maximum Standby Current (mA) Commercial Industrial Military 7C341-30 7C341-35
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CY7C3Logic Block Diagram
(A6) (A5) (K6) (J6) INPUT/CLK INPUT INPUT INPUT INPUT INPUT INPUT INPUT (C6) (C7) (L7) (J7)
SYSTEMCLOCK (C5) (A4) (B4) (A3) (A2) (B3) (A1) (B2) MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL 9-16 (C2) (B1) (C1) (D2) MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL 21-32 MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL 105-112 MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL 117-128 (J10) (K11) (J11) (H10)
(L6) (L8) (K8) (L9) (L10) (K9) (L11) (K10)
(D1) (E3) (F2) (F3)
MACROCELL MACROCELL MACROCELL MACROCELL
MACROCELL MACROCELL MACROCELL MACROCELL
(H11) (F10) (G9) (F9)
MACROCELL 37-48
MACROCELL 133-144
(G3) (G1) (F1) (H1)
MACROCELL MACROCELL MACROCELL MACROCELL
MACROCELL MACROCELL MACROCELL MACROCELL
(F11) (E11) (E9) (D11)
MACROCELL 53-64
MACROCELL 149-160
(H2) (J1) (K1) (J2)
MACROCELL MACROCELL MACROCELL MACROCELL
MACROCELL MACROCELL MACROCELL MACROCELL
(D10) (C11) (B11) (C10)
MACROCELL 69-80
MACROCELL 165-176
(L1) (K2) (K3) (L2) (L3) (K4) (L4) (J5)
MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL 89-96
MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL 185-192
(A11) (B10) (B9) (A10) (A9) (B8) (A8) (B6)
(B5, E10) (E1, G10, G11,
PERTAIN 84-PIN PACKAGE C341-1
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CY7C3Pin Configurations
PLCC/HLCC View
INPUT/CLK INPUT INPUT INPUT
Bottom View
INPUT
7C341 INPUT INPUT INPUT INPUT
INPUT
INPUT INPUT
INPUT INPUT
INPUT/ INPUT
C341-2
C341-3
Design Security (continued)
CY7C341 fully functionally tested guaranteed through complete testing each programmable EPROM internal logic elements thus ensuring 100% programming yield.
erasable nature these devices allows test programs used erased during early stages production flow. devices also contain on-board logic test circuitry allow verification function specification once encapsulated non-windowed packages.
EXPANDER DELAY tEXP LOGIC ARRAY CONTROL DELAY tLAC LOGIC ARRAY DELAY tLAD
REGISTER tCLR tPRE tRSU tCOMB tLATCH OUTPUT DELAY INPUT/ OUTPUT
INPUT
INPUT DELAY
SYSTEM CLOCK DELAY tICS DELAY tPIA CLOCK DELAY LOGIC ARRAY DELAY DELAY
C341-4
Figure CY7C341 Internal Timing Model
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CY7C3Maximum Ratings
(Above which useful life impaired. user guidelines, tested.) Storage Temperature .-65°C +150°C Ambient Temperature with Power Applied. +70°C Maximum Junction Temperature (Under Bias). 150°C Supply Voltage Ground Potential .-2.0V +7.0V Maximum Power Dissipation.2500 Current.500 Output Current, Input Voltage[1] .-3.0V +7.0V Program Voltage 13.0V Static Discharge Voltage.>1100V (per MIL-STD-883, method 3015)
Operating Range
Range Commercial Industrial Military Ambient Temperature +70°C -40°C +85°C -55°C +125°C (Case)
Electrical Characteristics Over Operating Range[2]
Parameter ICC1 ICC2 (Recommended) (Recommended) Description Output HIGH Voltage Output Voltage Input HIGH Level Input Level Input Current Output Leakage Current Output Short Circuit Current Power Supply Current (Standby) Power Supply Current[5] Input Rise Time Input Fall Time Max., VOUT Load) Load) MHz[3,
Test Conditions Min., -4.0 Min.,
Min.
Max. 0.45
Unit
-0.3 Com'l Mil/Ind Com'l Mil/Ind
VCC+0.3
Capacitance[6]
Parameter COUT Description Input Capacitance Output Capacitance Test Conditions 25°C, MHz, 5.0V Max. Unit
Notes: Minimum input -0.3V. During transitions, inputs undershoot -2.0V periods less than Typical values 25°C Guaranteed 100% tested. more than output should tested time. Duration short circuit should more than second. VOUT 0.5V been chosen avoid test problems caused tester ground degradation. This parameter measured with device programmed 16-bit counter each tested periodically sampling production material. Part Test Load Waveforms used parameters except tXZ, which used part Test Load Waveforms. external timing parameters measured referenced external pins device.
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CY7C3AC Test Loads Waveforms
OUTPUT INCLUDING SCOPE Equivalent OUTPUT 3.0V
C341-6
INPUT PULSES
C341-5
EQUIVALENT (commercial/military) OUTPUT 1.75V
External Synchronous Switching Characteristics Over Operating Range[6] 7C341-25 Parameter tPD1 tPD2 tPD3 tPD4 tCO1 tCO2 Description Dedicated Input Combinatorial Output Delay[7] Input Combinatorial Output Delay[8] Com'l Com'l Min. 7C341-30 Min. 7C341-35 Min. Unit
Dedicated Input Combinatorial Com'l Output Delay with Expander Delay[9] Input Combinatorial Output Delay with Expander Delay[3, Input Output Enable Delay
Com'l Com'l Com'l Com'l Com'l
Input Output Disable Delay[6] Synchronous Clock Input Output Delay Synchronous Clock Local Feedback Combinatorial Output[3,
Dedicated Input Feedback Set-up Com'l Time Synchronous Clock Output[6, Input Set-up Time Synchronous Clock Input[8] Com'l
Notes: This specification measure delay from input signal applied dedicated input combinatorial output output pin. This delay assumes expander terms used form logic function. When this note applied parameter specification indicates that signal (data, asynchronous clock, asynchronous clear, and/or asynchronous preset) applied dedicated input only signal path (either clock data) employs expander logic. input signal applied additional delay equal tPIA should added comparable delay dedicated input. expanders used, maximum expander delay tEXP overall delay comparable delay without expanders. This specification measure delay from input signal applied macrocell output. This delay assumes expander terms used form logic function. This specification measure delay from input signal applied dedicated input combinatorial output output pin. This delay assumes expander terms used form logic functions includes worst-case expander logic delay pass through expander logic. This specification measure delay from input signal applied macrocell output. This delay assumes expander terms used form logic function includes worst-case expander logic delay pass through expander logic. This parameter tested periodically sampling production material. This specification measure delay from synchronous register clock internal feedback register output signal input logic array then combinatorial output. This delay assumes expanders used, register synchronously clocked feedback within same LAB. This parameter tested periodically sampling production material. data applied input capture macrocell register, set-up time minimums should observed. These parameters synchronous operation tAS2 asynchronous operation.
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CY7C3External Synchronous Switching Characteristics Over Operating Range[6] (continued) 7C341-25 Parameter fMAX1 fMAX2 Description Input Hold Time from Synchronous Clock Input[6] Synchronous Clock Input High Time Synchronous Clock Input Time Asynchronous Clear Width[3, Asynchronous Clear Registered Output Delay[5] Asynchronous Clear Recovery[3, Asynchronous Preset Width[3, Asynchronous Preset Recovery Time[3, Asynchronous Preset Registered Output Delay[6] Synchronous Clock Local Feedback Input[3, External Synchronous Clock Period (1/fMAX3)[3] External Feedback Maximum Frequency (1/(tCO1 tS1))[3, Internal Local Feedback Maximum Frequency, lesser (1/(tS1 tCF)) (1/tCO1)[3, Com'l Com'l Com'l Com'l Com'l Com'l Com'l Com'l Com'l Com'l Com'l Com'l Com'l 34.5 34.5 55.5 55.5 62.5 62.5 62.5 62.5 27.7 27.7 Min. 22.2 22.2 40.0 40.0 40.0 40.0 7C341-30 Min. 7C341-35 Min. 12.5 12.5 12.5 12.5 Unit
fMAX3
Data Path Maximum Frequency, least Com'l 1/(tWL tWH), 1/(tS1 tH), (1/tCO1)[3, Maximum Register Toggle Frequency Com'l (1/(tWL tWH))[3, Output Data Stable Time from Synchronous Clock Input[3, Com'l
fMAX4
Notes: This specification measure delay associated with internal register feedback path. This delay from synchronous clock logic array input. This delay plus register set-up time, tS1, minimum internal period internal synchronous state machine configuration. This delay feedback within same LAB. This parameter tested periodically sampling production material. This specification indicates guaranteed maximum frequency, synchronous mode, which state machine configuration with external feedback operate. assumed that data inputs feedback signals applied dedicated inputs. feedback assumed local originating within same LAB. This specification indicates guaranteed maximum frequency which state machine, with internal-only feedback, operate. register output states must also control external points, this frequency still observed long this frequency less than 1/tCO1. This frequency indicates maximum frequency which device operate data path mode (dedicated input output pin). This assumes data input signals applied dedicated input pins expander logic used. data inputs pins, appropriate calculation. This specification indicates guaranteed maximum frequency, synchronous mode, which individual output buried register cycle clock signal applied dedicated clock input pin. This parameter indicates minimum time after synchronous register clock input that previous register output data maintained output pin.
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CY7C3External Synchronous Switching Characteristics Over Operating Range[6] (continued) 7C341-25 Parameter tACO1 tACO2 tAS1 tAS2 tAWH tAWL tACF fMAXA1 Description Dedicated Asynchronous Clock Input Com'l Output Delay[6] Asynchronous Clock Input Local Com'l Feedback Combinatorial Output[19] Dedicated Input Feedback Set-up Com'l Time Asynchronous Clock Input[6] Input Set-Up Time Asynchronous Clock Input[6] Input Hold Time from Asynchronous Clock Input[6] Asynchronous Clock Input HIGH Time[6] Asynchronous Clock Input Time[6, Asynchronous Clock Local Feedback Input[21] External Asynchronous Clock Period (1/fMAX4) External Feedback Maximum Frequency Asynchronous Mode 1/(tACO1 tAS1)[22] Maximum Internal Asynchronous Frequency[23] Data Path Maximum Frequency Asynchronous Mode[24] Com'l Com'l Com'l Com'l Com'l Com'l Com'l Com'l Com'l 33.3 33.3 33.3 33.3 Min. 33.3 33.3 28.5 28.5 33.3 33.3 7C341-30 Min. 7C341-35 Min. Unit
fMAXA2 fMAXA3 fMAXA4 tAOH
Maximum Asynchronous Register Com'l Toggle Frequency 1/(tAWH tAWL)[25] Output Data Stable Time from Asyn- Com'l chronous Clock Input[26]
Notes: This specification measure delay from asynchronous register clock input internal feedback register output signal input logic array then combinatorial output. This delay assumes expanders used logic combinatorial output asynchronous clock input. clock signal applied dedicated clock input feedback within single LAB. This parameter tested periodically sampling production material. This parameter measured with positive-edge-triggered clock register. negative-edge triggering, tAWH tAWL parameters must swapped. given input used clock multiple registers with both positive negative polarity, tAWH should used both tAWH tAWL. This specification measure delay associated with internal register feedback path asynchronous clock logic array input. This delay plus asynchronous register set-up time, tAS1, minimum internal period internal asynchronously clocked state machine configuration. This delay feedback within same LAB, assumes there expander logic clock path clock input signal applied dedicated input pin. This parameter tested periodically sampling production material. This specification indicates guaranteed maximum frequency which asynchronously clocked state machine configuration with external feedback operate. assumed that data inputs, clock inputs, feedback signals applied dedicated inputs, that expander logic employed clock signal path data path. This specification indicates guaranteed maximum frequency which asynchronously clocked state machine with internal-only feedback operate. This parameter determined lesser (1/tACF tAS1)) (1/(tAWH +tAWL)). register output states must also control external points, this frequency still observed long this frequency less than 1/tACO1. This frequency maximum frequency which device operate asynchronously clocked data path mode. This specification determined least 1/(tAWH tAWL), 1/(tAS1 tAH) 1/tACO1. assumes data clock input signals applied dedicated input pins expander logic used. This specification indicates guaranteed maximum frequency which individual output buried register cycled asynchronously clocked mode clock signal applied external dedicated input pin. This parameter indicates minimum time that previous register output data maintained output after asynchronous register clock input applied external dedicated input pin.
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CY7C3Internal Switching Characteristics Over Operating Range[2]
7C341-25 Parameter tEXP tLAD tLAC tRSU tLATCH tCOMB tICS tPRE tCLR Description Dedicated Input Buffer Delay Input Buffer Delay Expander Array Delay Logic Array Data Delay Logic Array Control Delay Output Buffer Delay Output Buffer Enable Delay
[27]
7C341-30 Min.
7C341-35 Min. 12.5 12.5 12.5 12.5 Page Unit
Min. Com'l Com'l Com'l Com'l Com'l Com'l Com'l Com'l Com'l Com'l Com'l Com'l
Output Buffer Disable Delay Register Set-Up Time Relative Clock Signal Register Register Hold Time Relative Clock Signal Register Flow-Through Latch Delay Register Delay Transparent Mode Delay Clock High Time Clock Time
[28]
Com'l Com'l Com'l
Asynchronous Clock Logic Delay Com'l Synchronous Clock Delay Feedback Delay Asynchronous Register Preset Time Asynchronous Register Clear Time Com'l Com'l Com'l Com'l
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CY7C3Internal Switching Characteristics Over Operating Range[2] (continued)
7C341-25 Parameter tPCW tPCR tPIA Description Asynchronous Preset Clear Pulse Width Asynchronous Preset Clear Recovery Time Programmable Interconnect Array Delay Com'l Com'l Com'l Min. 7C341-30 Min. 7C341-35 Min. Unit
Notes: Sample tested only output change This specification guarantees maximum combinatorial delay associated with macrocell register bypass when macrocell configured combinatorial operation.
Switching Waveforms
External Combinatorial
DEDICATED INPUT/ INPUT tPD1/tPD2 COMBINATORIAL OUTPUT
COMBINATORIAL REGISTERED OUTPUT HIGH IMPEDANCE 3-STATE HIGH-IMPEDANCE 3-ST
VALID OUTPUT
C341-7
External Synchronous
DEDICATED INPUT/ INPUT SYNCHRONOUS CLOCK tCO1 ASYNCHRONOUS CLEAR/PRESET REGISTERED OUTPUTS tCO2 COMBINATORIAL OUTPUT FROM REGISTERED FEEDBACK[10]
C341-8
tRW/tPW
tRR/tPR
tRO/tPO
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CY7C3Switching Waveforms (continued)
External Asynchronous
DEDICATEDINPUT/ I/OINPUT[7] tAS1 ASYNCHRONOUS CLOCK INPUT tACO1 ASYNCHRONOUS CLEAR/PRESET ASYNCHRONOUS REGISTERED OUTPUTS tACO2 COMBINATORIAL OUTPUT FROM ASYNCH. REGISTERED FEEDBACK
C341-9
tAWH
tAWL
tRW/tPW
tRR/tPR
tAOH tRO/tPO
Internal Combinatorial
INPUT tEXP EXPANDER ARRAY DELAY tLAC, tLAD LOGIC ARRAY INPUT tPIA
LOGIC ARRAY OUTPUT
C341-10
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CY7C3Switching Waveforms (continued)
Internal Asynchronous
tIOR CLOCK CLOCK INTO LOGIC ARRAY CLOCK FROM LOGIC ARRAY DATA FROM LOGIC ARRAY tRD,tLATCH REGISTER OUTPUT LOCAL LOGIC ARRAY tPIA REGISTER OUTPUT ANOTHER
C341-11
tAWH
tAWL
tRSU
tCLR,tPRE
Internal Synchronous
SYSTEM SYSTEM CLOCK REGISTER DATA FROM LOGIC ARRAY
C341-12
tICS
tRSU
Internal Synchronous
CLOCK FROM LOGIC ARRAY DATA FROM LOGIC ARRAY
OUTPUT
HIGH IMPEDANCE STATE
C341-13
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CY7C3Ordering Information
Speed (ns) Ordering Code CY7C341-25HC/HI CY7C341-25JC/JI CY7C341-25RC/RI CY7C341-30HC/HI CY7C341-30JC/JI CY7C341-30RC/RI CY7C341-30HMB CY7C341-30RMB CY7C341-35HC/HI CY7C341-35JC/JI CY7C341-35RC/RI CY7C341-35HMB CY7C341-35RMB Package Name Package Type 84-Lead Windowed Leaded Chip Carrier 84-Lead Plastic Leaded Chip Carrier 84-Lead Windowed Grid Array 84-Lead Windowed Leaded Chip Carrier 84-Lead Plastic Leaded Chip Carrier 84-Lead Windowed Grid Array 84-Lead Windowed Leaded Chip Carrier 84-Lead Windowed Grid Array 84-Lead Windowed Leaded Chip Carrier 84-Lead Plastic Leaded Chip Carrier 84-Lead Windowed Grid Array 84-Lead Windowed Leaded Chip Carrier 84-Lead Windowed Grid Array Military Commercial/Industrial Military Commercial/Industrial Operating Range Commercial/Industrial
MILITARY SPECIFICATIONS Group Subgroup Testing Characteristics
Parameter ICC1 Subgroups
Switching Characteristics
Parameter tPD1 tPD2 tPD3 tCO1 tACO1 tACO2 tAS1 Subgroups
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CY7C3Package Diagrams
84-Leaded Windowed Leaded Chip Carrier
51-80081
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CY7C3Package Diagrams (continued)
84-Lead Plastic Leaded Chip Carrier
51-85006-A
84-Lead Windowed Grid Array
51-80026-A
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Cypress Semiconductor Corporation, 2000. information contained herein subject change without notice. Cypress Semiconductor Corporation assumes responsibility circuitry other than circuitry embodied Cypress Semiconductor product. does convey imply license under patent other rights. Cypress Semiconductor does authorize products critical components life-support systems where malfunction failure reasonably expected result significant injury user. inclusion Cypress Semiconductor products life-support systems application implies that manufacturer assumes risk such doing indemnifies Cypress Semiconductor against charges.
CY7C3Document Title: CY7C341 192-Macrocell MAX® EPLD Document Number: 38-03034 REV. 106379 Issue Date 06/18/01 Orig. Change Description Change Change from Spec#: 38-00499 38-03034
Document 38-03034 Rev.
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192-Macrocell MAX® EPLD macrocells LABs dedicated inputs, bidirec

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