CY7C340 EPLD Family Multiple Array Matrix High-Density EPLDs

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CY7C340 EPLD Family Multiple Array Matrix High-Density EPLDs

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CY7C340 EPLD Family
Multiple Array Matrix High-Density EPLDs
Features
Erasable, user-configurable CMOS EPLDs capable implementing high-density custom logic functions 0.8-micron double-metal CMOS EPROM technology (CY7C34X) Advanced 0.65-micron CMOS technology increase performance (CY7C34XB) Multiple Array MatriX architecture optimized speed, density, straightforward design implementation Programmable Interconnect Array (PIA) simplifies routing Flexible macrocells increase utilization Programmable clock control Expander product terms implement complex logic functions CY7C342B. This allows designer replace more packages with just EPLD. family comes range densities, shown below. standardizing building blocks, designer replace hundreds different 7400 series part numbers currently used most digital systems. family based architecture flexible macrocells grouped together into Logic Array Blocks (LABs). Within group additional product terms called expander product terms. These expanders used shared macrocells, allowing complex functions product terms easily implemented single macrocell. Programmable Interconnect Array (PIA) globally routes signals within devices containing more than LAB. This architecture fabricated Cypress 0.8-micron, double-layer-metal CMOS EPROM process, yielding devices with significantly higher integration, density system clock speed than largest previous generation EPLDs. CY7C34XB devices 0.65-micron shrinks original 0.8-micron family. CY7C34XBs offer faster speed bins each device Cypress family. density performance CY7C340 family accessed using Cypress's WarpTM, Warp ProfessionalTM, Warp Enterprisedesign software. Warp provides state-of-the-art synthesis, fitting, simulation other development tools very cost. Warp Professional Warp Enterprise sophisticated tool that include behavioral simulation, graphical waveform editing more. Consult datasheets Warp, Warp Professional Warp Enterprisefor more information about these development tools.
General Description
Cypress Multiple Array Matrix (MAX®) family EPLDs provides user-configurable, high-density solution general-purpose logic integration requirements. With combination innovative architecture state-of-the-art process, EPLDs offer density without sacrificing speed. architecture makes ideal replacing large amounts logic. example, 74161 counter utilizes only macrocells available CY7C342B. Similarly, 74151 8-to-1 multiplexer consumes less than over 1,000 product terms
Family Members
Feature Macrocells Flip-Flops Latches Outputs Packages
CY7C344(B) 28H,J,W,P
CY7C343(B) 44H,J
CY7C342B 68H,J,R
CY7C346(B) 84H,J 100R,N
CY7C341B 84H,J,R
Inputs[2]
Key: P-Plastic DIP; H-Windowed Ceramic Leaded Chip Carrier; J-Plastic J-Lead Chip Carrier; R-Windowed Grid Array; W-Windowed Ceramic DIP; N-Plastic Quad Flat Pack
Notes: When expander product terms used implement latches. With output.
registered trademark Advanced Micro Devices. registered trademark Altera Corporation. FLASH370, Warp, Warp Professional, Warp Enterprise trademarks Cypress Semiconductor Corporation.
Cypress Semiconductor Corporation Document 38-03013 Rev.
3901 North First Street
Jose
95134 408-943-2600 Revised July 2000
CY7C340 EPLD Family
DEDICATED INPUTS
MULTIPLE ARRAYS (LABS) LOGIC BLOCK ARRAY (LAB)
DUAL FEEDBACK EXPANDER PRODUCT TERMS
MACROCELLS
PROGRAMMABLE INTERCONNECT ARRAY (PIA)
C340-1
Figure Features
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Functional Description
Logic Array Block logic array block, shown Figure heart architecture. consists macrocell array, expander product term array, block. number macrocells, expanders, vary, depending upon device used. Global feedback signals provided within LAB, giving each functional block complete access resources. itself programmable interconnect array dedicated input bus. feedbacks macrocells pins feed PIA, providing access them through other LABs device. members CY7C340 family EPLDs that have single global bus, needed (see Figure Macrocell Traditionally, PLDs have been divided into either (programmable AND, programmable OR), PAL® (programmable AND, fixed architectures. PLDs latter type provide faster input-to-output delays, inefficient fixed allocation product terms. Statistical analysis logic designs shown that logic functions (per macrocell) require three product terms less. macrocell structure been optimized handle variable product term requirements. shown Figure each macrocell consists product term array configurable register. macrocell, combinatorial logic implemented with three product terms ORed together, which then feeds gate. second input gate also controlled product term, providing ability control active HIGH active logic implement JK-type flip-flops. more product terms required implement given function, they added macrocell from expander product term array. These additional product terms added macrocell, allowing designer build gate-intensive logic, such address decoders, adders, comparators, complex state machines, without using extra macrocells. register within macrocell programmed either operation. alternately configured flow-through latch minimum input-to-output delays, bypassed entirely purely combinatorial logic. addition, each register supports both asynchronous preset clear, allowing asynchronous loading counters shift registers, found many standard functions. These registers clocked with synchronous system clock, clocked independently from logic array. Expander Product Terms expander product terms, shown Figure dedicated input bus, programmable interconnect array, macrocell feedback, expanders themselves, feedbacks. outputs expanders then each every product term macrocell array. This allows expanders "shared" product terms logic array block. expander feed macrocells LAB, even multiple product terms same macrocell. Since these expanders feed secondary product terms (preset, clear, clock, output enable) each macrocell, complex logic functions implemented without utilizing another macrocell. Likewise, expanders feed shared other expanders, implement complex multilevel logic input latches.
MACROCELL ARRAY
BLOCK
PINS
MACROCELL ARRAY
BLOCK
PINS
EXPANDER PRODUCT TERM ARRAY
EXPANDER PRODUCT TERM ARRAY
PROGRAMMABLE INTERCONNECT ARRAY
C340-2
C340-3
Figure Typical Block Diagram
Figure 7C344 Block Diagram
Document 38-03013 Rev.
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CY7C340 EPLD Family
MACROCELL FEEDBACKS 7C344)
PROGRAMMABLE INTERCONNECT SIGNALS
OUTPUT ENABLE
PROGRAMMABLEFLIP-FLOP T,JK,SR) REGISTEREDORFLOW- THROUGH-LA OPERATION PROGRAMMABLECLOCK ASYNCCLEARANDPRESET
PRESET
CONTROL
ARRAY CLOCK
CLEAR
MACROCELL FEEDBACK
NOTE: SYSTEM DEDICATED INPUTS EXPANDER PRODUCT TERMS 7C344)
C340-4
Figure Macrocell Block Diagram
MACROCELL P-TERMS
OUTPUT ENABLE
FROM MACROCELL
THREE-STATE BUFFER
(LAB 7C344) EXPANDER P-TERMS C340-5
C340-6
Figure Expander Product Terms
Figure Block Diagram
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CY7C340 EPLD Family
Block Separate from macrocell array control block LAB. Figure shows block diagram. three-state buffer controlled macrocell product term drives pad. input this buffer comes from macrocell within associated LAB. feedback path from feed other blocks within LAB, well PIA. decoupling pins from flip-flops, registers "buried," allowing pins used dedicated outputs, bidirectional outputs, additional dedicated inputs. Therefore, applications requiring many buried flip-flops, such counters, shift registers, state machines, longer consume both macrocell register associated pin, earlier devices. Programmable Interconnect Array density speed traditionally been limited signal routing; i.e., getting signals from macrocell another. smaller devices, single array used signals available macrocells. devices increase density, number signals being routed becomes very large, increasing amount silicon used interconnections. Also, because signal must global, added loading internal connection path reduces overall speed performance device. architecture solves these problems. based concept small, flexible logic array blocks that, larger devices, interconnected PIA. solves interconnect limitations routing only signals needed each LAB. architecture designed that every signal chip within PIA. then programmed give each access signals that requires. Consequently, each receives only signals needed. This effectively solves routing problems that arise design without degrading performance device. Unlike masked programmable gate arrays, which induce variable delays dependent routing, fixed delay from point point. This eliminates undesired skews among logic signals, which cause glitches internal external logic. Warp Enterprise Warp Enterprise provides even more features. provides unlimited timing simulation source-level behavioral simulation well debugger. ability generate graphical blocks from text. even generate testbenches. Warp available UNIX platforms. Some features available UNIX version. further information Warp Warp UNIX, Warp Professional Warp Enterprise datasheets. Third-Party Software Although Warp complete CPLD development tool own, interfaces with nearly every third party tool. major third-party software vendors provide support family devices. expedite this support, Cypress supplies vendors with pertinent architectural information well design fitters products.
Programming
Impulse3device programmers from Cypress will program Cypress PLDs, CPLDs, FPGAs, PROMs. unit standalone programmer that connects IBM-compatible printer port. Third-Party Programmers with development software, Cypress strongly supports third-party programmers. major third-party programmers support family.
Cross Reference
ALTERA PREFIX PREFIX: 22V10-10C 22V10-10C 22V10-10C 22V10-10C 22V10-15C 22V10-15C 5032DC 5032DC-2 5032DC-15 5032DC-17 5032DC-20 5032DC-25 5032DM 5032DM-25 5032JC 5032JC-2 5032JC-15 5032JC-17 5032JC-20 CYPRESS PREFIX: PREFIX: PALC PALC22V10D-7C PALC22V10D-10C PAL22V10C-7C+ PAL22V10C-10C+ PALC22V10B-15C PALC22V10D-15C 7C344-25WC 7C344-20WC 7C344-15WC Call Factory 7C344-20WC 7C344-25WC 7C344-25WMB 7C344-25WMB 7C344-25HC 7C344-20HC 7C344-15HC Call Factory 7C344-20HC Page
Development Software Support
Warp Warp state-of-the-art compiler complete CPLD design tool. design entry, Warp provides IEEE-STD-1076/1164 VHDL text editor, IEEE-STD-1364 Verilog text editor graphical finite state machine editor. provides optimized synthesis fitting replacing basic circuits with ones pre-optimized target device, implementing logic unused memory perfect communication between fitting synthesis. Warp provides other tools such graphical timing simulation analysis. Warp Professional Warp Professional contains several additional features. provides extra method design entry with graphical block diagram editor. allows timing simulation instead only allows comparing waveforms before after design changes.
Document 38-03013 Rev.
CY7C340 EPLD Family
Cross Reference (continued)
ALTERA 5032JC-25 5032JM 5032JM-25 5032LC 5032LC-2 5032LC-15 5032LC-17 5032LC-20 5032LC-25 5032PC 5032PC-2 5032PC-15 5032PC-17 5032PC-20 5032PC-25 5064JC 5064JC-1 5064JC-2 5064JI 5064JM 5064LC 5064LC-1 5064LC-2 5128AGC-12 5128AGC-15 5128AGC-20 5128AJC-12 5128AJC-15 5128AJC-20 5128ALC-12 5128ALC-15 5128ALC-20 5128GC 5128GC-1 5128GC-2 5128GM 5128JC 5128JC-1 5128JC-2 5128JI 5128JI-2 5128JM 5128LC 5128LC-1 CYPRESS 7C344-25HC 7C344-25HMB 7C344-25HMB 7C344-25JC 7C344-20JC 7C344-15JC Call Factory 7C344-20JC 7C344-25JC 7C344-25PC 7C344-20PC 7C344-15PC Call Factory 7C344-20PC 7C344-25PC 7C343-35HC 7C343-25HC 7C343-30HC 7C343-35HI 7C343-35HMB 7C343-35JC 7C343-25JC 7C343-30JC 7C342B-12RC 7C342B-15RC 7C342B-20RC 7C342B-12HC 7C342B-15HC 7C342B-20HC 7C342B-12JC 7C342B-15JC 7C342B-20JC 7C342-35RC 7C342-25RC 7C342-30RC 7C342-35RMB 7C342-35HC 7C342-25HC 7C342-30HC 7C342-35HI 7C342-30HI 7C342-35HMB 7C342-35JC 7C342-25JC Page
Cross Reference (continued)
ALTERA 5128LC-2 5128LI 5128LI-2 5130GC 5130GC-1 5130GC-2 5130GM 5130JC 5130JC-1 5130JC-2 5130JM 5130LC 5130LC-1 5130LC-2 5130LI 5130LI-2 5130QC 5130QC-1 5130QC-2 5130QI 5192AGC-15 5192AGC-20 5192AJC-15 5192AJC-20 5192ALC-1 5192ALC-2 5192GC 5192GC-1 5192GC-2 5192JM 5192JC 5192JC-1 5192JC-2 5192GM 5192JI 5192LC 5192LC-1 5192LC-2 CYPRESS 7C342-30JC 7C342-35JI 7C342-30HI 7C346-35RC 7C346-25RC 7C346-30RC 7C346-35RM 7C346-35HC 7C346-25HC 7C346-30HC 7C346-35HM 7C346-35JC 7C346-25JC 7C346-30JC 7C346-35JI 7C346-30JI 7C346-35NC 7C346-25NC 7C346-30NC 7C346-35NI 7C341B-15RC 7C341B-20RC 7C341B-15HC 7C341B-20HC 7C341B-15JC 7C341B-20JC 7C341-35RC 7C341-25RC 7C341-30RC 7C341-35HM 7C341-35HC 7C341-25HC 7C341-30HC 7C341-35RM 7C341-35HI 7C341-35JC 7C341-25JC 7C341-30JC
Document 38-03013 Rev.
Cypress Semiconductor Corporation, 2000. information contained herein subject change without notice. Cypress Semiconductor Corporation assumes responsibility circuitry other than circuitry embodied Cypress Semiconductor product. does convey imply license under patent other rights. Cypress Semiconductor does authorize products critical components life-support systems where malfunction failure reasonably expected result significant injury user. inclusion Cypress Semiconductor products life-support systems application implies that manufacturer assumes risk such doing indemnifies Cypress Semiconductor against charges.
CY7C340 EPLD Family
Document Title: CY7C340 EPLD Family Multiple Array Matrix High-Density EPLDs Document: 38-03013 REV. 106313 Issue Date 04/23/01 Orig. Change Description Change Change from Spec number: 38-03013
Document 38-03013 Rev.
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CY7C340 EPLD Family Multiple Array Matrix High-Density EPLDs

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