FISPbus INTERFACE DMA_END Microprocessor Peripherals FPGA/CP

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FISPbus INTERFACE DMA_END Microprocessor Peripherals FPGA/CP

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InventraDMAx1-B1 Controller
FISPbus INTERFACE
DMA_END
Microprocessor Peripherals FPGA/CPLD
DMAx1-B1 features:
Single-channel controller with
REGISTER INTERFACE
FISPbus INTERFACE
CHANNEL_ID
FISPbus interfaces
Fixed Incrementing address
source destination
Automatic packing, unpacking
DMAx1-B1
realignment data controller
FISPbus INTERFACE
DMA_END CHANNEL_ID
Simple FTS/FTR handshakes with
SYSTEM
S_RST DMA_REQ IR(2)
A_RST
other FISP products maximize bandwidths
strobes signal
both source destination slave devices
Generic `FISPbus' microprocessor
interface DMAx1-B1 Block Diagram
CPLD Specifics InventraDMAxN
Overview
Core Block
DMAx1-B1 single-channel implementation Supported Family Cypress Delta39KCPLD InventraDMAxN controller netlist 0.18µm SRAM process Device tested CY39100V676-200MBC Cypress Delta39Kfamily complex PLDs (CPLDs). Channels DMAxN core multi-channel controller Data Width bits; with FISPbus interfaces, which bits bits wide depending implementation. Post-Layout Performance 54MHz number channels also depends implementation. Utilization Parameters DMAx1-B1, interface bits wide Macrocells used 247/1536 other bits wide, there channel. Channel Memory Blocks used 0/12 Cluster Memory Blocks used 0/24 channel transfers between ports used (unidirectional) 163/294 interfaces either direction. core allows fixed incrementing addresses source destination, automatic packing, unpacking realignment data controller match CPLD Deliverables: source destination widths start addresses. strobes signal .vif database files Delta39Kof both source destination slave devices. CPLDs DMAx1-B1 connects other FISPbus products including priority Wrappers .vif files both round-robin based FISPbus arbiters. bandwidths maximized through Verilog VHDL simple FTS/FTR handshakes with other FISP products. Compiled testbench netlist simulThe DMAx1-B1 deliverables comprise modified .vif files each component ation model with ModelSim (toplevel submodules), wrappers .vif files Verilog VHDL, Core specification compiled testbench netlist simulation model with ModelSim, Readme/help file supporting documentation.
www.inventra.com
InventraDMAx1-B1 CPLD netlist
Description
DMAx1-B1 supports single channel, transferring data either direction across master interfaces, with different address data widths. third interface, Register Interface, slave handles accesses internal registers. controller decouples accesses between interfaces, buffering data internally. performs data reformatting required match data widths each aligns data byte address each interface. Single-bus achieved connecting both interfaces same bus. channel programmed with starting address each interface, number bytes transfer direction transfer. channel configured transfer data either direction. starts when channel's DMA_Req goes active start command issued channel's command register. From then channel generates read write request each appropriate interface, until requested bytes transferred. Once initiated, Controller starts reading from source accumulating data internal buffer. When enough data been received allow correct byte alignment destination, writes destination begin. either slave ready, transfers held waits corresponding bus. (Free Send) (Free Receive) signals FISPbus inform Controller that slave ready transfer with waits. They further qualify initiation access ensure quick response with minimum time bus. strobe generated with last read write each interface inform
slave device that transfer ended. interrupt also generated DMA. Accesses whole width where possible. Partial width accesses happen start depending start byte addresses number bytes remaining transfer. Both source destination addresses fixed. normally ends when bytes specified byte count have been transferred. possible terminate early command channel control registers. status indicates when been terminated before bytes transferred. design completely synchronous, using single clock. More detailed information given DMAxN Product Specification, which describes interface signal timing software register interfacing. FISPbus Interface FISPbus interface generic microprocessor interface specification developed specifically Inventra's telecom cores. provides user with easy use, fully featured, on-chip structure. FISPbus interface allows direct interconnection multiple cores, well indirect connection microprocessor other standard) Microprocessor Personality Module (MPM) core. Further information given FISPbus Engineering Specification. DMAx1-B1's Interfaces both type Master/4. Register Interface type Slave Full. Applications Applications DMAx1-B1 include microprocessor peripherals, memory management units communications processors.
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PD-62301.001-FO

FISPbus INTERFACE DMA_END Microprocessor Peripherals FPGA/CP

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