SMPTE-259M/DVB-ASI Descrambler/Framer-Controller 1CY7C9335 F

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SMPTE-259M/DVB-ASI Descrambler/Framer-Controller 1CY7C9335 F

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CY7C9335
SMPTE-259M/DVB-ASI Descrambler/Framer-Controller
1CY7C9335
Fully compatible with SMPTE-259M SMPTE-125M compliant 4:2:2 component video SMPTE-244M compliant 4fsc composite video Fully compatible with DVB-ASI Operates from single supply 100-pin TQFP package Decodes 10-bit parallel digital streams rate from 16-40 characters/sec (160-400 Mbits/sec serial) Operates with CY7B9334 SMPTE HOTLinkdeserializer/receiver descrambler NRZI-to-NRZ decoder bypassed data output
inputs CY7C9335 designed directly mated CY7B9334 HOTLink receiver, which converts SMPTE-259M compatible high-speed serial data stream into 10-bit parallel characters. This device performs both (sync) detection framing, data descrambling with SMPTE-259M algorithm, NRZI-to-NRZ decoding. These functions operate character rate from MHz. those systems operating with non-SMPTE-259M compliant video streams diagnostic purposes), descrambler NRZI decoding functions disabled. DVB-ASI Operation CY7C9335 also contains necessary multiplexers, control inputs outputs, control DVB-ASI compliant video stream. DVB-ASI operation enabled through activation single input signal. This allows single serial-to-parallel input port support both SMPTE data streams under software hardware control. DVB-ASI mode CY7C9335 automatically enables both 8B/10B decoder multi-byte framer present CY7B9334 receiver/deserializer. error detection, fill, command codes detected output CY7C9335. CY7C9335 operates from single supply. available 100-pin TQFP space saving package.
Functional Description
SMPTE-259M Operation CY7C9335 CMOS integrated circuit designed decode SMPTE-125M SMPTE-244M bit-parallel digital characters other data formats) using SMPTE-259M decoding rules. Following decoding, characters framed locating 30-bit pattern parallel character stream. framed characters then output.
Logic Block Diagram
D9(RVS)
BARREL SHIFTER
DETECTOR/FRAMER
NRZI-TO-NRZ DECODER
SMPTE DESCRAMBLER
MODE MULTIPLEXOR OUTPUT REGISTER
PD9(SVS) PD(SC/D) H_SYNC SYNC_ERR
INPUT REGISTER
D0(SC/D)
SYNC_EN BYPASS DVB_EN
HOTLink trademark Cypress Semiconductor Corporation.
Cypress Semiconductor Corporation Document 38-02011 Rev.
3901 North First Street
OFFSET
Jose
95134 408-943-2600 Revised March 1999
CY7C9335
Configuration
TQFP View
D9(RVS) D0(SC/D)
BYPASS SYNC_EN DVB_EN
SYNC_ERR H_SYNC
Maximum Ratings
(Above which useful life impaired. user guidelines, tested.) Storage Temperature -40°C +125°C Supply Voltage Ground Potential.-0.5V +7.0V Voltage Applied Outputs High-Z State.-0.5V +7.0V Output Current Into Outputs Input Voltage .-0.5V +7.0V Static Discharge Voltage.>2001 (per MIL-STD-883, Method 3015) Latch-Up Current.>200
PD9(RVS) (SC/D)
Operating Range
Range Commercial Industrial Ambient Temperature +70°C -40°C +85°C
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CY7C9335
Descriptions
CY7C9335 SMPTE-259M Decoder Name BYPASS Input Description Bypass SMPTE decoding. BYPASS ignored DVB_EN active (LOW). BYPASS HIGH rising edge (and DVB_EN HIGH), data latched into input register routed around both NRZI decoder SMPTE descrambler presented output register. BYPASS rising edge clock (and DVB_EN HIGH), data present input register routed through NRZI decoder SMPTE scrambler. Reframe. This output inverted DVB-EN signal. CY7B9334 Port Select. When DVB-ASI mode, this output will alternately select either INA± INB± receiver port based errors detected data stream. This allows CY7C9335 operate with normal inverted DVB-ASI data streams would commonly found DVB-ASI streams routed through SMPTE switches). This requires CY7B9334 INA± INB± inputs connected same signal, with INB± connected invert signal. Horizontal Sync. This output toggles once every time that field recognized. changes state clock cycle prior first character field (3FF 10-bit hex) appearing PD0-9 outputs. This output also toggles indicate detection sequence, even when characters different offset from present offset SYNC_EN active (HIGH). This toggling action disabled when DVB_EN active (LOW). Sync Filtering Enabled. This input controls operation SMPTE framer. When this signal active (HIGH) sequence detected, 10-bit character boundary different from previously received TRS, H_SYNC output toggled, character offset updated. immediately following also different offset, H_SYNC output again toggled character offset updated match that detected sequence. When this signal inactive (LOW), framer will update character offset toggle H_SYNC every detected sequence. Sync Error. This output pulses HIGH clock period when sequence detected that offset from previous 10-bit character offset. This pulse starts same time H_SYNC signal toggles, only occurs when SYNC_EN active (HIGH) character offset updated. Parallel Data Received Violation Symbol. This framed output data bus. latched output register rising edge CKR. When DVB_EN active (LOW), this output indicates that character present PD8-0 identifies type error detected character stream. When DVB_EN disabled (HIGH), character output register bits PD9-0 descrambled framed character SMPTE data stream. Parallel Data through signals present PD8-1 outputs latched output register rising edge CKR. When DVB_EN disabled (HIGH), these signals middle eight bits descrambled framed SMPTE 10-bit data character. When DVB_EN active (LOW), these signals full DVB-ASI data bus. Parallel Data Special Code/Data Select. This output data field. latched output register rising edge CKR. When DVB_EN active (LOW), this output identifies that character present PD8-1 either command (HIGH) data (LOW) character). When DVB_EN inactive (HIGH), this output data descrambled framed SMPTE data character. Input This input register. should connected directly CY7B9334 deserializer output signal RVS(Qj). Input Bits through These signals should connected directly CY7B9334 deserializer output signals Q7-0 respectively. Input This input register. should connected directly CY7B9334 deserializer output signal SC/D(Qa). Mode Enable. This signal sampled rising edge clock. DVB_EN active (LOW), data present D0-9 inputs latched routed PD0-9 outputs. Recovered Clock Read. This clock controls synchronous operations CY7C9335. operates character rate which equivalent tenth deserialized bit-rate. This clock driven directly output CY7B9334 deserializer. Output Enable. When this signal HIGH outputs driven their normal logic levels. When LOW, outputs placed High-Z state.
Output Output
H_SYNC
Output
SYNC_EN
Input
SYNC_ERR Output
PD9(RVS)
Output
PD8-1
Output
PD0(SC/D)
Output
D9(RVS) D8-1 D0(SC/D) DVB_EN
Input Input Input Input Input
Input
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CY7C9335
Descriptions (continued)
CY7C9335 SMPTE-259M Decoder Name Description Power. Ground. DVB-ASI Operation CY7C9335 designed operate both SMPTE-259M DVB-ASI environments. When operated SMPTE-only environments, DVB_EN inputs must tied driven HIGH. DVB-ASI operation enabled asserting DVB_EN LOW. This signal latched rising edge clock. When CY7C9335 placed mode, SMPTE NRZI decoders bypassed, data latched into input register routed directly output register. Error Detected Errors detected DVB-ASI data stream indicated being HIGH. specific type error identified remaining Q8-0 bits output register. Command Code Reception DVB-ASI interface does normally transmit command characters other than K28.5 code that used both synchronization fill character when data being transmitted. These K28.5 characters normally received C5.0 characters. other command characters also transmitted, these characters identified being HIGH, bits present Q8-1. Invert Controller DVB-ASI data streams 8B/10B encoded characters. these characters routed through SMPTE switches repeaters, signals inverted causing them decode into incorrect illegal characters. CY7C9335 contains state machine that, conjunction with CY7B9334 SMPTE HOTLink receiver, allows inverted DVB-ASI data streams decoded into their correct characters. This state machine only enabled when mode. monitors data stream errors, inverts data stream CY7B9334 exceeds preset statistical error rate. this operate output CY7C9335 needs connected input CY7B9334 SMPTE HOTLink receiver (through appropriate resistive divider). CY7C9335 used DVB-ASI operation, output left open.
CY7C9335 Description
Input Register input register clocked rising edge CKR. This register captures data present D0-9 inputs every clock cycle. addition data inputs, control inputs except also captured each rising edge CKR. This includes BYPASS, DVB_EN, SYNC_EN. NRZI-to-NRZ Decoder data input register routed through NRZI-to-NRZ decoder prior being SMPTE scrambler. This removes extra transitions added data stream NRZI encoder transmit interface. SMPTE Descrambler Once data been converted back NRZ, then routed through linear feed-forward descrambler. decodes data present decode register using polynomial remove extra transitions added data stream transmit interface. Framer Framer used detect 30-bit sequences (3FF, 000, 10-bit hex) character stream. Anytime this sequence detected, H_SYNC output toggles. This sequence also used frame received characters that characters delivered output register their correct 10-bit boundaries. SYNC_EN disabled (LOW) sequence detected decoded data stream, character offset register match offset sequence, both sequence following characters output their proper 10-bit boundaries. SYNC_EN enabled, sequence detected whose character offset does match that offset register, internal flag offset register updated. next consecutive sequence this flag cleared offset register updated. dethe
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CY7C9335
Electrical Characteristics Over Operating Range
Parameter Description Output HIGH Voltage Output Voltage Input HIGH Voltage Input Voltage Input Load Current Output Leakage Current Output Short Circuit Current
Test Conditions -3.2 Min. 16.0 Note Note VCC, Output Disabled Max., VOUT 0.5V
Min.
Max.
Unit
-0.5 -160
Capacitance[3]
Parameter COUT Description Input Capacitance Output Capacitance Test Conditions MHz, 5.0V Max. Unit
Test Loads Waveforms
OUTPUTS OUTPUT INCLUDING SCOPE OUTPUT INPUT PULSES 3.0V
INCLUDING SCOPE Equivalent OUTPUT
EQUIVALENT 2.08V
7C9335-9
Switching Characteristics Over Operating Range[4]
CY7C9335-27 Parameter tCPRH tCPRL tCKR Description Input Output (DVB_EN only) Input Data Set-Up Time Input Data Hold Time Pulse Width HIGH Pulse Width Read Clock Cycle[5] Output Access Time from Output Hold Time from Input Output Enable Input Output Disable
CY7C9335-40 Min. Max. Unit 62.5
Min.
Max.
62.5
Notes: These absolute values with respect device ground. overshoots with respect system tester noise included. more than output should tested time. Duration short circuit should exceed second. VOUT 0.5V been chosen avoid test problems caused tester ground degradation. Tested initially after design process changes that effect these parameters. parameters with outputs switching. clock period extended single clock cycle when framing occurs DVB-ASI mode. Test load used this parameter. Test load used other parameters.
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CY7C9335
Switching Waveform
tCKR
D0-9, DVB_EN, BYPASS, SYNC_EN,
tCPRL tCPRH
PD0-9, SYNC_ER H_SYNC,
DVB_EN
Ordering Information
Ordering Code CY7C9335-270AC CY7C9335-400AC Package Name A100 A100 Package Type 100-pin Thin Quad Flat Pack 100-pin Thin Quad Flat Pack Operating Range Commercial Commercial
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CY7C9335
Package Diagram
100-Pin Thin Plastic Quad Flat Pack (TQFP) A100
51-85048-A
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Cypress Semiconductor Corporation, 1999. information contained herein subject change without notice. Cypress Semiconductor Corporation assumes responsibility circuitry other than circuitry embodied Cypress Semiconductor product. does convey imply license under patent other rights. Cypress Semiconductor does authorize products critical components life-support systems where malfunction failure reasonably expected result significant injury user. inclusion Cypress
CY7C9335
Document Title: CY7C9335 SMPTE-259M/DVB-ASI Descrambler/Framer-Controller Document Number: 38-02011 REV. 105849 Issue Date 03/22/01 Orig. Change Description Change Change from Spec number: 38-00572 38-02011
Document 38-02011 Rev.
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SMPTE-259M/DVB-ASI Descrambler/Framer-Controller 1CY7C9335 F

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