8-bit Microcontroller with 128K Bytes In-System Programmable Flash ATm
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8-bit Microcontroller with 128K Bytes In-System Programmable Flash ATmega103(L) Summary
Rev. 0945GS-09/01
Note: This summary document. complete document available site www.atmel.com.
Configuration
(AD3) (AD4) (AD5) (AD6) (AD7) (A15)
TQFP
(A14) (A13) (A12) (A11) (A10) (A9) (A8)
(AD2) (AD1) (AD0)
(ADC7) (ADC6) (ADC5) (ADC4) (ADC3) (ADC2) (ADC1) (ADC0) AREF AGND AVCC
INDEX CORNER
(T2) (T1) (IC1) (INT3) (INT2) (INT1) (INT0) XTAL1 XTAL2
RESET TOSC1 TOSC2 (OC2/PWM2)
(PDI/RXD)
(PDO/TXD)
(AC+)
(AC-)
(INT4)
(INT5)
(INT6)
(INT7)
(SS)
(SCK)
(MOSI)
(MISO)
(OC0/PWM0)
(OC1A/PWM1A)
(OC1B/PWM1B)
ATmega103(L)
0945GS-09/01
ATmega103(L)
Description
ATmega103(L) low-power, CMOS, 8-bit microcontroller based RISC architecture. executing powerful instructions single clock cycle, ATmega103(L) achieves throughputs approaching MIPS MHz, allowing system designer optimize power consumption versus processing speed. core based enhanced RISC architecture that combines rich instruction with general-purpose working registers. registers directly connected Arithmetic Logic Unit (ALU), allowing independent registers accessed single instruction executed clock cycle. resulting architecture more code efficient while achieving throughputs times faster than conventional CISC microcontrollers. ATmega103(L) provides following features: 128K bytes In-System Programmable Flash, bytes EEPROM, bytes SRAM, general-purpose lines, input lines, output lines, general-purpose working registers, real-time counter (RTC), flexible timer/counters with compare modes PWM, UART, programmable watchdog timer with internal oscillator, serial port software-selectable power saving modes. Idle mode stops while allowing SRAM, timer/counters, port interrupt system continue functioning. Power-down mode saves register contents freezes oscillator, disabling other chip functions until next interrupt hardware reset. Power-save mode, timer oscillator continues run, allowing user maintain timer base while rest device sleeping. device manufactured using Atmel's high-density nonvolatile memory technology. On-chip Flash allows program memory reprogrammed in-system through serial interface conventional nonvolatile memory programmer. combining 8-bit RISC with large array Flash monolithic chip, Atmel ATmega103(L) powerful microcontroller that provides highly flexible cost-effective solution many embedded control applications. ATmega103(L) supported with full suite program system development tools including: compilers, macro assemblers, program debugger/simulators, incircuit emulators evaluation kits.
0945GS-09/01
Block Diagram
Figure ATmega103(L) Block Diagram
PORTF BUFFERS AVCC DATA REGISTER PORTA DATA DIR. REG. PORTA DATA REGISTER PORTC 8-BIT DATA PORTA DRIVER/BUFFERS PORTC DRIVERS
ANALOG
AGND AREF INTERNAL OSCILLATOR OSCILLATOR
XTAL1
XTAL1 PROGRAM COUNTER STACK POINTER WATCHDOG TIMER OSCILLATOR TOSC2
PROGRAM FLASH
SRAM
CONTROL REGISTER
TIMING CONTROL
TOSC1
INSTRUCTION REGISTER
GENERAL PURPOSE REGISTERS
TIMER/ COUNTERS
RESET
INSTRUCTION DECODER
INTERRUPT UNIT
CONTROL LINES
EEPROM
STATUS REGISTER
PROGRAMMING LOGIC
UART
ANALOG COMPARATOR
DATA REGISTER PORTE
DATA DIR. REG. PORTE
DATA REGISTER PORTB
DATA DIR. REG. PORTB
DATA REGISTER PORTD
DATA DIR. REG. PORTD
PORTE DRIVER/BUFFERS PORTB DRIVER/BUFFERS PORTD DRIVER/BUFFERS
ATmega103(L)
0945GS-09/01
ATmega103(L)
Descriptions
Port (PA7.PA0) Supply voltage. Ground. Port 8-bit bi-directional port. Port pins provide internal pull-up resistors (selected each bit). Port output buffers sink drive displays directly. When pins used inputs externally pulled low, they will source current internal pull-up resistors activated. Port serves Multiplexed Address/Data when using external SRAM. Port pins tri-stated when reset condition becomes active, even clock running. Port (PB7.PB0) Port 8-bit bi-directional port with internal pull-up resistors. Port output buffers sink inputs, Port pins that externally pulled low, will source current pull-up resistors activated. Port also serves functions various special features. Port pins tri-stated when reset condition becomes active, even clock running. Port (PC7.PC0) Port 8-bit output port. Port output buffers sink Port also serves Address output when using external SRAM. Since Port output only port, Port pins tri-stated when reset condition becomes active. Port (PD7.PD0) Port 8-bit bi-directional port with internal pull-up resistors. Port output buffers sink inputs, Port pins that externally pulled will source current pull-up resistors activated. Port also serves functions various special features. Port pins tri-stated when reset condition becomes active, even clock running. Port (PE7.PE0) Port 8-bit bi-directional port with internal pull-up resistors. Port output buffers sink inputs, Port pins that externally pulled will source current pull-up resistors activated. Port also serves functions various special features. Port pins tri-stated when reset condition becomes active, even clock running Port (PF7.PF0) RESET Port 8-bit input port. Port also serves analog inputs ADC. Reset input. external reset generated level RESET pin. Reset pulses longer than will generate reset, even clock running. Shorter pulses guaranteed generate reset. Input inverting oscillator amplifier input internal clock operating circuit. Output from inverting oscillator amplifier.
0945GS-09/01
XTAL1 XTAL2
TOSC1 TOSC2
Input inverting Timer/Counter oscillator amplifier. Output from inverting Timer/Counter oscillator amplifier. External SRAM write strobe External SRAM read strobe Address Latch Enable used when External Memory enabled. strobe used latch low-order address bits) into address latch during first access cycle, AD0-7 pins used data during second access cycle. Supply voltage Port including ADC. must connected when used ADC. "ADC Noise Canceling Techniques" page details when using ADC. AREF analog reference input converter. operations, voltage range AGND AVCC must applied this pin. board separate analog ground plane, this should connected this ground plane. Otherwise, connect GND. programming enable serial programming mode. holding this during power-on reset, device will enter serial programming mode. function during normal operation.
AVCC
AREF
AGND
ATmega103(L)
0945GS-09/01
ATmega103(L)
Register Summary
Address ($5F) ($5E) ($5D) ($5C) ($5B) ($5A) ($59) ($58) ($57) ($56) ($55) ($54) ($53) ($52) ($51) ($50) ($4F) ($4E) ($4D) ($4C) ($4B) ($4A) ($49) ($48) ($47) ($46) ($45) ($44) ($43) ($47) ($3F) ($3E) ($3D) ($3C) ($3B) ($3A) ($39) ($38) ($37) ($36) ($35) ($32) ($31) ($30) ($2F) ($2E) ($2D) ($2C) ($2B) ($2A) ($29) ($28) ($27) ($26) ($25) ($24) ($23) ($22) ($21) ($20) Name SREG XDIV RAMPZ EICR EIMSK EIFR TIMSK TIFR MCUCR MCUSR TCCR0 TCNT0 OCR0 ASSR TCCR1A TCCR1B TCNT1H TCNT1L OCR1AH OCR1AL OCR1BH OCR1BL ICR1H ICR1L TCCR2 TCNT2 OCR2 WDTCR EEARH EEARL EEDR EECR PORTA DDRA PINA PORTB DDRB PINB PORTC PORTD DDRD PIND SPDR SPSR SPCR UBRR ACSR ADMUX ADCSR ADCH ADCL PORTE DDRE PINE PINF ADEN ADC7 PORTE7 DDE7 PINE7 PINF7 ADSC ADC6 PORTE6 DDE6 PINE6 PINF6 ADC5 PORTE5 DDE5 PINE5 PINF5 RXCIE TXCIE UDRE UDRIE SPIF SPIE WCOL DORD PORTA7 DDA7 PINA7 PORTB7 DDB7 PINB7 PORTC7 PORTD7 DDD7 PIND7 PORTA6 DDA6 PINA6 PORTB6 DDB6 PINB6 PORTC6 PORTD6 DDD6 PIND6 PORTA5 DDA5 PINA5 PORTB5 DDB5 PINB5 PORTC5 PORTD5 DDD5 PIND5 PWM2 COM1A1 ICNC1 COM1A0 ICES1 COM1B1 Bit7 SP15 XDIVEN ISC71 INT7 INTF7 OCIE2 OCF2 Bit6 SP14 XDIV6 ISC70 INT6 INTF6 TOIE2 TOV2 PWM0 Bit5 SP13 XDIV5 ISC61 INT5 INTF5 TICIE1 ICF1 COM01 Bit4 SP12 XDIV4 ISC60 INT4 INTF4 OCIE1A OCF1A COM00 Bit3 SP11 XDIV3 ISC51 INT3 OCIE1B OCF1B CTC0 Bit2 SP10 XDIV2 ISC50 INT2 TOIE1 TOV1 CS02 Bit1 XDIV1 ISC41 INT1 OCIE0 OCF0 EXTRF CS01 Bit0 XDIV0 RAMPZ0 ISC40 INT0 TOIE0 TOV0 PORF CS00 Page page page page page page page page page page page page page page page page OCR0UB PWM11 CS11 TCR0UB PWM10 CS10 page page page page page page page page page page page CS21 CS20 page page page WDP1 EEAR9 WDP0 EEAR8 page page page page EEMWE PORTA2 DDA2 PINA2 PORTB2 DDB2 PINB2 PORTC2 PORTD2 DDD2 PIND2 CPHA CHR9 ACIC MUX2 ADPS2 ADC2 PORTE2 DDE2 PINE2 PINF2 EEWE PORTA1 DDA1 PINA1 PORTB1 DDB1 PINB1 PORTC1 PORTD1 DDD1 PIND1 SPR1 RXB8 ACIS1 MUX1 ADPS1 ADC9 ADC1 PORTE1 DDE1 PINE1 PINF1 EERE PORTA0 DDA0 PINA0 PORTB0 DDB0 PINB0 PORTC0 PORTD0 DDD0 PIND0 SPR0 TXB8 ACIS0 MUX0 ADPS0 ADC8 ADC0 PORTE0 DDE0 PINE0 PINF0 page page page page page page page page page page page page page page page page page page page page page page page page page page page WDP2 EEAR10 CS12 TCN0UB
Timer/Counter0 (8-bit) Timer/Counter0 Output Compare Register COM1B0 CTC1
Timer/Counter1 Counter Register High Byte Timer/Counter1 Counter Register Byte Timer/Counter1 Output Compare Register High Byte Timer/Counter1 Output Compare Register Byte Timer/Counter1 Output Compare Register High Byte Timer/Counter1 Output Compare Register Byte Timer/Counter1 Input Capture Register High Byte Timer/Counter1 Input Capture Register Byte COM21 COM20 CTC2 CS22 Timer/Counter2 (8-bit) Timer/Counter2 Output Compare Register WDTOE EEAR11
EEPROM Address Register EEPROM Data Register PORTA4 DDA4 PINA4 PORTB4 DDB4 PINB4 PORTC4 PORTD4 DDD4 PIND4 MSTR RXEN ADIF ADC4 PORTE4 DDE4 PINE4 PINF4 EERIE PORTA3 DDA3 PINA3 PORTB3 DDB3 PINB3 PORTC3 PORTD3 DDD3 PIND3 CPOL TXEN ACIE ADIE ADC3 PORTE3 DDE3 PINE3 PINF3
Data Register
UART Data Register
UART Baud Rate Register
Note:
compatibility with future devices, reserved bits should written zero accessed. Reserved memory addresses should never written. Some status flags cleared writing logical them. Note that instructions will operate bits register, writing back into flag read set, thus clearing flag. instructions work with registers only.
0945GS-09/01
Instruction Summary
Mnemonic ADIW SUBI SBCI SBIW ANDI RJMP IJMP RCALL ICALL CALL RETI CPSE SBRC SBRS SBIC SBIS BRBS BRBC BREQ BRNE BRCS BRCC BRSH BRLO BRMI BRPL BRGE BRLT BRHS BRHC BRTS BRTC BRVS BRVC BRIE BRID ELPM Operands Rdl, Rdl, Description Registers with Carry Registers Immediate Word Subtract Registers Subtract Constant from Register Subtract with Carry Registers Subtract with Carry Constant from Reg. Subtract Immediate from Word Logical Registers Logical Register Constant Logical Registers Logical Register Constant Exclusive Registers One's Complement Two's Complement Bit(s) Register Clear Bit(s) Register Increment Decrement Test Zero Minus Clear Register Register Relative Jump Indirect Jump Direct Jump Relative Subroutine Call Indirect Call Direct Subroutine Call Subroutine Return Interrupt Return Compare, Skip Equal Compare Compare with Carry Compare Register with Immediate Skip Register Cleared Skip Register Skip Register Cleared Skip Register Branch Status Flag Branch Status Flag Cleared Branch Equal Branch Equal Branch Carry Branch Carry Cleared Branch Same Higher Branch Lower Branch Minus Branch Plus Branch Greater Equal, Signed Branch Less Than Zero, Signed Branch Half-carry Flag Branch Half-carry Flag Cleared Branch T-flag Branch T-flag Cleared Branch Overflow Flag Branch Overflow Flag Cleared Branch Interrupt Enabled Branch Interrupt Disabled Extended Load Program Memory Move between Registers Load Immediate Operation Rdh:Rdl Rdh:Rdl Rdh:Rdl Rdh:Rdl ($FF STACK STACK (Rr(b) (Rr(b) (P(b) (P(b) (SREG(s) then (SREG(s) then then then then then then then then then then then then then then then then then then then RAMPZ) Flags Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,C,N,V Z,C,N,V,H Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V None None None None None None None None None Z,N,V,C,H Z,N,V,C,H Z,N,V,C,H None None None None None None None None None None None None None None None None None None None None None None None None None None None Clocks 1/2/3 1/2/3 1/2/3 1/2/3 1/2/3 ARITHMETIC LOGIC INSTRUCTIONS
BRANCH INSTRUCTIONS
DATA TRANSFER INSTRUCTIONS
ATmega103(L)
0945GS-09/01
ATmega103(L)
Instruction Summary (Continued)
Mnemonic PUSH SWAP BSET BCLR SLEEP Operands Y+q, Z+q, Description Load Indirect Load Indirect Post-increment Load Indirect Pre-decrement Load Indirect Load Indirect Post-increment Load Indirect Pre-decrement Load Indirect with Displacement Load Indirect Load Indirect Post-increment Load Indirect Pre-decrement Load Indirect with Displacement Load Direct from SRAM Store Indirect Store Indirect Post-increment Store Indirect Pre-decrement Store Indirect Store Indirect Post-increment Store Indirect Pre-decrement Store Indirect with Displacement Store Indirect Store Indirect Post-increment Store Indirect Pre-decrement Store Indirect with Displacement Store Direct SRAM Load Program Memory Port Port Push Register Stack Register from Stack Register Clear Register Logical Shift Left Logical Shift Right Rotate Left through Carry Rotate Right through Carry Arithmetic Shift Right Swap Nibbles Flag Flag Clear Store from Register Load from Register Carry Clear Carry Negative Flag Clear Negative Flag Zero Flag Clear Zero Flag Global Interrupt Enable Global Interrupt Disable Signed Test Flag Clear Signed Test Flag Two's Complement Overflow Clear Two's Complement Overflow SREG Clear SREG Half-carry Flag SREG Clear Half-carry Flag SREG Operation Sleep Watchdog Reset (see specific descr. Sleep function) (see specific descr. timer) Operation (X), (Y), (Z), STACK STACK I/O(P,b) I/O(P,b) Rd(n+1) Rd(n), Rd(0) Rd(n) Rd(n+1), Rd(7) Rd(0) Rd(n+1) Rd(n), =Rd(7) Rd(7) Rd(n) Rd(n+1), =Rd(0) Rd(n) Rd(n+1), Rd(3.0) =Rd(7.4), Rd(7.4) =Rd(3.0) SREG(s) SREG(s) Rr(b) Rd(b) Flags None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V None SREG(s) SREG(s) None None None None Clocks
BIT-TEST INSTRUCTIONS
0945GS-09/01
Ordering Information
Speed (MHz) Power Supply 3.6V Ordering Code ATmega103L-4AC ATmega103L-4AI 5.5V ATmega103-6AC ATmega103-6AI Package Operation Range Commercial (0°C 70°C) Industrial (-40°C 85°C) Commercial (0°C 70°C) Industrial (-40°C 85°C)
Package Type 64-lead, Thin (1.0 Plastic Gull Wing Quad Flat Package (TQFP)
ATmega103(L)
0945GS-09/01
ATmega103(L)
Packaging Information
64-lead, Thin (1.0 Plastic Quad Flat Package (TQFP), 14x14mm body, 2.0mm footprint, 0.8mm pitch. Dimensions Millimeters (Inches)* JEDEC STANDARD MS-026
16.25(0.640) 15.75(0.620)
0.45(0.018) 0.30(0.012) 0.80(0.0315)
14.10(0.555) 13.90(0.547) 0.20(0.008) 0.09(0.004)
0°~7°
1.20 (0.047)
0.75(0.030) 0.45(0.018)
*Controlliing dimension: millimeter
0.15(0.006) 0.05(0.002
REV.
04/11/2001
0945GS-09/01
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0945GS-09/01/xM
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