CY7C9536 POSIC(Packet Over SONET/SDH highly integrated sophisticated S
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CY7C9536 Interfaces with CYS25G0101DX Microprocessor
CY7C9536 POSIC(Packet Over SONET/SDH highly integrated sophisticated SONET/SDH frame device. used transport ATM, HDLC, packets over SONET/SDH links. This device provides five interfaces communicate external peripherals. These five interfaces include Line Interface (i.e., interface PHY), Memory Interface, CPU/Microprocessor Interface, System Interface (i.e. Tx/Rx UTOPIA/POSPHY Level interface), Serial Interface. This application note will mainly focus discussion Line Interface Microprocessor Interface.
Block Diagram
Figure shows block diagram connections between CY7C9536 (POSIC), CYS25G0101DX (OC-48 PHY) Microprocessor. Line Interface CY7C9536 programmed support HSTL LVTTL interface devices. interface CYS25G0101DX HSTL signal level (details found CYS25G0101DX data sheet). very simple connect CYS25G0101DX with CY7C9536. Microprocessor Interface CY7C9536 designed interface with most microprocessors (i.e., Intel Motorola processors).
POSIC CY7C9536
Address Data RxD[15:0] Control Signals
RxD[15:0]
CYS25G0101DX
Microprocessor
Optical Transceiver
TxD[15:0]
TxD[15:0]
Control Signals
Figure Block Diagram CY7C9536 Interface with CYS25G0101DX Microprocessor
Cypress Semiconductor Corporation
3901 North First Street
Jose
95134 408-943-2600 August 2001, rev.
CY7C9536 Interface with CY7B9532 Microprocessor
Interface with CYS25G0101DX
Line Interface CY7C9536 programmed support HSTL signal level resetting "GloTable Definition Global Configuration Register Global Configuration Register Number 31:7 Name MPCTX_SEL MPCRX_SEL SON_MODE SON_IO_SEL SON_IO_EN SLEW_CTRL Unused
Configuration Register" Table connected directly CYS25G0101DX length trace less than 70mm). Figure illustrates connection between CY7C9536 CYS25G0101DX.
Block Address: Read/Write Default
Register Address: 8'h0d Description transmit engine selection HDLC, ATM/DOS receive engine selection HDLC, ATM/DOS SONET mode OC48, OC12, SONET selection HSTL, LVTTL SONET enable Three-stated, Enable SONET slew rate control Unused. Read
CY7C9536 Interface with CY7B9532 Microprocessor
CY7C9536
RXD15 RXD14 RXD13 RXD12 RXD11 RXD10 RXD9 RXD8 RXD7 RXD6 RXD5 RXD4 RXD3 RXD2 RXD1 RXD0 RXCLK
CYS25G0101DX
RXD15 RXD14 RXD13 RXD12 RXD11 RXD10 RXD9 RXD8 RXD7 RXD6 RXD5 RXD4 RXD3 RXD2 RXD1 RXD0 RXCLK OUT+ OUT- 0.1uF
ZO=50ohm
IN108 ZO=50ohms 0.1uF ZO=50ohm 0.1uF
ZO=50ohm
TXD0 TXD1 TXD2 TXD3 RXD4 TXD5 TXD6 TXD7 TXD8 TXD9 TXD10 TXD11 TXD12 TXD13 TXD14 TXD15
TXD0 TXD1 TXD2 TXD3 TXD4 TXD5 TXD6 TXD7 TXD8 TXD9 TXD10 TXD11 TXD12 TXD13 TXD14 TXD15
0.1uF
OPTICAL MODULE
ZO=50ohm
REFCLK- REFCLK+
ZO=50ohm
Out*
155.52MHz
TXCLKO
TXCLKI RESET PWRDN FIFO_RST LOCKREF LOOPA LINELOOP DIAGLOOP LOOPTIME FIFO_ERR
TXCLKI
TXCLK0
Figure Connection Between CY7C9536 CYS25G0101DX
Interface with Microprocessor
Microprocessor Interface CY7C9536 supports both Motorola Intel type specifications. Table summary Microprocessor interface signals CY7C9536. glue logic required connecting Motorola some types Intel Microprocessors) with CY7C9536. following three examples illustrate interface Motorola Intel microprocessors. number wait states during read write cycle depends signal CpuTa_n from POSIC. This signal tells that data data either ready
(write cycle) being sampled POSIC (read cycle). reference, Table shows estimated number wait states inserted POSIC during different access cycles.
Interface with Motorola
CY7C9536 configured interface either Motorola Intel microprocessor. Apply "LOW" CpuSel (see Table support Motorola microprocessor interface. interface CY7C9536 multiplexing architecture demultiplexing signals from
CY7C9536 Interface with CY7B9532 Microprocessor
Motorola must converted multiplexing signals. Figure block diagram interface Motorola Power Microprocessor. Motorola Processor uses "Big-Endian" Address/Data structure. A[0] D[0] A[31] D[31] LSB. POSIC, A/D[31] A/D[0] LSB. this example, CY7C9536 configured support Motorola Table Summary Interface Signals Signal Name CpuClk CpuSel CpuTs_n/CpuAds_n CpuWrRd CpuTa_n CpuBdip_n CpuInt CpuClkFail CpuAD[31:0] ChipSel Mode Number Pins
with 32-bit width data bus. CPLD (glue logic) used convert demultiplex Address/Data multiplex decode address ChipSel. Figure shows example logic used convert demultiplex multiplexed bus. addition, Figure illustrates decoding ChipSel signal.
Description Clock Select between Intel Motorola Microprocessor. Motorola, HIGH Intel Transfer Start. Active LOW. Write/Read Signal. Active write operation Transfer Acknowledge/Data Ready. Active Used with Burst Transaction. Active Interrupt CPU. Active fail signal. level indicates failure clock Address/Data multiplex Chip Select. Active HIGH 32/16 data mode selection. bit, HIGH
Table Estimated Number Wait States Inserted POSIC 32-bit Operation Modes Number Wait States Mode Operation Motorola Motorola Intel Intel Read Write Burst Read Burst Write
Note: wait state vary cycle depending phase difference between clock system clock during access cycle.
CY7C9536 Interface with CY7B9532 Microprocessor
133MHz
EXTCLK
SYSCLK CLKOUT CpuClk
CY7C9536
RESETOUT_n RxD[15:0] RXCLK TXCLKOUT TXCLKI TxD[15:0] RESET RxD[15:0] RXCLK TXCLKI TXCLKO TxD[15:0]
CPLD
Motorola Power Microprocessor
A[0:31] D[0:31] RD/WR
A[0:31] CpuAD[31:0] D[0:31] CpuTs_n CpuWrRd ChipSel
CpuAD[31:0] CpuTs_n/CpuAds_n CpuWrRd ChipSel CpuBdip_n CpuInt CpuTa_n Mode CpuSel
BDIP IRQn
PWRDN LOCKREF LOOPTIME LINELOOP LOOPA DIAGLOOP FIFO_RST FIFO_ERR
PN0M0 PN1M1 PN2M2 PN3M3 PN4M4 PN5M5 PN6M6 PN7M7
Figure Block Diagram Interface using Motorola Power Microprocessor
A[n][2] CpuAD[n]
D[n] ChipSel DinEn CpuADEn
Figure Example Logic Design Demultiplex Multiplex Conversion Motorola Processor
Note: Address/Data number from
CYS25G0101DX
CY7C9536 Interface with CY7B9532 Microprocessor
Address Decoder
A[0:31] A[0:31] ChipSel
Figure Address Decoder Generate ChipSel Signal Read Cycle Timing Write Cycle Timing Figure Single-Beat Read Cycle timing diagram Figure Single-Beat Write Cycle timing diagram Figure Figure Figure During address acFigure Figure Figure During address access cycle, control signal, CpuADEn Figure encess cycle, control signal, CpuADEn, enabled ChipSel. address signal will output abled ChipSel. address signal will output CpuAD[]. During data access cycle, CpuAD[]. During data access cycle, DinEn disCpuADEn disabled DinEn enabled ChipSel abled signal CpuADEn enabled signals. data signal from POSIC input ChipSel signals. data signal from (from CpuAD[]). Table shows truth table Figure output CpuAD[]. Table truth table Figure during read cycle. during write cycle. Table Truth Table Logic Figure During Read Cycle[3, Address Access Data Access Inactive ]/HZ CpuAD[ CpuADEn Enable Disable Disable DinEn Disable Enable Disable ChipSel
EXTCLK CpuClk A[0:31] (from CPU) CpuWrRd CpuTs_n ChipSel CpuADEn DinEn D[0:31] (from CPU) CpuAD[31:0]
DO[31:0] A[0:31] Address FromCPU (Big Endian) DO[31:0] Data From POSIC (Little Endian Structure)
Figure Single-Beat Read Cycle Timing Diagram Demultiplex Multiplex Converter (Motorola CPU)
Notes:
address data signals from respectively.*(note( data signal output from POSIC. High Impedance. state.
CY7C9536 Interface with CY7B9532 Microprocessor
EXTCLK CpuClk A[0:31] (from CPU) CpuWrRd CpuTs_n ChipSel CpuADEn DinEn D[0:31] (from CPU) CpuAD[31:0]
D[0:31] A[0:31] Address FromCPU (Big Endian) D[0:31] Data From (Big Endian Structure)
Figure Single-Beat Write Cycle Timing Diagram Demultiplex Multiplex Converter (Motorola CPU)
Interface with Intel Microprocessor
"HIGH" applied CpuSel CY7C9536, device will configured support Intel microprocessor interface (see Table Intel 960i Processor family kinds architectures Demultiplexing (like 80960Hx Product Family) Multiplexing (like 80960Jx Product Family). interface CY7C9536 multiplexing architecture. interfacing with 80960Hx (demultiplexing architecture), necessary convert demultiplexing signals from multiplexing signals. following sections will discuss interface both demultiplexing multiplexing bus.
Interface with Demultiplexing Figure shows block diagram connection CY7C9536 Intel demultiplexing (like 80960Hx). Intel Microprocessor uses "Little-Endian" Address/Data structure. A[31] D[31] A[0] D[0] LSB. CPLD used convert demultiplex Address Data signals multiplex Address/Data signals, decode address ChipSel signal CY7C9536, provide port interface CYS25G0101DX control signal pins. Figure illustrates logic used perform demultiplex multiplexed conversion. Figure shows example address decoding logic design port.
Table Truth Table Logic Figure During Write Cycle Address Access Data Access Inactive ]/HZ CpuAD[ CpuADEn Enable Enable Disable DinEn Disable Disable Disable ChipSel
CY7C9536 Interface with CY7B9532 Microprocessor
SYSCLK CLKOUT CpuClk CpuInt CpuTa_n
CY7C9536
RESETOUT_n RxD[15:0] RXCLK TXCLKOUT TXCLKI TxD[15:0] RESET RxD[15:0] RXCLK TXCLKI TXCLKO TxD[15:0]
80960HA
CLKIN /XINTn /READY /BLAST
CpuBlast_n/CpuBdip_n
CPLD
CLKIN A[31:2] BE[3:0] D[31:0] A[31:2] BE[3:0] CpuWrRd D[31:0] ChipSel /ADS /DEN DT/R /ADS /DEN DT/R PN0M0 PN1M1 PN2M2 PN3M3 PN4M4 PN5M5 PN6M6 PN7M7 CpuSel Mode CpuAD[31:0] CpuAds_n CpuAD[31:0] CpuTs_n/CpuAds_n CpuWrRd ChipSel
PWRDN LOCKREF LOOPTIME LINELOOP LOOPA DIAGLOOP FIFO_RST FIFO_ERR
Figure Block Diagram Interface with Intel 80960Hx
A[n] CpuAD[n]
D[n] DT/R ChipSel DinEn
CpuADEn
Figure Example Logic Design Demultiplex Multiplex Conversion Intel 80960Hx
CYS25G0101DX
133MHz
CY7C9536 Interface with CY7B9532 Microprocessor
D[n]
InPort
D[n] O[n]
D[n] O[n]
OutPort
Address Decoder
AD[31:0] AD[31:0] ChipSel
Figure Example Logic Design Address Decode Port Intel 80960Hx Read Cycle Timing Figure Single-Beat Read Cycle Timing Diagram Figure Figure Figure During address access cycle, CpuADEn enabled ChipSel. Address signal output CpuAD[]. During data access cycle, CpuADEn disabled DinEn enabled. data signal from POSIC output D[]. Table truth table Figure during Read Cycle. Write Cycle Timing Figure Single-Beat Write Cycle Timing Diagram Figure Figure Figure During address access cycle, CpuADEn enabled both ChipSel (active). Address signal output CpuAD[]. During data access cycle, CpuADEn enabled DinEn disabled. data signal from will output CpuAD[]. Table truth table Figure Interface with Multiplexing Intel 80960Jx multiplexing architecture directly connect interface CY7C9536. Figure shows block diagram connection CY7C9536 Intel 80960JA CPU. CPLD used decode address ChipSel signal CY7C9536, provide port interface CYS25G0101DX control signal pins. Figure shows example address decoding logic design port. Read Cycle Timing Figure shows Single-Beat Read Cycle Timing Diagram. During cycle, will extends cycle (generate wait state until RDYRCV# asserted CpuTa_n from CY7C9536.
Table Truth Table Logic Figure During Read Cycle[3, Address Access Data Access Inactive ]/HZ CpuAD[ CpuADEn Enable Disable Disable DinEn Disable Enable Disable /ADS /DEN DT/R ChipSel
Table Truth Table Logic Figure During Write Cycle[3, Address Access Data Access Inactive ]/HZ CpuAD[ CpuADEn Enable Enable Disable DinEn Disable Disable Disable /ADS /DEN DT//R ChipSel
CY7C9536 Interface with CY7B9532 Microprocessor
CLKIN CpuClk A[31:2], BE[3:0] CpuWrRd CpuTs_n BLAST# CpuBlast_n CpuTa_n RDYRCV# ChipSel CpuADEn DinEn D[31:0] CpuAD[31:0] A[31:0]
D[31:0] D[31:0] Data From POSIC
Address From
Figure Single-Beat Read Cycle Timing Diagram Demultiplex Multiplex Converter (80960Hx) Write Cycle Timing Figure shows Single-Beat Write Cycle Timing Diagram. During cycle, will extends cycle (generate wait state until RDYRCV# asserted CpuTa_n from CY7C9536. timing interface similar Intel Motorola Processor. operational voltage (i.e., VCC) microprocessor glue logic 3.3V must support LVTTL interface. details access cycle timings, necessary refer Motorola Intel datasheet. "Big-Endian" "Little-Endian" another important issue. Motorola Microprocessor "Big-Endian" (which means A[0] D[0] MSB, A[31] D[31] LSB) Intel "Little-Endian" (which means A[31] D[31] MSB, A[0] D[0] LSB).
Summary
interface between CY7C9536, CYS25G0101DX Microprocessor quite simple straightforward. Microprocessor, highly recommended
POSIC HBST trademarks Cypress Semiconductor Corporation. Motorola trademark Motorola Corporation. Intel registered trademark Intel Corporation.
CY7C9536 Interface with CY7B9532 Microprocessor
CLKIN CpuClk A[31:2], BE[3:0] CpuWrRd CpuTs_n BLAST# CpuBlast_n CpuTa_n RDYRCV# ChipSel CpuADEn DinEn D[31:0] CpuAD[31:0] A[31:0]
D[31:0] D[31:0] Data From
Address From
Figure Single-Beat Write Cycle Timing Diagram Demultiplex Multiplex Converter (80960Hx)
CY7C9536 Interface with CY7B9532 Microprocessor
SYSCLK CLKOUT RESETOUT_n RxD[15:0] RESET RxD[15:0] RXCLK TXCLKI TXCLKO TxD[15:0]
Intel 80960JA
CLKIN AD[31:0] ADS# W/R# RDYRCV# BLAST# /IRQn
CpuClk CpuAD[31:0] CpuTs_n/CpuAds_n CpuWrRd CpuTa_n CpuBlast_n/CpuBdip_n CpuInt ChipSel
RXCLK TXCLKOUT TXCLKI TxD[15:0]
CpuSel Mode
PWRDN LOCKREF LOOPTIME LINELOOP LOOPA DIAGLOOP FIFO_RST FIFO_ERR
CPLD
AD[31:0] /DEN /ALE ChipSel PN0M0 PN1M1 PN2M2 PN3M3 PN4M4 PN5M5 PN6M6 PN7M7
DEN# ALE#
Figure Block Diagram Interface with Intel 80960Jx
D[n] InPort
D[n] O[n]
D[n] O[n]
OutPort
Address Decoder
AD[31:0] AD[31:0] ChipSel
Figure Example Logic Design Address Decode Port Intel 80960Jx
CYS25G0101DX
133MHz
CY7C9536
CY7C9536 Interface with CY7B9532 Microprocessor
CLKIN CpuClk AD[31:0] CpuAD[31:0] A[31:0]
D[31:0]
Data From POSIC
Address From
W/R# CpuWrRd CpuTs_n BLAST# CpuBlast_n CpuTa_n RDYRCV# ALE#
ChipSel
Figure Single-Beat Read Cycle Timing Diagram Intel 80960Jx
CY7C9536 Interface with CY7B9532 Microprocessor
CLKIN CpuClk AD[31:0] CpuAD[31:0] A[31:0]
D[31:0]
Address Data From
W/R# CpuWrRd CpuTs_n BLAST# CpuBlast_n CpuTa_n RDYRCV# ALE#
ChipSel
Figure Single-Beat Write Cycle Timing Diagram Intel 80960Jx
Cypress Semiconductor Corporation, 2001. information contained herein subject change without notice. Cypress Semiconductor Corporation assumes responsibility circuitry other than circuitry embodied Cypress Semiconductor product. does convey imply license under patent other rights. Cypress Semiconductor does authorize products critical components life-support systems where malfunction failure reasonably expected result significant injury user. inclusion Cypress Semiconductor products life-support systems application implies that manufacturer assumes risk such doing indemnifies Cypress Semiconductor against charges.
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