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SH7709 Windows®CE Reference Platform (PFM-DS3) Application Note (


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Hitachi Company Confidential
SH7709 Windows®CE Reference Platform (PFM-DS3) Application Note
(Rev.1.0)
Application Laboratory Semiconductor Integrated Circuits Division Hitachi, Ltd. Page
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Notice
When using this document, keep following mind: This document may, wholly partially, subject change without notice. rights reserved: permitted reproduce duplicate, form, whole part this document without Hitachi's permission. Hitachi will held responsible damage user that result from accidents other reasons during operation user's unit according this document. Circuitry other examples described herein meant merely indicate characteristics performance Hitachi's semiconductor products. Hitachi assumes responsibility intellectual property claims other problems that result from applications based examples described herein. license granted implication otherwise under patents other rights third party Hitachi, Ltd. MEDICAL APPLICATIONS Hitachi's products authorized MEDICAL APPLICATIONS without written consent appropriate officer Hitachi's sales company. Such includes, limited life support systems. Buyers Hitachi's products requested notify relevant Hitachi sales offices when planning products MEDICAL APPLICATIONS.
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Contents
OVERVIEW. BASIC SPECIFICATION. MODE SELLECTION SWITCH SPECIFICATION. 2.1.1 DSW1 SPECIFICATION. 2.1.2 DSW2 SPECIFICATION. PORT READ SWITCH (DSW2) STATUS. JUMPER DEFINITION. 2.3.1 (OSCILLATOR VOLTAGE SELECT) 2.3.2 (MAIN FPGA CLOCK MASK) 2.3.3 VOLTAGE SELECT). 2.3.4 (HD64461 INTERRUPT OUTPUT MODE) 2.3.5 (CPU BOARD POWER SELECT) 2.3.6 (LCD CONTRAST CONTROL) 2.3.7 J9/J10 (AFE LOOP BACK MODE). 2.3.8 (AFE EXTEND MODE). SEPARATE MODE. SH7709CE REFERENCE PLATFORM BLOCK DIAGRAM. SH7709 INTERNAL CONSTRUCTION 3.2.1 ADDRESS MAP. 3.2.2 INITIAL VALUE SH7709. 3.2.3 HD64462 COMPANION CHIP REGISTER 3.2.4 SH7709 FUNCTION 3.2.5 HD64461 FUNCTION
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INTERNAL/EXTERNAL FUNCTIONAL CONSTRUCTION. 3.3.1 PERIPHERAL FUNCTION ASSIGNMENT 3.3.2 INTERRUPT SIGNAL ASSIGNMENT. 3.3.3 DMAC ASSIGNMENT 3.3.4 CHANNEL ASSIGNMENT. 3.3.5 CHANNEL ASSIGNMENT. 3.3.6 PORT. CONNECTOR SPECIFICATION. 3.4.1 (CONNECTOR KEYBOARD I/F). 3.4.2 (CONNECTOR I/F) 3.4.3 (CONNECTOR LCD/TOUCH PANEL I/F). 3.4.5 (CONNECTOR D9000 I/F). 3.4.6 (CONNECTOR D9000). 3.4.7 (CONNECTOR EXPANSION) 3.4.8 CN11 (CONNECTOR RS-232C I/F) 3.4.9 CN12 (CONNECTOR EXTENDED MODE) 3.4.10 (CONNECTOR SPEAKER). MEMORY 3.5.1 DRAM 3.5.1.1 SPECIFICATION. 3.5.2 FLASH MEMORY 3.5.2.1 SPECIFICATION. TOUCH PANEL INTERFACE. 3.6.1 OVERVIEW. 3.6.2 FEATURES 3.6.3 BLOCK DIAGRAM
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3.6.4 RESOURCE CONFIGURATION TOUCH PANEL. 3.6.5 REGISTER DEFINITION. 3.6.6 TOUCH PANEL INTERFACE OPERATION. 3.6.7 NOISE CANCEL SIGNAL INTERFACE. 3.7.1 OVERVIEW. 3.7.2 FEATURES 3.7.3 RESOURCE CONFIGURATION. 3.7.4 BLOCK DIAGRAM 3.7.5 REGISTER DEFINITION. 3.7.6 INTERFACE. 3.7.6.1 REGISTER ALLOCATION. 3.7.6.2 LCDC DISPLAY FORMAT 3.7.6.3 INTERFACE TIMING AUDIO PLAYBACK INTERFACE 3.8.1 OVERVIEW. 3.8.2 FEATURES 3.8.3 RESOURCE CONFIGURATION AUDIO PLAYBACK 3.8.4 REGISTER SPECIFICATION AUDIO RECORD INTERFACE 3.9.1 OVERVIEW. 3.9.2 FEATURES 3.9.3 BLOCK DIAGRAM 3.9.4 RESOURCE CONFIGURATION. 3.9.5 REGISTER DEFINITION. 3.10 KEYBOARD INTERFACE
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3.10.1 OVERVIEW. 3.10.2 FEATURE 3.10.3 BLOCK DIAGRAM 3.10.4 RESOURCE CONFIGURATION. 3.10.5 REGISTER DEFINITION. 3.11 IRDA INTERFACE. 3.11.1 OVERVIEW. 3.11.2 FEATURES 3.11.3 BLOCK DIAGRAM 3.11.4 RESOURCE CONFIGURATION. 3.11.5 REGISTER DEFINITION. 3.12 CARD INTERFACE 3.12.1 OVERVIEW. 3.12.2 FEATURES 3.12.3 PCMCIA FUNCTION. 3.12.4 BLOCK DIAGLRAM. 3.12.5 CARD CONTROLLER REGISTERS CONFIGURATION. 3.12.6 PCMCIA PHYSICAL ADDRESS AREA. 3.12.7 PCMCIA REGISTERS 3.12.8 PCMCIA SLOT ALLOCATIONS 3.13 SERIAL COMMUNICATION INTERFACE 3.13.1 OVERVIEW. 3.13.2 FEATURES 3.13.3 BLOCK DIAGRAM 3.13.4 FUNCTION CONFIGURATION. 3.13.5 REGISTER CONFIGURATION
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APPENDIX-1 I/F. A-1-1 OVERALL A-1-2 SOFTWARE MODEM SYSTEM A-1-3 SUPPORT FUNCTION A-1-4 MODEM INTERFACE A-1-5 SOFTWARE SPECIFICATION APPENDIX-2 DEBUG BOARD A-2-1 OVERVIEW A-2-2 FEATURE A-2-3 MODE. A-2-3-1 NORMAL OPERATION MODE. A-2-3-2 FLASH MEMORY PROGRAM MODE. A-2-3-3 FPGA PROGRAM MODE. A-2-4 OUTWARD FORM DEBUG BOARD. APPENDIX-3 NATIVE MODE. A-3-1 CHANGE NATIVE MODE. A-3-1-1 CHANGE HARDWARE A-3-1-2 CHANGE SOFTWARE.
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OVERVIEW
This platform which SH7709 HD64461 reference platform that covers function Windows®CE Ver.2.0. this platform appraise SH7709 HD64461, develop hardware software. SH7709 high-speed access/low voltage supply 300MIPS/watt, optimum portable consumer equipment drive electric battery. SH7709 peripheral functions(MMU, cache memory, etc.). SH7709 does need external analog circuit, because SH7709 converter touch panel/power control converter audio play back. other side, HD64461 function Windows®CE Ver.2.0. such color controller colors, high speed IrDA, analog front interface(AFE I/F) software modem, card controller, timer, UART, etc. Particularly, realized high-performance description. Windows® registered trademarks Microsoft Corporation.
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BASIC SPECIFICATION
following table shows basic specification SH7709CE reference platform. Table 1.1-1 Basic specification Operating frequency Internal clock 80MHz Internal Peripheral clock 20MHz External clock 20MHz 32bits 16Mbytes/ 4Mword 16bits/60ns (x2) 8Mbytes/ 128Kword 8bits/100ns (x2) 640(W) 240(H)/ colors rate: Maximum 115.2kbps Communication mode Select start/stop synchronous mode clock synchronous mode. Full duplex mode. Select serial data communication format 12type). Conform PCMCIA Rev.2.1/ JEIDA Ver.4.2 [Resolution] vertical: 42mm/512dots horizontal: 115mm/ 1024dots Sampling frequency 44.1KHz Sampling frequency 44.1KHz matrix Conform IR-SIR Ver.1.0 rate 4Mbps
DRAM
size Capacity/ Construction/ Access time Capacity/ Construction/ Access time
Interface
Resolution/ color RS-232C Serial
card Touch panel
Audio playback Audio record keyboard IrDA
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Table 1.1-2 Design specification memory DRAM Flash memory controller panel SH7709 (HD6417709) HM5165165ATT-6 (8Mbytes HN29WT800T10 (1Mbytes controller included HD64461. [Display size] Display range 122.86 46.07 (mm) size 0.044 0.172 (mm) interval 0.02 (mm) SCIF included SH7709. RS-232C driver PCMCIA included HD64461. HD151015 (level shifter), slots 10bits converter included SH7709. 8bits converter included SH7709. included HD64461. STLC7550 (AFE chip) Scan type keys keyboard unit UART included HD64461. Glass epoxy layers print board
Interface
Serial (SCI) card Touch panel Audio playback Audio record Keyboard IrDA
Board
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MODE SELLECTION Switch Specification
operation mode SH7709CE reference platform selected switch (DSW1, DSW2). Status switch (DSW2) read port. following figure table show specification switch related mode selection.
2.1.1 DSW1 Specification
DSW1 (SHMD0~SHMD5) correspond with SH7709 MODE (0~5) each other. DSW1 "ON", SH7709 MODE "0". DSW1 "OFF", SH7709 MODE "1". Test terminal this platform test. Test keep state shipment.
DSW1
Test 1pin Test 2pin SHMD5 SHMD4 SHMD3 SHMD2 SHMD1 SHMD0
Figure 2.1.1-1 switch (DSW1) mode selection
Table 2.1.1-1 relation between switch (DSW1) SH7709 mode switch (SHMD0) (SHMD1) (SHMD2) (SHMD3) (SHMD4) (SHMD5) (Test2) (Test1) Select contents SH7709 clock mode SH7709 clock mode SH7709 clock mode width area width area Endian Test Test switch initial state
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Clock mode Select 3(SHMD2) 2(SHMD1) ON(0) OFF(1)
1(SHMD0) OFF(1)
Mode
Clock Ratio(I:B:P) H'01e0 4:1:1 FRQCR register name which select clock ratio inside clock(I),external clock internal peripheral clock. Please refer "SH7709 Hardware Manual" more information. size area 5(SHMD4) 4(SHMD3) size ON(0) ON(0) Reserved ON(0) OFF(1) bits OFF(1) ON(0) bits OFF(1) OFF(1) bits SH7709CE reference platform initial value bits size. (3)Endian 6(SHMD5) Endian ON(0) Endian OFF(1) Little Endian change Endian, need change software. SH7709CE reference platform initial value little Endian. painted line table this document shows initial value SH7709CE reference platform.
FRQCR
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2.1.2 DSW2 Specification
SH7709CE reference platform operation mode, display mode card mode selected DSW2. Setting constants shown below:
DSW2
SYSMD0 Mode SYSMD1 Mode CCMD0 Card Mode TEST1 Test TEST3 Test SHCS0 Mode SHRAS3L Mode TEST2 Test
Figure 2.1.2-1 switch (DSW2) operation mode ,display mode card mode
Table 2.1.2-1Operation Mode 2(SHRAS3L) OFF(1) ON(0) 3(SHCS0) OFF(1) ON(0) 7(SYSMD1) ON(0) ON(0) OFF(1) 8(SYSMD0) ON(0) OFF(1) ON(0) Mode Modem evaluation mode Native mode Separate mode
SH7709CE reference platform operating mode selected [SHRAS3L, SHCS0, SYSMD1, SYSMD0]. Native mode used SH7709CE reference platform card D9000. Refer Appendix-3 more information. refer Appendix-1 about Modem evaluation mode more information. DSW2 select [SHRAS3L,SHCS0,SYSMD1,SYSMD0] ,off ,on] separate mode selected. D9000 needed. This mode operates memory SH7709CE reference platform. used this mode connect directly power supply with SH7709CE reference platform. Please refer Chapter "Separate mode" more information. Initial state SH7709CE reference platform separate mode.
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Table 2.1.2-2 Card Mode CCMD0 ON(0) OFF(1) Mode PCMCIA channels PCMCIA channel
CCMD selects card mode. This connects with (180 pin) HD64461. MD1(181 pin) HD64461 connect with "ON(0)" advance CCMD0 select "ON(0)" "OFF(1)" HD64461 mode selects "1". When this selects "ON" HD64461 mode selects slots card available. When this selects "OFF" HD64461 mode selects slot card available. Initial value SH7709CE reference platform that HD64461 mode selects "ON". Test 1/2/3 pins used test mode. have effect operation either case "ON" "OFF" when normal mode. These pins keep state shipment. Table 2.1.2-3 relation between DSW2 SH7709 mode DSW2 (TEST2) (SHRAS3L) (SHCS0) (TEST3) (TEST1) (CCMD0) (SYSMD1) (SYSMD0) Contents Test Operation mode Operation mode Test Test card mode Operation mode Operation mode Initial value
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port read switch (DSW2) status
Status switch (DSW2) read port. Port specification shown below. (But status SHCS0 read. Table 2.2-1 port switch (DSW2) Switch name SHRAS3L SHCS0 TEST3 CKSEL CCMD0 SYSMD0 SYSMD1 Port name Port data register Port data register Port data register Port data register Port data register Port data register Abbreviation/bit PJDR/bit PEDR/bit0 PLDR/bit5 PEDR/bit1 PEDR/bit2 PEDR/bit7 Address h'04000130 h'04000128 h'04000134 h'04000128 h'04000128 h'04000128 Access size 8bits 8bits 8bits 8bits 8bits 8bits
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Port Data Register (PEDR)
Port data register show switch status that select operating mode. SH7709CE reference platform initial value separate mode. When this data register read, "(bit7,bit2)=(1,0)". Operating mode Modem evaluation mode Native mode Separate mode used
Please refer Appendix-4 about Native mode. Please refer Appendix-1 about Modem evaluation mode.
Port data register shows switch status that select PCMCIA mode. SH7709CE reference platform initial value PCMCIA mode. When this data register read, "1". Description PCMCIA PCMCIA
Port data register show switch status that select Display mode. SH7709CE reference platform initial value mode. When this data register read, "0". Bit0 Description selected selected
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Jumper Definition 2.3.1 (Oscillator voltage select)
This jumper selects voltage oscillator (OSC1/ OSC2/ OSC3).The following figure shows definition. this jumper selects "3.3V", please connect with this jumper selects "5V", please connect with pin. SH7709CE reference platform initial state connect with pin, because driven "3.3V".
3.3V
Figure 2.3.1-1 specification (Oscillator Power Select)
2.3.2 (Main FPGA clock mask)
This jumper specifies clock enable signal (CLKE) used main FPGA D9000. don't CLKE, please connect with pin. CLKE, please connect with pin. SH7709CE reference platform connected with pin, because CLKE used.
CLKE used CLKE used
Figure 2.3.2-1 specification (Main FPGA clock mask)
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2.3.3 voltage select)
This jumper specifies voltage AFE. voltage crystal oscillator "3.3V", please connect with pin. voltage crystal oscillator "5V", please connect with pin. SH7709CE reference platform initial state connect with pin, because driven "5V".
+3.3V +5.0V
Figure 2.3.3-1 specification voltage select)
2.3.4 (HD64461 interrupt output mode)
This jumper specifies interrupt signal from HD64461 connected main FPGA D9000. When SH7709CE reference platform card D9000, HD64461 interrupt signal inputted main FPGA, please connect with (short). HD64461 interrupt signal inputted main FPGA, please don't connect with (open). SH7709CE reference platform initial state don't connect with 2pin,because D9000 used. don't D9000, SH7709CE reference platform effected "connect"
OPEN(not connect) from HD64461 connected main FPGA. SHORT(connect) from HD64461 connected main FPGA.
Figure 2.3.4-1 specification (HD64461 interrupt output mode)
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2.3.5 (CPU board power select)
This jumper specifies board power supply from D9000. When SH7709CE reference platform card D9000, supply power source from D9000, please connect 1pin with (short). don't supply from D9000, connect (open). Though SH7709CE reference platform initial state "short", doesn't influence operation.
OPEN(not connect) Power board supplied base board. SHORT(connect) Power board supplied base board. Figure 2.3.5-1 specification (CPU board power select)
2.3.6 (LCD contrast control)
This jumper specifies contrast control. necessary control contrast, please connect with 1pin (short). necessary control contrast, please connect with (short). SH7709CE reference platform initial state that connected with (short), because necessary control contrast.
Reserved Contrast controlled volume.
Figure 2.3.6-1 specification (LCD contrast control)
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2.3.7 J9/J10 (AFE loop back mode)
This jumper specifies loop back mode interface. following figure shows specification.
loop back mode Dout signal from HD64461 connected signal. connected J10.
Normal mode Dout signal from HD64461 connected interface.
signal from HD64461 connected interface.
Figure 3.7-1 J9/J10 (AFE loop back mode)
2.3.8 (AFE extend mode)
This jumper specifies extend mode. following figure shows specification.
OPEN signal connected CN12. SHORT signal connected circuit card.
Figure 2.3.8-1 (AFE extend mode)
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Separate mode
Separate mode operating mode that SH7709CE reference platform operates oneself. SH7709CE reference platform initial state separate mode. Please refer Chapter about setting switch.
SH7709CE reference platform block diagram
Figure 4.1-1 shows SH7709CE reference platform block diagram separate mode. Main FPGA Debug FPGA board. About board, please refer board specifications.
Main FPGA
DRAM FLASH Host Control IEEE 1284 Download Control Register Master Serial RS-232C Debug
SH7709
Timer Cache SCIF INTC DMAC Port
HD64461
Timer UART IrDA LCDC Card
Color Panel Frame memory PCMCIA/compact flash PSTN
Debug FPGA
Digitizer
Optical module
RS-232C Bias controller
Keyboard
IrDA/4Mbps
Figure 3.1-1 Block Diagram
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SH7709 internal construction 3.2.1 Address
following figure shows address SH7709CE reference platform.
Virtual Address Space 00000000 area
00000000 Flash Memory Area
04000000 SH7709 Peripheral Register 08000000 Debug FPGA Area Main FPGA 0C000000 Area
20000000 Mapped P0/U0 40000000
area
area
60000000 area 10000000 12000000 14000000
DRAM
Area
80000000
Fixed Physical Address Cached area Fixed Physical Address cached area Mapped area
Companion Register
Area
A0000000
PCMCIA
Area
C0000000
18000000 PCMCIA Area
E0000000
Control Space area
1C000000 Reserved 1FFFFFFF
Figure 3.2.1-1. Address
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3.2.2 Initial value SH7709
Initial value SH7709 register shown follow. Table 3.2.2-1 SH7709 register Module INTC INTC INTC Register PTEH PTEL MMUCR EXPEVT INTEVT BASRA BASRB ICR0 IPRA IPRB INTEVT2 ICR1 ICR2 INTER IPRC IPRD IPRE IPR0 IPR1 IPR2 IPR3 IPR4 BARA BAMRA BBRA BARB BAMRB BBRB BDRB BDMBR BRCR STBCR STBCR2 FRQCR WTCNT Size 8/16 Address H'FFFFFFF0 H'FFFFFFF4 H'FFFFFFF8 H'FFFFFFFC H'FFFFFFE0 H'FFFFFFD0 H'FFFFFFD4 F'FFFFFFD8 F'FFFFFFEC H'FFFFFFE4 H'FFFFFFE8 H'FFFFFED0 H'FFFFFEE2 H'FFFFFEE4 H'04000000 H'04000010 H'04000012 H'04000014 H'04000016 H'04000018 H'0400001A H'04000004 H'04000006 H'04000008 H'0400000A H70400000C H'FFFFFFB0 H'FFFFFFB4 H'FFFFFFB8 H'FFFFFFA0 H'FFFFFFA4 H'FFFFFFA8 H'FFFFFF90 H'FFFFFF94 H'FFFFFF98 H'FFFFF82 H'FFFFFF88 H'FFFFFF80 H'FFFFFF84 SH7709 initial value Undefined Undefined Undefined Undefined H'00000100/ H'00000000 Undefined H'000/H'020 Undefined H'00000000 Undefined Undefined H'8000/H'0000 H'0000 H'0000 Undefined H'4000 H'0000 H'0000 H'0000 H'0000 H'0000 H'00 H'00 H'00 H'00 H'00 Undefined Undefined H'0000 Undefined Undefined H'0000 Undefined Undefined H70000 H'00 H'00 H'0102 H'0000 Platform initial value H'00000001 H'FF00 H'0002 H'00FF H'000D H'0500 H'A000 H'00
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Hitachi Company Confidential WTCSR BCR1 BCR2 WCR1 WCR2 RTCSR RTCNT RTCOR RFCR BCR3 SDMR 8/16 H'FFFFFF86 H'FFFFFF60 H'FFFFFF62 H'FFFFFF64 H'FFFFFF66 H'FFFFFF68 H'FFFFFF6A H'FFFFFF6C H'FFFFFF6E H'FFFFFF70 H'FFFFFF72 H'FFFFFF74 H'FFFFFF7E H'FFFFD000H'FFFFEFFE H'04000020 H'04000024 H'04000028 H'0400002C H'04000030 H'04000034 H'04000038 H'0400003C H'04000040 H'04000044 H'04000048 H'0400004C H'04000050 H'04000054 H'04000058 H'0400005C H'04000060 H'04000070 H'04000072 H'04000074 H'04000076 H'FFFFFE90 H'FFFFFE92 H'FFFFFE94 H'FFFFFE98 H'FFFFFE9C H'FFFFFEA0 H'FFFFFEA4 H'FFFFFEA8 H'FFFFFEAC H'FFFFFEB0 H'FFFFFEB4 H'FFFFFEB4 H'0000 H'0000 H'3FF0 H'3FF3 H'FFFF H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 Undefined H'0013 H'2AF0 H'1512/H'1516 H'DB5E/ H'DB3E/H'FFFF H'005C/H'0055
H'A518 H'A500 H'A590
DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC
SAR0 DAR0 DMATCR0 CHCR0 SAR1 DAR1 DMATCR1 CHCR1 SAR2 DAR2 DMATCR2 CHCR2 SAR3 DAR3 DMATCR3 CHCR3 DMAOR CMSTR CMCSR CMCNT CMCOR TOCR TSTR TCOR0 TCNT0 TCR0 TCOR1 TCNT1 TCR1 TCOR2 TCNT2 TCR2 TCPR2
Undefined Undefined Undefined H'00000000 Undefined Undefined Undefined H'00000000 Undefined Undefined Undefined H'00000000 Undefined Undefined Undefined H'00000000 H'0000 H'0000 H'0000 H'0000 H'FFFF H'00 H'00 H'FFFFFFFF H'FFFFFFFF H'0000 H'FFFFFFFF H'FFFFFFFF H'0000 H'FFFFFFFF H'FFFFFFFF H'0000 Undefined
H'AC020200 H'000800 H'0201
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Hitachi Company Confidential CARD CARD CARD CARD CARD CARD CARD SCIF SCIF SCIF SCIF SCIF SCIF SCIF SCIF IRDA IRDA IRDA IRDA IRDA IRDA IRDA IRDA PORT R64CNT RSECCNT RMINCNT RHRCNT RWKCNT RDAYCNT RMONCNT RYRCNT RSECAR RMINAR RHRAR RWKAR RDAYAR RMONAR RCR1 RCR2 SCSMR SCBRR SCSCR SCTDR SCSSR SCRDR SCPDR SCPCR SCSMR SCBRR SCSCR SCTDR SCSSR SCRDR SCSCMR SCSMR2 SCBRR2 SCSCR2 SCSFDR2 SCSSR2 SCFRSR2 SCFCR2 SCFDR2 SCSMR1 SCBRR1 SCSCR1 SCFTDR1 SCSSR1 SCFRDR1 SCFCR1 SCFDR1 PACR H'FFFFFEC0 H'FFFFFEC2 H'FFFFFEC4 H'FFFFFEC6 H'FFFFFEC8 H'FFFFFECA H'FFFFFECC H'FFFFFECF H'FFFFFED0 H'FFFFFED2 H'FFFFFED4 H'FFFFFED6 H'FFFFFED8 H'FFFFFEDC H'FFFFFEDC H'FFFFFEDE H'FFFFE80 H'FFFFE82 H'FFFFE84 H'FFFFE86 H'FFFFE88 H'FFFFE84 H'04000136 H'04000116 H'FFFFFE80 H'FFFFFE82 H'FFFFFE84 H'FFFFFE86 H'FFFFFE88 H'FFFFFE8A H'FFFFFE8C H'04000150 H'04000152 H'04000154 H'04000156 H'04000158 H'0400015A H'0400015C H'0400015E H'04000140 H'04000142 H'04000144 H'04000146 H'04000148 H'0400014A H'0400014C H'0400014E H'04000100 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined H'00 H'09 H'00 H'FF H'00 H'FF H'84 H'00 H'00 H'A888 H'00 H'FF H'00 H'FF H'84 H'00 H'00 H'00 H'FF H'00 Undefined H'0060 Undefined H'00 H'0000 H'00 H'FF H'00 Undefined H'0060 Undefined H'00 H'0000 H'0000 H'70 H'06
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Hitachi Company Confidential PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PBCR PCCR PDCR PECR PFCR PGCR PHCR PJCR PKCR PLCR SCPCR PADR PBDR PCDR PDDR PEDR PFDR PGDR PHDR PJDR PKDR PLDR SCPDR ADDRAH ADDRAL ADDRBH ADDRBL ADDRCH ADDRCL ADDRDH ADDRDL ADDRCSR ADCR DADR0 DADR1 DACR DASTCR H'04000102 H'04000104 H'04000106 H'04000108 H'0400010A H'0400010C H'0400010E H'04000110 H'04000112 H'04000114 H'04000116 H'04000120 H'04000122 H'05000124 H'04000126 H'04000128 H'0400012B H'0400012D H'0400012E H'04000130 H'04000132 H'04000134 H'04000136 H'04000080 H'04000082 H'04000084 H'04000086 H'04000088 H'0400008A H'0400008C H'0400008E H'04000090 H'04000092 H'040000A0 H'040000A2 H'040000A4 H'040000A6 H'0000 H'AAAA H'AAAA H'AAAA H'AAAA H'AAAA H'AAAA H'0000 H'0000 H'0000 H'A888 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'3F H'00 H'00 H'1F Undefined H'46A4 H'A0AA H'2AAA H'4020 H'0004 H'0104 H'0003 H'A88B H'00 H'DF
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3.2.3 HD64462 Companion Chip Register
HD64461 Companion Chip Register initial value shown follow. Table 3.2.3-1 HD64461 Companion Chip Register initial value Module Standby System LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC Register STBCR SYSCR LCDCBAR LCDCLOR LCDCCR LDR1 LDR2 LDHNCR LDHNSR LDVNTR LDVNDR LDVSPR LDR3 CRTVTR CRTVRSR CRTVRER CPTWAR CPTWDR CPTRAR CPTRDR GPDOR GRSCR GRCFCGR LNSARH LNSARL LNAXLR LNDGR LNAXR LNERTR LNMDR BBTSSARH BBTSSARL BBTDSARH BBTDSARL BBTDWR BBTDHR BBTPARH BBTPARL BBTMARH BBTMARL BBTROPR BBTMDR Size Address H'10000000 H'10000002 H'10001000 H'10001002 H'10001004 H'10001010 H'10001012 H'10001014 H'10001016 H'10001018 H'1000101A H'1000101C H'1000101E H'10001020 H'10001022 H'10001024 H'10001030 H'10001032 H'10001034 H'10001036 H'10001040 H'10001042 H'10001044 H'10001046 H'10001048 H'1000104A H'1000104C H'1000104E H'10001050 H'10001052 H'10001054 H'10001056 H'10001058 H'1000105A H'1000105C H'1000105E H'10001060 H'10001062 H'10001064 H'10001066 H'10001068 H'1000106A Companion Chip Initial value H'0000 H'0000 H'0000 H'0280 H'0000 H'0001 H'0002 H'9F9F H'0A80 H'00EF H'00EF H'68F0 H'0004 Undefined Undefined Undefined H'0000 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Platform Initial value H'0080 H'0000 H'0280 H'0011 H'0000 H'00C4 H'4F54 H'0051 H'00F1 H'00F1 H'3002 H'0204 H'020E H'01E0 H'0005 H'0000
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Hitachi Company Confidential PCC0 PCC0 PCC0 PCC0 PCC0 PCC1 PCC1 PCC1 PCC1 PCC1 PCC0ISR PCC0GCR PCC0CSCR PCC0CSCIER PCC0SCR PCC1ISR PCC1GCR PCC1CSCR PCC1CSCIER PCC1SCR MCCISR MCCGCR MCCSCR MCCSCIER P0OCR P1OCR PGCR MCIHCR MCIHSR MCIHAR MCICDR MCIFDR MCIFBCR MCIFCR MCIFFR ACTR ASTR ARXDR ATXDR ARXDBR0/1 ATXDBR0/1 H'10002000 H'10002002 H'10002004 H'10002006 H'10002008 H'10002010 H'10002012 H'10002014 H'10002016 H'10002018 H'10002020 H'10002022 H'10002024 H'10002026 H'1000202A H'1000202C H'1000202E H'10002030 H'10002032 H'10002034 H'10002036 H'10002038 H'1000203A H'1000203C H'1000203E H'10003200 H'10003202 H'10003204 H'10003206 H'10003000H'1000305F H'10003000H'1000305F Depend card H'00 H'00 H'00 H'00 Depend card H'00 H'00 H'00 H'00 Depend card H'00 H'00 H'00 H'00 H'00 H'00 H'xx00 H'xx00 H'00A0 H'007A H'xxxx H'xx00 H'xxx0 H'xxx8 H'0000 H'0002 H'0000 H'0000 Undefined Undefined
H'C8
H'C8
H'0000
Port PACR H'10004000 Port PBCR H'10004002 Port PCCR H'10004004 Port PDCR H'10004006 Port PADR H'10004010 Port PBDR H'10004012 Port PCDR H'10004014 Port PDDR H'10004016 Port PAICR H'10004020 Port PBICR H'10004022 Port PCICR H'10004024 Port PDICR H'10004026 Port PAISR H'10004040 Port PBISR H'10004042 Port PCISR H'10004044 Application Laboratory Semiconductor Integrated Circuits Division Hitachi, Ltd. Page
H'AAAA H'AAAA H'AAAA H'AAAA H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00
Hitachi Company Confidential Port INTR INTR Timer Timer Timer Timer Timer Timer Timer Timer IrDA IrDA IrDA IrDA IrDA IrDA IrDA IrDA IrDA IrDA UART UART UART UART UART UART UART UART UART UART PDISR TCVR1 TRVR1 TCR1 TIRR TCVR0 TRVR0 TCR0 TIMR IrRBR IrIER IrIIR IrLCR IrMCR IrDLL IrDLM IrLSR IrMSR IrSCR URBR UIER UIIR ULCR UMCR UDLL UDLM ULSR UMSR USCR H'10004046 H'10005000 H'10005002 H'10006000 H'10006004 H'10006008 H'1000600C H'10006002 H'10006006 H'1000600A H'1000600E H'10007000 H'10007002 H'10007004 H'10007006 H'10007008 H'10007002 H'10007004 H'1000700A H'1000700C H'1000700E H'10008000 H'10008002 H'10008004 H'10008006 H'10008008 H'10008000 H'10008002 H'1000800A H'1000800C H'1000800E H'00 Undefined H'0000 H'FFFF Undefined H'0000 H'0000 H'FFFF Undefined H'0000 H'0000 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined H'FFFF H'0D H'03 H'08
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3.2.4 SH7709 function
SH7709 function shown follow. name Vcc(RTC) XTAL2 EXTAL2 Vss(RTC) IRL0 IRL1 IRL2 IRL3 IRL4 Function Mode Mode Dedicated power supply Crystal resonator Crystal resonator Dedicated power supply RTC(0V) Interrupt request Interrupt request Interrupt request Interrupt request Interrupt request Interrupt request Data Data Data Data Data Data Data Power supply Data Data Data Data Data Data Power supply Data Data Data Data Data Data Data Data Data Data Data Data Data Data
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3.2.5 HD64461 function
HD64461 function shown follow. name FD15 FD14 FD13 FD12 FD11 FD10 VccC PCC0DRV CE1B CE2B ICIORDB ICIOWRB VccB PCC0RESET PCC0WAIT PCC0WP PCC0RDY PCC0BVD1 PCC0BVD2 PCC0CD1 PCC0CD2 PCC0VS1 PCC0VS2 PCC0A25 PCC0A24 function Flame memory address Frame memory address Frame memory address Frame memory address Frame memory address Frame memory data Frame memory data Frame memory data Frame memory data Frame memory data Frame memory data Frame memory data Frame memory data Power supply Frame memory data Frame memory data Frame memory data Frame memory data Frame memory data Frame memory data Frame memory data Frame memory data card drive Card enable Card enable card read card write card read Power supply card write card power supply card reset card wait card write protect card ready card battery voltage detect card battery voltage detect card card detect card card detect card voltage sense card voltage sense card address card address
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Internal/External functional construction 3.3.1 Peripheral Function Assignment
following table shows assignment peripherals. Table 3.3.1-1. Peripheral function assignment Peripheral
RS-232C IrDA Touch Panel
Function
Serial Interface Modulation De-modulation transfer Analog input position) Analog input position) Bias control Bias control Bias control signal detection signal detection down detection Timing generator scan sense Timing generator control converter transfer Timing Generator converter Timing Generator PCMCIA Interface Serial interface
Resource
SCI2/SH7709 IrDA/HD64461 DMAC CH1/SH7709 CH0/SH7709 CH1/SH7709 PTK1/SH7709 PTK4/SH7709 PTH7/SH7709 IRL2/SH7709 PTG0/SH7709 IRL1/SH7709 Timer CH1/SH7709 PTF7~0/SH7709 Timer CH0/HD64461 controller/HD64461 CH0/SH7709 DMAC CH2/SH7709 Timer CH1/SH7709 SGS-Thomson Timer CH1/SH7709 HD64461 HD64461 Main FPGA
Keyboard
Sound playback
Sound record Card Debug Serial
3.3.2 Interrupt Signal Assignment
Interrupt signal uses IRQ. selected (IRQLVL) interrupt control register (ICR1). Interrupt signal IRL0 IRL1 IRL2 IRL3 IRL4 Interrupt factor Interruption HD64461 Touch panel/Pen down detect interruption signal interruption Main FPGA interruption (Carrier Detect)
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3.3.3 DMAC assignment
channel allocation DMAC shown follow. DMAC channel DMAC DMAC DMAC DMAC Function Reserved IrDA Sound playback Reserved require assignment IrDA module/HD64461 Timer ch1/SH7709
3.3.4 channel assignment
channel assignment shown follow. Analog input signal Description coordinates/Touch panel coordinates/Touch panel Reserved Reserved Reserved port that detected states switch Reserved Used
3.3.5 channel assignment
channel assignment shown follow. signal function Sound playback Reserved
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3.3.6 port
status port shown follow. Port name name PTA7 PTA6 PTA5 PTA4 PTA3 PTA2 PTA1 PTA0 PTB7 PTB6 PTB5 PTB4 PTB3 PTB2 PTB1 PTB0 PTC7 PTC6 PTC5 PTC4 PTC3 PTC2 PTC1 PTC0 PTD7 PTD6 PTD5 PTD4 PTD3 PTD2 PTD1 PTD0 PTE7 PTE6 PTE5 PTE4 PTE3 PTE2 PTE1 PTE0 PTF7 PTF6 PTF5 PTF4 PTF3 PTF2 PTF1 Function Used data Used data Used data Used data Used data Used data Used data Used data Used data Used data Used data Used data Used data Used data Used data Used data Used scan output Keyboard Used scan output Keyboard Used scan output Keyboard Used scan output Keyboard Used scan output Keyboard Used scan output Keyboard Used scan output Keyboard Used scan output Keyboard Used BVPPEN1 (power supply control signal PCMCIA) Used DREQ DMAC Used BVPPEN0 (power supply control signal PCMCIA) used Used scan output Keyboard Used scan output Keyboard Used AVPPEN0 (power supply control signal PCMCIA) Used DRACK DMAC Used SYSMD1 DSW2 Used scan output Keyboard Used CE2B Used CE2A Used scan output Keyboard Used SYSMD0 DSW2 Used CCMD0 DSW2 Used TEST DSW2 Used scan input Keyboard Used scan input Keyboard Used scan input Keyboard Used scan input Keyboard Used scan input Keyboard Used scan input Keyboard Used scan input Keyboard
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Connector specification 3.4.1 (Connector Keyboard I/F)
following figure shows connector specification keyboard I/F.
Figure 3.4.1-1 connector specification
Table 3.4.1-1 connector specification Connector Signal name KSCN0 KSCN1 KSCN2 KSCN3 KSCN4 KSCN5 KSCN6 KSCN7 KSCN8 KSCN9 KSCN10 KSCN11 KSCN12 Connector Signal name +3.3V KSNS0 KSNS1 KSNS2 KSNS3 KSNS4 KSNS5 KSNS6 KSNS7
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3.4.2 (Connector I/F)
following figure shows connector specification I/F.
Figure 3.4.2-1 connector specification
Table 3.4.2-1 connector specification Connector Signal name AGND AGND AGND AGND HSYNC VSYNC
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3.4.3 (Connector LCD/Touch Panel I/F)
following figure table show connector specification LCD/Touch Panel I/F.
Figure 3.4.3-1 connector specification
Table 3.4.3-1 connector specification Connector Signal name +3.3V LCDVAA LCDDON MIRQ2 LCDM0 LCDM1 LCDM2 LCDM3 LCDM4 LCDM5 LCDM6 LCDM7 LCDFLM Connector Signal name LCDCL1 LCDCL2 +12V TPX2 TPY1 TPX1 TPY2
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3.4.4 (Connector D9000 I/F)
following figure table show connector specification D9000
Figure 3.4.4-1 connector specification
Table 3.4.4-1 connector specification Connector Signal name SHCS2 +3.3v(Pull SHRAS3L P2RES SHBREQ SHWE1 Connector Signal name
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Table 3.4.4-2 connector specification Connector Signal name SHCS0 SHWAIT SHNMI SHSTATUS1 SHSTATUS0 SHWE0 SHRDWR Connector Signal name
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Table 3.4.4-3 connector specification Connector Signal name CHB3P2 Connector Signal name
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Table 3.4.4-4 connector specification Connector Signal name CLK368 Connector Signal name CHB3P1
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3.4.5 (Connector D9000 I/F)
following figure table show connector specification D9000 I/F.
Figure 3.4.5-1 (Connector specification)
Table 3.4.5-1 CN7-1 (CN7 connector specification) Connector Signal name Connector Signal name
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3.4.5-2 connector specification Connector Signal name CCIRQ0 Connector Signal name
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Table 3.4.5-3 connector specification Connector Signal name Connector Signal name SHCKIO
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Table 3.4.5-4 connector specification Connector Signal name SHMD0 SHMD1 P2IRL0 P2IRL1 SHCASLL SHCASLH SHCS3 SHCS4 Connector Signal name SHMD2 SHBACK P2IRL2 P2IRL3 SHCASHL SHCASHH +3.3v (pull +3.3v (pull
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3.4.6 (Connector D9000)
following figure table show connector specification D9000.
Figure 3.4.6-1 (Connector specification)
Table 3.4.6-1 (Connector specification) Connector Signal name Connector Signal name
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Table 3.4.6-2 (Connector specification) Connector Signal name +3.3v (pull SHCKE SHTCLK SHD24 SHA8 SHD9 SHA16 SHA24 SHA1 Connector Signal name SHD10 SHA25 SHD26 SHD3 SHA18 SHD19 SHD27 SHA11 SHA19 SHBS CLKEN SHWE2/ICIORD SHD12 SHD28 SHA12 SHD5 SHD13 SHD29 SHA13 SHD6 SHD14 SHD30 SHD7
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Table 3.4.6-3 (Connector specification) Connector Signal name SHD15 SHD23 SHA7 +3.3v (pull Connector Signal name
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Table 3.4.6-4 (Connector specification) Connector Signal name SHRD SHD0 SHD8 SHD16 SHA0 SHD1 SHD17 SHD25 SHD2 SHA9 SHA17 SHD18 SHA2 SHA10 SHD11 SHA3 +3.3v(pull SHIRQOUT Connector Signal name ERROR SHD4 SHD20 SHA4 SHA20 SHD21 SHA5 SHA21 SHD22 SHA6 SHA14 SHA22 SHD31 SHWE3ICIOWR SHA15 SHA23
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3.4.7 (Connector expansion)
following figure table show connector specification expansion.
Figure 3.4.7-1 (Connector specification)
Table 3.4.7-1 CN9-1 (Connector specification) Connector Signal name +3.3v LCDVAA +12v SHCASLH SHCASHH BVPPEN1 PTH5 PTH6 SHBACK SHWAIT PTG1 Connector Signal name PTG2 PTG3 PTG4 PTG5 PTG6 PTD4 SHSTATUS0 SHTCLK SHCKIO
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3.4.7-2 (Connector specification) Connector Signal name AVPPEN1 P2RES SHAN2 SHAN4 SHAN6 +3.3v +3.3v LCDVAA +12v SHRAS3L SHCKE SHCASLL SHCASHL BVPPEN0 SHTxD0 SHRxD0 Connector Signal name SHSCLK SHBREQ RTS# CTS# DTR# DSR# DCD# SHMD0 SHEXTAL SHSTATUS1 SHIRQOUT
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3.4.7-3 (Connector specification) Connector Signal name SHMD3 SHMD5 SHAN3 N.C. SHCS4 SHCS2 SHWE3ICIOWR SHWE1 SHRD SHA25 SHA23 SHA21 SHA19 SHA17 SHA15 Connector Signal name SHA13 SHA11 SHA9 SHA7 SHA5 SHA3 SHA1 SHD0 SHD2 SHD4 SHD6 SHD8 SHD10 SHD12 SHD14 SHD16 SHD18 SHD20 SHD22 SHD24 SHD26 SHD28 SHD30 DCD2 SHIRQ2 SHIRQ0 SHMD2
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3.4.7-4 (Connector specification) Connector Signal name +3.3v +3.3v LCDVAA +12v SHCS3 SHCS0 SHRDWR SHWE2ICIORD SHWE0 SHBS SHA24 SHA22 SHA20 SHA18 SHA16 SHA14 SHA12 SHA10 SHA8 SHA6 SHA4 SHA2 Connector Signal name SHA0 SHD1 SHD3 SHD5 SHD7 SHD9 SHD11 SHD13 SHD15 SHD17 SHD19 SHD21 SHD23 SHD25 SHD27 SHD29 SHD31 SHIRQ3 SHIRQ1 SHNMI SHMD1 +3.3v
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3.4.8 CN11 (Connector RS-232C I/F)
Figure 3.4.8-1 CN11 (Connector specification)
Table 3.4.8-1 CN11 (Connector specification) Signal DCD2 SHRxD2 SHTxD2 DTR2 DSR2 SHRTS2 SHCTS2
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3.4.9 CN12 (Connector extended mode)
following figure table show connector specification extended mode.
Figure 3.4.9-1 CN12 (Connector specification)
Table 3.4.9-1 CN12 (Connector specification) Connector Signal name SHD0 SHD1 SHD2 SHD3 SHD4 SHD5 SHD6 SHD7 SHD8 SHD9 SHD10 SHD11 SHD12 SHD13 SHD14 SHD15 SHD24 SHD25 SHRD SHWE Connector Signal name SHCS2 CHB3P1 CHB3P2 RLYCNT RDET MCLK PWRDNT AFERES SCLK DOUT +3.3V +3.3V
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3.4.10 (Connector speaker)
following figure table show connector specification speaker.
Figure 3.4.10-1 (Connector specification)
Table 3.4.10-1 (Connector speaker) Signal speaker speaker
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Memory
This chapter shows about Flash memory DRAM.
3.5.1 DRAM
DRAM SH7709CE reference platform bytes DRAM (HITACHI:HM5165165) About timing DRAM, please refer SH7709 Hardware Manual HITACHI memory data sheet.
3.5.1.1 Specification
SH7709CE reference platform have bytes DRAM space, because this platform used DRAM following figure shows Block Diagram DRAM. SH7709/area used DRAM space. DRAM parallel, 32bits size supported. Address range from h'0C000000 h'0CFFFFFF.
SH7709 Data[31:0] Address[13:2] RD/WR CASHH CASHL CASLH CASLL Data[31:16] Data[31:16]
HM5165165 Data[15:0] Address[11:0] RD/WR CASHH CASHL HM5165165 Data[15:0] Address[11:0] RD/WR
CASHH CASHL
Figure 3.5.1.1-1 DRAM block diagram
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3.5.2 Flash memory
Flash memory SH7709CE reference platform HN29WT800 (HITACHI). This memory CMOS flash memory word bits, driven 3.3V. impossible control without difficult writing erasing, because have auto-writing auto erasing. Please refer flash memory data sheet more information.
3.5.2.1 Specification
(1)Specification SH7709CE reference platform have 8Mbytes flash memory space, because flash memory used. SH7709/area used flash memory space, flash memory parallel 2flash memory series, 32bits size supported memory space 2Mword 32bits. Address decode When SH7709 access flash memory, device switching that occurs over flow address done external address decoder. Contents this address decoder shown follow. Accessible address word 32bits flash memory H'00000000 H'07FFFFFF. Memory address series flash memories H'00000000 H'03FFFFFF H'04000000 H'07FFFFFF. Therefore, select series flash memories, bit22 address used. necessary signal select These bits active. logic bit22 address CE/WE/OE, when bit22 low, memory selected, when bit22 high, memory selected. Acknowledge signal write erase confirm that data have been written flash memory data have been erase from flash memory, RDY/BSY signal outputted from flash memory. This signal connected SH7709. Therefore, checked, possible acknowledge state. when this signal low, writing erasing, impossible user access, when this signal high, possible user access.
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Touch Panel Interface 3.6.1 Overview
Touch panel interface function integrated SH7709 chip. function converter, port Bias controller. down interrupt signal that made bias controller inputted SH7709. Sampling coordinate started interrupt signal. Each sampling timing generated timer SH7709.
3.6.2 Features
Feature touch panel interface function shown follow. resolution noise cancel function down interrupt Timing generator
3.6.3 Block Diagram
Figure shows block diagram touch panel interface.
SH7709
PTH1 PTK4 PTK7 position Bias controller position IRL1 IRL2 down
Digitizer
signal from panel
Figure 3.6.3-1 Block Diagram Touch Panel Interface
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3.6.4 Resource Configuration Touch Panel
Table 3.6.4-1 Resource Configuration Touch Panel Interface Peripheral Touch Panel Function Analog input position) Analog input position) Bias control Bias control Bias control signal detection down detection Timing Generator Resource channel SH7709 channel SH7709 port PTK1 SH7709 port PTK4 SH7709 port PTH7 SH7709 Interrupt IRQ2 SH7709 Interrupt IRQ1 SH7709 Timer channel SH7709
3.6.5 Register Definition
following table shows register about touch panel. Please refer SH7709 hardware manual more information. Table 3.6.5-1 Register list
Name data register (high) data register (low) data register (high) data register (low) control/status register control register Port control register Port data register Port control register Port data register Timer output control register Timer start register Timer control register Timer count register Timer constant register Interrupt priority level setting register Interrupt Control Register Abbreviation ADDRAH ADDRAL ADDRBH ADDRBL ADCSR SDCR PHCR PHDR PKCR PKDC TOCR TSTR TCR1 TCNT1 TCOR1 IPRC ICR1 R/(W) Initial Value H'00 H'00 H'00 H'00 H'00 H'3F H'0000 H'00 H'0000 H'00 H'00 H'00 H'0000 H'FFFFFFFF H'FFFFFFFF H'0000 H'0000 Address H'04000080 H'04000082 H'04000084 H'04000086 H'04000090 H'04000092 H'0400010E H'0400012E H'04000112 H'04000132 H'FFFFFE90 H'FFFFFE92 H'FFFFFEA8 H'FFFFFEA4 H'FFFFFEA0 H'04000016 H'04000010
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Register ADDRA (A/D Data Register
data registers (ADDRA, ADDRB) 16-bits read-only registers that store result conversion (pen sampling). conversion produces bits data, which transferred storage into data register corresponding selected channel. upper bits sampling data stored upper byte data register. lower bits stored lower byte. lower bits lower byte reserved, these data always ADDRx initialized h'0000 reset stand mode. Bit: ADDRnH Initial value: R/W: Bit: ADDRnL Initial value: R/W:
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ADCSR (A/D Control/Status Register
ADCSR 8-bit readable/writable register that selects mode controls converter. ADCSR initialized H'0000 reset stand mode. Bit: ADCSR Initial value: R/W:
Note:
R/(W)*
ADIE
ADST
SCAN
Only written, clear flag.
(ADF) status flag that indicates conversion 7:ADF Description [Clearing condition] (Initial value) Cleared reading while then writing Cleared when DMAC activated interrupt ADDR read [Setting conditions] Single mode: conversion ends. Scan mode: conversion that channel end. (ADIE) Enables disables interrupt (ADI) requested sampling (A/D conversion). SH7709CE reference platform that interrupt request (ADI) enable. 6:ADIE Description interrupt request (ADI) disabled (Initial value) interrupt request (ADI) enabled. When sampling completed, controller generates interrupt signal. (ADST) Starts stops sampling (A/D conversion). ADST remains during conversion. also external trigger input ADTRG pin. Please refer SH7709CE reference platform application (software) more information. 5:ADST Description conversion stopped (Initial value) Single mode: Sampling (A/D conversion) starts; ADST automatically cleared when sampling (A/D conversion) ends. Scan mode: Sampling (A/D conversion) starts; Selected channel converted until this cleared software reset stand mode. (SCAN) Selects single mode scan mode. Clear ADST before changing mode. 4:SCAN Description Single mode (Initial value) Scan mode
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(CKS) Selects conversion time. Clear ADST before changing mode. 3:CKS Description Conversion time states (maximum) (Initial value) Conversion time states (maximum) Bits (CH2 CH0) These bits SCAN select analog input channels. Clear ADST before changing channel selection. Group Channel Selection Description Selection Scan Mode Note sampling sampling used used used used used used
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ADCR (A/D Control Register)
ADCR 8-bit read/write register that enables disables external triggering conversion. ADCR initialized when reset stand mode. SH7709CE reference platform Bit: Initial value: R/W: TRGE
7-Trigger Enable (TRGE): Enables disables external triggering conversion. conversion started external trigger SH7709CE reference platform. 7:TRGE Description conversion cannot externally triggered (Initial value) used (Reserved) Read-only bits, always read
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Port register PHCR (Port Control Register)
Port Control Register (PHCR) 16-bit read/write register. PHCR initialized H'0000 power-on resets. initialized manual reset, stand mode sleep mode. SH7709CE reference platform initialized H'4020.
Bit: Name Initial value: R/W: Bit: Name Initial value: R/W: PH7MD1 PH7MD0 PH6MD1 PH6MD0 PH5MD1 PH5MD0 PH4MD1 PH4MD0 PH3MD1 PH3MD0 PH2MD1 PH2MD0 PH1MD1 PH1MD0 PH0MD1 PH0MD0
(2n+1) PHnMD1
PHnMD0
Description Other function (Initial value) Port output Port input (Pull Port input (Pull off)
PHDR (Port Data Register)
Bit: name: Initial value: R/W: PH7DT PH6DT PH5DT PH4DT PH3DT PH2DT PH1DT PH0DT
7-Port Data (PH7DT): This controls bias touch panel.
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PKCR (Port Control Register)
Port Data Register (PKCR) 16-bit read/write register. PKCR initialized H'0000 power-on resets. initialized manual reset, stand mode sleep mode. SH7709CE reference platform initialized H'0104. Bit: name: Initial value: R/W: Bit: name: Initial value: R/W:
PK7MD1 PK7MD0 PK6MD1 PK6MD0 PK5MD1 PK5MD0 PK4MD1 PK4MD0
PK3MD PK3MD PK2MD PK2MD PK1MD PK1MD PK0MD PK0MD0
(2n+1) PKnMD1
PKnMD0
Description Other function (Initial value) Port output Port input (Pull Port input (Pull off)
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PKDR (Port Data Register)
Bit: name: Initial value: R/W: PK7DT PK6DT PK5DT PK4DT PK3DT PK2DT PK1DT PK0DT
Bit4 Bit1 used output controls bias touch panel. PTH7 PTK4 PTK1 Description bias sampling mode (Initial value) used used used used bias status mode bias sampling mode used Please refer SH7709CE reference platform (Software volume) more information about mode change.
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Timer register TOCR (Timer output control register)
TOCR selects external terminal TCLK. Bit: name: Initial value: R/W: TCOE
Bit0 (TCOE) TCLK terminal used input terminal input capture control. 0:TCOE Description Timer clock terminal external clock input terminal internal timer input terminal input capture controller. Timer clock terminal output clock terminal output clock internal RTC.
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TSTR (Timer start register)
TSTR operated stopped timer counter channel TSTR 8bit read/write register. TSTR initialized H'0000 power-on resets manual reset. When stand mode, when magnification PLL1 clock mode changed, when MSTB2 STBCR select TSTR initialized peripheral clock external clock((TCLK) that selected from each channel. SH7709CE reference platform initialized H'00. Please refer SH7709CE reference platform application note (software value) more information about timing that TSTR start stop. Bit: name: Initial value: R/W: STR2 STR1 STR0
Bit2: STR2 2:STR2 Description TCNT2 don't count. (initial value) TCNT2 count. Bit1: STR1 STR1 Description TCNT1 don't count. (initial value) TCNT1 count. Bit0: STR0 STR0 Description TCNT0 don't count. (initial value) TCNT0 count.
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TCR1 (Timer control register)
TCR1 controls timer counters (TCNT) interrupts. three TCR, registers each channel. TCR1 register 16-bit read/write register that controls issuance interrupts when flag indicating timer counter (TCNT) underflow been also carry counter clock selection. When external clock been selected, they also select edge. TCR1 initialized H'0000 power-on reset manual reset. SH7709CE reference platform H'00. Bit: name: Initial value: R/W: Bit: name: Initial value: R/W: UNIE TPSC1 TPSC0
CKEG1 CKEG0 TPSC2
Bit8: Status flag that show under flow TCNT 8:UNF Description TCNT under flow. (initial value) [Clear requirement] written TCNT under flow. [Set requirement] TCNT under flow. Bit5: Control under flow interruption. 5:UNIE Description Disable interruption UNF. Enable interruption UNF. Bit4,3 These bits select external clock edge when external clock selected, when input capture function used. Bit4 CKEG1 Bit3 CKEG0 Description Count/ capture register rising edge (Initial value) Count/ capture register falling edge Count/ capture register both rising falling edge Bit2, These bits select TCNT count clock. Bit2 TPSC2 Bit1 TPSC1 Bit0 TPSC0
Description Internal clock count Internal clock count P/16 Internal clock count P/64 Internal clock count P/256 Internal clock count clock output on-chip (RTCCLK) External clock count TCLK input Reserved Reserved
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TCOR (Timer Constant Register)
timer constant register 32-bit read/write register. three TCOR registers, each three channels. When TCNT count-down results underflow, TCOR value TCNT count-down continues from that value. TCOR initialized H'FFFFFFFF power- reset manual reset; initialized stand-by mode, retains contents. SH7709CE reference platform H'FFFFFFFF. name Initial value UNIE TPSC1 TPSC0
TCNT (Timer Counters)
timer counters 32-bit read/write register. three timer counters, each channel. TCNT counts down upon input clock. clock input selected using TPSC2 TPSC0 bits timer control register (TCR). When TCNT count-down results underflow underflow flag (UNF) timer control register (TCR) relevant channel set. TCOR value simultaneously TCNT itself count-down continues from that value. Because internal SH7709 onchip supporting modules bits wide, time occur between time when upper bits lower bits read. Since TCNT counts sequentially, this time create discrepancies between data upper lower halves. correct discrepancy, buffer register connected TCNT that upper lower halves read separately. entire 32-bit data TCNT thus once. TCNT initialized H'FFFFFFFF poweron reset manual reset; initialized stand-by mode, retains contents. name Initial value
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Interrupt Register IPRC (Interrupt Priority Register)
Interrupt priority registers (IPRC) 16-bit read/write register that priority levels from "touch panel down interrupt" "LCD signal interrupt". This register initialized H'0000 power-on reset, manual reset, hardware standby mode, initialized software standby mode. Bit: name: Initial value: R/W: Bit: name: Initial value: R/W:
11-8 -LCD signal interrupt level Interrupt level signal interrupt specified. These bits with values from (0000) (1111). Setting means priority level (masking requested); priority level (the highest level). H'0000 should mask signal interrupt. -Pen Down Interrupt Level Interrupt level down interrupt specified. These bits with values from (0000) (1111). Setting means priority level (masking requested); priority level (the highest level). H'0000 should mask down interrupt.
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ICR1 (Interrupt control register)
ICR1 16-bit read/write register that sets mask function interrupt request input, detection mode external interrupt input pins IRQ0 IRQ5. This register initialized H'0000 power-on reset, manual reset, initialized standby mode. Bit: name: Initial value: R/W: Bit: name: Initial value: R/W: IRQLVL BLMSK IRQ51S IRQ50S IRQ41S IRQ40S
IRQ31S IRQ30S IRQ21S IRQ20S IRQ11S IRQ10S IRQ01S IRQ00S
15-Mask Interrupts(MAI): Selects whether interrupt requests masked when level being input pin. Description interrupt requests masked interrupt requests masked 14-IRQ, Select (IRQLVL): Select whether IRL0-3 IRQ0 IRQ0-3 mode used SH7709CE reference platform. IRQLVL Description IRL0 (not used) IRQ0 Bits 4-IRQ2 Sense Select (IRQ21S IRQ20S) Selects whether signal interrupt IRQ2 detected rising edge, falling edge, level. IRQ21S IRQ20S Description interrupt request detected IRQ2 input falling edge (initial value) interrupt request detected IRQ2 input rising edge interrupt request detected IRQ2 input level (not used) Reserved Bits 0-IRQ0 Sense Select (IRQ01S IRQ00S): Selects whether down interrupt detected rising edge, falling edge, level. Description IRQ01S IRQ00S interrupt request detected IRQ0 input falling edge (initial value) interrupt request detected IRQ0 input rising edge interrupt request detected IRQ0 input level (not used) Reserved
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3.6.6 Touch Panel Interface Operation
detect down, sample position detect status, software should control BC2BC0 signal using port. Please refer SH7709CE reference platform more information about software touch panel. Table 3.6.6-1Touch Panel Operation Mode Status Mode Sampling Mode Sampling Mode Note Detect down, check status Sample position Sample position
following future show basic operation.
Vcc(3.3v)
TPy2
TPx2
Figure 3.6.6-1 Touch panel above future shows state that input detected. This state that Tr2, Tr4, "ON". lower resister 3.3V, because "ON". When input occurs, upper resister gets touch with lower resister, voltage occurs voltage almost same voltage Vcc, because resister between very larger than touch panel resister. this time, input interrupt occurs. And, after input occurs, transfer measure mode point. sampling state that "ON" above. this time, Voltage descent occurs between voltage divided point. divided voltage, point measured. sampling same.
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3.6.7 Noise cancel signal
regularly reversed signal, because must protected. When signal reverses, high frequency noise occurs influence sampling data. necessary touch panel interface cancel this noise. About noise cancel, please refer SH7709CE reference platform application (software) signal inputted SH7709CE reference platform interrupt signal.
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Interface 3.7.1 Overview
SH7709CE reference platform color (640x480, dual scan citizen:K6488L-FF), display area only 640x240. SH7709CE reference platform uses controller (LCDC) HD64461. LCDC exclusive memory. LCDC reads data from memory, display data. SH7709CE reference platform used about control display contrast. please refer HD64461 hardware manual more information about LCDC. (LCDC only corresponds single scan type. dual scan type normally operated.
3.7.2 Features
color colors within 260K Half resolution (640 resolution) local frame memory controller HD64461 used. have external circuit.)
3.7.3 Resource configuration
Table 3.7.3-1 shows resource configuration interface. Table 3.7.3-1 Resource Configuration Interface Peripheral
Function
control
Resource
controller HD64461
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3.7.4 Block Diagram
Figure 3.7.4-1 shows block diagram Color LCD. Companion Chip Color colors Data Color Controller Data
SH7709 IRL2
Frame Memory 4MDRAM FA8-FA0 FD15-FD0 UCAS
FA8-FA0 FD15-FD0 FRAS
Figure 3.7.4-1Block Diagram Interface
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3.7.5 Register Definition
following table shows Register definition LCD. Name base address register line address offset register LCDC control register display register1 display register2 number characters horizontal register start position horizontal register total vertical lines register display vertical line register vertical synchronize position register display register3 color pallet write address register color pallet write data register color pallet read address register color pallet read data register Abbreviation LCDCBAR LCDCLOR LCDCCR LDR1 LDR2 LDHNCR LDHNSR LDVNTR LDVNDR LDVSPR LDR3 CPTWAR CPTWDR CPTRAR CPTRDR Address H'10001000 H'10001002 H'10001004 H'10001010 H'10001012 H'10001014 H'10001016 H'10001018 H'1000101A H'1000101C H'1000101E H'10001030 H'10001032 H'10001034 H'10001036 Access Size
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LCDC Base Address Register (LCDCBAR)
LCDCBAR 16-bit read/write register that select start address memory display this register, provides display area start address 24-12 display memory. H'0000 initialize value. case output data from display area start address, H'0000.
name Initial value name Initial value
BAD7
BAD6
BAD5
BAD12 BAD11 BAD10 BAD4 BAD3 BAD2
BAD9 BAD1
BAD8 BAD0
Line Address Offset Register (LCDCLOR)
LCDCLOR 16-bit read/write register that provides line increment address. H'0000 initialize value. case horizontal number 640(8bpp), H'0280. H'0000 SH7709CE reference platform. name Initial value name Initial value LO10
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LCDC Control Register (LCDCCR)
LCDCCR read/write register, which used control Controller. Initial value H'0000. H'0011 SH7709CE reference platform. name Initial value name Initial value SPON STBAC STREQ
REFSEL EPON
DSPSEL DSPSEL DSPSEL
10-Standby Back (STBACK): This shows LCDC current state. STBACK Description shows default state shows standby state VRAM access from forbidden. 8-Standby Request (STREQ): When this LCDC begins standby sequence. STREQ Description requires default state requires standby state SH7709CE reference platform usually default state. But, when initialized suspended, case standby state. About timing, please refer SH7709CE reference platform application manual (software) more information. 6-Refresh Select (REFSEL): When this LCDC makes display memory self refresh mode standby sequence. REFSEL Description self refresh self refresh Bit5-End Power (EPON): this shows that LCDC finished power sequence. EPON Description default power sequential
4-Start Power (SPON): When this LCDC begins power sequence. About timing, please refer SH7709CE reference platform application note (software) more information. SPON Description default start power sequential
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2-0-Display select (DSPSELn (n=1 2)): These bits select display type. Stand alone mode native mode mode mode both. DSPSEL2 DSPSEL0 Description DSPSEL1 mode used mode used mode mode used used used
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LCDC display register1 (LDR1)
LDR1 16bit read/write register, which controls display LCD. Initial value H'0001.
name Initial value Bit: name: Initial value: R/W:
DINV
8-Display invert (DINV): When this monochrome display data inverted grayscale. DINV Description default invert monochrome data 0-Display (DON): Select start/stop display. Description usually operated state "LCD on". "LCD off" occurs software control. About timing that "on/off changed, please refer SH7709CE reference platform application note (software).
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LCDC display register2 (LDR2)
LDR2 16bit read/write register, which select output type data control signal. H'00C4 SH7709CE reference platform. name Initial value name Initial value reserved reserved reserved
reserved reserved reserved
7-Clock control (CC1): Select output type retrace period. Description output retrace period. output retrace period. 6-Clock control (CC2): Select output type retrace period. Description output retrace period. output retrace period. 2-0-LCD mode (LM2- LM0): display data output interface. Description Monochrome, screen, 4bits output Monochrome, screen, 8bits output reserved reserved Color, screen, output bits reserved reserved reserved SH7709CE reference platform uses color mode.
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LCDC Display Register (LDR3)
LDR3 16bit read/write register, which decides type output data speed etc. H'0204 SH7709CE reference platform. name Initial value name Initial value
Bit9-5-Clock select (CS9-CS5) Select frequency. Bit9:CS4 8:CS3 7:CS2 6:CS1 5:CS0
Description 2.5MHz 3.75MHz 5MHz 7.5MHz 10MHz 15MHz
Bit3-0-Color/Grayscale (CG3-CG0) Select mode. Bit3:CG3 Bit2:CG2 Bit1:CG1 Bit0:CG0 Description Monochrome, 1bit, grayscale Monochrome, 1bit, grayscale Monochrome, 4bits, grayscale Monochrome, 6bits, grayscale Color, 8bits, color Color, 16bits, R,G,B: 5-6-5 bits/64k color SH7709CE reference platform uses color mode.
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Number Characters Horizontal Register (LDHNCR)
LDNCHR 16bits read/write register, which select number characters horizontal. number characters calculated following numerical formula. H'4F54 SH7709CE reference platform. number characters (Number pixel horizontal)/8-1 Number horizontal display characters Number horizontal total characters name Initial value name Initial value NHD7 NHT7 NHD6 NHT6 NHD5 NHT5 NHD4 NHT4 NHD3 NHT3 NHD2 NHT2 NHD1 NHT1 NHD0 NHT0
Start Position Horizontal Register (LDHNSR)
LDHNSR 16bits register, which used specify output start position width clock. H'0051is SH7709CE reference platform. width number characters. output start position number characters. name Initial value R/W: name Initial value HSP7 HSP6 HSP5 HSP4 HSW3 HSP3 HSW2 HSP2 HSW1 HSP1 HSW0 HSP0
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Total Vertical Lines Register (LDVNTR)
LDVNTR 16bits read/write register, which used specify total vertical lines. H'00F1 SH7709CE reference platform. (Number total vertical lines) name Initial value name Initial value VTL7 VTL6 VTL5 VTL4 VTL3 VTL2 VTL9 VTL1 VTL8 VTL0
Display Vertical Lines Register (LDVNDR)
LDVNDR 16bits read/write register, which used specify number vertical display lines. H'00F1 SH7709CE reference platform. (Number vertical display lines) name Initial value name Initial value VDL7 VDL6 VDL5 VDL4 VDL3 VDL2 VDL9 VDL1 VDL8 VDL0
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Vertical Synchronous Position Register (LDVSPR)
LDVSPR 16bits read/write register, which used specify frequency driving signal alternation vertical synchronization position. H'3002 SH7709CE reference platform. signal set. (Total number lines) (Vertical synchronous position) name Initial value name Initial value VSP7 VSP6 VSP5 VSP4 VSP3 VSP2 VSP9 VSP1 VSP8 VSP0
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Color Pallet Write Address Register (CPTWAR)
CPTWAR 16bits read/write register, which pallet number color pallet. Pallet automatically increment return R/G/B, whenever data written data register. case striding over pallet, automatically transfer next pallet. (Please take care number writing times, because increment usually return R/G/B. please refer SH7709CE reference platform application note (software) more information about setup contents pallet. name Initial value name Initial value
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Color Pallet Write Data Register (CPTWDR)
CPTWDR 16bits write register, which writes color information color pallet. lower 6bits available this register. necessary write turn R/G/B writing data this register. pallet number automatically increment, possible write data continuously. (Please refer SH7709CE reference platform application note (software) more information about setup contents pallet.) name Initial value name Initial value
Color Pallet Read Address Register (CPTRAR)
CPTRAR 16bits read only register, which shows color pallet number. After CPTRAR read times, this register increment. (Please refer SH7709CE reference platform application note (software) more information about setup contents pallet.)
Color Pallet Read Data Register (CPTRDR)
CPTRDR 16bits read only register, which read color information that color pallet. This register outputs turn R/G/B. Continue reading, pallet number have increment able continue reading next pallet data too. (Please refer SH7709CE reference platform application note (software) more information about setup contents pallet.)
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3.7.6 Interface
following shows about interface SH7709 HD64461/LCDC.
3.7.6.1 Register allocation
register HD64461 assigned lower 32Mbytes area SH7709. display memory assigned upper 32Mbytes. Address H'00000000~H'01FFFFFF H'02000000~H'03FFFFFF Area SH7709 HD64461 register Display memory
3.7.6.2 LCDC display format
following figure shows LCDC display format. This format 8bpp format.
Dot1
Dot0
Display Area
Figure 3.7.6.2-1 LCDC display format
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3.7.6.3 interface timing
following figure shows timing chart interface.
Horizontal Total Line Output Start Position LCMD[7:0] Display Area width Next Line
Figure 3.7.6.3-1 CL1, output data timing
Display Lines Total Lines Number line Data
line
line
line
line
Figure 3.7.6.3-2 signal, FLM, output data timing
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Audio Playback Interface 3.8.1 Overview
Audio Playback converter, DMAC Timer. although need only amplifier external, need other peripheral circuit.
3.8.2 Features
Figure shows block diagram Audio playback.
SH7709
Speaker Amplifier converter Timer (CMT) Request Sample rate DMAC Address sound data
Sound data
Memory
Figure 3.8.2-1 Block Diagram Audio Playback Interface
3.8.3 Resource Configuration Audio Playback
Table3.8.3-1 Resource Configuration Audio Playback Interface Peripheral
Audio playback
Function
converter transfer Timing Generator
Resource
channel SH7709 DMAC channel SH7709 timer SH7709
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3.8.4 Register specification
Shows register specification audio playback. register used SH7709CE reference platform.
data register (DADR0)
data register (DADR0) read/write register that store data converted. When conversion enable, data register values constantly converted. DADR0 Initial value
control register (DACR)
control register (DACR) 8-bit read/write register that controls operation converter. DACR initialized H'1F. DACR Initial value DAOE1 DAOE0
Bit7, (DA0E1, DA0E0, DAE) controls converter analog output. This cleared channel channel individually controlled. When converter transfers software standby mode movement, output value held. control power consumption software standby mode, necessary stop converter before transferring standby mode. 7:DAOE1 6:DAOE0 5:DAE Description channel 1are stopped. channel enabled channel disabled Channel enabled channel enabled channel disabled Channel enabled Channel enabled
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Register source address register (SAR2)
source address registers (SAR2) 32-bit read/write registers that specify source address transfer. During transfer, these registers indicate next source address. initial value after resets hardware software standby mode undefined. SAR2 Initial value Bit: SAR2 Initial value: R/W:
Destination Address Register (DAR2)
destination address registers (DAR2) 32-bit read/write registers that specify destination address transfer. During transfer, this register indicates next destination address. initial value after resets hardware software standby mode undefined. name Initial value name Initial value
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Transfer Count Register (DMATCR2)
transfer count registers (DMATCR2) 24-bit read/write registers that specify transfer count. number transfers when setting H'0001, 65535 when H'FFFF, 65536 (the maximum) when H'0000. During transfer, these registers indicate remaining transfer count. Upper eight bits DMATCR2 invalid. read these bits read. initial value after resets hardware standby mode software standby mode undefined. DMATCR2 Initial value Bit: name: DMATCR2 R/W:
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Channel Control Register (DMACHCR2)
channel control registers (DMACHCR2) 32-bit read/write registers that specifies operation mode, transfer method. These register values initialized after power-on resets software standby mode hardware standby mode. name Initial value name Initial value name Initial value (R/W) (R/W) (R/W) (R/W)
Bit20 (DI) This selects direct address mode indirect address mode. This only valid CHCR3. Writing this invalid CHCR0 CHCR2; read this read. Bit19 (RO) This selects whether source address initial value reloaded channel This only valid CHCR3. Writing this invalid CHCR0 CHCR2; read this read. Description source address reloaded (initial value) source address reloaded Bit17 (AM) This specifies whether DACK output data read cycle data write cycle dual address mode. This only valid CHCR0 CHCR1. Writing this invalid CHCR2 CHCR3; read this read. Bit16 (AL) This specifies DACK (acknowledge) signal output high active active. This only valid CHCR0 CHCR1. Writing this invalid CHCR2 CHCR3; read this read.
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Bit15, (DM1, DM0) These select whether destination address incremented, decremented, left fixed. These initialized "00" when reset standby mode. Description Fixed destination address (initial value) Destination address incremented 8-bit transfer, 16-bit transfer, 32-bit transfer) Destination address decremented 8-bit transfer, 16-bit transfer, 32-bit transfer) Illegal setting Bit13, (SM1, SM0) These select whether source address incremented, decremented, left fixed. These initialized "00" when reset standby mode. Description Fixed source address (initial value) Source address incremented 8-bit transfer, 16-bit transfer, 32-bit transfer) Source address decremented 8-bit transfer, 16-bit transfer, 32-bit transfer) (Reserved) Illegal setting Bits 11-8 (resource select bits (RS3-RS0)) RS3-RS0 specify which transfer requests will sent DMAC. Perform change transfer request source, when enable (DE) "0". These initialized "0000" when reset standby mode. Description External request*, dual address mode (initial value) Illegal setting Illegal setting Illegal setting Auto-request Illegal setting Illegal setting Illegal setting Illegal setting Illegal setting SCI1 transmission SCI1 reception SCI2 transmission SCI2 reception Internal Bit5 (TM) specifies mode when transferring data. Description Cycle steal mode (initial value) Burst mode
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Bit4, (TS1, TS0) specifies size data transferred. transfer source transfer only byte access register internal module, surely select byte access. These initialized "00" when reset standby mode. Description Byte size bits) (initial value) Word size bits) Longword size bits) Illegal setting Bit2 (IE) When transfer ends, this specifies which request interrupt. When "1", set, this requests interrupt (DEI) CPU. This initialized Description Interrupt request generated even data transfer ends specified count (initial value) Interrupt request generated data transfer ends specified count
Bit1 (TE) when data transfer ends count specified DMATCR. this time, interrupt request generated. Before this data transfer ends interrupt cleaning DMAOR, this clear bit, write after reading When set, transfer disabled "1". This initialized when reset standby mode. Description Data transfer does count specified DMATCR (initial value) Clear condition: Writing after read, power-on reset, manual reset, standby Data transfer ends specified count Bit0 (DE) These enables disables transfer. necessary auto-request that NMIF DMAOR "0". After have been when transfer required from device internal peripheral module, transfer starts internal peripheral module request mode. this case, necessary that NMIF DMAOR too. cleared, transfer stops. When reset stand-by mode, initialized Description Disables channel operation (initial value) Enables channel operation
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Timer Register Compare Mach Timer Start Register (CMSTR)
compare match timer start register (CMSTR) 16-bit register that selects whether operate halt channel counter (CMCNT). initialized H'0000 power-on resets standby mode. Initial value Initial value
(STR): Selects whether operate halt compare match timer counter. Description CMCNT count operation halted (initial value) CMCNT count operation
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Compare Mach Timer Control/Status Register (CMCSR)
compare match timer control/status register (CMCSR) 16-bit register that indicates occurrence compare matches, sets enable/disable interrupts, establishes clock used incrementation. initialized H'0000 power-on resets standby mode. Initial value Initial value R/(W)* CKS1 CKS0
(CMF) This flag indicates whether CMCNT CMCOR values have matched. Description CMCNT CMCOR values have matched (initial status) Clear condition: Write after reading from CMCNT CMCOR values have matched Bits (CKS1, CKS0) These bits select clock input CMCNT from among four internal clocks obtained dividing peripheral clock When CMSTR CMCNT begins incrementing with clock selected CKS1 CKS0. CKS1 CKS0 Description Peripheral clock 15MHz/4 3.75MHz (initial status) Peripheral clock 15MHz/4 1.875MHz Peripheral clock 15MHz/16 0.9375MHz Peripheral clock 15MHz/64 0.234375MHz
Compare match Constant Register (CMCOR)
compare match constant register (CMCOR) 16-bit register that sets compare match period with CMCNT. CMCOR initialized H'FFFF power-on resets standby mode. CMSTR Initial value CMSTR Initial value
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Audio Record Interface 3.9.1 Overview
Audio record interface realized using SGS-Thomson STLC7550 which same Interface chip. Software modem Audio record operate concurrently since these interface share STLC7550.
3.9.2 Features
STLC7550 function sampling resolution Sampling Ratio 11.025KHz 22.05KHz 44.1KHz
3.9.3 Block Diagram
HD64461 MCLK Clock Modem Divider 5.348MHz Data Interface Clock Select Clock Select Selector MCLK Audio Microphone
Data
GPIO GPIO
Figure 3.9.3-1 Audio record block diagram
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3.9.4 Resource Configuration
following table shows resource configuration audio record interface. Table 3.9.4-1 Resource Configuration Sound Record Interface Peripheral
Audio record
Function
interface converter
Resource
HD64461 interface SGS-Thomson STLC7546
3.9.5 Register Definition
following table shows register definition audio record. value SH7709CE reference platform. Register interface control register interface status register Transmit data register Receive data register Transmit data buffers register Receive data buffers register Abbreviation ACTR ASTR ATXDR ARXDR ATXDBR0,1 ARXDBR0,1 Address H'10003200 H'10003202 H'10003206 H'10003204 H'10003100-5F H'10003000-5F Access size
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control register (ACTR)
control register (ATCR) 16-bit read/write register, which used control interface. bits this register initialized reset. ACTR initialized standby mode. ACTR Initial value ACTR Initial value RDE0 Div2 TEIT Div1 REIE TEIX CNT2 REIX CNT1 BUFD
(HC) This used register chip. (HC) Description Transmit/Receive normal data Send data that stored ATXDR chip command (Div2, This specifies division ratio clock. (Div2) (Div1) Description Division ratio Division ratio Division ratio Reserved (RLY) This specifies signal that output from RLYCNT pin. (RLY) Description output from RLYCNT pin. output from RLYCNT pin. (CNT2) This specifies signal that output from PWRDWN0 pin. (CNT2) Description output from PWRDWN0 pin. output from PWRDWN0 pin. (CNT1) This specifies signal that output from RESET0 pin. (CNT1) Description output from RESET0 pin. output from RESET0 pin. (TSW) This specifies change RLYCNT pin. (TSW) Description value output that with ACTR. Transmit data output from RLYCNT pin.
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(RSW) This specifies receive data input pin. (RSW) Description input receive data. RING input receive data. (RDETM) This specifies enable/disable RDET interrupt. (TSW) Description RDET interrupt enable. RDET interrupt disable. (TEIE) This specifies enable/disable transmit error interrupt. (TEIE) Description transmit error interrupt (TERI) disable. transmit error interrupt (TERI) enable. (REIR) This specifies enable/disable receive error interrupt. (REIR) Description receive error interrupt (RERI) disable. receive error interrupt (RERI) enable. (TXIE) This specifies enable/disable transmit data empty interrupt. (TXIE) Description transmit data empty interrupt (TDEI) disable. transmit data empty interrupt (TDEI) enable. (RXIR) This specifies enable/disable receive data full interrupt (RDFI). (RXIR) Description receive data full interrupt (RDFI) disable. receive data full interrupt (RDFI) enable. (BUFD) This specifies transmit/receive mode. (RXIR) Description receive data full interrupt (RDFI) disable. receive data full interrupt (RDFI) enable. (TE) This specifies enable/disable transmit. (TE) Description Transmit disable. Transmit enable. (RE) This specifies enable/disable receive. (RE) Description Receive disable. Receive enable.
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Status Register (ASTR)
status register (ASTR) 16bit read only register only written lower four bits clearing after read), which used indicate status interface. ASTR initialized standby mode. ASTR must read word. byte read performed, valid values cannot guaranteed after that read. ASTR Initial value ASTR Initial value R/(W) Reserved Reserved Reserved Reserved Reserved Reserved R/(W) RERR R/(W) R/(W) R/(W)
Reserved Reserved Reserved Reserved TERR R/(W)
This indicates bank number ATXDBR that user access. (TAB) Description Read/write performed ATXDBR0. Read/write performed ATXDBR1. This indicates bank number ARXDBR that user access. (RAB) Description Read/write performed ARXDBR0. Read/write performed ARXDBR1. This indicates state transmit error. (TERR) Description Indicates that transmit error does occur. Indicates that transmit error occurred. This indicates state receive error. (RERR) Description Indicates that receive error does occur. Indicates that receive error occurred. This indicates state transmit data buffers. (TDE) Description Indicate that both transmit data buffers include transmit data. Indicate that least either transmit data buffers (ATXDR) includes transmit data. This indicates state receive data buffers. (RDF) Description Indicate that receive data buffers full. Indicate that least receive data buffer full receive data.
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Transmit Data Register (ATXDR)
ATXDR 16bit read/write register, which transmit data stored. case transmitting register mode, write data this register. case transferring command register chip, write data this register regardless transfer mode. bits this register initialized reset. ATXDR initialized standby mode. ATXDR Initial value
Receive Data Register (ARXDR)
ARXDR 16bit read only register, which receive data stored. case receiving register mode, read receive data from this register. bits this register initialized reset. ARXDR initialized standby mode. ATXDR Initial value
Transmit Data Buffers (ATXDBR 0,1)
ATXDBR ATXDBR read/write register. These transmit data storage buffers, each which 48-word data stored. case transferring buffer mode, write transmit data this register. Users access only buffer that used transmit.
Receive Data Buffers (ARXDBR 0,1)
ARXDBR ARXDBR 16bit read only register. These receive data storage buffers, each which 48-word data stored. case receiving buffer mode, read receive data from this register. Users access only buffer that used receive.
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STLC7550 (SGS-Thomson) Register
STLC7550 (SGS-Thomson) used chip SH7709CE reference platform. following shows specification this register. name Initial value name Initial value
(D1) This selects Auxiliary input main input. (D1) Description Main receive input Auxiliary receive input (D2) This selects receive signal gain. (D2) Description gain (Differential Input) gain (Single Ended) gain (Differential Input) gain (Single Ended) (D5, These bits select oversampling ratio. Bir5 (D5) (D4) (D3) Description Reserved Reserved Reserved (D7,D6) These bits select transmit attenuation. (D7) (D6) Description Infinite Reserved
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(Q2, These bits select divider clock generator. Bir11 (Q2) Bit10 (Q1) Bit9 (Q0) Description divider divider divider divider divider divider divider divider (T1, These bits select divider clock generator. Bit13 (T1) Bit12 (T0) Bit8 Description divider divider Reserved Reserved divider divider (Test3, Test2) These bits test pin. sure write Bit15 (Test3) Bit14 (Test2) Description Test (Not used)
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3.10 Keyboard Interface 3.10.1 Overview
This keyboard scanning keyboard scanned ports SH7709.Key down detected interrupt request SH7709. Device Driver does scan Keyboard while After down starts, software start TIMER scan keyboard. Please refer SH7709CE reference platform application manual (software) more information about management order keyboard.
3.10.2 Feature
Maximum keys Generate down interrupt
3.10.3 Block Diagram
Figure shows block diagram keyboard interface. Keyboard keys Max)
SH7709
SCPT,E,D,C Input Output PINT
Port Input
Figure 3.10.3-1 Block Diagram Keyboard Interface
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3.10.4 Resource Configuration
Table 3.10.4-1 Resource Configuration Keyboard Interface Peripheral Keyboard Function scan sense Timing Generator Resource scan (SCPT2, PTE6, PTE3, PTD3, PTD2, PTC7-0) SH7709 sense (PTF7-0) SH7709 Timer channel HD64461
3.10.5 Register Definition
Name Port control register Port data register Port control register Port data register Port control register Port data register Port control register Port data register Port SCPT control register Port SCPT data register Timer control register Timer constant value register Timer interrupt mask register Abbreviation PFCR PFDR PCCR PCDR PECR PEDR PDCR PDDR SCPCR SCPDR TCR1 TCRV1 TIMR Initial Value H'AAAA H'00 H'AAAA H'00 H'AAAA H'00 H'AAAA H'00 H'A888 H'00 H'0000 H'FFFF H'0000 Address Access Size H'400010A H'400012A H'4000104 H'4000124 H'4000108 H'4000128 H'4000106 H'4000126 H'4000116 H'4000136 H'12006008 H'12006000 H'1200600E
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PFCR (Port Control Register)
Port control register (PFCR) 16bit read/write register that selects function. PFCR initialized power-on resets. However, initialized manual resets, software standby mode, sleep mode. This register initialized H'AAAA SH7709CE reference platform. name PF7MD1 PF7MD0 PF6MD1 PF6MD0 PF5MD1 PF5MD0 PF4MD1 PF4MD0 Initial value name Initial value PF3MD1 PF3MD0 PF2MD1 PF2MD0 PF1MD1 PF1MD0 PF0MD1 PF0MD0 (2n) PFnMD1 Description Other function Reserved Port input (Pull Port input (Pull off)
(2n+1) PFnMD1
Port Data Register (PFDR)
PFCR Initial value PF7DT PF6DT PF5DT PF4DT PF3DT PF2DT PF1DT PF0DT
(PF7DT-PF0DT) These bits used sense. PF7DT-PF0DT correspond each sense 7-0.
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PCCR (Port Control Register)
Port control register (PCCR) 16bit read/write register that selects function. PCCR initialized power-on resets. However, initialized manual resets, software standby mode, sleep mode. This register initialized H'AAAA SH7709CE reference platform. name Initial value name Initial value
PC7MD1 PC7MD0 PC6MD1 PC6MD0 PC5MD1 PC5MD0 PC4MD1 PC4MD0
PC3MD1 PC3MD0 PC2MD1 PC2MD0 PC1MD1 PC1MD0 PC0MD1 PC0MD0 (2n) PCnMD1 Description Other function Port output Port input (Pull Port input (Pull off)
(2n+1) PCnMD1
Port Data Register (PCDR)
PCDR Initial value PC7DT PC6DT PC5DT PC4DT PC3DT PC2DT PC1DT PC0DT
(PC7DT-PC0DT) These bits used sense. PC7DT-PC0DT correspond each sense 7-0.
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PDCR (Port Control Register)
Port control register (PDCR) 16bit read/write register that selects function. PDCR initialized power-on resets. However, initialized manual resets, software standby mode, sleep mode. This register initialized H'464A SH7709CE reference platform. name Initial value name Initial value PD7MD PD7MD PD6MD PD6MD PD5MD PD5MD PD4MD PD4MD0 PD3MD PD3MD PD2MD PD2MD PD1MD PD1MD PD0MD PD0MD0 (2n) PDnMD1 Description Other function Port output Port input (Pull Port input (Pull off)
(2n+1) PDnMD1
Port Data Register (PDDR)
PDDR Initial value PD7DT PD6DT PD5DT PD4DT PD3DT PD2DT PD1DT PD0DT
(PD3DT, PD2DT) These bits used sense. PD3DT, PD2DT correspond each sense
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PECR (Port Control Register)
Port control register (PECR) 16bit read/write register that selects function. PECR initialized power-on resets. However, initialized manual resets, software standby mode, sleep mode. This register initialized H'A0AA SH7709CE reference platform. name Initial value name Initial value PE7MD1 PE7MD0 PE6MD1 PE6MD0 PE5MD1 PE5MD0 PE4MD1 PE4MD0
PE3MD1 PE3MD0 PE2MD1 PE2MD0 PE1MD1 PE1MD0 PE0MD1 PE0MD0
(2n+1) PEnMD1
(2n) PEnMD0
Description Other function Port output Port input (Pull Port input (Pull off)
Port Data Register (PEDR)
PEDR Initial value PE7DT PE6DT PE5DT PE4DT PE3DT PE2DT PE1DT PE0DT
(PE6DT, PE3DT) These bits used sense. PE6DT, PE3DT correspond each sense
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SCPCR (Port Control Register)
Port control register (SCPCR) 16bit read/write register that selects function. SCPCR initialized power-on resets. However, initialized manual resets, software standby mode, sleep mode. This register initialized H'A88B SH7709CE reference platform. name Initial value name Initial value SCP7 SCP3 SCP7 SCP3 SCP6 SCP2 SCP6 SCP2 SCP5 SCP1 SCP5 SCP1 SCP4 SCP0 SCP4 SCP0
SCP2MD0 SCPT2 used scan keyboard.
SCP2MD1
Description Other function Port output Port input (Pull Port input (Pull off)
Port Data Register (SCPDR)
SCPT Initial value SCP7DT SCP6DT SCP5DT SCP4DT SCP3DT SCP2DT SCP1DT SCP0DT
(SCP2DT) This used scan output. SCP2DT correspond scan
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Timer Register
Used timer keyboard timer HD64461. used generating scan timing, when down. following shows timer register HD64461 that used keyboard interface.
Timer Control Register
TCR0 Initial value TCR0 Initial value Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved ETM01 PST11 PST10 T1STP
(ETM01) :This used enable disable timer output. 3:ETM01 Description Disable timer output (Initial value) Enable timer output (PST11, PST10) Clock input timer1 selected these bits. 2:PST11 1:PST10 Description Timer input clock CKIO Timer input clock CKIO Timer input clock CKIO Timer input clock CKIO
(T1STP) This used start stop counting timer 0:T1STP Description Stop Timer1 count Start Timer1 count
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Timer Interrupt Mask Register (TIMR)
TIMR Initial value TIMR Initial value Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved TMU1M TMU0M
(TMU1M) This used mask interrupt request timer1. 1:TMU1M Description mask interrupt request timer1 Mask interrupt request timer1 (TMU0M) This used mask interrupt request timer0. 0:TMU0M Description mask interrupt request timer0 Mask interrupt request timer0
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Timer Constant Value Register (TCRV1)
Timer constant value register (TCRV1) 16-bit read/write register that indicate count value timer This register initialized H'FFFF resets. TCRV Initial value TCRV Initial value
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3.11 IrDA Interface 3.11.1 Overview
This board IrDA interface. This IrDA interface IrDA1.1 compatible. internal module HD64461 used IrDA interface. TFDS6000 (TEMIC) used IrDA module. Please refer HD64461 hardware manual more information about IrDA interface.
3.11.2 Features
Ir-FIR compatible Support speed 4Mbps
3.11.3 Block Diagram
Figure shows block diagram IrDA Interface. Infrared Transfer Module MODSEL Companion Chip MODSEL DREQ DACK Data Address DMAC0 SH7709
UART
Memory
Figure3.11.3 Block Diagram IrDA Interface
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3.11.4 Resource Configuration
Table3.11.4-1 Resource Configuration IrDA Interface Peripheral
IrDA
Function
Serial Interface Modulation De-modulation transfer
Resource
UART HD64461 IrDA controller HD64461 DMAC channel SH7709
3.11.5 Register Definition
following shows register definition IrDA. Address H'10007100 Bank Read/Write Contents Master control register Master control register Master control register Master status register Control register Address register Configuration register FIFO register FIFO register byte count register Transceiver control register control register byte count register Configuration register control register ring frame pointer register Timer register status register ring frame pointer register Configuration register control register byte count register Reserved status register Reset command register byte count register Reserved read data port write data port Reserved
H'10007102
H'10007104
H'10007106
H'10007108
H'1000700A
H'1000700C
H'1000700E
H'10007110 H'10007112 H'10007FFE
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Master control register
Master control register 8bit read/write register that selects enable disable access bank, transfer/receiver, interruption. Initial value: R/W:
(IE) This selects enable/disable interface interrupt.
7:IE Description Disable interface interrupt Enable interface interrupt
(TxE) This selects enable/disable interface transfer.
6:TxE Description Disable interface transfer Enable interface transfer
(RxE) This selects enable/disable interface receiver.
5:TxE Description Disable interface receiver Enable interface receiver
(BS4~BS0) These bits select access bank.
Bank
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Master Status Register
Master status register 8bit read only register that distinguish IrDA interface interrupt source. Bit: Reserved Reserved
(TI) This indicates state timer interrupt.
6:TI Description Timer interrupt doesn't occurs Timer interrupt occur
(TxI) This indicates state transfer interrupt.
5:TxI Description Transfer interrupt doesn't occurs Transfer interrupt occurs
(RxI) This indicates state receiver interrupt.
4:RxI Description Receiver interrupt doesn't occur Receiver interrupt occurs [clear condition] Reading Ring Frame Counter Register
(ID2 ID0) These recognize interrupt factor. Bit3 Bit2 Bit1 Priority Interrupt Type (the other state)*1 data detect buffer empty (the other state)*2 These factors FIFO over run, frame error, EOF, stop etc. These factors FIFO under line, EOM, early etc.
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Control register
Control register 8bit read/write register which decides channel Controller Loopback. DCS1 DCS0 Reserved Reserved Reserved Reserved
Bit7,6 (DSC1,DSC0) These bits select channel. Bit7 DSC1 Bit6 DSC0 Description used. Channel used receive. Channel used transfer. Reserved Bit5 (CL) This sets controller loopback. Bit5 Description loopback test mode. loopback test mode. Bit4 (ML) This modem loopback. Bit4 Description modem loopback test mode. modem loopback test mode.
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FIFO register
FIFO register 8bit read only register. Receive packet data read from this register.
FIFO register
FIFO register 16bit read/write register. Transmit packet data written this register.
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control register
control control register 8-bit read/write register which controls transmission.
ARRTS
AREOM
TxIDL
Bit7 (RTS) This select signal modem (active active). enable (Master control register bit6) before this set, write data FIFO register. Bit7 Description signal active. signal active. Bit6 (ETI) This enables/disables FIFO ready interrupt factor. Bit6 Description FIFO ready interrupt enabled. FIFO ready interrupt disabled. Bit5 (ETU) This enable/disable under /EOM interrupt FIFO. Bit5 Description Under run/EOM interrupt FIFO disabled. Under run/EOM interrupt FIFO enabled. Bit4 (TFL) This sets threshold FIFO. Bit4 Description Threshold FIFO Half-empty. Threshold FIFO Not-Full. Bit3 (ARRTS) This automatically signal after transmit. When loopback mode, this (Refer HD64461 hardware manual more information.) Bit3 ARRTS Description signal automatically non-active. signal automatically non-active. Bit2 (AREOM) This automatically which cleared after register read. Bi

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