Bidirectional Controlled Synthesiser DS3743 ISSUE June 1998

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Bidirectional Controlled Synthesiser DS3743 ISSUE June 1998

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SP5655
Bidirectional Controlled Synthesiser
DS3743 ISSUE June 1998
SP5655 single chip frequency synthesiser designed tuning systems. Control data entered standard format. device contains addressable current limited outputs addressable bidirectional open-collector ports, which 3-bit ADC. information these ports read BUS. device fixed address programmable addresses, programmed applying specific input voltage current limited outputs. This enables more synthesisers used system.
Ordering Information
SP5655 KG/MPAS (Tubes) SP5655S KG/MPAD (Tape reel)
FEATURES Complete Single Chip System High Sensitivity Inputs
CHARGE PUMP CRYSTAL CRYSTAL
DRIVE OUTPUT INPUT INPUT OUTPUT PORT OUTPUT PORT/ SELECT PORT
Programmable Power Consumption (5V, 30mA) Radiation Phase Lock Detector Varactor Drive Disable Controllable Outputs, Bidirectional 5-Level Variable Address Multi-tuner Applications Protection: 4kV, Mil-Std-883C, Method 3015 Switchable 4512/1024 Reference Divider Function Compatible with SP5055S
Normal handling precautions should observed. SP5055S does have switchable reference division ratio.
SP5655
PORT
PORT
PORT
MP16
Logic level port 3-bit input
Fig. connections view
APPLICATIONS Satellite
High Cable Tuning Systems
THERMAL DATA
41°C/W 111°C/W
SP5655
ELECTRICAL CHARACTERISTICS
TAMB 220°C 180°C, reference frequency 4MHz. These Characteristics guaranteed either production test design. They apply within specified ambient temperature supply voltage ranges unless otherwise stated. Value Characteristic Min. Supply current Prescaler input voltage Prescaler input impedance Prescaler input capacitance SDA, Input high voltage Input voltage Input high current Input current Leakage current Output voltage Charge pump current Charge pump current high Charge pump output leakage current Charge pump drive output current Charge pump amplifier gain Recommended crystal series resistance Crystal oscillator drive level Crystal oscillator negative resistance External reference input frequency External reference input amplitude Output Ports sink current leakage current P4-P7 sink current P4-P7 leakage current Input Ports input current high input current input voltage input voltage high input current high input current 13,14 13,14 6400 9,8,6 9,8,6 1000 Parallel resonant crystal (note coupled sinewave mVrms coupled sinewave VOUT VOUT VOUT VOUT Typ. Max. (note mVrms 120MHz sinewave, Fig. Units Conditions
Input voltage Input voltage When Sink current Byte Byte Byte
Table levels
NOTES Maximum power consumption 220mW with ports off. Resistance specified maximum under conditions.
ABSOLUTE MAXIMUM RATINGS
voltages referred Parameter Min. Supply voltage input voltage Port voltage 13,14 6-11 Total port output current Address select voltage input offset Charge pump offset Drive output offset Crystal oscillator offset SDA, input voltage Storage temperature Junction temperature 13-14 Value Max. Units
SP5655
Conditions
Port state Port state Port state
PREAMP PRESCALER 15-BIT PROGRAMMABLE DIVIDER PHASE COMP FCOMP DIVIDER 4512/1024
CRYSTAL CHARGE PUMP
LOCK
POWER
15-BIT LATCH DIVIDE RATIO
CHARGE PUMP CONTROL DATA LATCHES CONTROL LOGIC
DRIVE/ VARICAP
TRANSCEIVER
ADDRESS SELECT
3-BIT
LEVEL COMP
6-BIT LATCH PORT INFO
PORT OUTPUT DRIVERS
Fig. Block diagram
SP5655
from 1024, controlled byte (TS0); logic 512, logic 1024. SP5655 differs from SP5055 this respect, only being available SP5055. Note that comparison frequency when 4MHz reference used, divide selected. byte programming data (CP) controls current charge pump circuit, logic ±170µA logic ±50µA, allowing compensation variable tuning slope tuner also enable fast channel changes over full band. When device frequency locked, charge pump current internally ±50µA regardless byte (T0) disables charge pump when logic byte (OS) switches charge pump drive amplifier's output when logic byte (T1) enables various test modes when high. These modes selected bits byte (TS2, TS1, TS0) detailed Table When low, assigned `don't care' condition, selects reference divider ratio previously described. Byte programs output ports logic high impedance output logic impedance (on).
FUNCTIONAL DESCRIPTION
SP5655 programmed from Bus. Data Clock lines respectively, defined format. synthesiser either accept data (write mode) send data (read mode). address byte (R/W) sets device into write mode read mode high. Tables Fig. illustrate format data. device programmed respond several addresses, which enables more than synthesiser system. Table shows address selected applying voltage When device receives correct address byte, pulls line during acknowledge period, during following acknowledge periods after further data bytes programmed. When device programmed into read mode, controller accepting data must pull line during status byte acknowledge periods read another status byte. controller fails pull line during this period, device generates internal STOP condition, which inhibits further reading.
WRITE Mode (Frequency Synthesis)
When device write mode bytes select synthesised frequency, while bytes control output port states, charge pump, reference divider ratio various test modes. Once correct address received acknowledged, first next byte determines whether that byte interpreted byte logic frequency information logic control output port information. When byte received device always expects byte next. Similarly, when byte received device expects byte next. Additional data bytes entered without need readdress device until stop condition recognised. This allows smooth frequency sweep fine tuning purposes. transmission data stopped mid-byte (for example, another device bus) then previously programmed byte maintained. Frequency data from bytes stored 15-bit register used control division ratio 15-bit programmable divider. This preceded divide-by-16 prescaler amplifier give excellent sensitivity local oscillator input, Fig. input impedance shown Fig. programmed frequency calculated multiplying programmed division ratio times comparison frequency FCOMP. When frequency data entered, phase comparator, charge pump varicap drive amplifier, adjusts local oscillator control voltage until output programmable divider frequency phased locked comparison frequency. reference frequency generated external source capacitively coupled into provided onchip crystal controlled oscillator. comparison frequency FCOMP derived from reference frequency reference divider. reference divider division ratio switchable
READ Mode
When device read mode status byte read from device line takes form shown Table (POR) power-on reset indicator logic supply device dropped below 25°C), example, when device initially turned reset when read sequence terminated stop command. When high programmed information lost output ports high impedance. (FL) indicates whether device phase locked, logic present device locked, logic device unlocked. Bits (I2, show status Ports respectively. logic indicates level logic high level. ports used inputs they should programmed high impedance state (logic These inputs will then respond data complying with type voltage levels. Bits (A2, combine give output 5-level ADC. used feed information microprocessor from section receiver, illustrated typical application circuit.
APPLICATION
typical application shown Fig. input/output interface circuits shown Fig. SP5655 function equivalent SP5055 device apart from switchable reference divider, much lower power dissipation, improved sensitivity better performance.
SP5655
Address Programmable divider Programmable divider
Byte Byte Byte Byte Byte
Charge pump test bits port control bits
Table Write data format (MSB transmitted first)
Address Status byte Byte Byte
Table Read data format
Voltage input Address select input voltage Always valid
Table levels
Table Address selection
Operation mode description
Normal operation, test modes disabled, reference divider ratio 1024 Normal operation, test modes disabled, reference divider ratio Charge pump source (down). Status Charge pump sink (up). Status Ports P7set state Port FPD/2; state Port FPD; FCOMP; state
NOTES don't care further details test modes, Table
Table Operation modes
MA1, TS2, TS1,
Acknowledge Variable address bits (see Table Charge Pump current select Test mode selection Charge pump disable Operation mode control bits (see Table Varactor drive Output disable Switch Control output port states Power Reset indicator Phase lock detect flag Digital information from ports respectively 5-level data from (see Table Don't care
Fig. Data formats
SP5655
112V
112V
SIGNAL
SECTION
4MHz CRYSTAL
SATELLITE TUNER
OSCILLATOR OUTPUT
SP5655
CONTROL MICRO
130V
VARICAP INPUT BCW31
180n
Fig. Typical application
INTO
OPERATING WINDOW
1000
2000
2700
3000
3500
FREQUENCY (MHz)
Fig. Typical input sensitivity
SP5655
VREF
CHARGE PUMP
INPUTS DRIVE OUTPUT (O/P DISABLE)
input
Loop amplifier
SCL/SDA CRYSTAL
CRYSTAL
ONLY
Reference oscillator inputs
PORT ONLY PORT PORT
Ports P7-P4
Ports P0-P3
Fig. SP5655 input/output interface circuits
SP5655
S11:ZO NORMALISED
FREQUENCY MARKER STEP 500MHz
Fig. Typical input impedance,
APPLICATION NOTES
application note, AN168, available designing with synthesisers such SP5655. covers aspects such loop filter design, decoupling radiation problems. application note published Zarlink Semiconductor Media Handbook. generic test/demonstration board been produced, which used SP5655. circuit diagram layout board shown Figs. board used following purposes: Measuring sensitivity perfomance Indicating port function Synthesising voltage controlled oscillator (D)Testing external reference sources programming codes relevant these tests given Table
EXTERNAL REFERENCE 220n 4MHz
100n 100n
130V 100n
112V
(NOT FITTED, NOTE)
2N3904 112V RFINPUT
DATA/SDA 100p
SP5655
CLOCK/SCL 100p
2N3906
ENABLE/ADDRESS
NOTE external reference, capacitor must fitted capacitor removed from board.
112V
Fig. Test board circuit
SP5655
BIAS
view (ground plane)
Underside (surface mounted components side)
NOTES CIRCUIT SCHEMATIC SHOWN FIG. SUFACE MOUNT COMPONENTS MOUNTED UNDERSIDE BOARD
Fig. Test board layout
SP5655
TEST MODES
NOTE: When looking FCOMP signals from ports byte should sent twice, first desired reference division ratio then switch chosen test mode. pulses then measured simply connecting oscilloscope counter relevant output test board. code (byte Operation mode description high mode mode
explained functional description, SP5655 programmed into numb test modes. These invoked programming codes into byte those most commonly used being shown Table Other codes will also apply don't care conditions, which assumed Table.
Normal operation, reference divider ratio 1024 Normal operation, reference divider ratio Charge pump source (down), Charge pump sink (up), Port FPD/2 Port FPD, FCOMP Charge pump disable, reference divider ratio Varactor line disable, reference divider ratio Charge pump varactor line disable, reference divider ratio
Table Operation modes
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Bidirectional Controlled Synthesiser DS3743 ISSUE June 1998

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