MPC8260 GPCM Timing Diagram Motorola NetComm, Austin Introdu
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Order Number: MPC8260 1.0, 8/2000
MPC8260 GPCM Timing Diagram
Motorola NetComm, Austin
Introduction
timing diagrams generated based simulations. GPCM allows glueless flexible interface between MPC8260, SRAM, EPROM, FEPROM, device, external peripherals. timing diagrams organized access Local access Early termination Read-Modify-Write Cycle GPCM ARTRY cycle
Access
access partitioned sub-groups: single MPC8260 mode external mode (60x compatible).
This document contains information product under development Motorola. Motorola reserves right change discontinue this product without notice. Motorola, Inc., 2000. rights reserved.
1.1.1 Single MPC8260 Mode single MPC8260 mode entered clearing HardResetConfiguration[EBM] during configuration. Under this mode, MPC8260 only master device system. internal memory controller controls devices external bus. signals used slave device because addresses have memory timing, address/data tenure timing. timing diagrams 32-bit access, while port sizes either Other combinations data size port size similar. Assemble Language Example: SIUMCR[BCTLC] control BCTL0 polarity addis 0x0000 0x0000 addis 0x0f01 0x0000 0x0000(r1) 0xffff_0860 addis 0xffff 0x0860 addis 0x0f01 0x010c 0x0000(r1) 0x0100_0001 addis 0x0100 0x0001 addis 0x0f01 0x0108 0x0000(r1)
address addis r0,0x0100 0x0000 Read from 0x0100_0018 which controlled GPCM 0x0018(r2) Write 0x0100_0018 which controlled GPCM 0x0018(r2)
Notes: Basic steps program GPCM: bus, program SIUMCR[BCTLC] BCTL0 polarity. Program timing(1). Program BRx[MS] select GPCM appropriate bus, BRx[PS] port size, etc. Reference: MPC8260 PowerQUICC IIUser's Manual, P10-53.
1.1.1.1 access single MPC8260 mode, Port Size=64, 32-bit read.
CLKIN
Address
Data
BCTL0
PSDVAL
Fig. GPCM, 60x, Port Size=64, 32-bit read cycle wait When GPCM used peripheral device, strobe signal both read write. BCTL0 used indicate read/write direction. Peripherals drive data asserted. memory device, data output enabled valid after asserted. timing controlled programming ORx.
1.1.1.2 access single MPC8260 mode, Port Size=64, 32-bit write.
CLKIN
Address
Data
BCTL0
PSDVAL
Fig. GPCM, 60x, Port Size=64, 32-bit write, cycle wait Data might valid several cycles earlier than asserted. timing controlled programming ORx.
1.1.1.3 access single MPC8260 mode, Port Size=16, 32-bit read
CLKIN
Address
Data
BCTL0
PSDVAL
Fig. GPCM, 60x, Port Size=16, 32-bit read cycle wait same program except BRx[PS] port size bits. port size limitation, 32-bit access split beat 16-bit access. When GPCM used peripheral device, strobe both read write. BCTL0 used indicate read/write dirction. Peripherals drive data asserted. memory device, data output enabled valid after asserted. timing controlled programming ORx.
1.1.1.4 access single MPC8260 mode, Port Size=16, 32-bit write
CLKIN
Address
Data
BCTL0
PSDVAL
Fig. GPCM, 60x, Port Size=16, 32-bit write cycle wait same program except BRx[PS] port size bits. port size limitation, 32-bit access split beat 16-bit access.
When GPCM used peripheral device, strobe both read write. BCTL0 used indicate read/write dirction. Peripherals drive data asserted. memory device, data output enabled valid after asserted. timing controlled programming ORx.
1.1.2 External Mode (60x compatible) 60x-compatible mode entered setting HardResetConfiguration[EBM] during configuration. Under this mode, lower bits address memory controlled baddr[27:31]. Note that baddr[29:31] muxed with other signals. muxing controlled SIUMCR[L2CPC]. baddr[29:31] function chosen when L2CPC bits configuration word during power programming directly SIUMCR after configuration. Assemble Language Example: Same GPCM single MPC8260 mode.
Note: external mode, signals added better illustrate nature access.
1.1.2.1 access 60x-compatible mode, port size 32-bit read
CLKIN
Address Attr
Data
AACK
PSDAL
BCTL0
BADDR
Fig. GPCM, 60x, Port Size=64, 32-bit read, cycle wait Note: 60x-compatible mode, should used latch address bus.
1.1.2.2 access 60x-compatible mode, port size 32-bit write
CLKIN
Address Attr
Data
AACK
PSDAL
BCTL0
BADDR
Fig. GPCM, 60x, Port Size=64, 32-bit write, cycle wait
1.1.2.3 access 60x-compatible mode, port size 32-bit read
CLKIN
Address Attr
Data
AACK
PSDAL
BCTL0
BADDR
addr
addr
Fig. GPCM, 60x, Port Size=16, 32-bit read, cycle wait
1.1.2.4 access 60x-compatible mode, port size 32-bit write
CLKIN
Address Attr
Data
AACK
PSDAL
BCTL0
BADDR
addr
addr
Fig. GPCM, 60x, Port Size=16, 32-bit write, cycle wait
Local Access
Local access functions same both Single MPC8260 mode 60x-compatible mode. Local signals: read output enable write enable read/write direction: 0-write; 1-read. Local address pins muxed with signals. Local function those pins chosen setting HardResetConfiguration[L2CPC] during configuration programming them after configuration.
1.2.1 Local access, Port Size=32, 32-bit read
CLKIN
L_A[14:31]
LCL_D[0:31]
Fig. GPCM, local bus, Port Size=32, 32-bit read, cycle wait When GPCM used peripheral device, strobe both read write. Data valid after asserted. memory device, data will valid after asserted. timing controlled programming ORx.
1.2.2 Local access, Port Size=32, 32-bit write
CLKIN
L_A[14:29]
LCL_D[0:31]
Fig. 1-10 GPCM, local bus, Port Size=32, 32-bit write, cycle wait Data valid several cycles earlier than asserted. timing controlled programming ORx.
1.2.3 Local access, Port Size=16, 32-bit read
CLKIN
L_A[14:29]
LCL_D[0:31]
Fig. 1-11 GPCM, local bus, Port Size=16, 32-bit read, cycle wait same program except BRx[PS] port size bits. port size limitation, 32-bit access split beat 16-bit access. When GPCM used peripheral device, strobe both read write. used indicate read/write dirction. Data valid after asserted. memory device, data output enabled valid after asserted. timing controlled programming ORx.
1.2.4 Local access, Port Size=16, 32-bit write
CLKIN
L_A[14:29]
LCL_D[0:31]
Fig. 1-12 GPCM, local bus, Port Size=16, 32-bit write, cycle wait same program except BR1[PS] port size bits. port size limitation, 32-bit access split beat 16-bit access. When GPCM used peripheral device, strobe both read write. used indicate read/write dirction. Data valid after asserted. memory device, data output enabled valid after asserted. timing controlled programming ORx.
Early Termination
ORx[SETA] PSDVAL generated memory controller. asserted least clocks earlier before wait state counter expired, cycle will terminate result assertion. Local access terminated LGTA.
1.3.1 GPCM access terminated
CLKIN
Address
Data
PSDVAL
BCTL0
BADDR
addr
addr
Fig. 1-13 GPCM, compatible mode, port Size=16, 32-bit read, cycle wait Notes: port size limitation, 32-bit access split 16-bit access. first access terminated normally internal memory controller with cycle wait. second access terminated earlier result assertion.
1.3.2 GPCM local access terminated LGTA
CLKIN
Address
Data
LGTA
Fig. 1-14 GPCM, local bus, port Size=16, 32-bit read, cycle wait Notes: port size limitation, 32-bit access split 16-bit access. first access terminated normally internal memory controller with cycle wait. second access terminated earlier result LGTA assertion.
Read-Modify-Write Cycle
GPCM programmed read-modify-write parity checking correction checking, every write access memory that less than port size will cause read-modify-write cycle automatically.
Notes: Figure 1-15: 32-bit write 64-bit port trigger cycle
1.4.1 Read-modify-write cycle 60x-compatible mode
CLKIN
Address Attr
Data
AACK
PSDAL
WE[0:7]
BCTL0
BADDR
addr
Fig. 1-15 GPCM, 60x, Port Size=64, 32-bit write, cycle wait
1.4.2 Read-modify-write cycle single MPC8260 mode
CLKIN
Address
Data
PSDAL
WE[0:7]
BCTL0
Fig. 1-16 GPCM, 60x, Port Size=64, 32-bit write, cycle wait Notes: cycle triggered 32-bit write port with size
1.4.3 Read-modify-write cycle local
CLKIN
L_A[14:29]
LCL_D[0:31]
LWE[0:3]
Fig. 1-17 GPCM, local bus, Port Size=32, 32-bit write, cycle wait Notes: BRx[DECC] (RMW parity checking). on;y work 64-bit port, can't used local bus.The cycle triggered 32-bit write port with size interesting note that local bus, port size size write including 32-bit will trigger cycle.
ARTRY cycle
60x-compatible mode, address transfer terminated with requirement retry ARTRY asserted during address tenure through cycle following AACK. assertion causes entire transaction (address data tenure) rerun.
1.5.1 ARTRY cycle 60x-compatible mode, port size 32-bit write
CLKIN
Address Attr
addr
retry addr
Data
AACK ARTRY
PSDAL
BCTL0
Fig. 1-18 GPCM, 60x, Port Size=32, 32-bit write
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MPC8260
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