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18-bit Power Asynchronous Stereo Audio with Integrated Power Amplifier


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STw5094A
18-bit Power Asynchronous Stereo Audio with Integrated Power Amplifiers Voice Codec
FEATURES Complete stereo audio digital analog converters filters 18-bit, with sample-rate conversion Linear phase analog&digital filters load stereo headphones drivers, load mono loudspeaker driver group listening
TFBGA pins) ORDER CODES: STw5094AD/LF, STw5094ADT/LF
Stereo audio features Asynchronous sampling DAC: does require oversampled clock information audio data sampling frequency. Jitter tolerant Multibit modulator with data weighted averaging dynamic range, 0.01% over load performance Support sampling frequency range functions bass-treble-volume controls, deemphasis filter dynamic compression Tones from tone generator injected audio paths
Complete CODEC filter system 14-bit linear 8-bit companded Transmit receive digital band-pass filters Active antialias smoothing filters load earpiece/loudspeaker driver, load auxiliary driver
Voice CODEC features Support sampling rate microphone biasing output Remote control function Three switchable microphone amplifier inputs. 42.5 range programmable gain Transient supression during power power down Internal programmable sidetone Internal ring, tone dtmf generator Programmable buzzer driver
Stereo headphones loudspeaker/earpiece power amplifiers features stereo input radio features: bandwidth stereo headphones outputs. Driving capability: (typ. 0.1% T.H.D) over with range programmable gain Balanced earpiece/ loudspeaker output. Driving capability: (typ. 0.1% T.H.D) over with 30dB range programmable gain Analog stereo input radio with range programmable gain
General features Single supply Extended temperature range operation standby power (typ. 2.7V). operating power audio listening mode (typ.
1.Functionality guaranteed range -40°C +85°C; Timing Electrical Spec. guaranteed range -30°C +85°C.
April 2005
Rev. 1/51
STw5094A
operating power voice codec mode (typ. CMOS compatible digital interfaces Programmable interface compatible control interface Programmable master/slave serial audio data input interface (I2S other formats) Frequency programmable clock output APPLICATIONS CDMA,GSM,DCS1800,PCS1900,JDC digital cellular telephones with radio stereo listening functions Portable devices with stereo digital audio source radio listening function does requires oversampled clock. audio data serial interface master slave, compatible supports other standard serial interface formats. internal converters work with input resolution. stereo headphones drivers also used radio listening auxiliary stereo analog input. loudspeaker driver also used monophonic group listening. STw5094A voice Codec section configured either 14-bit linear 8-bit companded coder. frame voice Codec sample rate either standard value extended one. addition stereo audio Codec/ filter functions, STw5094A includes tone/ ring/ DTMF generator that used both audio listening mode voice Codec mode, sidetone generation, buzzer driver output remote control function tailored handle external on-hook off-hook button. STw5094A Voice Codec fulfills exceeds CCITT recommendations ETSI requirements digital handset terminals. Stereo Audio part fulfills exceeds requirements quality radio quality listening. Main applications include digital mobile phones with added low-power high-quality radio listening features, battery powered equipment that requires Stereo Audio with Headphones drivers. ORDER CODES
Part Number STw5094AD/LF STw5094ADT/LF Description TFBGA Tray TFBGA Tape Reel
GENERAL DESCRIPTION STw5094A power asynchronous stereo audio device with headphones amplifiers high quality radio listening. STw5094A includes also high performance power combined Codec/ filter tailored implement audio front-end functions required voltage power consumption digital cellular terminals with added radio listening. STw5094A registers accessed through I2C-bus compatible interface. STw5094A asynchronous stereo audio section suited MP3, other audio stereo source, listening. supports rate from kHz, tolerate jitter audio data
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STw5094A
TABLE CONTENT
CONNECTIONS (TOP VIEW) FUNCTIONAL BLOCK DIAGRAM SIGNAL DESCRIPTION FUNCTIONAL DESCRIPTION PROGRAMMABLE REGISTERS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS OPERATIVE SUPPLY VOLTAGES TIMING SPECIFICATIONS AMCK timing MCLK AUXCLK timing Audio interface signals timing interface timing control port timing ELECTRICAL CHARACTERISTICS Digital Interfaces (Figure Analog Interfaces ANALOG INPUT/OUTPUT OPERATIVE RANGES Microphone Input Levels Absolute levels MIC1, MIC2, MIC3 Input Levels Absolute levels FML, Power Output Levels Absolute levels LSP-LSN (Differentially measured) Tones Levels VOICE CODEC CHARACTERISTICS VOICE CODEC AMPLITUDE RESPONSE VOICE CODEC AMPLITUDE RESPONSE (continued) VOICE CODEC ENVELOPE DELAY DISTORTION WITH FREQUENCY VOICE CODEC NOISE VOICE CODEC CROSSTALK VOICE CODEC DISTORTION VOICE CODEC DISTORTION STEREO AUDIO CHARACTERISTICS POWER DISSIPATION TFBGA PACKAGE OUTLINE REVISION HISTORY
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STw5094A
CONNECTIONS (TOP VIEW)
MIC2N
MIC2P REMOUT MCLK
MIC1P MIC1N MBIAS
MIC3 VCCA CAP2 REMIN AUXCLK LRCK
GNDA GNDCM VCCIO
GNDP VCMHP AMCK
VCCP
TFBGA 6x6x1.2 Pin)
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VCCA
GNDA
VCCP
GNDP
GNDCM
VCCIO
MBIAS
Mic. Bias
Power
Reset 0:22.5 Control Logic Registers
MIC1P
MIC1N
MIC2P Voice PreAmp -12:-27 Channel Filter Anti Alias Filter
MIC2N
0/20dB Gain.
AUXCLK
exact hardware implementation
MIC3 0:-27 SideTone Gain MCLK
FUNCTIONAL BLOCK DIAGRAM
Generator
Buzzer
Tone Tone Att.
CAP2
+18:-20 Step
PreAmp Bandgap Channel Filter Remocon
+18:-20 Step
REMIN REMOUT/
PreAmp
+6:-24
Digital
Diff Driver Mode Analog Filter
Transient
AMCK
Suppression Filter
Voice Mode
0:-40
Transient
Left Driver
Modulator
Master Mode
Suppression Filter
Interpolation
Audio Mode Filter
Dyn. Compress., Deemph.,Gain, Tone Controls
LRCK
VCMHP
Driver Mode Analog Filter
Generator Voice Mode
Audio
0:-40
Transient
Right Driver
Modulator
Suppression Filter
Interpolation
Audio Mode Filter
Dyn. Compress., Deemph., Gain, Tone Controls
STw5094A
Note: This diagram shows functionality device some register bits does necessarily reflect
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STw5094A
SIGNAL DESCRIPTION
Type definitions: Analog input, Analog Output, Digital Input, Digital output, Digital Output Tristate, DIOD Digital Input Output Open Drain, DIOT Digital Input Output Tristate, Power Supply Ground.
Name MIC1P MIC1N MIC2P MIC2N Type Description Positive high impedance input transmit preamplifier microphone connection. Negative high impedance input transmit preamplifier microphone connection. Positive high impedance input transmit preamplifier microphone connection. Negative high impedance input transmit preamplifier microphone connection. High impedance single ended input transmit preamplifier microphone connection. MIC3 used monophonic input path place Microphone Biasing Switch. Auxiliary analog audio Left channel input. Auxiliary analog audio Right channel input. Receive analog amplifier complementary outputs. This differential output drive 50nF (with series resistor) directly earpiece transductor signal this output Receive Speech signal from MIC3) input, Internal Tone Generator Sidetone signal, Audio Left channel, MIC3) input Internal Tone Generator, come from MIC3) input. Audio headphone amplifier Left channel output. This output drive 50nF (with series resistor) directly earpiece transductor signal this output Audio Left channel, MIC3) input Internal Tone Generator, Receive Speech signal from MIC3) input, Internal Tone Generator, Sidetone signal, come from MIC3) input. Audio headphone amplifier Right channel output. This output drive 50nF (with series resistor) directly earpiece transductor signal this output Audio Right channel, MIC3) input Internal Tone Generator, Receive Speech signal from MIC3) input, Internal Tone Generator, Sidetone signal, come from MIC3) input. Remocon function digital output Oversampled Clock out. Remocon function input. high level this detected pressed key, while level detected pressed key. Pulse width modulated buzzer driver output. I2C-bus interface serial clock input. asynchronous with other system clocks. I2C-bus interface serial data input-output. Left Right clock Frame Sync Audio interface input Slave mode, output Master mode. Audio interface Serial Clock input Slave mode, output Master mode. Audio interface Data input. Master Clock Input Audio Mode. also used Master Clock Tone Only Modes.
MIC3 MBIAS
F2,F1
LSP,
REMOUT/OCK REMIN LRCK AMCK
DIOD DIOT DIOT
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STw5094A
Name Type Description Transmit Data output: Data shifted this during assigned transmit time slots. Elsewhere output high impedance state. delayed non-delayed normal frame sync modes, voice data byte shifted from tristate output MCLK frequency rising edge MCLK, while non-delayed reverse frame sync mode voice data shifted falling edge MCLK. Receive data input: Data shifted during assigned Received time slots delayed non-delayed normal frame sync modes voice data byte shifted MCLK frequency falling edges MCLK, while non-delayed reverse frame sync mode voice data byte shifted rising edge MCLK. Frame Sync input Voice Mode: This signal 16kHz clock which defines start transmit receive frames. three formats used this signal: delayed normal mode, delayed mode, delayed reverse mode. Master Clock Input Voice Mode. also used Master Clock Tone Only Modes. allowed clock frequencies kHz, 1.536 MHz, 2.048 2.56 MHz. MCLK Voice Data Clock. Auxiliary Clock Input. used Master Clock Tone Only Modes. Allowed clock frequencies 512kHz, 1.536MHz, 2.048MHz 2.56MHz. Driver Output. used common mode node outputs. capacitor must connected between this node Ground. Power supply input analog section. VCCA directly connected together cost applications. Analog Ground: analog signals referenced this pin. GNDA connected together cost applications. Power supply input output drivers. Power ground. Output drivers referenced this pin. GNDP GNDA must connected together. Analog Ground connection. GNDCM connected GNDA. Power supply input digital section. Ground digital section Power supply Input Digital pins.
MCLK
AUXCLK
VCMHP CAP2 VCCA GNDA VCCP GNDP GNDCM VCCIO
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STw5094A
FUNCTIONAL DESCRIPTION DEVICE MODES
STw5094A work different modes, selected bits Control Register (CR21). Depending mode different data interfaces, clock inputs, internal blocks selected. built-in power consumption management function keeps power down blocks that needed selected operating mode. modes Output Drivers activated different combinations with bits PLS, PHL, case stereo input driver selected Left channel sent this driver, while case voice input drivers selected same signal sent both drivers). Audio Mode Audio mode path from Audio interface output drivers active allow Stereo Audio function. active while inactive. master clock device AMCK. AMCK frequency fixed, independent from audio samples data rate (LRCK frequency). AMCK source fixed system clock whose nominal frequency value lies range 9.5MHz 28MHz (the full range covered three sub-ranges, selected bits AMCK_DIV CR18). rate audio data (LRCK frequency) value range 8kHz 48kHz (non standard values allowed) does need specified. Since AMCK clock used directly Converters section, jitter spectral properties must adequate desired Audio quality. Audio Mode there additional functions audio signal processing: digital volume control with range implemented (bits CR20). digital volume used addition with analog gain regulation 94dB range volume obtained. Bass controls regulated -12.5dB +12.5dB range step (bits BASS CR19). Treble controls regulated -6dB +6dB range step (bits TREBLE CR19). 50µs 15µs de-emphasis filter activated instead treble controls (bits TREBLE CR19). Note: time constants referred 44.1kHz dynamic range compressor implemented (bit CR20).
Note:The de-emphasis filter Bass/Treble controls freq. responses scale with input sampling rate.
tone/ ring/ DTMF generator activated needed. audio mode frequency values tones function AMCK frequency value explained Table Voice Mode Voice mode path from microphone input path from output drivers active allow CODEC function. active while inactive. master clock device MCLK, frequency clock selected with bits CR0. tone/ ring/ DTMF generator activated needed. Tone Only Mode tone only mode path from tone generator output drivers buzzer active allow tones ringer listening only. Both inactive, Audio Voice converters functions. master clock device selected AUXCLK, MCLK AMCK (bits CR21). Mode mode path from analog inputs output Drivers active allow Stereo Radio listening. Both inactive, Audio Voice converters functions. master clock device selected AUXCLK, MCLK AMCK (bits CR21). Tone Ring DTMF generator power down.
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STw5094A
DEVICE OPERATION
Power Initialization, Software Reset When power first applied, "power reset" circuitry initializes STw5094A puts into power down state. Registers initialized indicated Control Register description section. functions disabled. registers also initialized default state writing (software reset) CR21. Power down control recommended that programmable functions (excluding gain controls, bass-treble controls dynamic compression function) while device powered down. Power state control then included last programming instruction (the power located last address register (CR21) that multi-byte mode control interface easily used program required functions before power up). When power command given, circuits needed selected mode activated Voice mode output will remain high impedance state until second pulse after power arrives). built-in power consumption management function keeps power down blocks that needed selected operating mode. Power down state Following period activity, power down state reentered writing CR21. Control Registers remain their current state changed control interface. addition power down instruction, detection absence current Master Clock transition detected) automatically puts device power down state without setting transitions master clock detected device again power Voice Transmit section This section active Voice Mode. Voice Transmit analog preamplifier gain designed stages enable gains 42.5 Stage provides selectable gain CR4. Stage programmable gain amplifier which provides from 22.5 additional gain 1.5dB step. programmed with bits CR4. Three microphone inputs provided, differential (MIC1P MIC2P single ended (MIC3). They also used connect auxiliary audio circuit. microphone input Transmit Mute selected with bits CR4. Mute case, analog transmit signal grounded. separate MBIAS output used bias microphone (bit CR4). active anti-alias filter then precedes single analog digital converter that followed order digital channel filter. channel filter band-pass frequency 8kHz low-pass frequency 16kHz (bit CR0). precision chip voltage reference ensures accurate highly stable transmission levels. offset voltage arising analog blocks cancelled internal autozero circuit. Voice data sent serially sent output. Voice Receive section This section active Voice Mode. Voice Data coming from sent order digital channel filter. filter selected band-pass low-pass, with CR5, when frequency 8kHz, while always low-pass when frequency 16kHz. filter followed digital analog converter order switched-capacitor reconstruction filter. Sidetone summed received signal (bit CR5) amplitude programmed with bits CR5. Stereo Audio section This section active Audio Mode. Left Right Audio samples coming from Audio Interface interpolated with filter synchronized AMCK clock order feed oversampled multi-bit modulator, digital analog converter followed order switched-capacitor reconstruction filter.
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STw5094A
Input Path device provided with stereo mono single ended analog inputs, designed amplify analog signals from decoder they considered generic analog inputs. stereo analog inputs pins, alternatively MIC3 mono input (sent left right channels). selection between FML-FMR MIC3 done with CR20. analog inputs connected programmable gain stage that amplify signals range -20dB +18dB steps. gain control independent Left Right channel selected with bits FMLA CR10 (Left) bits FMRA CR11 (Right). There ways connect inputs output drivers. first select Mode (bits CR21). second activate Audio Voice Tone Only modes CR20. last case signal coming from inputs will summed Audio Voice Tones signals respectively. Output Drivers section There Analog Output Drivers. differential driver delivers 300mW typical power with 0.1% T.H.D. (250mW minimum undistorted) earpiece loudspeaker (piezoceramic loads 50nF also driven with series resistor), 30dB range gain control (bits CR7). single ended drivers (HPL HPR) deliver 40mW typical power with 0.1% T.H.D. (30mW minimum undistorted) stereo headphones, they have 40dB range gain control (CR8 HPR). possible drivers power-down power-up programming bits PLS, PHL, CR6. These settings dependent from selected operative Mode. common mode voltage drivers selected with bits CR18 range 1.2V 1.65V with 150mV steps. This feature useful common mode voltage VCCP/2 therefore extend output range increase output power. enabled together Voice Mode Tone Only Mode same signal sent both Drivers. active Drivers muted (keeping them power-up state) using CR6. power-up after change bits outputs muted avoid unwanted noise. transient suppression filter used avoid clicks when gain value changed. Common Mode Driver common mode voltage driver (VCMHP pin) simplifies application stereo headset connection saving decoupling capacitors series with HPR. loads single ended drivers connected side respectively, other VCMHP, that same common mode voltage. driver enabled with CR18. output voltage VCMHP selected with bits CR18 range 1.2V 1.65V with 150mV steps. 2.10 Tone Generator Tone Generator activated (writing CR12) STw5094A operating modes except mode. Voice Audio modes tones summed signal. possible generate summed waveforms (either sinusoidal square wave), their frequencies CR13 first (f1) CR14 second (f2) accordingly values listed Table active master clock MCLK AUXCLK. active master clock AMCK frequency values specified Table must multiplied factor kfAMCK that depends AMCK frequency value. amplitude generated waveform regulated CR12 over 33dB range. When both selected amplitude lowered respectively with respect amplitude single waveform. this amplitude summed waveforms does overload there difference between amplitude required DTMF generation. Tone Generator output sent Voice Transmit section Voice Mode), Power amplifiers, possibly mixed with audio voice, modes except mode) buzzer output modes except mode).
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STw5094A
2.11 Buzzer Output output intended drive Buzzer, external BJT, with squarewave pulse width modulated (PWM) signal. frequency signal stored CR13 (see Tone Generator section Table frequency values). some applications also possible multiply this signal with squarewave signal having frequency stored CR14. duty cycle buzzer output varied CR15 order change buzzer volume. Maximum load 50pF 2.12 Voice Data Interface (PCM used exchange Voice data both direction, programmed linear format data companded A-law µ-law format (see Fig.1, Frame Sync input determines beginning frame. have duration from single cycle MCLK squarewave. Three different relationships established between Frame Sync input first time slot frame setting bits CR1. delayed normal reverse data mode (long frame timing) first time slot starts rising edge delayed data mode (short frame sync timing) input must high least half cycle MCLK before frame start. When linear code selected (bit CR0) transmitted received first, word length bit. When companded code selected (bit CR0) time slot assignment used timing modes (bit CR1), that allows connection voice data channels. data formats available: Format time slot corresponds MCLK cycles that immediately follow rising edge while time slot corresponds MCLK cycles that immediately follow time slot Format time slot identical Format while time slot appears slots after time slot This bits space left available insertion channel data. Data format selected CR0. enables disables data transfer Outside selected time slot high impedance condition. During selected time slot output input synchronized follow: delayed non-delayed modes selected transmit voice data sent output rising edges MCLK receive voice data read input falling edges MCLK. non-delayed reverse mode selected transmit voice data register sent output falling edges MCLK receive voice data read input rising edges MCLK. When 16kHz Frame Sync frequency selected (bit CR0) filters both low-pass their cutoff frequencies doubled. possible access channel data when companded A-law µ-law formats used (bits CR1). byte written into CR3A will sent output place transmit channel data. byte written CR2A will sent receive path. current byte received input read CR2A. 2.13 Audio Data Interface used receive Stereo Audio data. pins related are: frame synchronism Left/Right indicator LRCK, serial clock SCK, serial data input SDI. LRCK input output depending configured Slave Master mode. interface configured different modes programming bits SPIM, DSPM CR17. each mode different parameters (word length, signal polarity etc.) writing CR16. selects Master Slave. When MSM=0 Slave: serial clock frame sync LRCK input device. When MSM=1 Master: LRCK generated inside device. frequency LRCK programmed CR2B CR3B while shape frequency change automatically with selected mode (see paragraph below). Master mode available when configured SPI-mode (SPIM=1) regardless value MSM. possible mode modes are: I2S-Mode Slave (SPIM=0, MSM=0 DSPM=0) this mode compatible (see Fig. clock left/right indicator LRCK signals input device. must have periods channel case 16bit data word periods channel case 18bit 24bit data word. either continuous clock sequence bursts.
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STw5094A
I2S-Mode Master (SPIM=0, MSM=1 DSPM=0) this mode functionally equivalent I2S-mode Slave (see Fig. clock left/right indicator LRCK signals generated device. generated with periods channel case 16bit data word periods channel case 18bit 24bit data word DSP-Mode Slave (SPIM=0, MSM=0 DSPM=1) this mode starting from frame sync pulse LRCK receives Left Right data after other (see Fig. 11). free running clock: between successive frame sync pulse there number periods from minimum necessary transfer data bits max. frequency limit specified SCK. DSPmode suited interface with Master Multi-Byte Serial Interface. DSP-Mode Master (SPIM=0, MSM=1 DSPM=1) this mode functionally equivalent DSP-mode Slave LRCK signals generated device (see Fig. 12). generated with periods frame sync. case 16bit data word periods frame sync. case 18bit 24bit data word. DSP-mode Master suited interface with Slave Multi-Byte Serial Interface. SPI-Mode (SPIM=1 DSPM=0) this mode Left Right data received with separate data burst. Every burst identified with level LRCK signal (see Fig. 13). There timing difference between Left Right data burst: channels identified fact that first burst after Audio mode power-up identifies Left channel data second Right channel data then Left Right data repeat after other. must have periods channel case 16bit data word periods channel case 18bit 24bit data word. SPI-mode only Slave: when SPIM=1 values written disregarded while DSPM must some above listed modes combinations bits CR16 available meaningful: DSP-Mode always received first (bit ORD=0), data word justification LRCK polarity have meaning. SPI-mode data word must always left-justified (bit DIF=0) non-delayed (bit FOR=1) LRCK polarity must always Left=0 (INV=0). audio data sample rate (LRCK frequency) value range 8kHz 48kHz. Left channel data always received first. first Data frames after power discarded while interpolation filters data memory cleared. 2.14 LRCK generation Master Mode Setting MSM=1 SPIM=0 CR17 enables internal generation frame synchronism clock LRCK serial clock SCK. These clocks obtained variable division from AMCK system clock. Given AMCK frequency (fAMCK), desired sample rate frequency (fLRCK) obtained writing CR2B least significant byte CR3B most significant byte the16bit integer result calculated with following formula:
fAMCK))
precision obtained fLRCK always better than ±1.7Hz. shape LRCK waveform number periods each LRCK period automatically depending values DSPM CR17 CR16 content (see Fig. 7,8,10 12). Since CR2B CR3B overlaid registers, order write division factor CR2B CR3B master mode must selected advance setting MSM=1. NOTE: LRCK part Master mode generation also used Frame Sync Master clock Voice Mode connecting them MCLK this case fixed clock AMCK needed).
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STw5094A
RCK=44.1kHz,
Example: master clock frequency fAMCK=12MHz, required sampling frequency value
12000000)) 30828
30828 decimal corresponds 786C CR2B CR3B must loaded with respectively, frequency LRCK will then
fLRCK 44099.8
2.15 output clock generation Setting SPIM CR17 enables internal generation clock REMOUT OCK. clock output used master clock digital device that provides Audio Data STw5094A. This function compatible with both Master mode Slave mode used Normal mode mode while cannot used mode. activated also Voice mode (provided AMCK clock available). Because clock obtained variable division from master clock AMCK, cannot have frequency higher than AMCK master clock frequency. When frequency comprised between AMCK frequency half AMCK frequency obtained removing pulses, evenly spaced possible, from AMCK thus reducing frequency programmed value. When frequency lower than half AMCK frequency obtained division rising edge AMCK. polarity inverted setting ROI=1 CR17. Master Mode: when used Master Mode frequency times sampling frequency programmed CR2B CR3B using formula described Section 2.14 fOCK fLRCK). Slave Mode: when used Slave Mode frequency value (lower than AMCK frequency) related incoming LRCK frequency, then limited oversampling. this case obtain desired frequency following formula used:
fAMCK))
where fOCK lower than fAMCK (this corresponds fact that cannot greater than 7FFF hex). Example: master clock frequency fAMCK=19.2MHz, oversampling factor sampling rate 44.1 kHz, then required frequency fOCK 44.1 16934400 value
19200000)) 28901
28901 decimal corresponds 70E5 CR2B CR3B must loaded with respectively, frequency will then
fOCK 16934179.7 44099.4
output clock function alternative Remocon function because both share same output pin: setting will disable Remocon function REMOUT REMOCON output status will still available reading CR17 (see paragraph II.18 more details REMOCON function). Since CR2B CR3B overlaid registers, order write division factor CR2B CR3B, output clock function must selected advance setting
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STw5094A
2.16 Control Interface (I2C used program device writing reading control registers (see Fig. 15). interface compatible, being STw5094A Slave device. bidirectional open-drain data input clock pin. Device Address hex. writing hex. reading. interface internal address register that keeps current address control register read written. each write access interface address register loaded with data register address field. value address register increased after each data byte read write. possible access interface modes: single-byte mode which address data single register specified, multi-byte mode which address first register written read specified following bytes exchanged data successive address registers starting from specified multi-byte mode internal address counter restart from register after last register 21). Using multi-byte mode possible write read registers with single access device bus. Control interface used both power-up power-down state. 2.17 Master clock mode tone only modes mode Tone Only mode Master Clock device selected AUXCLK, MCLK AMCK writing bits CR21. Auxiliary clock AUXCLK used when Audio mode clock AMCK Voice mode clock MCLK available. AUXCLK MCLK frequency selection done with bits CR0. 2.18 REMOCON function REMOCON (Remote Control) function used detect status headset button. REMOCON function enabled setting CR17. enabled, this function active also when STw5094A power-down state. REMOUT/OCK output REMOCON function only CR17 (Section 2.15). High level REMIN input detected pressed button, while level detected pressed button. "Pressed Button" information treated ways depending CR17: (Transparent mode) information REMIN seen REMOUT/OCK after debounce time 50ms maximum; (Latched Mode) information stored CR17 seen REMOUT/OCK. after debounce time 50ms maximum when level REMIN detected. reset with power initialization also reset writing RDL. REMOUT/OCK output polarity inverted setting CR17: pressed button information presented REMOUT/OCK output logic polarity inverted.
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STw5094A
PROGRAMMABLE REGISTERS
Control Register Functions (Address: 0x00)
Function F(1:0) MCLK AUXCLK MCLK AUXCLK 1.536 MCLK AUXCLK 2.048 MCLK AUXCLK 2.560 Voice Data Voice Data Linear code Companded code Linear Code
(1): significant companded mode only state power initialization
Companded Code µ-law: CCITT D3-D4 µ-law: Bare Coding A-law including even inversion A-law: Bare Coding
2-complement sign magnitude 2-complement 1-complement consecutive separated bits time-slot bits time-slot
Control Register Functions (Address: 0x01)
Function DM(1:0)
significant companded mode only state power initialization reserved: write
delayed data timing non-delayed normal data timing non-delayed reverse data timing
connected path CR2A connected path path connected CR3A connected disabled enabled channel selected channel selected
Normal operation Digital Loopback (Data from sent with frame delay)
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STw5094A
Control Register CR2A Functions (Address: 0x02) (Active when MSM=0 OCE=0 CR17)
Function DRD(7:0)
Data sent Receive path Data received from input
Significant companded mode only. CR2A available only Master mode CR17 enabled (MSM=0 OCE=0).
Control Register CR2B Functions (Address: 0x02) (Active when MSM=1 OCE=1 CR17)
Function DIVL(7:0) Least significant byte frequency division factor LRCK,SCK generation.
CR2B available only Master mode CR17 enabled (MSM=1 OCE=1, SPIM=0).
Control Registers CR3A Functions (Address: 0x03) (Active when MSM=0 OCE=0 CR17)
Function DXD(7:0) data transmitted
Significant companded mode only. CR3A available only Master mode CR17 enabled (MSM=0 OCE=0).
Control Registers CR3B Functions (Address: 0x03) (Active when MSM=1 OCE=1 CR17)
Function DIVH(7:0) Most significant byte frequency division factor LRCK, generation.
CR3B available only Master mode CR17 enabled (MSM=1 OCE=1, SPIM=0).
Control Register Functions (Address: 0x04)
Function MS(1:0)
state power initialization
TXA(3:0) Transmit input muted MIC1 Selected MIC2 Selected MIC3 Selected MBIAS output disabled MBIAS output enabled 20dB preamplifier gain preamplifier gain Transmit Amplifier gain Transmit Amplifier gain Transmit Amplifier step 22.5 Transmit Amplifier gain
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STw5094A
Control Register Functions (Address: 0x05)
Voice Codec Receive High Pass filter enabled Voice Codec Receive High Pass filter disabled Voice Codec internal sidetone disabled Voice Codec internal sidetone enabled -12.5 Sidetone gain -13.5 Sidetone gain Sidetone gain step -27.5 Sidetone gain Function SA(3:0)
(1): Valid only when Voice Data Fs=8kHz (VFS=0). When Voice data Fs=16kHz (VFS=1) High Pass Filter always disabled. state power initialization reserved: write
Control Register Functions (Address: 0x06)
state power initialization reserved: write
Function
active output Drivers operative active output Drivers muted output Driver power down output Driver power output Driver power down output Driver power output Driver power down output Driver power Audio Voice Codec Signal disabled Audio Voice Codec Signal enabled. Ring Tone disabled Ring Tone enabled.
Control Register Functions (Address: 0x07)
Function LSA(3:0)
state power initialization reserved: write
Earpiece Earpiece Earpiece Earpiece Earpiece Earpiece
Loudspeaker Amplifier gain Loudspeaker Amplifier gain Loudspeaker Amplifier gain Loudspeaker Amplifier gain Loudspeaker Amplifier gain step Loudspeaker Amplifier gain
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STw5094A
Control Register Functions (Address: 0x08)
HPLA(4:0)
state power initialization reserved: write
Function
Headphones amplifier (Left channel) gain Headphones amplifier (Left channel) gain Headphones amplifier (Left channel) gain Headphones amplifier (Left channel) gain Headphones amplifier (Left channel) gain step Headphones amplifier (Left channel) gain
Control Register Functions (Address: 0x09)
HPRA(4:0)
state power initialization reserved: write
Function
Headphones amplifier (Right channel) gain Headphones amplifier (Right channel) gain Headphones amplifier (Right channel) gain Headphones amplifier (Right channel) gain Headphones amplifier (Right channel) gain step Headphones amplifier (Right channel) gain
Control Register CR10 Functions (Address: 0x0A)
FMLA(4:0)
state power initialization reserved: write
Function
Preamplifier (Left channel) gain Preamplifier (Left channel) gain Preamplifier (Left channel) gain step Preamplifier (Left channel) gain Preamplifier (Left channel) gain step Preamplifier (Left channel) gain
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STw5094A
Control Register CR11 Functions (Address: 0x0B)
FMRA(4:0)
state power initialization reserved: write
Function
Preamplifier (Right channel) gain Preamplifier (Right channel) gain Preamplifier (Right channel) gain step Preamplifier (Right channel) gain Preamplifier (Right channel) gain step Preamplifier (Right channel) gain
Control Register CR12 Functions (Address: 0x0C)
Tone gain Tone gain Tone gain step Tone gain
state power initialization reserved write
Function
TONEG(3:0)
FSEL(1:0)
muted selected selected summed mode Squarewave signal selected Sinewave signal selected Tone Ring Generator connected Transmit path Tone Ring Generator connected Transmit path
Control Register CR13 Functions (Address: 0x0D)
Function F1(7:0) Binary equivalent decimal number used calculate Table
Control Register CR14 Functions (Address: 0x0E)
Function F2(7:0) Binary equivalent decimal number used calculate Table
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Control Register CR15 Functions (Address: 0x0F)
Function BZ(5:0) Buzzer output disabled (set Buzzer output enabled Duty Cycle intended relative width logic Duty cycle intended relative width logic
Binary equivalent decimal number used calculate duty cycle, using formula: Duty Cycle BZ(5:0) 0.78125%
state power initialization
Control Register CR16 Functions (Address: 0x10)
Function PREC(1:0) AMCK Inverted AMCK Inverted Audio data order, received first (I2S) Audio data order, received first
Audio data alignment, word left justified (I2S)(1) Audio data alignment, word right justified
LRCK polarity, when LRCK=0 Left data received (I2S) LRCK polarity, when LRCK=1 Left data received
Audio format, format (first delayed) Audio format, delayed formats
polarity, LRCK sampled rising edge (I2S) polarity, LRCK sampled falling edge
Audio data width clocks frame) Audio data width clocks frame) Audio data width clocks frame) Audio data width clocks frame)
significant word mode only Left Channel data always received first. First delay, word mode, applied only word left justified. state power initialization
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Control Register CR17 Functions (Address: 0x11)
Function
significant SPIM=0 (bit CR17) state power initialization reserved write
SPIM DSPM Remocon Function disabled Remocon Function enabled Remocon output transparent mode Remocon output latched mode REMOUT/OCK output inverted REMOUT/OCK output inverted Remocon detection latch reset Remocon detection latch internal logic
REMOUT/OCK used REMOCON function REMOUT/OCK used Oversampled Clock function
Audio interface works mode Audio interface works slave mode Audio interface works Slave mode Audio interface works Master mode Audio interface works mode Audio interface works mode
Control Register CR18 Functions (Address: 0x12)
state power initialization reserved write
Function
AMCK_DIV VCMHP output voltage 1.20 VCMHP output voltage 1.35 VCMHP output voltage 1.50 VCMHP output voltage 1.65 VCMHP output Disabled VCMHP output Enabled
9.5MHz -14MHz 14MHz -19MHz 19MHz -28MHz
AMCK clock-range AMCK clock-range AMCK clock-range
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Control Register CR19 Functions (Address: 0x13)
TREBLE(2:0)
state power initialization reserved write
Function
BASS(3:0)
+6dB Treble Gain +4dB Treble Gain +2dB Treble Gain Treble Gain -2dB Treble Gain -4dB Treble Gain -6dB Treble Gain De-emphasis filter enabled +12.5dB +10.0dB +7.5dB +5.0dB +2.5dB -2.5dB -5.0dB -7.5dB -10.0dB -12.5dB Bass Gain Bass Gain Bass Gain Bass Gain Bass Gain Bass Gain Bass Gain Bass Gain Bass Gain Bass Gain Bass Gain
Control Register CR20 Functions (Address: 0x14)
(4:0)
function disabled function disabled
state power initialization
Function
input from FML, input from MIC3 Left Right) Audio Dynamic compressor Audio Dynamic compressor Audio Attenuation Audio Attenuation Audio Attenuation Audio Attenuation Audio Attenuation Audio Attenuation Audio Attenuation Audio Attenuation Audio Attenuation Audio Attenuation Audio Attenuation Audio Attenuation Audio Attenuation Audio Attenuation Audio Attenuation Audio Attenuation Audio Attenuation Audio Attenuation Audio Attenuation Audio Attenuation
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Control Register CR21 Functions (Address: 0x15)
Function MD(1:0)
CFM(1:0)
Voice Mode Audio Mode. Tone Only Mode. Mode.
Master Clock Input Tone Only Mode AUXCLK* Master Clock Input Tone Only Mode MCLK Master Clock Input Tone Only Mode AMCK
Normal Operation Software Reset, registers their default. Device Power Down Device Power
state power initialization reserved write
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Note: Audio mode when AMCK Master Clock selected, true frequency value obtained multiplying value table (F1/ Tone Frequency) following constant: k=(fAMCK/fDIV) where fAMCK frequency AMCK expressed fDIV= where AMCK_DIV content CR18, bits1-0.
Table Tone generator frequency versus CR13 CR14 register corresondence voice mode tone mode only (when master clock AUXCLK MCLK)
CR13/14 Value (dec.)
F1/F2 Tone Frequency (Hz)
11.7 15.6 19.5 23.4 27.3 31.2 35.2 39.1 43.0 46.9 50.8 54.7 58.6 62.5 66.4 70.3 74.2 78.1 82.0 85.9 89.8 93.8 97.7 101.6 105.5 109.4 113.3 117.2 121.1 125.0 128.9 132.8 136.7 140.6 144.5 148.4 152.3 156.2 160.2 164.1 168.0 171.9 175.8 179.7 183.6 187.5 191.4 195.3 199.2 203.1 207.0 210.9 214.8 218.8 222.7 226.6 230.5 234.4 238.3 242.2 246.1
CR13/14 Value (dec.)
F1/F2 Tone Frequency (Hz)
250.0 257.8 265.6 273.4 281.2 289.1 296.9 304.7 312.5 320.3 328.1 335.9 343.8 351.6 359.4 367.2 375.0 382.8 390.6 398.4 406.2 414.1 421.9 429.7 437.5 445.3 453.1 460.9 468.8 476.6 484.4 492.2 500.0 507.8 515.6 523.4 531.2 539.1 546.9 554.7 562.5 570.3 578.1 585.9 593.8 601.6 609.4 617.2 625.0 632.8 640.6 648.4 656.2 664.1 671.9 679.7 687.5 695.3 703.1 710.9 718.8 726.6 734.4 742.2
CR13/14 Value (dec.)
F1/F2 Tone Frequency (Hz)
750.0 765.6 781.2 796.9 812.5 828.1 843.8 859.4 875.0 890.6 906.2 921.9 937.5 953.1 968.8 984.4 1000.0 1015.6 1031.2 1046.9 1062.5 1078.1 1093.8 1109.4 1125.0 1140.6 1156.2 1171.9 1187.5 1203.1 1218.8 1234.4 1250.0 1265.6 1281.2 1296.9 1312.5 1328.1 1343.8 1359.4 1375.0 1390.6 1406.2 1421.9 1437.5 1453.1 1468.8 1484.4 1500.0 1515.6 1531.2 1546.9 1562.5 1578.1 1593.8 1609.4 1625.0 1640.6 1656.2 1671.9 1687.5 1703.1 1718.8 1734.4
CR13/14 Value (dec.)
F1/F2 Tone Frequency (Hz)
1750.0 1781.2 1812.5 1843.8 1875.0 1906.2 1937.5 1968.8 2000.0 2031.2 2062.5 2093.8 2125.0 2156.2 2187.5 2218.8 2250.0 2281.2 2312.5 2343.8 2375.0 2406.2 2437.5 2468.8 2500.0 2531.2 2562.5 2593.8 2625.0 2656.2 2687.5 2718.8 2750.0 2781.2 2812.5 2843.8 2875.0 2906.2 2937.5 2968.8 3000.0 3031.2 3062.5 3093.8 3125.0 3156.2 3187.5 3218.8 3250.0 3281.2 3312.5 3343.8 3375.0 3406.2 3437.5 3468.8 3500.0 3531.2 3562.5 3593.8 3625.0 3656.2 3687.5 3718.8
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TIMING DIAGRAMS
Figure Voice interface (PCM I/F) delayed data timing mode1
tSFM tWMH
MCLK
tHMF
tHMF
tWLM
tDFD tDMD tDMZ
tSDM
tHMD
Note: case companded code timing applied bits instead bits.
Figure Voice interface (PCM I/F) delayed data timing mode1
tSFM
tWMH
MCLK
tSFM tHMF
tWLM
tDMD
tDMZ
tSDM
tHMD
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Figure Voice interface (PCM I/F) delayed reverse data timing mode
tSFMR tWMH
MCLK
tHMFR
tHMFR
tWLM
tDFD tDMDR tDMZR
tSDM
tHMD
Note: case companded code timing applied bits instead bits.
Figure AMCK timing
tPAMCK
AMCK
tHAMCK tLAMCK
Figure Audio interface I/F) timing: slave mode
tPLRCK
LRCK
tD1SCK tPSCK1 tD2SCK tHSCK
When SCL=0
tLSCK
When SCL=1
tSSDI tHSDI
bit2 CR16
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Figure Audio interface I/F) timing: slave mode
tPLRCK
LRCK
tSLR tHLR tHSCK
When SCL=0
tPSCK2 tLSCK
When SCL=1
tSSDI tHSDI
bit2 CR16
Figure Audio interface I/F) timing: master mode
tPLRCK
LRCK
tDLR
tDLR
When SCL=0
When SCL=1
tSSDI tHSDI
bit2 CR16
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Figure Audio interface I/F) timing: master mode
tPLRCK
LRCK
tDLR tDLR
When SCL=0
When SCL=1
tSSDI tHSDI
bit2 CR16
Figure Audio interface I/F) timing: SPI-mode (slave only)
tPLRCK
LRCK
tD3SCK tPSCK1
When SCL=0
tHSCK
When SCL=1
tSSDI tHSDI tLSCK
bit2 CR16
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Figure Audio interface I/F) formats master slave modes
Format (delayed), Data word bit, first (default)
LRCK
Left channel Right channel
Non-delayed Format, polarity inverted, Data word bit, first
LRCK
Left channel Right channel
Format (delayed), Data word bit, Left justified, first
LRCK
Left channel Right channel
Non-delayed Format, Data word bit, Left justified, first, LRCK polarity inverted
LRCK
Left channel Right channel
Data word bit, Right justified, first
LRCK
Left channel Right channel
other possible formats Control Register CR16 description
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Figure Audio interface I/F) formats slave mode
Delayed, Data word bit, polarity normal (CR16 default values)
value greater than
LRCK
Left channel Right channel
Non-delayed, polarity inverted, Data word
value greater than
LRCK
Left channel Right channel
other possible formats Control Register CR16 description
Figure Audio interface I/F) formats master mode
Delayed, Data word bit, polarity normal (CR16 default values)
LRCK
Left channel Right channel
Non-delayed, polarity inverted, Data word
LRCK
Left channel Right channel
other possible formats Control Register CR16 description
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Figure Audio interface I/F) formats mode
polarity normal, Data word
LRCK
Right Left channel
Left Right channel
polarity inverted, Data word
LRCK
Right Left channel
Left Right channel
NOTE: SPI-mode first high transition LRCK after power-up defines Left channel first couple audio data subsequent couples Left/Right audio data. other possible formats Control Register CR16 description
Figure Control interface (I2C I/F) formats
DATA STOP DATA DATA data bytes STOP
WRITE SINGLE BYTE
START
DEVICE ADDRESS
ADDRESS
11100010
WRITE MULTI BYTE
START
DEVICE ADDRESS
ADDRESS
11100010
CURRENT ADDR READ SINGLE BYTE
START
DEVICE ADDRESS
Current DATA STOP
11100011
CURRENT ADDR READ MULTI BYTE
START
DEVICE ADDRESS
Current DATA
Curr REG+m DATA data bytes STOP
11100011
RANDOM ADDR READ SINGLE BYTE
START
DEVICE ADDRESS ADDRESS
DEVICE ADDRESS
DATA
11100010
START DEVICE ADDRESS ADDRESS START
11100011
STOP DEVICE ADDRESS DATA DATA data bytes STOP
RANDOM ADDR READ MULTI BYTE
START
11100010
11100011
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Figure Control interface (I2C I/F) timing
tBUF
(STA)
tLOW
(DAT)
tHIGH
(DAT)
(STA)
(STA)
(STO)
STOP START START repeated
Figure A.C. Testing input, output waveform INPUT OUTPUT
0.8VCCIO 0.2VCCIO 0.7VCCIO 0.3VCCIO 0.7VCCIO
Test points
0.3VCCIO
Testing: inputs driven 0.8VCCIO logic 0.2VCCIO logic "0". Timing measurements made 0.7VCCIO logic 0.3VCCIO logic "0".
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ABSOLUTE MAXIMUM RATINGS
Parameter Voltage (VCC 3.3V) Current LSP/N Current HPR,HPL Current VCCP,GNDP Current digital output Voltage digital input (VCCIO 3.3V); limited 50mA Storage temperature range Value +0.5 -0.5 VCCIO -0.5 Unit
OPERATIVE SUPPLY VOLTAGES
Symbol VCCA VCCIO VCCP Min. Max. Unit
TIMING SPECIFICATIONS
Unless otherwise specified, VCCIO 1.8V 3.3V,Tamb -30°C 85°C, capacitive load 20pF; typical characteristics specified VCCIO 3.0V, Tamb signals referenced (see next Note timing definitions). AMCK timing
Symbol tPAMCK Parameter Test Condition AMCK Range 9.5MHz-14MHz 14MHz-19MHz 19MHz-28MHz Measured from 9.5MHz-14MHz 14MHz-19MHz 19MHz-28MHz 9.5MHz-14MHz 14MHz-19MHz 19MHz-28MHz Min. Typ. Max. Unit
Period AMCK
tHAMCK
Period AMCK high
tLAMCK
Period AMCK
Measured from
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MCLK AUXCLK timing
Symbol Parameter Test Conditions Frequency programmable with bits Measured from Measured from Measured from Measured from Min. Typ. 1.536 2.048 2.560 Max. Unit
fMCLK tWMH tWML
Frequency MCLK, AUXCLK
Period MCLK, AUXCLK high Period MCLK, AUXCLK Rise Time MCLK, AUXCLK Fall Time MCLK, AUXCLK
Audio interface signals timing
Symbol tPLRCK DCLRCK tD1SCK tD2SCK tPSCK1 tPSCK2 tHSCK tLSCK tSSDI tHSDI tDLR tD3SCK Parameter Period LRCK Duty Cycle LRCK mode Slave Delay edge from LRCK edges mode Slave Delay last edge next LRCK edges mode Slave Period mode Slave Period mode Slave Period high Period Setup time active edge Hold time from active edge Delay LRCK edges from edge Master mode Delay edge from LRCK falling edge mode LRCK frequency 30kHz LRCK frequency 30kHz Measured from Measured from Test Condition Min. Typ. Max. Unit
interface timing
Symbol tHMF tSFM tDMD tDMZ tDFD tSDM Parameter Hold Time MCLK Setup Time, high MCLK Delay Time, MCLK high data valid Delay Time, MCLK disabled Delay Time, high data valid Setup Time, valid MCLK receive edge Load 20pF; Applies only rises later than MCLK rising edge Delayed Mode only Load 20pF Test Condition Min. Typ. Max. Unit
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Symbol tHMD tHMFR tSFMR tDMDR tDMZR tHMDR Parameter Hold Time, MCLK invalid Hold Time MCLK High Setup Time, high MCLK High Delay Time, MCLK data valid Delay Time, MCLK High disabled Hold Time, MCLK High invalid Load 20pF Test Condition Min. Typ. Max. Unit
control port timing
Symbol fSCL tHIGH tLOW tHD:STA tSU:STA tHD:DAT tSU:DAT tSU:STO tBUF Parameter Clock Frequency Clock High Time Clock Time Rise Time Fall Time Start Condition Hold Time Start Condition Setup Time Data Input Hold Time Data Input Setup Time Stop Condition Setup Time Free Time 1300 1300 1000 Test Condition Min. Typ. Max. Unit
Note: signal valid above below invalid between VIH.For purpose this specification following conditions apply (see Fig. 15): input signal defined 0.2VCCIO, 0.8VCCIO, 10ns, 10ns. Delay times measured from inputs signal valid output signal valid. Setup times measured from data input valid clock input invalid. Hold times measured from clock signal valid data input invalid.
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ELECTRICAL CHARACTERISTICS
Unless otherwise specified, VCCIO 1.8V 3.3V, Tamb -30°C 85°C; typical characteristic specified VCCIO 3.0V, Tamb 25°C; signals referenced GND. Digital Interfaces (Figure
Symbol VILREM VIHREM Parameter Input Voltage Input High Voltage Input Voltage Input High Voltage Output Voltage Output High Voltage Input Current Input High Current Output Current High impedance (Tristate) Test Condition digital inputs except REMIN digital inputs except REMIN REMIN input REMIN input digital outputs, 10µA digital outputs, digital outputs, 10µA digital outputs, digital input, digital input, VCCIO VCCIO-0.1 VCCIO-0.4 0.7VCCIO 0.8VCCIO Min. Typ. Max. 0.3VCCIO 0.2VCCIO Unit
Analog Interfaces
Symbol RMBIAS IMIC RMIC RLHP CLHP ROVHP RLLS CLLS ROLS VOSLS Parameter MBIAS Output Resistance Input Leakage Input Resistance Input Resistance Single Ended Drivers Load Resistance Single Ended Drivers Load Capacitance Single Ended Drivers Output Resistance Differential Driver Load Resistance Differential Driver Load Capacitance Differential Driver Output Resistance Differential offset Voltage LSP, Test Condition MBIAS 100mV under VMIC VMIC FML, CAP2 HPL, GNDP VCMHP HPL, GNDP VCMHP Steady zero code applied ±1mA Steady zero code applied ±1mA Alternating zero code applied maximum receive gain; -100 Min. Typ. Max. +100 Unit
with series resistors
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ANALOG INPUT/OUTPUT OPERATIVE RANGES
Microphone Input Levels Absolute levels MIC1, MIC2, MIC3
Symbol Parameter dBm0 level Overload level dBm0 level Overload level dBm0 level Overload level Test Condition Transmit gain Transmit gain Transmit gain 20dB Transmit gain 20dB Transmit gain 42.5dB Transmit gain 42.5dB Min. Typ. Max. Unit mVRMS mVRMS mVRMS mVRMS mVpp mVRMS mVRMS mVpp
Input Levels Absolute levels FML,
Symbol Parameter Overload level Overload level Test Condition FML, gain FML, gain from -20dB Min. Typ. Max. Unit mVRMS mVRMS
Power Output Levels Absolute levels HPL,
Symbol Parameter Maximum undistorted level Test Condition Load Min. Typ. Max. Unit mVRMS
Power Output Levels Absolute levels LSP-LSN (Differentially measured)
Symbol Parameter dBm0 level dBm0 level Maximum undistorted level Test Condition Min. Typ. 62.1 1.41 Max. Unit mVRMS mVRMS VRMS
gain gain -24dB
Load
Tones Levels
Symbol Parameter Tone level LSP-LSN Test Condition Min. Typ. 1.41 Max. Unit VRMS mVRMS
Single tone, sinusoidal waveform, tone gain 0dB,
gain
Tone level HPL,
Single tone, sinusoidal waveform, tone gain 0dB,
HPL, gain -6dB Voice mode, Single tone, sinusoidal waveform, tone gain
Tone level
-1.64
dBFS
Note: when tones enabled amplitude lowered amplitude lowered with respect amplitude single tone.
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VOICE CODEC CHARACTERISTICS
Unless otherwise specified, 2.7V 3.3V, Tamb -30°C 85°C; Frequency 8kHz; typical characteristics specified 3.0V, Tamb 25°C, MIC1 0dBm0, -6dBm0 code, 1015.625 signals referenced GND. VOICE CODEC AMPLITUDE RESPONSE Transmit path
Symbol Parameter Test Condition Transmit Gain Programmed minimum. Measure deviation Digital Code from ideal 0dBm0 code Measure Transmit Gain over range from Maximum minimum setting. Calculate deviation from programmed gain relative GXA, i.e. GAXG actual prog. Measured relative GXA. min. gain Max. gain Measured relative Minimum gain Digital filter characteristics 3000 3400 4000 4600 8000 Digital filter characteristics Transmit Gain Variation with frequency. Frequency 16kHz (VFS=1) 6000 6800 8000 9200 16000 Sinusoidal Test method. Reference Level dBm0 VMIC dBm0 dBm0 VMIC dBm0 dBm0 VMIC dBm0 dBm0 Min. Typ. Max. Unit
Transmit Gain Absolute Accuracy
-0.5
GXAG
Transmit Gain Variation with programmed gain
-0.5
GXAT GXAV
Transmit Gain Variation with temperature Transmit Gain Variation with supply
-0.1 -0.1
GXAF8
Transmit Gain Variation with frequency. Frequency 8kHz (VFS=0)
-1.5 -0.5 -1.5
GXAF16
-1.5 -0.5 -1.5
GXAL
Transmit Gain Variation with signal level
-0.5 -0.5 -1.2
limit frequencies between 4600Hz 8000Hz lies straight line connecting frequencies linear (dB) scale versus (Hz) scale.
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VOICE CODEC AMPLITUDE RESPONSE (continued) Receive path
Symbol GRAHPL GRAHPR GRALS Parameter Test Condition Receive gain programmed maximum Apply dBm0 code Measure HPL, HPR, LSP-LSN Measure HPL, HPR, LSP-LSN Gain over range from Maximum minimum setting. Calculate deviation from programmed gain relative GRA, i.e. GRAGLS actual prog. GRALS Measured relative GRA. (HPL, LSP-LSN) min. gain Max. gain Measured relative GRA. (HPL, LSP-LSN) Maximum Gain Digital filter characteristics Receive Gain Variation with frequency (HPL, LSP-LSN) frequency 8kHz (VFS=0). High Pass Filter enabled (HPB Receive Gain Variation with frequency (HPL, LSP-LSN) frequency 8kHz (VFS=0). High Pass Filter disabled (HPB Receive Gain Variation with frequency (HPL, LSP-LSN) frequency 16kHz (VFS=1). 60Hz 100Hz 3000 3400 4000 Digital filter characteristics 50Hz 3000 3400 4000 Digital filter characteristics 100Hz 6000 6800 8000 -1.5 -0.5 -1.5 -1.5 -0.5 -1.5 Min. Typ. Max. Unit
Receive Gain Absolute Accuracy
-0.5
GRAGHPL Receive Gain Variation with GRAGHPR programmed gain GRAGLS
-0.5
GRAT
Receive Gain Variation with temperature Receive Gain Variation with Supply
-0.1
GRAV
-0.1
GRAF8
-1.5 -0.5 -1.5
GRAF16
Sinusoidal Test Method GRALHPL Receive Gain Variation with signal Reference Level dBm0 GRALHPR level dBm0 dBm0 dBm0 dBm0 GRALLS (HPL, LSP-LSN) dBm0 dBm0
-0.5 -0.5 -1.2
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VOICE CODEC ENVELOPE DELAY DISTORTION WITH FREQUENCY
Symbol Parameter Delay, Absolute Test Condition 1600 1000 1000 1600 1600 2600 2600 2800 2800 3000 1600 1000 1000 1600 1600 2600 2600 2800 2800 3000 Min. Typ. Max. Unit
Delay, Relative
Delay, Absolute
Delay, Relative
VOICE CODEC NOISE
Symbol Parameter Test Condition Min. Typ. Max. Unit dBm0p µVRMS Noise, weighted 35dB) VMIC Noise, C-message weighted Load (gain max. undistorted output level) PSRR, Receive code Zero, LSA='0100' (gain -2dB) mVRMS; 100Hz 50kHz Code equals Positive Zero, 3.0VDC mVRMS Digital filter characteristics 4600 5600 5600 7600 7600 8400
PSRTX
PSRRX
PSRR,
Spurious Out-Band signal output
3400Hz bandwidth
VOICE CODEC CROSSTALK
Symbol CTX-R Parameter Transmit Receive Test Condition Transmit Level dBm0, 3400 Quiet Code Receive Level dBm0, 3400 Min. Typ. -100 Max. Unit
CTR-X
Receive Transmit
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VOICE CODEC DISTORTION Receive path
Symbol Parameter Test Condition Sinusoidal Test Method (measured using linear 3400 weighting, FS=8kHZ) Level dBm0 Level dBm0 Level dBm0 Level dBm0 Level dBm0 Level dBm0 Level dBm0 Level dBm0 Sinusoidal Test Method (measured using linear 6800 weighting, FS=16kHZ) Level dBm0 Level dBm0 Level dBm0 Level dBm0 Level dBm0 Level dBm0 Level dBm0 Level dBm0 Sinusoidal Test Method (measured using linear 3400 weighting, FS=8kHZ) Level dBm0 Level dBm0 Level dBm0 Level dBm0 Level dBm0 Level dBm0 Level dBm0 Level dBm0 Sinusoidal Test Method (measured using linear 6800 weighting, FS=16kHZ) Level dBm0 Level dBm0 Level dBm0 Level dBm0 Level dBm0 Level dBm0 Level dBm0 Level dBm0 Min. Typ. Max. Unit
STDRLS
Signal Total Distortion (LSP-LSN) 14dB attenuation) Load Typical values measured with 14dB attenuation.
Signal Total Distortion (LSP-LSN) 14dB attenuation) Load Typical values measured with 14dB attenuation.
Signal Total Distortion (HPL, HPR) 14dB attenuation) Typical values measured with 14dB attenuation
Signal Total Distortion (HPL, HPR) 14dB attenuation) Typical values measured with 14dB attenuation
limit curve shall determined straight lines joining successive coordinates given table.
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VOICE CODEC DISTORTION Transmit path
Symbol Parameter Test Condition Sinusoidal Test Method (measured using linear 3400 weighting) Level dBm0 Level dBm0 Level dBm0 Level dBm0 Level dBm0 Level dBm0 Level dBm0 Level dBm0 Level dBm0 Sinusoidal Test Method (measured using linear 6800 weighting) Level dBm0 Level dBm0 Level dBm0 Level dBm0 Level dBm0 Level dBm0 Level dBm0 Level dBm0 Level dBm0 Min. Typ. Max. Unit
STDX
Signal Total Distortion 35dB gain) frequency 8kHz. Typical values measured with 30.5dB gain
Signal Total Distortion frequency 16kHz. Typical values measured with 30.5dB gain
limit curve shall determined straight lines joining successive coordinates given table.
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STEREO AUDIO CHARACTERISTICS Unless otherwise specified, 2.7V 3.3V, Tamb -30°C 85°C; typical characteristics specified VCMHP=1.5V, Tamb 25°C; fAMCK 13.0MHz; Full-Scale Input Sine Waves 1015.625Hz; Input Sample Rate (Fs) 48kHz; Input Data 18Bits; Measurement Bandwidth 20Hz 20kHz, unweighted. Resistive load HPL, 16).
Symbol DYNR Resolution* Dynamic Range A-weighted 2Vpp output HPL, gain -6dB load A-weighted unweighted kHz) 2Vpp output HPL, gain -6dB load 2Vpp output HPL, gain -6dB load Measurement Bandwidth 20Hz 20kHz, 48kHz. Combined digital analog filter characteristics. Combined Digital Analog filter characteristics. Combined Digital Analog filter characteristics. Combined Digital Analog filter characteristics. Measurement Bandwidth 3.45Fs Combined Digital Analog filter characteristics. 0.55Fs Parameter Test Condition Min. Typ. Max. Unit Bits
Signal noise ratio
0.01 0.03
THDL
Total Harmonic Distortion Worst case load
Total Harmonic Distortion
0.004
Deviation from Linear Phase*
Passband* Passband Ripple*
0.45Fs
StopBand*
StopBand Attenuationv
Transient suppression filter cutoff frequency** Band Noise Measurement Bandwidth 20kHz 100kHz. Zero input signal
2Vpp output HPR, unloaded HPR, with VCMHP
Group Delay* Interchannel Isolation* Interchannel Gain Mismatch Gain Error
13.8
Startup Time from Power Up**
Valid Audio interface input (Audio Mode). **Calculation SUT: define: (fAMCK fDIV) where fAMCK frequency AMCK expressed fDIV where AMCK_DIV content CR18, bits1-0. approximate startup time obtained dividing 10.6 transient suppression filter cutoff frequency obtained multiplying 20Hz Note: range: 8kHz 48kHz.
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POWER DISSIPATION Unless otherwise specified, 2.7V 3.3V, Tamb -30°C 85°C, LSP, HPL, outputs loaded; typical characteristics specified Tamb 25°C
Symbol ICC0 Parameter Power down Current, REMOCON Test Condition SDA, SCL= VCCIO-0.1V REMOCON function disabled (REN SDA, SCL= VCCIO-0.1V REMOCON function enabled (REN REMIN VILREM REMIN VIHREM Min. Typ. Max. Unit
ICC0R
Power down Current, REMOCON
ICC1 ICC2 ICC3
Power Current Voice Codec Fs=8kHz. LSP/N output selected Mode Fs=44.1 kHz, AMCK=12 Power Current Stereo Audio HPL,HPR outputs selected, Mode VCE=0, FSEL=0. Power Current Stereo Mode HPL,HPR outputs selected, VCE=0.
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TYPICAL PERFORMANCE CHARACTERISTICS (simulations)
Bass-Treble controls
De-emphasis Filter
Amplitude [dB] Amplitude [dB] 1000 Freq. [Hz] 10000
1000 Freq. [Hz] 10000
Plot Bass treble gains independently selectable combination. Filters characteristics Fs=44.1kHz plotted
Plot filter compensates pre-emphasis used some audio CDs. gain error from ideal filtering lower than 0.1dB. de-emphasis filter selection implies flat treble control.
Digital Audio Filter Characteristic
Amplitude [dB] -0.1 -0.2 -0.3 -0.4 -0.5
Digital Audio Filter Characteristic
Amplitude [dB] -100 Normalized Freq. [Fs]
0.05
0.15
0.25 0.35 Normalized Freq. [Fs]
0.45
Plot Frequency response 3.45
Plot band Frequency response
Digital Voice Filter Characteristic
Amplitude [dB] 2000 4000 6000 8000 10000 12000 14000 16000 18000 20000 Freq. [Hz] Amplitude [dB]
Digital Voice Filter Characteristic
-0.5
1000
1500 2000 Freq. [Hz]
2500
3000
3500
Plot Frequency response 2.5Fs
Plot band Frequency response. FS=8
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STw5094A
TYPICAL PERFORMANCE CHARACTERISTICS (cont.)
Digital Voice Filter Characteristic High Pass Filt.)
0.75 Output Amplitude [FS] Amplitude [dB] 0.25 -0.25 -0.5 -0.75 1000 1500 2000 Freq. [Hz] 2500 3000 3500 -0.75 -0.5 -0.25 0.25 Input Amplitude [FS] 0.75
Dynamic Compressor Transfer Function
-0.5
Plot band Frequency response. FS=8 High Pass filter disabled (HPB=1).
Plot Audio signal transfer function when Dynamic Compressor active.
TYPICAL PERFORMANCE CHARACTERISTICS (Measures)
Signal Noise ratio Signal Amplitude Audio Mode
[dB] Signal Amplitude [Hz] Signal Amplitude [dBr]
Audio Performance with load VCMHP
-100 -120 5000 10000 Frequency [Hz] 15000 20000
Plot Input signal applied input Left right single ended drivers gain VCC=2.7V, Fs=48kHz, bits input word. A-weighted
Plot audio mode (8192 points). load Full scale 1kHz input signal applied input. Both channels active, Left channel plotted VCC=2.7V, Fs=48kHz, bits input. 12MHz AMCK
mode Performance with load VCMHP
Signal Amplitude [dBr] -100 -120 5000 10000 Frequency [Hz] 15000 20000
Voice Mode SINAD: Receive (RX) Transmit (TX) path
S/(N+THD) [dB] Signal Amplitude [dB] Path
Path
Plot Signal applied (RX) Mic1 (TX) input. gain differential output (0dB=4Vpp out), load. input gain (0dB=0.2Vpp input). VCC=2.7V, Fs=8kHz, 300-3400 Linear Weight.
Plot mode (8192 points). load Signal applied inputs Both channels active loaded, left channel plotted VCC=2.7V, 12MHz AMCK
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STw5094A
APPLICATION NOTE
MBIAS 1.8k 100nF MIC1P 10µF Electret 100nF MIC1N 100k 1.8k BC556 100nF MIC2P Mic. 100nF MIC2N 10µF 1.5k REMIN 100nF MIC3 Electret Call/Answer Button 10µF CAP2 MCLK Voice [8kHz/16kHz] Data Data 100k BC546
REMOUT/OCK
Microprocessor/ Clock Auxiliary Clock
AUXCLK
Buzzer
STw5094A
Interface
Min.
VCMHP
Data Clock
AMCK 0.47µF Line (From Stereo Decoder) 0.47µF LRCK Min.
System Clock (Audio)
[9.5MHz-28MHz]
[8kHz-48kHz] Data Data Clock
Audio Data Interface
GNDCM
100nF
VDDP
100nF
100nF
VCCIO VDDIO 100nF
GNDA
GNDP
VCCA
VCCP
10µF
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STw5094A
TFBGA PACKAGE OUTLINE
Table TFBGA 6x6x1.20 F6x6 0.80
1.Max mounted height 1.16 Based 0.37 ball diameter. Solder paste 0.15 thick with 0.37 diameter. TFBGA stands Thin Profile Fine Pitch Ball Grid Array. Thin profile: total profile height (DIm measured from seating plane component. 1.01 1.20 Fine pitch 1.00 pitch. terminal corner must identified surface using corner chamfer, ink, metallized markings other feature package body integral heatslug. distinguishing feature allowable bottom surface package identify terminal corner. Exact shape each corner optional.
Min. 1.01 0.21
Typ.
Max. 1.20
0.820 0.35 5.85 0.40 6.00 4.00 5.85 6.00 4.00 0.72 0.85 0.80 1.00 0.88 1.15 1.00 6.15 0.45 6.15
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STw5094A
Figure TFBGA36 drawing
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STw5094A
REVISION HISTORY
Date 28-Apr- 2005 Revision First Release Description Changes
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STw5094A
Information furnished believed accurate reliable. However, STMicroelectronics assumes responsibility consequences such information infringement patents other rights third parties which result from use. license granted implication otherwise under patent patent rights STMicroelectronics. Specifications mentioned this publication subject change without notice. This publication supersedes replaces information previously supplied. STMicroelectronics products authorized critical components life support devices systems without express written approval STMicroelectronics. logo registered trademark STMicroelectronics. other names property their respective owners 2005 STMicroelectronics rights reserved STMicroelectronics group companies Australia Belgium Brazil Canada China Czech Republic Finland France Germany Hong Kong India Israel Italy Japan Malaysia Malta Morocco Singapore Spain Sweden Switzerland United Kingdom United States America www.st.com
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