AN1228 Interfacing M68HC05 MC145051 Converter Mark Glenewink
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AN1228
Interfacing M68HC05 MC145051 Converter
Mark Glenewinkel CSIC Applications Austin, Texas
Introduction
This application note describes interface between Motorola's M68HC05 Family microcontrollers Motorola's MC145051 analogto-digital converter (ADC). MC145051 10-bit, 11-channel, serial interface ADC. microcontroller unit (MCU) interface must able "talk" MC145051 using serial communication link. most popular hardware modules available M68HC05 Family serial peripheral interface (SPI). This application note provides hardware software design link module MC68HC705C8 MC145051. M68HC05 Family members have modules. M68HC05 without must interface MC145051 using software driver. This method "bit bangs" port communicate with MC145051. Although efficient hardware method, provides MCUs without means retrieve data from MC145051. This application note will utilize MC68HC705K1 demonstrate software driver routine.
Motorola, Inc., 1995; Revised 1997
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Application Note MC145051
MC145051 ratiometric 10-bit providing analog channels conversion with internal sample-and-hold. MC145051 internal resistor capacitor (RC) clock oscillator internal digital circuitry. maximum conversion time MC145051 with maximum sample rate 21.4 ksamples/s. faster conversion time needed, MC145050 used that same MC145051 except requires external clock. With 2.1-MHz clock, MC145050 provides conversion time maximum sample rate ksamples/s. MC145051 operates with single voltage supply between volts. serial interface used receive channel address convert transmit converted values outside world.
Successive Approximation
MC145051 utilizes successive approximation convert analog input signal digital value. This technique consists comparing unknown analog input known analog voltage created digital-toanalog converter (DAC). digital number given number that will eventually result ADC's output. This process "guessing" analog input voltage similar weighing with balance. three weights consisting 1/2, 1/4, gram, could measure something gram within ±1/16 gram weight. side scale would hold unknown other side would contain various weights "guessing" weighted value unknown. Consider 3-bit converter would convert unknown signal. Figure shows block diagram very simple 3-bit converter. digital number into converts this analog voltage comparator use. input analog voltage larger than DAC's output voltage, result comparison. input analog voltage smaller than DAC's output, result comparison. result comparison back into successive approximation register. control logic adds smaller digitally "weighted" value "guess" input analog
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Application Note MC145051
voltage. This sequence continues until smallest digital "weight" used guess input voltage. Figure illustrates this
COMPARATOR ANALOG INPUT
ANALOG REFERENCE
3-BIT DIGITAL OUTPUT
START CONVERSION CLOCK
SHIFT REGISTER CONTROL LOGIC OUTPUT REGISTER CONVERSION OUTPUT
Figure Simple 3-Bit Converter
DIGITAL OUTPUT BINARY FRACTIONAL TEST ANSWER TEST ANSWER TEST ANSWER TIME
ANALOG INPUT VOLTAGE
Figure 3-Bit Weighing Sequence
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Application Note
process with graph that depicts testing signal magnitude between full scale analog reference voltage. After guesswork done, binary answer written output register further processing. this example, input voltage does change over entire conversion process. have assumed that signal does change there noise change input voltage. most cases sample-and-hold circuit used sample voltage signal hold specific length time until conversion process complete. accuracy, linearity, speed successive approximating converter dependent properties comparator. settling time speed comparator determine speed conversion process. Likewise, conversion demands more resolution, time convert will lengthened. DAC's non-linearity will result non-linearities within ADC. these factors affect digital output result ADC.
Inside MC145051
stated earlier, MC145051 will convert analog inputs into 10-bit digital representation analog signal. 10-bit digital value transmitted outside world serial bus. Figure shows block diagram MC145051. sequence starting conversion, converting voltage, transmitting result signal driven initialize serial port that 4-bit address going received previous 10-bit digital result will transmitted. After 4-bit address received address register, analog inputs selected from analog multiplexer. This signal sent sample-and-hold start 10-bit conversion process. While 4-bit address received, 10-bit previously converted value sent DOUT pin. internal clock drives digital control circuitry, which turn manipulates successive approximation register until 10-bit conversion complete.
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Application Note MC145051
Once conversion complete, final value successive approximation register written data register. 10-bit result will stay here until queued sent DOUT next serial transmission. Also, MC145051 will signal ending conversion driving end-of-conversion (EOC) high. some transmission scenarios, must negated high before another transmission conversion occur.
AN10
VREF
COMPARATOR SAMPLE/HOLD
ANALOG 10-BIT
SUCCESSIVE APPROXIMATION REGISTER
ADDRESS REGISTER
DATA REGISTER DOUT
INTERNAL CLOCK
DIGITAL CONTROL (MC145051 ONLY) (MC145050 ONLY)
SCLK ADCLK
Figure MC145051 Block Diagram
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Application Note
Analog Interface analog input consists converter's high voltage reference pins analog input pins. analog specifications listed Table Table Analog Specifications
Symbol VREF Parameter Reference Voltage Analog Ground Analog Input Voltage +4.0 -0.1 +0.1 VREF -4.0 VREF
MC145051 will take voltage samples analog input convert number equivalent ratio input voltage difference between VREF VAG. This number converter's digital representation sampled voltage input. Figure illustrates this ratio describes equation that predicts ADC's conversion value. example, 2.34 volts, then 10-bit representation that voltage $1DF.
VREF
VREF-VAG
VREF-VAG
1023
Figure Conversion Ratio
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Application Note MC145051
Digital Interface
digital interface MC145051 composed serial data port that synchronously transceives data. Each digital pin's function explained here. Active-Low Chip Select When asserted low, this initializes chip start performing conversions. While high, DOUT forced highimpedance state disabled. DOUT Serial Data This serves serial output data conversion result. After asserted low, DOUT driven with most significant previous 10-bit result. value DOUT changes second most significant after falling edge serial clock (SCLK). After bits transmission, DOUT driven low. result always driven DOUT most significant (MSB) first. Serial Data This serves input data line that receives 4-bit address serial stream. address shifted rising edge SCLK with being first received. After four bits have been received, ignored. SCLK Serial Data Clock This input that drives serial transmission lines. drives data shift registers that next address received previous conversion driven out. End-of-Conversion Output This driven 10th falling edge SCLK. low-tohigh transition occurs after conversion complete.
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Application Note
MC145051 capable various stream formats. timing diagram used this application note shown Figure MC145051 will wait patiently until asserted low. This signifies that serial clock will driving SCLK transfer next channel address converted. same time, MC145051 will driving converted value previous conversion. After 10-bit address driven DOUT, will driven high signify transmission process.
SCLK
LEVEL
Figure MC145051 Timing Diagram
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Application Note Description MC68HC705C8 Interface
Description MC68HC705C8 Interface
following paragraphs describe MC68HC705C8 interface.
Hardware
MC68HC705C8 most popular members M68HC05 Family 8-bit MCUs. serial peripheral interface (SPI) that will used interface MC145051. essence, 8-bit serial shift register that manipulated software instructions. programmed with different clock polarities clock phases correctly communicate with number devices. also configured master slave. Each signal explained below. more detail SPI, consult MC68HC705C8 Technical Data, Rev. (MC68HC705C8/D). Serial Data Clock signal used synchronize movement data module. This output input dependent whether configured master slave. Data shifted side clock edge sampled other. signal configured accommodate different serial peripheral structures. MOSI Master Output, Slave Input When configured master, this used output shift 8-bit serial data with most significant (MSB) first. used slave data input when configured slave. MISO Master Input, Slave Output configured master, this utilized input. When slave mode, used output. Slave Select When slave, this enables incoming transfer. master, this should tied high.
correctly interface MC145051, configured master with timing diagram shown Figure This configuration
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Application Note
enables drive data with MOSI rising edge receive data with MISO falling edge.
MOSI
MISO
Figure Timing Diagram schematic used this interface shown Appendix MC68HC705C8/MC145051 Schematic. MC68HC705C8 clocked 4-MHz crystal circuit. This provides with 2-MHz internal frequency 500-ns period instruction cycle. MC34064 used low-voltage inhibitor circuit. This 3-pin, T0-92 device ensures that reset pulled operating voltage falls below volts. lines connected appropriate pins MC145051. MOSI drives data MC68HC705C8 into MC145051. DOUT drives data MC145051 into MISO MC68HC705C8. Since configured master, driving SCLK MC145051 tied high. MC68HC705C8 programmed utilize read MC145051. Channel MC145051 used read voltage created potentiometer between VREF levels. 0.22 capacitor used between VREF pins filter high frequency noise. This capacitor should mounted close MC145051 possible. After MC68HC705C8 receives data from MC145051, driven onto ports MC68HC705C8. circuit given Appendix MC68HC705C8/MC145051 Schematic minimizes noise often found emulated systems. Instead programming MC68HC705C8, M68HC05EVM used emulate MC68HC705C8. This evaluation module will give accurate reading circuit Appendix
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Application Note Description MC68HC705C8 Interface
MC68HC705C8/MC145051 Schematic, allows more flexibility code development than using programmed MC68HC705C8.
Software
flowchart SPI-driven MC145051 shown Appendix MC68HC705C8/MC145051 Flowchart, actual M68HC05 assembly code given Appendix MC68HC705C8/MC145051 Assembly Code. This code written programmed MC68HC705C8. Extra lines code were added that routine would perform standalone application. "talk" MC145051, must configured match with MC145051 timing diagram, shown earlier Figure Also, transmissions must sent form 16-bit transfer. Before transmissions start, must asserted low. This initializes MC145051 tells that address will sent start conversion process. first transfer sends channel number MC145051, MC145051 sends upper eight bits previously converted value. These eight bits written 16-bit result register port second transfer sends channel MC145051 MC145051 ignores because needed. MC145051 sends 705C8 least significant bits (LSB) from previously converted value. These bits most significant bits received data. This byte written 16-bit result register port After both transmissions done, negated high. Port port have 10-bit value previous conversion. This output value port port illustrated Figure routine will infinite loop waiting reset.
10-BIT RESULT $1C2 01,1100,0010% PORT 0111,0000% PORT 1000,0000%
Figure Value Port Port
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Application Note
following example provided test software routine. Follow these steps after programming MC68HC705C8 with code Appendix MC68HC705C8/MC145051 Assembly Code constructing schematic Appendix MC68HC705C8/MC145051 Schematic. potentiometer reading 2.20 volts. VREF-VAG exactly 5.00 volts, should convert reading $1C2. (See Figure Power circuit. value will outputted port port This value previously converted value. Since there previous conversion, data will garbage. Pull RESET then high. routine will again, previous value channel conversion represented port port value port should port should $80. result might differ least significant (LSB). (See Figure This routine simplest example test learn interface from MC68HC705C8 MC145051. Notice that address must high nibble byte before written data register. Also, since this routine hard-coded, channel already known written into memory. code easily adapted subroutine, which requires that channel converted input subroutine. application requires that successive conversions made, make sure that MC145051 enough time convert present channel before initializing another conversion. needed, MC145051 provides pin. During conversion process, held low. After conversion complete, driven high. Another port MC68HC705C8 might used read pin.
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Application Note Description MC68HC705K1 Interface
Description MC68HC705K1 Interface
following paragraphs describe MC68HC705K1 interface.
Hardware
With only pins, MC68HC705K1 smallest members M68HC05 Family. total bytes erasable programmable read-only memory (EPROM) includes input/output (I/O) pins. schematic MC68HC705K1 MC145051 interface shown Appendix MC68HC705K1/MC145051 Schematic. With this interface, M68HC705KICS development board used write test code. circuitry surrounding MC145051 same MC68HC705C8 design. only changes serial pins MC145051. These pins connected emulation header M68HC705KICS board. This emulation header exact pinout MC68HC705K1. pins used drive MC145051 MC68HC705K1 are: Port This (CS) configured output drive MC145051. Port This (SER_CLK) configured output drive serial clock serial transmission bus. Port This (SER_OUT) configured output drive serial data into 5051. Port This (SER_IN) configured input receive data driven from DOUT MC145051.
emulation test circuit also configured standalone design. further information programming MC68HC705K1, consult MC68HC705K1 Technical Data, Rev. (MC68HC705K1/D) M68HC705KICS development board documentation.
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Application Note
Software flowchart bit-banged-driven MC145051 shown Appendix MC68HC705K1/MC145051 Flowchart, actual M68HC05 assembly code given Appendix MC68HC705K1/MC145051 Assembly Code. Bit-banging process toggling pins with software instructions emulate certain piece hardware peripheral. This bit-banged routine written especially MC145051. full featured representation MC68HC705C8 module. Enhancements routine were included maximize efficiency code. stated preceding Hardware section, pins have been used send correct serial transmission protocol MC145051. M68HC05 provides special instructions specifically manipulate single pins. MC145051 serial stream shown Figure will re-created four pins MC68HC705K1. best describe code list each segment code explain purpose bit-bang MC145051. shorthand port
Equivalents
SER_CLK SER_OUT SER_IN
Initialize Port
output SER_CLK output SER_OUT output SER_IN input
Begin Acquisition
driven start serial transmission. CHANNEL byte read. address nibble byte. 16-bit RESULT registers cleared copy CHANNEL stored TMP_CHN future use. When emulating, make sure that location initialized with channel $00.
AN1228 Rev. MOTOROLA
Application Note Description MC68HC705K1 Interface
Initialize Loop1
index register
Read serial input Start Loop
branch-if-clear instruction used read SER_IN. purpose this transfer logic state SER_IN carry (C). branch taken. next line code always executed. rotate left instructions rotate into 16-bit RESULT register composed RESULT RESULT+1. first read SER_IN previous result from MC145051.
Write serial output
TMP_CHN rotated left. TMP_CHN read. high, written SER_OUT. low, written SER_OUT. This first transmitted 4-bit channel address.
Clock serial clock
SER_CLK written high then written low.
Loop done?
index register decremented checked code executed start Loop This loop continues until four transmissions completed.
Initialize Loop
index register
Read serial input Start Loop
This same code that executed start loop above. Notice that loop does transmit more bits SER_OUT. This because MC145051 ignores last transmitted bits because already received four address bits needs.
Clock serial clock
SER_CLK written high then written low.
AN1228 Rev. MOTOROLA
Application Note
Loop done?
index register decremented checked code executed start Loop This loop continues until transmissions completed.
Negate
written This completes serial transmission MC145051. Since this code written emulation M68HC705KICS board, easy experiment with different applications. code easily adapted custom application that needs 10-bit data.
Layout Considerations
There many things consider when laying mixed signal designs such MC145051 M68HC05 MCU. accuracy MC145051 greatly affected proper layout design followed. Listed here some things check ensure accuracy your converter. more in-depth study layout issues, consult Reducing Errors Microcontroller Applications (AN1058/D). Physically separate critical analog circuits from digital circuits MCU. possible, split your board half separate analog digital circuits. Each half will have power ground system. analog input line traces cross digital traces. this happen, make sure they cross right angles each other. power ground traces isolate analog-input pins from digital pins. Bypass power supplies proper ground MC145051 power pins with quality ceramic capacitors. Keep bypass capacitors lead lengths short possible.
AN1228 Rev. MOTOROLA
Application Note References/Further Reading
bypass frequency power supply noise, tantalum aluminum electrolytic capacitors These should placed near point where power supplies enter board.
References/Further Reading
Analog-Digital Conversion Handbook, Third Edition, York: Prentice-Hall, 1986. MC145050/51 Technical Data Sheet, (MC145050/D), Motorola, 1993. MC68HC05 Applications Guide, (M68HC05AG/AD), Motorola, 1989. MC68HC705C8 Technical Data, (MC68HC705C8/D), Motorola, 1990. MC68HC705K1 Technical Data, (MC68HC705K1/D), Motorola, 1993. Reducing Errors Microcontroller Applications, (AN1058/D), Motorola, 1990.
AN1228 Rev. MOTOROLA
Application Note Appendix MC68HC705C8/MC145051 Schematic
RESET MC68HC705C8S
OSC1 OSC2 TCAP TCMP PD5/SS PD4/SCK PD3/MOSI PD2/MISO PD1/TDO PD0/RDI
INPUT
RESET
MC34064
SERIAL_CLOCK SERIAL_OUT SERIAL_IN
CHIP_SELECT
AN1228 Rev. MOTOROLA
Application Note Appendix MC68HC705C8/MC145051 Schematic
SERIAL_IN SERIAL_OUT SERIAL_CLOCK CHIP_SELECT
DOUT SCLK
AN10 VREF
VDDA 0.22
MC145051P
AGND
AN1228 Rev. MOTOROLA
Application Note Appendix MC68HC705C8/MC145051 Flowchart
START
"INITIALIZE PORTS" PORT PORT PORT DATA DATA DATA
"INITIALIZE CHANNEL CHANNEL
"INITIALIZE MODULE" TURN MASTER MODE CPHA CPOL
"BEGIN ACQUISITION"
"1ST 8-BIT SERIAL TRANSFER" LOAD ACCA UPPER NIBBLE WITH CHANNEL STORE ACCA DATA REGISTER START TRANSMISSION
SERIAL TRANSFER DONE?
AN1228 Rev. MOTOROLA
Application Note Appendix MC68HC705C8/MC145051 Flowchart
READ DATA REGISTER STORE RESULT STORE PORT
"2ND 8-BIT SERIAL TRANSFER" LOAD ACCA WITH CHANNEL STORE ACCA DATA REGISTER START TRANSMISSION
SERIAL TRANSFER DONE?
READ DATA REGISTER STORE RESULT STORE PORT
"END ACQUISITION"
AN1228 Rev. MOTOROLA
Application Note Appendix MC68HC705C8/MC145051 Assembly Code
Program Name: C8_5051.ASM (705C8 145051 interface) Revision: 1.00 Date: October 1993 Written Mark Glenewinkel Motorola CSIC Applications Assembled Under: Microcomputer Systems IASM05 Revision History 1.00 10/07/93 M.R. Glenewinkel Initial Release Program Description: This software routine provides MCUs with module chip interface Motorola MC145051 bit, channel analog digital converter. This program specifically uses MC68HC705C8 test code. HC705C8 "talks" 5051 with appropriate serial data transfer from module. more information, please consult Motorola Application Note AN1228/D. PORTA DDRA PORTB DDRB PORTC DDRC Equates 705C8 ;port ;data ;port ;data ;port ;data data data data
AN1228 Rev. MOTOROLA
Application Note Appendix MC68HC705C8/MC145051 Assembly Code
SPCR SPSR SPDR RESULT
;spi ctrl ;spi status ;spi data ;bit chip select ;start static bytes needed result ;a/d channel ;start program ;port ;port ;port ;port ;port ;port outputs outputs outputs
storage variables
CHANNEL
Start program $1000 #$FF PORTA DDRA PORTB DDRB PORTC DDRC #$00 CHANNEL
START
;CHANNEL ;turn spi, mstr mode ;cpha=cpol=0 ;CS* ;load ACCA with CHANNEL
Initialize module #$50 SPCR
Send frame bclr CS,PORTA CHANNEL
WAIT1
Send address, receive most significant byte SPDR ;store ACCA data brclr 7,SPSR,WAIT1 ;wait until SPIF flag SPDR ;load ACCA with result RESULT ;store this RESULT PORTB ;store MSBs Port
AN1228 Rev. MOTOROLA
Application Note
WAIT2 Start another transmission receive least significant bits CHANNEL ;load ACCA with CHANNEL SPDR ;store ACCA data brclr 7,SPSR,WAIT2 ;wait until SPIF flag SPDR ;load ACCA with result RESULT+1 ;store this RESULT PORTC ;store LSBs Port bset CS,PORTA ;CS* high, frame
Wait ever until reset ;branch itself $1FFE START ;define reset vector
AN1228 Rev. MOTOROLA
Application Note Appendix MC68HC705K1/MC145051 Schematic
Appendix MC68HC705K1/MC145051 Schematic
MC68HC705K1 EMULATION HEADER SERIAL_IN SERIAL_OUT SERIAL_CLOCK CHIP_SELECT DOUT SCLK VDDA 0.22
AN10 VREF
MC145051P
AGND
AN1228 Rev. MOTOROLA
Application Note Appendix MC68HC705K1/MC145051 Flowchart
START
"INITIALIZE PORT PORT PORT DIRECTION
"BEGIN ACQUISITION" TMP_CHN= CHANNEL CLEAR RESULT REGISTERS
"INIT LOOP1 COUNTER"
"READ SERIAL INPUT PIN" CARRY ACCORDING VALUE SER_IN ROTATE LEFT INTO RESULT REGISTERS
"WRITE SERIAL OUTPUT PIN" ROTATE LEFT TMP_CHN
CLEAR SER_OUT
TMP_CHN?
SER_OUT
"CLOCK SERIAL CLOCK PIN" SER_CLK CLEAR SER_CLK
DECREMENT
AN1228 Rev. MOTOROLA
Application Note Appendix MC68HC705K1/MC145051 Flowchart
"INIT LOOP2 COUNTER"
"READ SERIAL INPUT PIN" CARRY ACCORDING VALUE SER_N ROTATE LEFT INTO RESULT REGISTER
"CLOCK SERIAL CLOCK PIN" SER_CLK CLEAR SER_CLK
DECREMENT
"END ACQUISITION"
AN1228 Rev. MOTOROLA
Application Note Appendix MC68HC705K1/MC145051 Assembly Code
Program Name: K1_5051.ASM 705K1 145051 interface Revision: 1.00 Date: September 1993 Written Mark Glenewinkel Motorola CSIC Applications Assembled Under: Microcomputer Systems IASM05 Revision History 1.00 09/22/93 M.R. Glenewinkel Initial Release Program Description: This software routine provides MCUs with module chip interface Motorola MC145051 bit, channel analog digital converter. This program specifically uses MC68HC705K1 test code. HC705K1 "bit bangs" 5051 with appropriate serial data transfer 5051 understands. more information, please consult Motorola Application Note AN1228/D. PORTA PORTB DDRA DDRB Equates 705K1 ;port ;port ;data ;data data data
AN1228 Rev. MOTOROLA
Application Note Appendix MC68HC705K1/MC145051 Assembly Code
SER_CLK SER_OUT SER_IN
;bit ;bit ;bit ;bit
chip select serial clock serial data serial data
storage variables
RESULT CHANNEL TMP_CHN
;start static bytes needed result ;a/d channel ;temp channel routine ;start user eprom ;init port ;init port
Start program $200
START
Initialization #$01 PORTA #$07 DDRA
Init start bclr CS,PORTA ;CS* line CHANNEL TMP_CHN RESULT+1 RESULT ;load ACCA with channel ;(for emulation, init $E2=$00) ;store ACCA temp channel ;clear result regs ;init counter LOOP1
LOOP1 L1_1
Read serial input brclr SER_IN,PORTA,L1_1 ;carry serial RESULT+1 ;rotate left result RESULT Write serial output TMP_CHN brclr 4,TMP_CHN,L1_2 bset SER_OUT,PORTA L1_3 bclr SER_OUT,PORTA ;rotate left TMP_CHN tmp_chn bit4 goto L1_2 ;ser_out ;goto L1_3 ;ser_out
L1_2
AN1228 Rev. MOTOROLA
Application Note
L1_3 Clock serial clock bset SER_CLK,PORTA ;ser_clk bclr SER_CLK,PORTA ;ser_clk decx LOOP2 LOOP1 ;decrease counter loop LOOP1 finished? ;init counter LOOP2
Read serial input brclr SER_IN,PORTA,L2 ;carry serial RESULT+1 ;rotate left result RESULT Clock serial clock bset SER_CLK,PORTA ;ser_clk bclr SER_CLK,PORTA ;ser_clk decx LOOP2 ;decrease counter loop LOOP2 finished?
high finish serial transfer bset CS,PORTA ;CS* line high $03FE START ;branch forever ;reset vector
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Application Note Notes
Notes
AN1228 Rev. MOTOROLA
Application Note
Motorola reserves right make changes without further notice products herein. Motorola makes warranty, representation guarantee regarding suitability products particular purpose, does Motorola assume liability arising application product circuit, specifically disclaims liability, including without limitation consequential incidental damages. "Typical" parameters which provided Motorola data sheets and/or specifications vary different applications actual performance vary over time. operating parameters, including "Typicals" must validated each customer application customer's technical experts. Motorola does convey license under patent rights rights others. Motorola products designed, intended, authorized components systems intended surgical implant into body, other applications intended support sustain life, other application which failure Motorola product could create situation where personal injury death occur. Should Buyer purchase Motorola products such unintended unauthorized application, Buyer shall indemnify hold Motorola officers, employees, subsidiaries, affiliates, distributors harmless against claims, costs, damages, expenses, reasonable attorney fees arising directly indirectly, claim personal injury death associated with such unintended unauthorized use, even such claim alleges that Motorola negligent regarding design manufacture part. Motorola registered trademarks Motorola, Inc. Motorola, Inc. Equal Opportunity/Affirmative Action Employer.
reach USA/EUROPE/Locations Listed: Motorola Literature Distribution; P.O. 5405, Denver, Colorado 80217. 1-800-441-2447 303-675-2140 MfaxTM: RMFAX0@email.sps.mot.com TOUCHTONE 602-244-6609, Canada ONLY 1-800-774-1848 INTERNET: http://motorola.com/sps JAPAN: Nippon Motorola Ltd. SPD, Strategic Planning Office 4-32-1, Nishi-Gotanda Shinagawa-ku, Tokyo 141, Japan. 81-3-5487-8488 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Ping Industrial Park, Ting Road, N.T., Hong Kong. 852-26629298
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AN1228/D
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