STDL131 0.18µm 1.8V CMOS Standard Cell Library Pure Logic Products
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Revision History 1'st Edition: October 2000 2'nd Edition: April 2003 Chapter Introduction Chapter Electrical Characteristics(Recommended Operating Conditions) Chapter Primitive Cells Chapter Complied Memories
STDL131 0.18µm 1.8V CMOS Standard Cell Library Pure Logic Products
STDL131 0.18µm 1.8V CMOS Standard Cell Library Pure Logic Products Data Book Copyright 2003, 2002 Samsung Electronics Co., Ltd. rights reserved. part this document reproduced, form means, without prior written consent publisher. Samsung assumes responsibility errors resulting from information contained herein, does convey license under patent rights Samsung others. Samsung reserves right make changes products product specification improve function design time, without notice. STDL131 trademarks Samsung Electronics Co., Ltd. Verilog registered trademark Cadence Design Systems, Inc. Viewlogic registered trademark Viewlogic Systems, Inc. Mentor registered trademark Mentor Graphics Synopsys registered trademark Synopsys, Inc.
Head Office Samsung Electronics Co., System Business, ASIC Infro #24, Nongseo-Ri, Giheung-Eup, Yongin-City, Gyunggi-Do, Korea 449-711 82-2-760-6500, 6501 (Hot Line) 82-31-209-4920 ASIC Printed Republic Korea
Marketing Team Samsung Electronics Co., System Business, ASIC Division, ASIC Marketing Team #24, Nongseo-Ri, Giheung-Eup, Yongin-City, Gyunggi-Do, Korea 82-2-31-209-1930 82-2-31-209-1919
Introduction
This databook contains information about STDL131 0.18µm 1.8V standard cell library pure Logic products developed (Samsung Electronics Corporation). "library" basically contains various kinds primitive cells cores which used developing ASIC (Application Specific Integrated Circuit). also includes design helping designers work workstation platform, sorts design environments needed automatic chip design. There chapters this databook: Chapter Chapter Chapter Chapter Chapter Chapter Introduction Electrical Characteristics Primitive Cells Input/Output Cells Compiled Memories Appendix
this databook, each cell followed electrical characteristics, these characteristic values almost equal when corresponding cell operated real chip. purpose this databook prevent misuse misapplication STDL131 cell library providing precise information about cell list, electrical data, directions use, matters demanding special attention. want more information about digital cores analog cores that included this databook, access Samsung ASIC contact head office.
Samsung ASIC
STDL131
Contents
Introduction
Library Description .1-1 Features .1-2 Support .1-4 Product Family .1-4 1.4.1 Analog Cores .1-4 1.4.2 Primitive Cells .1-8 1.4.3 Compiled Memories .1-9 1.4.4 Input/Output Cells .1-11 Timings .1-14 Design Test (DFT) Methodology.1-22 Maximum Fanouts .1-25 Packages Capability Pitch Lead Count .1-32 Power Dissipation .1-33
1.10 VDD/VSS Rules Guidelines .1-37 1.11 Crystal Oscillator Considerations .1-45
Electrical Characteristics
Electrical Characteristics.2-1
Primitive Cells
Overview .3-1 Summary Tables .3-2 Primitive Cells .3-14 .3-16 AD3_LP/AD3D2_LP/AD3D4_LP .3-18 AD4_LP/AD4D2_LP/AD4D4_LP .3-20 AD5_LP/AD5D2_LP/AD5D4_LP .3-22 .3-25 ND3_LP/ND3D2_LP/ND3D4_LP .3-29 ND4_LP/ND4D2_LP/ND4D4_LP .3-35
Samsung ASIC
STDL131
Contents ND5_LP/ND5D2_LP/ND5D4_LP .3-37 ND6_LP/ND6D2_LP/ND6D4_LP .3-40 ND8_LP/ND8D2_LP/ND8D4_LP .3-44 .3-48 .3-52 NR4_LP/NR4D2_LP/NR4D4_LP .3-55 NR5_LP/NR5D2_LP/NR5D4_LP .3-57 NR6_LP/NR6D2_LP/NR6D4_LP .3-61 NR8_LP/NR8D2_LP/NR8D4_LP .3-65 .3-69 OR3_LP/OR3D3_LP/OR3D4_LP.3-73 OR4_LP/OR4D2_LP/OR4D4_LP.3-75 OR5_LP/OR5D2_LP/OR5D4_LP.3-77 XN2_LP/XN2D2_LP/XN2D4_LP .3-80 XN3_LP/XN3D2_LP/XN3D4_LP .3-82 XO2_LP/XO2D2_LP/XO2D4_LP .3-84 XO3_LP/XO3D2_LP/XO3D4_LP .3-86 AO2111_LP/AO2111D2_LP.3-92 AO22A_LP .3-96 AO222A_LP .3-104 AO2222D2_LP/AO2222D4_LP .3-105 AO311_LP.3-111 AO3111_LP.3-112 AO321_LP.3-115 AO322_LP.3-116 AO33_LP.3-118 AO331_LP.3-120 AO332_LP.3-122 OA2111_LP/OA2111D2_LP.3-128 OA22A_LP/OA22D2A_LP/OA22D4A_LP .3-132
STDL131
Samsung ASIC
Contents OA311_LP.3-147 OA3111_LP.3-148 OA32_LP.3-149 OA321_LP.3-150 OA322_LP.3-151 OA33_LP.3-153 SCG1_LP/SCG1D2_LP .3-154 SCG6_LP/SCG6D2_LP .3-170 SCG7_LP/SCG7D2_LP .3-172 SCG8_LP/SCG8D2_LP .3-174 SCG9_LP/SCG9D2_LP .3-176 SCG10_LP/SCG10D2_LP .3-178 SCG11_LP/SCG11D2_LP .3-180 SCG13_LP/SCG13D2_LP .3-184 SCG14_LP/SCG14D2_LP .3-186 SCG15_LP/SCG15D2_LP .3-188 SCG16_LP/SCG16D2_LP .3-190 SCG17_LP/SCG17D2_LP .3-192 SCG18_LP/SCG18D2_LP .3-194 SCG19_LP/SCG19D2_LP .3-196 SCG20_LP/SCG20D2_LP .3-198 SCG21_LP/SCG21D2_LP .3-200 SCG22_LP/SCG22D2_LP .3-202 DL1D2_LP.3-204 DL2D2_LP.3-205 DL5D2_LP.3-206 DL10D2_LP.3-207 .3-211 .3-216 Flip-Flops FD1_LP/FD1D2_LP .3-221
Samsung ASIC
STDL131
Contents FD1S_LP/FD1SD2_LP .3-223 FD1SQ_LP/FD1SQD2_LP .3-225 FD1Q_LP/FD1QD2_LP.3-227 FD2_LP/FD2D2_LP .3-229 FD2S_LP/FD2SD2_LP .3-231 FD2SQ_LP/FD2SQD2_LP .3-233 FD2Q_LP/FD2QD2_LP.3-235 FD3_LP/FD3D2_LP .3-237 FD3S_LP/FD3SD2_LP .3-239 FD3SQ_LP/FD3SQD2_LP .3-241 FD3Q_LP/FD3QD2_LP.3-243 FD4_LP/FD4D2_LP .3-245 FD4S_LP/FD4SD2_LP .3-248 FD4SQ_LP/FD4SQD2_LP .3-252 FD4Q_LP/FD4QD2_LP.3-255 FD5_LP/FD5D2_LP .3-257 FD5S_LP/FD5SD2_LP .3-259 FD6_LP/FD6D2_LP .3-261 FD6S_LP/FD6SD2_LP .3-263 FD7_LP/FD7D2_LP .3-265 FD7S_LP/FD7SD2_LP .3-267 FD8_LP/FD8D2_LP .3-269 FD8S_LP/FD8SD2_LP .3-272 FDS2_LP/FDS2D2_LP .3-276 FDS2S_LP/FDS2SD2_LP.3-278 FDS3_LP/FDS3D2_LP .3-280 FDS3S_LP/FDS3SD2_LP.3-282 FJ2_LP/FJ2D2_LP .3-284 FJ2S_LP/FJ2SD2_LP .3-286 FJ4_LP/FJ4D2_LP .3-288 FJ4S_LP/FJ4SD2_LP .3-291 FT2_LP/FT2D2_LP .3-294 Latches LD1_LP/LD1D2_LP.3-297 LD1Q_LP/LD1QD2_LP .3-299 LD2_LP/LD2D2_LP.3-301 LD2Q_LP/LD2QD2_LP .3-304 LD3_LP/LD3D2_LP.3-306 LD4_LP/LD4D2_LP.3-309 LD5_LP/LD5D2_LP.3-312 LD5Q_LP/LD5QD2_LP .3-314 LD6_LP/LD6D2_LP.3-316
STDL131
viii
Samsung ASIC
Contents LD6Q_LP/LD6QD2_LP .3-319 Holder BUSHOLDER_LP.3-321 Input Clock Driver Adders FA_LP/FAD2_LP .3-325 HA_LP/HAD2_LP .3-327 Multiplexers MX2_LP/MX2D2_LP/MX2D4_LP.3-330 MX4_LP/MX4D2_LP/MX4D4_LP.3-338 Integrated Clock-Gating Cells CGLN_LP/CGLND2/CGLND4.3-343 CGLP_LP/CGLPD2/CGLPD4 .3-346
Input/Output Cell
Overview .4-1 Summary Tables .4-2 Input Buffers PvIC_LP/PvICD_LP/PvICU_LP.4-11 PvIS_LP/PvISD_LP/PvISU_LP .4-17 Output Buffers PvOByz_LP .4-24 PvODyz_LP.4-40 PvOTyz_LP.4-60 Bi-Directional Buffers PvBaDyz_LP/PvBaUDyz_LP .4-95 .4-95 Input Clock Drivers PvSCKDCaby_LP .4-97 PvSCKDSaby_LP.4-107
Samsung ASIC
STDL131
Contents Oscillators PHSOSC(K1/K2/M1/M2/M3)_LP.4-119 PMSOSC(K1/K2/M1/M2)_LP .4-131 PSOSC(K1/K2/M1/M2)_LP .4-136 Buffers PTIPCI_LP .4-143 PTOPCI_LP.4-144 PTBPCI_LP .4-146 Power Pads VDD2(O/P/OP)_LP/VDD1IH_LP, VDD3(O/P/OP)_LP VSS1,2,3(I/O/P/IP/OP/T)_LP .4-147 VDD1(I/OP/T)_ABB_LP/VDD1IM_LP, VDD2I_LP, VDD1IH_LP, VDD3I_LP, VDD2, 3(I/OP/T)_ABB_LP/ VSS1,2,3(I/OP/T/BB)_ABB_LP, VBB1,2,3_ABB_LP .4-148 Analog Interfaces PIC_ABB_LP.4-151 PICC_ABB_LP .4-155 PICEN_ABB_LP.4-156 PIS_ABB_LP .4-158 POB_ABB_LP .4-162 POD_ABB_LP .4-166 POT_ABB_LP .4-168 Slot Cells .4-181 Common Slot Cell ECA0CA0_VBB_LP/ECA0A0D_VBB_LP .4-182
Compiled Memories
Overview .5-1 Compiled Memory Naming Convention.5-1 Characteristics Timing Power.5-2 Built-In Self Test Compiled Memories .5-4 Selection Guide Compiled Memories.5-5
STDL131
Samsung ASIC
Contents High-Density Compiled Memories SPSRAM_HDL .5-9 SPSRAMBW_HDL .5-24 SPSRAMR_HDL .5-39 DPSRAM_HDL .5-49 DPSRAMBW_HDL .5-60 DROM_HDL .5-71 MROM_HDL.5-83 ARFRAM_HDL .5-95 FIFO_HDL .5-115 CAM_HDL .5-127 Low-Power Compiled Memories SPSRAM_LPL .5-141 SPSRAMBW_LPL .5-151 DPSRAM_LPL .5-162 DPSRAMBW_LPL.5-173
PLL2099X .6-1
APPENDIX
Glossary Analog Terms Equivalent Standard loads 4-layer, 5-layer 6-layer Metal Interconnect Maximum Fanout Internal Macrocells Package Capabilities
Samsung ASIC
STDL131
NOTE
Introduction
Table Contents
Library Description Features Support Product Family. 1.4.1 Analog Core Cells. 1.4.2 Standard Logic Cells 1.4.3 Compiled Memory 1.4.4 Input/Output Cells 1-11 Timings. 1-14 Design Test (DFT) Methodology 1-22 Maximum Fanouts. 1-25 Package Capability Pitch Lead Count 1-32 Power Dissipation. 1-33 1.10 VDD/VSS Rules Guidelines. 1-37 1.11 Crystal Oscillator Considerations 1-45
Introduction
Library Description
Library Description
STDL131 Samsung's next generation Standard Cell library containing standard cells implemented Samsung's 0.18um, L18L process technology. focus Samsung's L18L process lowest leakage current. loff value that process 3pA/um typical conditions. This value least times smaller than that generic 0.18um process. Although L18L process little poor performance than that generic process, extremely save leakage current standby powers portable applications. Because L18L process based generic 0.18um process, L18, supports combined process chip that combination L18L process also supports cores libraries those process. excellently compensatory method poor performance. STDL131 library contains diverse application specific digital analog System-on-Chip (SoC) applications. Samsung provides full range cells within STDL131 library address challenges designing producing ultra power well high density devices that take advantage integration. With reduced power dissipation high density, STDL131 help reduce system cost leakage corrent applications such PDA, CDMA portable applications. STDL131 library supports gate counts million gates with usability. Logic memory densities respectively times better than STD110. STDL131 library also contains fully user configurable complied memories high density power applications. High capacity memory compilers designs also contain redundant elements memory repair. STDL131 library also supports various interface voltages standards. cells that drive 1.8V, 2.5V, 3.3V available 3.3V tolerant I/O's. Available standards include LVTTL, LVCMOS, PCI, OSC, ATA, AGP, PECL, SSTL2, GTLp, LVDS, 1.1. better support design, robust collection digital analog cores available. Digital cores include ARM7TDMI, ARM9TDMI, ARM920T, ARM940T from Ltd., well Teak TeakLite cores from Group. Analog cores include ADCs, DACs, CODECs, PLLs with various configurations frequency ranges. thick oxide process option allows high resolution operation analog cores with 3.3V power supply. addition, STDL131 library supports communication data transmission cores such 1.1, IEEE1284, IEEE1394 link controller, UART, controller, PCMCIA controller 10/100 ethernet MAC. Samsung's design methodology offers comprehensive timing driven design flow including automated time budgeting, tight floor plan synthesis integration, powerful timing analysis, timing driven layout. advanced characterization flow provides accurate timing data robust delay models L18L, 0.18um very deep sub-micron process technology. Static verification methods, such static timing analysis formal1 equivalence checking, provide effective verification methodology with variety simulators. Samsung's Design-for-Test (DFT) methodology supports full partial scan chain design, BIST, JTAG boundary scan, Built-in-Redundancy-Analysis (BIRA) reparable SRAM. Samsung provides full test ready cores with efficient core test integration methodology.
Samsung ASIC
STDL131
Features
Introduction
Features
Robust 1.8V standard cell library including processor, DSP, analog cores. 0.18µm CMOS process technology with optional metal layers. High gate count design million gates with utilization layer metal. Typical input NAND gate delay 80ps with fanout 3pA/um Ioff value typical condition. Characterized industrial (-40°C 85°C) commercial (0°C 70°C) temperature ranges. Robust digital cores Hard macro cells ARM7TDMI, ARM9TDMI, ARM920T, ARM940T, Teak, TeakLite. core peripherals AMBA, controller, SDRAM controller, Interrupt controller, IIC, WDT, RTC. Soft macro cells USB1.1, IrDA, 16C450 16C550 UART, Fast Ether MAC, P1394a LINK, IEEE1284, controller, PCMCIA controller. Ultra Voltage (1.8V) High Resolution (3.3V) Analog Cores Analog core supply voltages -1.8V, 2.5V, 3.3V. ADC: 10-bit (500K, 30MHz, 1.8V) DAC: 8-bit (2MHz, 50MHz, 1.8V) CODEC: 14-bit Sigma-Delta (8kHz 11kHz, 2.5V) PLL: 1.8V FSPLL (20MHz 150MHz, 20MHz 300MHz 50MHz 500MHz) combine high resolution analog cores with 2.5V 3.3V supply voltage STD130 library with STDL130 library. more information regarding high resolution analog cores, please refer STD130 databook. Fully User Configurable SRAM High density power memory configurations Single port (1RW, 1R), dual port (2RW), multi port (1R1W 2R2W) Zero hold time synchronous mode Bit-write capability bank architecture Flexible aspect ratio 512K-bit single port SRAM 256K-bit dual port SRAM 512K-bit diffusion metal programmable 16K-bit multi port register files 64K-bit FIFOs 32K-bit (Content Addressable Memory) megabit reparable SRAM with redundancy. Full Compliment Cells 1.8V/2.5V/3.3V drive 3.3V/5.0V tolerant I/Os levels (high, medium, slew rate control Minimum wire bonded pitch 70µm single line I/Os 35µm staggered I/Os Drive capabilities 24mA drive I/Os tolerant I/Os
STDL131
Samsung ASIC
Introduction
Features
Standard Interface compliant,33/66MHz, tolerant compliant, full speed/low speed, 3.3V SSTL2 Class-I SDRAM interface, 200MHz ATA4/UDMA66, 3.3V, tolerant compliant, 66MHz 133MHz 266MHz PECL, 200MHz single ended, 500MHz differential point-to-point Ainterface HSTL, 300MHz, 1.5V SRAM interface with programmable output impedance control Swap pre-charge, pre-charge PCI-X, compliant, 133MHz, 3.3V Fully Integrated software support Logic synthesis: Synopsys Design compiler Physical synthesis: Synopsys Physical compiler Logic simulation: Cadence Verilog Cadence NC-Verilog, Mentor ModelSim-VHDL, Mentor ModelSim-Verilog, Synopsys VCS. DFT, scan insertion ATPG: Synopsys TestGen, Synopsys TestCompiler, Synopsys TetraMax, Mentor Fastscan. Static timing analysis: Synopsys PrimeTime analysis: Avant! Star-RCXT Power analysis: Synopsys DesignPower, CubicPower (Samsung in-house tool). Formal verification: Synopsys Formality, Avant! Design VERIFYer, Verplex Tuxedo-LEC Fault simulation: Cadence Verifault Delay calculator: CubicDelay (Samsung in-house tool). Floor planner: Avant! PlanerPL, CubicPlan (Samsung in-house tool). Place Route: Avant! Apollo, Cadence Silicon Ensemble LVS: Dracula, Hercules, Calibre Easy Accurate Clock Tree Insertion user selectable clock tree cells Accurate pre-layout post-layout correlation Insertion delay, skew, transition time management Clock tree information file generation Tightly coupled with in-house delay calculator, CubicDelay. more information flow, refer "CTS Flow with Clock Tree Cell User Guide CubicDelay" included Samsung Design Kit.
Samsung ASIC
STDL131
Support
Introduction
Support
Samsung provides effective solution multi-million gate designs very deep submicron technology. large designs, static timing verification methodology will reduce design cycle time reduce ever increasing time-tomarket pressure. design-for-test (DFT) methodology service enables phases test insertion, test pattern generation, fault grading resulting highest test coverage. STDL131 design methodology supports rich collection industry standard tools from Cadence, Synopsys, Mentor Graphics, Avant! Solaris platforms. Customers choose from among industry leading tools design capture, synthesis, simulation, layout. Several powerful proprietary software tools seamlessly integrated design kits improve design quality. STDL131 design methodology uses proprietary delay calculator, CubicDelay, high timing simulation accuracy. Cell delay calculated based matrix delay parameters each macrocell signal interconnection delay calculated based tree analysis.
Product Family
STDL131 library includes following design elements: Analog core cells Digital core cells Internal macrocells Compiled memory macrocells Input/Output cells 1.4.1 ANALOG CORE CELLS Introduction Analog Cores (see Appendix glossary analog terms) Samsung leading supplier cell based mixed signal design elements. leading supplier mixed signal elements, Samsung more analog design experience than other ASIC suppliers. Analog cell development been will continue part strategic focus Samsung ASIC. Symbolic representations analog cells supplied design entry Customers Samsung design technology center replaced with cell physicals during place route. Samsung design methodology uses same automatic layout verification tools analog cells digital cells. Mixed signal designs processed same production line pure digital designs. Samsung's analog core family consists ADCs, DACs, PLLs, CODECs. brief description each follows. Analog-to-Digital Converter Analog-to-digital converters, ADCs, provides link between analog world digital systems. produces digital output, function analog input, f(A) While input assume infinite number values, output takes only finite digital values determined converter's resolution output word length. Thus, must approximate each input level with these values. This process also called quantization.
STDL131
Samsung ASIC
Introduction
Product Family
digital systems, input signal amplitude, sampled discrete time intervals then quantized into discrete steps output digital value, sampling time interval also known sampling frequency. Digital-to-Analog Converter Digital-to-Analog Converters, DACs, digital value analog signal conversion circuits. output form current voltage wave form. DACs provide interface between digital systems analog world. DACs employed variety applications from display systems voice synthesizers automatic test systems, digital controlled attenuators, process control actuators. Figure shows functional block diagram basic DAC. input digital value, made stream bits. output analog current voltage quantity, related input KVREF
where scale factor, VREF reference voltage, resolution expressed total number bits, coefficients. output exhibits discrete voltage levels ranging from zero maximum value
Vo(max)= VREF
with minimum step change given
Figure 1-1.
Functional Block Diagram Basic
Digital Data Input
Analog Output
Samsung ASIC
STDL131
Product Family
Introduction
Sigma-Delta ADC/DAC Samsung's L18L process offers high speed high density, reduced accuracy signal range (dynamic range) analog components. Hence, exchange digital complexity resolution time resolution signal amplitude needed. good solution this trade-off over sampling data converter. over sampling sigma-delta converter ideal slow speed (audio band) applications. It's noise shaping (sigma-delta) feature produces high resolution output with signal noise ratio 100dB. ADC, analog signal converted differential signal then filtered with anti-aliasing filter. sigma delta modulator converts signal into over sampled noise-shaping 1-bit pulse density modulated (PDM) signal. digital decimation filter then rejects out-of-band noise outputs 16-bit high resolution digital signal that down sampled sampling rate, DAC, digital data over sampled interpolation filter converted noise shaped 1-bit signal through digital sigma-delta modulator. analog post filter rejects out-of-band noise. anti-image filter then rejects sampling images outputs high resolution analog signal. Phase Locked Loop Samsung's cores implemented analog function provide frequency multiplication enabling designers synchronize chip level clock networks common reference signal. past, designers wishing incorporate into digital design only options: special mixed signal process, typically expensive process combing bi-polar CMOS processing same silicon, implement analog functions. digital design requiring very large silicon area that could implemented standard CMOS digital process. This type design usually exhibits poor locking time. Samsung's cores analog PLLs implemented standard digital CMOS process. Advantages Samsung's cores are: Require only off-chip passive components implement function. need expensive mixed signal (bi-polar CMOS) process. Provide faster locking time than full digital implementation. Have jitter characteristics. Customer Service Technical Support Samsung provides full support customers needing analog cores. Support provided through Samsung's worldwide Technology Design Centers. addition, Samsung analog design engineers available design customize Samsung analog cores meet specific customer needs. Since mixed signal design quite different from digital design terms design techniques, layout, test methodology, Samsung provides mixed signal technical guide describing development steps. addition, each core fully documented delivered with data sheet. following description analog core data sheets:
STDL131
Samsung ASIC
Introduction
Product Family
Core Preview Describes main features specifications core that under development. Some specifications, such exact pin-out, finalized time publication. purpose this document provide customers with advanced product planning information. Preliminary Data Sheet Completely describes core. preliminary data sheet contains feature list, applications notes, timing diagrams, theory operation, core information, test guide, layout guide, preliminary AC/DC electrical information. electrical information based worst case simulation data prototype silicon performance. purpose this data sheet allow customers confidently begin active development with core. Final Data Sheet Updated version preliminary data sheet reflecting fully characterized silicon performance. Updates include more complete tighter electrical specifications. purpose this data sheet communicate confirmed performance core after full characterization passing qualification.
Samsung ASIC
STDL131
Product Family
Introduction
1.4.2 STANDARD LOGIC CELLS Samsung standard cell library designed enable designers achieve high-integration with best performance STDL131. addition, this standard cell library carefully verified silicon ensure much higher manufacturability. this, System-On-Chips (SoC) designed using these standard cells will obtained much higher yield. Rich standard cells, consisting about cells, with least four drive strengths have been optimized specifically synthesis place route tools. cells were selected achieve best performance with synthesis tool give designers elements need create high-integration designs. Each cell been carefully hand-crafted provide optimal solution high-integration applications with best performance. Each cells been very accurately modeled both timing power guarantee timing closure eliminate many meaningless iterative design cycles. models carefully qualified tested using in-house library automation environment. Some features STDL131 standard cell library summarized follows: Complete optimized library with synthesis place route tool Hand-crafted layouts optimal densities each process manufacturing cost Reducing design time Providing more accurate timing power Complete interfaces with popular tools STDL131 standard cell library contains protection diode cell. protection diode cell used avoid antenna effect. During place route, router connect wires input gates cells that longer than maximum length allowable antenna effect rule. protection diode cell used this case diode close input gates which meet rule. Also, protection diode added input drivers softmacro cores. protection diode cell composed forward reverse diodes. included this databook. addition, STDL131 standard cell library contains several filler cells. During place route, filler cells used connect power ground rails across area including cells. filler cells also used make sure that gaps occur between well implant layers which cause some design rule violations.
STDL131
Samsung ASIC
Introduction
Product Family
1.4.3 COMPILED MEMORY STDL131 library memories fully user configurable provided through compilers. different memory types provided STDL131 targeted different types applications follows: STDL131HD compiled memory targeted high density applications STDL131LP compiled memory targeted power applications Twelve types STDL131HD high density compiled memories available follows: Single-port synchronous SRAM with without bit-write. Dual-port synchronous SRAM with without bit-write. Single-port asynchronous SRAM with without bit-write. Single-port synchronous SRAM redundancy. Synchronous diffusion programmable metal programmable ROM. Multi-port asynchronous register file. Synchronous FIFO (First-in-First-Out) Memory). Synchronous (Content Addressable Memory). types STDL131LP power compiled memories available follows: Single-port synchronous SRAM with without bit-write. Dual-port synchronous SRAM with without bit-write. Single-port asynchronous SRAM with without bit-write. Synchronous memories fully synchronous rising edge clock have zero wait state. They also have optional write capability. Address, DataIn, other control pins have zero hold time. Asynchronous memories have synchronous write operation asynchronous read operation. Multi-port register files have synchronous write operation rising edge clock asynchronous read operation. Four types configurations available multi port register files. They port read write), port read, write read, write), port read write). STDL131 library contains types speciality memories: FIFO (First-InFirst-Out) (Content Addressable Memory). FIFOs, widely used communications buffering applications, fully synchronous rising edge clock. CAMs, widely used cache tables translation look-up tables, also fully synchronous rising edge clock. Memory becoming much more dominant larger memory required designs. STDL131 library memory compilers support high capacity memories, from 64Kb with redundancy. These repairable memories redundancy scheme BIRA (Built-In-Redundancy-Analysis) help guarantee higher yield. number redundant rows varies with memory size. STDL131 compiled memories provide power down mode significantly reduce power during read write operation. addition, stand-by mode provided which memory contents outputs stable power greatly reduced.
Samsung ASIC
STDL131
Product Family
Introduction
STDL131LP, power compiled memories, also partial array activation architecture divided word line structure reduce power even more. bank architecture provided STDL131 memories, except dual port synchronous SRAM specialty memories, improve performance reduce power. this bank architecture, only bank active while other bank stand-by mode. Flexible memory aspect ratios provided facilitate floor planning design. addition, automated datasheet generator documents memory configuration, timing, aspect ratio power consumption. Physical abstract data, also called phantoms black boxes, Silicon Ensemble Apollo generated provided. BIST (Built-In Self Test) circuitry provided most STDL131 compiled memories. BIST circuits designed detect fault types that impact functionality memory. BIST circuitry generated soft macro based BIST generator. BIST generator generates both individual BIST netlist each memory shared BIST netlist memories used design. However, when several memories used design, better generate shared BIST netlist eliminate redundancy BIST circuitry over generating BIST circuits each memory.
STDL131
1-10
Samsung ASIC
Introduction
Product Family
1.4.4 INPUT/OUTPUT CELLS There about 1000 different cells STDL131 library designer choose from. Three types output buffers bi-directional buffers (non-inverting, tri-state, open drain) available range drive capabilities from 24mA 1.8V, 2.5V, 3.3V drive outputs, from 3.3V tolerant cells. Three levels slew rate control provided each buffer type except drive buffers, reduce output power ground noise signal ringing, especially simultaneously switching outputs. buffers have been fully characterized protection latch-up resistance. Test logic provided enable efficient parametric testing input buffers including LVCMOS level converters, Schmitt trigger input buffers, clock drivers, oscillator buffers. 100K pull-down pull-up resistors optional features. 1.4.4.1 Applications
support mixed voltage environments, LVCMOS Schmitt trigger cells available 1.8V, 2.5V, 3.3V interface 3.3V, tolerant interface. application diagram follows. Figure 1-2. Applications
1.8V 1.8/ 3.3V tolerant 1.8V 2.5V Internal Circuit 2.5/ tolerant operating voltage: 1.8V 2.5V 3.3V 3.3/ tolerant
3.3V
Input Buffer
Output Buffer
Samsung ASIC
1-11
STDL131
Product Family
Introduction
1.4.4.2
Cell Drives Options
provide flexibility, designer choose from various output current drive levels. choice current drive level affects propagation delay noise. Slew rate control helps decrease system noise output signal overshoot undershoot caused switching output buffers. output signal edge slew rates slowed down selecting high slew rate control cells. 1.4.4.3 3.3V Tolerant Buffers
STDL131 library optimized Samsung's L18L, 0.18µm drawn, process technology. L18L process technology optimized operation 1.8V. specified maximum voltage across thin gate oxide 1.95V avoid gate oxide breakdown. special circuit available 3.6V tolerant LVCMOS driver 6mA. This 3.6V tolerant driver used normal 1.8V buffer. Figure 1-3. 3.3V Tolerant Buffers
1.8V Output voltage 1.8V Open drain output 3.3V tolerant input Tri-state output Bi-directional 0.18µm 1.8V process Normal 3.3V process 1.8V 3.3V
STDL131
1-12
Samsung ASIC
Introduction
Product Family
1.4.4.4
Tolerant Buffers
Samsung's L18L process thick gate oxide option that optimized 3.3V circuit operation. specified maximum voltage across gate oxide this process option 5.25V avoid gate oxide breakdown. special circuit available 5.25V tolerant LVCMOS driver 6mA. This 5.25V tolerant driver used normal 2.5V 3.3V buffer. Figure 1-4. Tolerant Buffers
2.5V/3.3V Output voltage 2.5V/3.3V Open drain output tolerant input Tri-state output Bi-directional 0.18µm 3.3V process Normal 5.0V process 2.5V/3.3V 5.0V
1.4.4.5
Buffers
buffers designed industry standard high performance local applications. STDL131 library offers input, output, bi-directional buffers 33MHz 66MHz operation compliant with local specification 2.2. 1.4.4.6 (Universal Serial Bus) Buffers
STDL131 library offers full speed speed compliant buffers. 1.4.4.7 Other Buffers
STDL131 library also offers various other buffers including HSTL, SSTL, GTLp, AGP, PECL, LVDS. more information about buffers that included this data book, please contact your local Samsung Technology Design Centers.
Samsung ASIC
1-13
STDL131
Timings
Introduction
Timings
1.5.1 WIRE LENGTH LOAD Table 1-1, Table Appendix show equivalent standard load matrix metal layer interconnect. equivalent standard load values function gate count fanout. These values based capacitive loading used with wire length estimates which affect propagation delay. Equivalent Standard Loads 4-layer 5-layer Metal Interconnect
Fanouts 0.795 0.893 1.224 1.374 4.104 7.429 8.171 8.915 9.944 10.647 12.267 13.781 17.931 21.816 25.456 28.856 33.106 37.122 41.625 0.755 0.848 1.163 1.305 3.899 7.057 7.761 8.470 9.446 10.116 11.653 13.092 17.035 20.726 24.183 27.413 31.450 35.265 39.545 43.045 48.265 1.635 2.015 2.517 2.799 6.291 8.427 8.952 10.269 12.015 12.681 15.511 16.214 21.675 26.935 32.411 35.562 39.990 48.001 52.812 1.553 1.915 2.391 2.659 5.976 8.005 8.505 9.755 11.415 12.047 14.736 15.403 20.590 25.588 30.791 33.785 37.990 45.602 50.173 60.980 68.374 2.297 2.840 3.533 4.370 8.021 9.480 10.427 11.297 12.690 13.663 15.875 17.944 23.578 28.858 33.799 38.419 44.076 49.423 55.417 2.183 2.698 3.356 4.151 7.620 9.005 9.905 10.732 12.057 12.980 15.082 17.047 22.399 27.415 32.108 36.498 41.872 46.952 52.645 65.492 73.437 3.204 4.104 5.909 6.312 10.181 10.929 12.165 13.127 14.722 15.828 18.354 20.712 27.149 33.181 38.826 44.106 50.600 56.736 63.620 3.045 3.899 5.614 5.998 9.671 10.381 11.557 12.472 13.986 15.037 17.437 19.677 25.791 31.521 36.885 41.901 48.070 53.899 60.438 72.098 80.842 3.840 4.907 7.234 7.549 11.003 12.000 13.326 14.413 16.147 17.344 20.086 22.649 29.643 36.200 42.344 48.068 55.145 61.836 69.338 3.647 4.661 6.872 7.171 10.452 11.399 12.659 13.692 15.340 16.476 19.082 21.517 28.161 34.389 40.218 45.665 52.387 58.744 65.872 76.480 85.755 4.702 5.976 8.277 9.194 12.494 13.362 14.814 16.045 17.962 19.285 22.314 25.145 32.879 40.127 46.911 53.251 61.094 68.503 76.812 4.468 5.677 7.864 8.734 11.870 12.694 14.074 15.242 17.064 18.320 21.198 23.887 31.236 38.122 44.564 50.588 58.039 65.078 72.972 81.466 91.350 5.263 6.893 10.830 12.147 13.385 14.297 15.836 17.169 19.210 20.616 23.840 26.854 35.088 42.803 50.027 56.775 65.137 73.039 81.899 5.000 6.549 10.289 11.539 12.716 13.582 15.045 16.311 18.250 19.584 22.647 25.511 33.334 40.663 47.525 53.937 61.879 69.387 77.805 86.862 97.397 7.047 8.326 11.748 12.744 14.358 15.116 16.726 18.102 20.299 21.822 25.305 28.559 37.435 45.751 53.535 60.812 69.767 76.259 87.718 6.694 7.909 11.161 12.106 13.639 14.360 15.889 17.196 19.283 20.732 24.039 27.131 35.562 43.464 50.858 57.771 66.279 74.316 83.332 96.755 108.492 10.096 11.992 14.370 16.594 18.222 19.155 21.169 22.883 24.356 25.055 27.076 28.954 41.425 53.533 58.472 63.080 75.133 77.242 91.773 9.592 11.391 13.651 15.763 17.311 18.196 20.110 21.740 23.137 23.803 25.722 27.507 39.354 50.856 55.549 59.927 71.377 73.379 87.185 101.602 113.482 17.588 20.442 22.346 24.009 26.590 28.159 31.078 33.533 35.700 36.732 39.708 42.474 50.795 58.578 65.850 72.631 83.328 93.437 104.769 16.708 19.421 21.228 22.809 25.261 26.751 29.525 31.856 33.915 34.895 37.722 40.350 48.255 55.649 62.557 69.000 79.161 88.765 99.531 123.818 138.836 34.192 40.696 43.582 48.909 51.212 53.340 56.183 59.104 63.417 67.431 75.316 78.842 95.393 106.937 123.366 138.822 158.169 166.500 196.954 32.482 38.661 41.403 46.464 48.651 50.673 53.374 56.149 60.246 64.059 71.551 74.899 90.624 101.590 117.198 131.881 150.259 158.175 187.106 246.722 251.716
Table 1-1.
Gate Count 5000 10000 50000 100000 150000 200000 300000 400000 500000 600000 800000 1000000 1500000 2000000 2500000 3000000 4000000 5000000 6000000 5000 10000 50000 100000 150000 200000 300000 400000 500000 600000 800000 1000000 1500000 2000000 2500000 3000000 4000000 5000000 6000000 7000000 8000000
STDL131
1-14
Samsung ASIC
Introduction
Timings
Table 1-2.
Gate Count 5000 10000 50000 100000 150000 200000 300000 400000 500000 600000 800000 1000000 1500000 2000000 2500000 3000000 4000000 5000000 6000000 7000000 8000000
Equivalent Standard Loads 6-layer Metal Interconnect
Fanouts 1.472 1.814 2.265 2.519 5.661 7.584 8.057 9.242 10.814 11.413 13.960 14.592 19.507 24.242 29.169 32.005 35.990 43.202 47.531 57.769 64.775 2.066 2.557 3.181 3.933 7.218 8.531 9.383 10.167 11.421 12.297 14.287 16.149 21.220 25.972 30.419 34.576 39.669 44.480 49.875 62.045 69.570 2.883 3.694 5.318 5.681 9.163 9.836 10.948 11.814 13.250 14.246 16.519 18.641 24.435 29.862 34.944 39.694 45.539 51.062 57.257 68.303 76.586 3.456 4.417 6.511 6.795 9.903 10.799 11.994 12.972 14.533 15.610 18.078 20.383 26.679 32.580 38.100 43.261 49.631 55.653 62.405 72.454 81.242 4.232 5.377 7.448 8.275 11.244 12.025 13.332 14.440 16.167 17.356 20.082 22.631 29.592 36.116 42.220 47.927 54.984 61.653 69.131 77.179 86.541 4.738 6.204 9.748 10.933 12.047 12.868 14.251 15.452 17.289 18.555 21.456 24.169 31.578 38.523 45.025 51.098 58.624 65.736 73.708 82.289 92.271 6.342 7.494 10.572 11.470 12.923 13.604 15.053 16.291 18.269 19.639 22.775 25.702 33.690 41.177 48.181 54.732 62.791 68.437 78.946 91.663 102.781 9.086 10.793 12.933 14.935 16.399 17.240 19.053 20.596 21.921 22.549 24.370 26.059 37.283 48.181 52.625 56.773 67.620 69.517 82.596 96.253 107.509 15.830 18.399 20.112 21.608 23.931 25.344 27.970 30.181 32.129 33.059 35.738 38.226 45.716 52.720 59.265 65.368 74.996 84.092 94.293 117.301 131.529 30.773 36.627 39.224 44.017 46.090 48.005 50.564 53.194 57.074 60.688 67.785 70.958 85.854 96.244 111.029 124.940 142.352 149.850 177.259 233.736 238.466
0.716 0.805 1.102 1.236 3.694 6.687 7.354 8.023 8.950 9.582 11.041 12.403 16.137 19.635 22.911 25.970 29.795 33.409 37.462 40.779 45.724
Samsung ASIC
1-15
STDL131
Timings
Introduction
1.5.2 TIMING PARAMETERS This section defines discusses timing parameters. 1.5.2.1 Rise Fall Transition Time Rise time, fall time, defined time that waveform takes transition between supply voltage (Figure 1-5). Figure 1-5. Rise Fall Transition Time
1.5.2.2
Propagation Delay
Propagation delay, defined time from when input waveform reaches supply voltage time that output waveform reaches supply voltage (Figure 1-6). Figure 1-6. Propagation Delay
tPLH
tPHL
tPLH
tPHL
STDL131
1-16
Samsung ASIC
Introduction
Timings
1.5.2.3
Setup Hold Time
Setup time, tSU, defined minimum time that data signal must stable before active clock transition. change data signal within this time results timing violation, result invalid data being clocked into circuit (Figure 1-7). Hold time, tHD, defined minimum time that data signal must remain valid after active clock transition. change data signal within this time results timing violation, result invalid data being clocked into circuit (Figure 1-7). Figure 1-7. Setup Hold Time
1.5.2.4 Recovery Time Recovery time, tRC, defined time between release asynchronous control signal from active state circuit next active clock edge (Figure 1-8). active clock edge occurs soon after release control signal, violation occurs that result erroneous value being clocked circuit. Figure 1-8. Recovery Time
Samsung ASIC
1-17
STDL131
Timings
Introduction
1.5.2.5
Removal Time
Removal time, tRM, defined minimum time between active clock edge release asynchronous control signal from active state (Figure 19). control signal released from active state soon after active clock edge, violation occurs that result erroneous value being clocked INTO circuit. Figure 1-9. Removal Time
1.5.2.6
Minimum Pulse Width
Minimum pulse width, tPW, defined minimum time allowed high phase signal measured time between rising falling edges reaching supply voltage (Figure 1-10). short pulse width results timing violation result signal being recognized circuitry. Figure 1-10. Minimum Pulse Width
tPWH tPWL
1.5.2.7
Minimum Period
Minimum period, tPRD, defined minimum allowable time complete cycle signal (Figure 1-11). short period results timing violation result signal being recognized circuitry. Figure 1-11. Minimum Period
tPRD
STDL131
1-18
Samsung ASIC
Introduction
Timings
1.5.3 BEST WORST CASE CONDITIONS timing value best-case (worst-case) calculated using derating factor derived from following equations: (TWC) TNOM where, (TWC) best-case (worst-case) timing. local process derating factor which different value according each cell, local temperature derating factor which different value according each cell, local voltage derating factor which different value according each cell, TNOM nominal timing characterized under typical-process, 25°C 1.8V power supply. best-case (worst-case) timing values determined picking proper derating values from Table 1-3, Table Table 1-5. Derating factors conditions between those shown tables determined linear interpolation. 1.5.4 DERATING FACTORS STDL131 Cell timing primarily determined cell drive capability loading determined cell input capacitance wiring. following critical variables also affect timing system environment design: Process variation Supply voltage Junction Temperature Process variation occurs manufacturing environments variation change physical characteristics. variation affects electrical characteristics devices, increasing decreasing performance power. other hand, design chips which operate wide range voltage temperature environments, have consider typical-case, worstcase best-case conditions compensate variations. yield much more timing accuracy, cell-specific local derating factor used STDL131 standard cells. example, process, temperature voltage derating factors cell follows Table 1-3, Table Table respectively. Table 1-3. STDL131 Cell Process Derating Factor (KP) Slow 1.2227 1.000 Fast 0.8833
Process Factor (KP) Table 1-4. Temp. Table 1-5. Voltage (oC)
STDL131 Cell Temperature Derating Factor (KT) 1.1186 1.0721 1.0543 1.000 0.9832 0.9500
STDL131 Cell Voltage Derating Factor (KV) 1.65 1.1303 1.80 1.000 1.95 0.9340
Samsung ASIC
1-19
STDL131
Introduction
1.5.5
DELAY MODEL
STDL131 cell timing characteristics consist following components: Cell propagation delay from input output transitions based input waveform slope, fanout distributed interconnection wire resistances capacitances. Interconnection wire delay. Timing requirement parameters including time, hold time, recovery time, skew time, minimum pulse width. Derating factors junction temperature, power supply voltage, process variation. accomplish accurate timing model, dimensional table look-up delay model been developed. index variables this table input waveform slope output load capacitance (Figure 1-12). Samsung's design methodology supports n-dimensional table model, even though dimensional model used. Figure 1-12. 2-Dimensional Table Delay Model
Propagation Delay [ns] Input Waveform Slope [ns] Load [pF]
Table shows propagation delay data 2-input NAND cell. data this table high-to-low transition delay times from input pins output pin. number points values index variables differ each cell. Table 1-6.
CAP[pF] SLOPE[n] 0.019 0.186 0.355 0.693 1.200
Table Delay Model Example
0.008 0.04718 0.07759 0.09257 0.10700 0.11522 0.032 0.08909 0.12534 0.15618 0.19125 0.21987 0.062 0.14084 0.17733 0.21600 0.27178 0.32093 0.124 0.24748 0.28437 0.32292 0.40037 0.48507 0.215 0.40390 0.44105 0.47948 0.55744 0.67301 0.337 0.61356 0.65087 0.68926 0.76677 0.88466
STDL131
1-20
Samsung ASIC
Introduction
Notice that 5-by-6 table used. This general table delay model provides great flexibility well high accuracy since extensive software revisions required when cell library updated. other timing components, such interconnection wire delay, timing requirement parameters derating factors characterized commonly accepted industry. Figure 1-13 summarizes features STDL131 library delay model. Figure 1-13. Features Delay Model
dimensional table delay model output loading input waveform slope used. rise fall times delay times cell instances calculated recursively. input waveform slope each primary input loading capacitance each primary output assigned individually default. delays cells interconnection wires defined. effect distributed interconnection wire resistances capactitances cell delay analysed using lumped capacitances.
Samsung ASIC
1-21
STDL131
Design Test (DFT) Methodology
Introduction
Design Test (DFT) Methodology
Samsung's libraries designed with mind. Samsung's methodology includes ability include full partial scan path testing, boundary-scan JTAG board level testing, Memory BIST, analog testing. brief description features Samsung's scan, BIST, JTAG well more detailed discussion boundary scan architecture follows. 1.6.1 SCAN DESIGN Multiplexed scan flip-flops that minimize area delay overhead needed implement scan design. Automated design rule checking, scan insertion, test pattern generation High fault coverage synchronous designs
1.6.2 BIST (BUILT-IN SELF-TEST) Efficient test solution compiled memory macrocells speed parallel testing multiple memories Combination with internal scan design core testing
1.6.3 BOUNDARY-SCAN IEEE 1149.1 JTAG boundary scan registers implemented with primitive cells Boundary -Scan Description Language (BSDL) board testing combed with internal scan design core testing
JTAG Boundary Scan Architecture Boundary scan architecture contains (Test Access Port), controller, instruction register, group test data registers. instruction test data registers separate shift-register-based paths connected parallel with common serial data input common serial data output. common serial data input output connected TAP, signals. controller selects alternative instruction test data register paths between TDO. schematic view level design JTAG test logic architecture shown Figure 1-14.
STDL131
1-22
Samsung ASIC
Introduction
Design Test (DFT) Methodology
Figure 1-14. JTAG Test Access Port (TAP) Block Diagram
Scannable Register Device Identity Register Instruction Register Controller Bypass Register TEST ACCESS PORT (TAP)
SYSTEM LOGIC
Multiplexer
Boundary Scan Path
Functional Block Descriptions (Test Access Port) general-purpose port that provides access many test support functions built into component including test logic. includes three inputs (TCK -Test Clock Signal; -Test Mode Signal; -Test Data Input) output (TDO -Test Data Output) required test logic. optional fourth input (TRSTN Test Reset) provided asynchronous initialization test logic. values applied pins sampled rising edge TCK, value placed changes falling edge TCK. Controller controller receives TCK, interprets signals TMS, generates clock control signals both instruction test data registers other parts test circuit required. Instruction Register/Instruction Decoder Test instructions shifted into held instruction register. Test instructions include tests performed test data register addresses accessed. basic 3-bit instruction register instruction decoder provided macrofunctions library. Test Data Registers Test data registers include bypass register, boundary scan register, device identification register other design specific registers. Only bypass boundary scan registers mandatory; rest optional.
Samsung ASIC
1-23
STDL131
Design Test (DFT) Methodology
Introduction
Test Data Registers Description Bypass register: bypass register provides single-bit serial connection through circuit when none other test data registers selected. used allow test data flow through given device other components product without affecting normal operation. Boundary scan register: boundary scan register detects typical production defects board interconnects, such opens, shorts. also allows access component inputs outputs when testing their logic sample flow-through signals. Special boundary scan register macrocells provided this purpose. Design-specific test data register: These optional registers provided allow access designspecific test support features integrated circuit, such self-test scan test. Device identification register: This optional test data register that allows manufacturer part number revision identified. 32-bit identification register partitioned into four fields:
Device version identifier field Device part number Manufacturer's JEDEC number
first four bits beginning from field bits field bits field tied High
ASIC designer free fill version part number manner long twenty bits used. Samsung's JEDEC code: decimal 1001110 Continuation field bits) 0000 Contents device identification register: XXXX XXXXXXXXXXXXXXXX 0000 1001110 Users define these fields.
STDL131
1-24
Samsung ASIC
Introduction
Maximum Fanouts
Maximum Fanouts
1.7.1 INTERNAL MACROCELLS maximum fanouts STDL131 primitive cells tabulated Table Appendix Note that these fanout limitation values calculated when rise fall times input signal 0.186ns. Depending rise fall times, maximum fanout limitations varied case case. following table maximum fanout values pins STDL131 internal macrocells listed. Table 1-7. Maximum Fanouts Internal Macrocells (When input tR/tF 0.186ns, fanout (SL) 0.00803pF)
Cell Name
ad2_lp ad2b_lp ad2bd2_lp ad2bd4_lp ad2bd8_lp ad2d2_lp ad2d4_lp ad2d8_lp ad3_lp ad3d2_lp ad3d4_lp ad4_lp ad4d2_lp ad4d4_lp ad5_lp ad5d2_lp ad5d4_lp ao21_lp ao211_lp ao2111_lp ao2111d2_lp ao211d2_lp ao211d4_lp ao21d2_lp ao21d4_lp ao22_lp ao221_lp ao221d2_lp ao221d4_lp ao222_lp ao2222_lp ao2222d2_lp ao2222d4_lp ao222a_lp ao222d2_lp ao222d4_lp ao22a_lp ao22d2_lp ao22d4_lp ao31_lp ao311_lp
Cell Name
ao3111_lp ao31d2_lp ao31d4_lp ao32_lp ao321_lp ao322_lp ao32d2_lp ao33_lp ao331_lp ao332_lp busholder_lp cgln_lp cglnd2_lp cglnd4_lp cglp_lp cglpd2_lp cglpd4_lp dl1d2_lp dl2d2_lp dl5d2_lp dl10d2_lp fa_lp fad2_lp fd1_lp fd1d2_lp fd1q_lp fd1qd2_lp fd1s_lp fd1sd2_lp fd1sq_lp fd1sqd2_lp fd2_lp fd2d2_lp fd2q_lp fd2qd2_lp fd2s_lp fd2sd2_lp fd2sq_lp fd2sqd2_lp fd3_lp fd3d2_lp fd3q_lp fd3qd2_lp fd3s_lp fd3sd2_lp fd3sq_lp fd3sqd2_lp fd4_lp fd4d2_lp
Output
Maximum Fanouts
10000
Output
Maximum Fanouts
Samsung ASIC
1-25
STDL131
Maximum Fanouts
Introduction
Cell Name
fd4q_lp fd4qd2_lp fd4s_lp fd4sd2_lp fd4sq_lp fd4sqd2_lp fd5_lp fd5d2_lp fd5s_lp fd5sd2_lp fd6_lp fd6d2_lp fd6s_lp fd6sd2_lp fd7_lp fd7d2_lp fd7s_lp fd7sd2_lp fd8_lp fd8d2_lp fd8s_lp fd8sd2_lp fds2_lp fds2d2_lp fds2s_lp fds2sd2_lp fds3_lp fds3d2_lp fds3s_lp fds3sd2_lp fj2_lp fj2d2_lp fj2s_lp fj2sd2_lp
Output
Maximum Fanouts
Cell Name
fj4_lp fj4d2_lp fj4s_lp fj4sd2_lp ft2_lp ft2d2_lp ha_lp had2_lp iv_lp ivd2_lp ivd3_lp ivd4_lp ivd6_lp ivd8_lp ivd16_lp ivd24_lp ivt_lp ivtd2_lp ivtd4_lp ivtd8_lp ivtd16_lp ld1_lp ld1d2_lp ld1q_lp ld1qd2_lp ld2_lp ld2d2_lp ld2q_lp ld2qd2_lp ld3_lp ld3d2_lp ld4_lp ld4d2_lp ld5_lp ld5d2_lp ld5q_lp ld5qd2_lp ld6_lp ld6d2_lp ld6q_lp ld6qd2_lp mx2_lp mx2d2_lp mx2d4_lp mx2i_lp
Output
Maximum Fanouts
1081
STDL131
1-26
Samsung ASIC
Introduction
Maximum Fanouts
Cell Name
mx2ia_lp mx2id2_lp mx2id2a_lp mx2id4_lp mx2id4a_lp mx4_lp mx4d2_lp mx4d4_lp nd2_lp nd2b_lp nd2bd2_lp nd2bd4_lp nd2bd8_lp nd2d2_lp nd2d4_lp nd2d8_lp nd3_lp nd3b_lp nd3bd2_lp nd3bd4_lp nd3bd8_lp nd3d2_lp nd3d4_lp nd3d8_lp nd4_lp nd4d2_lp nd4d4_lp nd5_lp nd5d2_lp nd5d4_lp nd6_lp nd6d2_lp nd6d4_lp nd8_lp nd8d2_lp nd8d4_lp nid_lp nid16_lp nid2_lp nid3_lp nid4_lp nid6_lp nid8_lp nid24_lp nit_lp nitd16_lp nitd2_lp nitd4_lp nitd8_lp nr2_lp nr2a_lp nr2b_lp nr2bd2_lp nr2bd4_lp nr2bd8_lp nr2d2_lp nr2d4_lp nr2d8_lp nr3_lp nr3a_lp nr3d2_lp nr3d4_lp nr4_lp nr4d2_lp nr4d4_lp
Output
Maximum Fanouts
1051
Cell Name
nr5_lp nr5d2_lp nr5d4_lp nr6_lp nr6d2_lp nr6d4_lp nr8_lp nr8d2_lp nr8d4_lp oa21_lp oa211_lp oa2111_lp oa2111d2_lp oa211d2_lp oa211d4_lp oa21d2_lp oa21d4_lp oa22_lp oa221_lp oa221d2_lp oa221d4_lp oa222_lp oa2222_lp oa2222d2_lp oa2222d4_lp oa222d2_lp oa222d4_lp oa22a_lp oa22d2_lp oa22d2a_lp oa22d4_lp oa22d4a_lp oa31_lp oa311_lp oa3111_lp oa31d2_lp oa31d4_lp oa32_lp oa321_lp oa322_lp oa33_lp or2_lp or2b_lp or2bd2_lp or2bd4_lp or2bd8_lp or2d2_lp or2d4_lp or2d8_lp or3_lp or3d2_lp or3d4_lp or4_lp or4d2_lp or4d4_lp or5_lp or5d2_lp or5d4_lp scg1_lp scg1d2_lp scg2_lp scg2d2_lp scg2d4_lp scg3_lp scg3d2_lp
Output
Maximum Fanouts
Samsung ASIC
1-27
STDL131
Maximum Fanouts
Introduction
Cell Name
scg3d4_lp scg4_lp scg4d2_lp scg4d4_lp scg5_lp scg5d2_lp scg5d4_lp scg6_lp scg6d2_lp scg7_lp scg7d2_lp scg8_lp scg8d2_lp scg9_lp scg9d2_lp scg10_lp scg10d2_lp scg11_lp scg11d2_lp scg12_lp scg12d2_lp scg12d4_lp scg13_lp scg13d2_lp scg14_lp scg14d2_lp scg15_lp scg15d2_lp scg16_lp scg16d2_lp scg17_lp scg17d2_lp scg18_lp scg18d2_lp scg19_lp scg19d2_lp scg20_lp scg20d2_lp scg21_lp scg21d2_lp scg22_lp scg22d2_lp xn2_lp xn2d2_lp xn2d4_lp xn3_lp xn3d2_lp xn3d4_lp xo2_lp xo2d2_lp xo2d4_lp xo3_lp xo3d2_lp xo3d4_lp
Output
Maximum Fanouts
STDL131
1-28
Samsung ASIC
Introduction
Maximum Fanouts
1.7.2 Cells maximum fanouts cells follows. Table 1-8. Maximum Fanouts Cells (When input tR/tF 0.186ns, fanout (SL) 0.00803pF)
Cell Name
phic_lp phic_abb_lp phicc_abb_lp phicd_lp phicd_abb_lp phicen_abb_lp phicu_lp phicu_abb_lp phis_lp phis_abb_lp phisd_lp phisd_abb_lp phisu_lp phisu_abb_lp phsckdc2_lp phsckdc4_lp phsckdc6_lp phsckdc8_lp phsckdcd2_lp phsckdcd4_lp phsckdcd6_lp phsckdcd8_lp phsckdcu2_lp phsckdcu4_lp phsckdcu6_lp phsckdcu8_lp phsckds2_lp phsckds4_lp phsckds6_lp phsckds8_lp phsckdsd2_lp phsckdsd4_lp phsckdsd6_lp phsckdsd8_lp phsckdsu2_lp phsckdsu4_lp phsckdsu6_lp phsckdsu8_lp phtic_lp phticd_lp phticu_lp phtis_lp phtisd_lp phtisu_lp phsosck1_lp phsosck17_lp phsosck2_lp phsosck27_lp phsoscm1_lp phsoscm16_lp phsoscm2_lp phsoscm26_lp phsoscm3_lp phsoscm36_lp pic_lp pic_abb_lp picc_abb_lp
Cell Name
picd_lp picd_abb_lp picen_abb_lp picu_lp picu_abb_lp pis_lp pis_abb_lp pisd_lp pisd_abb_lp pisu_lp pisu_abb_lp pmic_lp pmic_abb_lp pmicc_abb_lp pmicd_lp pmicd_abb_lp pmicen_abb_lp pmicu_lp pmicu_abb_lp pmis_lp pmis_abb_lp pmisd_lp pmisd_abb_lp pmisu_lp pmisu_abb_lp pmsckdc2_lp pmsckdc4_lp pmsckdc6_lp pmsckdc8_lp pmsckdcd2_lp pmsckdcd4_lp pmsckdcd6_lp pmsckdcd8_lp pmsckdcu2_lp pmsckdcu4_lp pmsckdcu6_lp pmsckdcu8_lp pmsckds2_lp pmsckds4_lp pmsckds6_lp pmsckds8_lp pmsckdsd2_lp pmsckdsd4_lp pmsckdsd6_lp pmsckdsd8_lp pmsckdsu2_lp pmsckdsu4_lp pmsckdsu6_lp pmsckdsu8_lp pmsosck1_lp pmsosck2_lp pmsoscm1_lp pmsoscm2_lp psckdc2_lp psckdc4_lp psckdc6_lp psckdc8_lp psckdcd2_lp psckdcd4_lp psckdcd6_lp psckdcd8_lp psckdcu2_lp psckdcu4_lp psckdcu6_lp psckdcu8_lp psckds2_lp psckds4_lp psckds6_lp
Output
Maximum Fanouts
1251 1251 1251 1251 1251 1251 1096 1392 1095 1389 1095 1391 1030
Output
Maximum Fanouts
1248 1248 1248 1248 1248 1248
Samsung ASIC
1-29
STDL131
Maximum Fanouts
Introduction
Cell Name
psckds8_lp psckdsd2_lp psckdsd4_lp psckdsd6_lp psckdsd8_lp psckdsu2_lp psckdsu4_lp psckdsu6_lp psckdsu8_lp psosck1_lp psosck2_lp psoscm1_lp psoscm2_lp ptic_lp pticd_lp pticu_lp ptis_lp ptisd_lp ptisu_lp
Output
Maximum Fanouts
1264 1027 1258 1029 1261
STDL131
1-30
Samsung ASIC
Introduction
<Condition> Library STDL131 1.8V Fanout 0.00914pF input FD1_LP) Standard Load (SL) 0.00803pF Input slope 0.186ns Maximum output transition time (mott) 1.2ns Maximum frequency 300MHz length (µm/fanout): branch length each fanout except trunk
Trunk width (µm) length (µm/fanout) Trunk length (µm) ck2_lp ck4_lp ck6_lp ck8_lp
2000 5000 2000 5000
case that interconnection considered 1210 1612
Trunk width (µm) length (µm/fanout) Trunk length (µm) nid_lp nid2_lp nid3_lp nid4_lp nid6_lp nid8_lp nid16_lp nid24_lp
0.28 2000 5000 2000
5000
case that interconnection considered 1051
high fanout nets including clock net, Samsung strongly recommends using clock tree synthesis.
Samsung ASIC
1-31
STDL131
Package Capability Pitch Lead Count
Introduction
PACKAGE CAPABILITY PITCH LEAD COUNT
Appendix Samsung's package capability this writing. most current package availability capability obtained from your local Samsung Technology Design Centers.
STDL131
1-32
Samsung ASIC
Introduction
Power Dissipation
Power Dissipation
1.9.1 ESTIMATION POWER DISSIPATION CMOS CIRCUIT primary advantage CMOS circuits power consumption since they draw very small amount current under steady state, conditions. However, circuit densities clock rates increase, power dissipation CMOS circuits becomes substantial. Power dissipation CMOS circuits affected various factors such number gates, switching frequency, gate output loading. Circuit operating temperature important factor determining circuit speed reliability. Circuit power dissipation major factor determining circuit operating temperature. Designers must estimate power dissipation circuit accurately choose appropriate package system operating conditions circuit insure best performance reliability. following sections describe components power dissipation CMOS circuit (static dynamic), method calculating them Samsung STDL131 library elements. 1.9.2 STATIC (DC) POWER DISSIPATION types static current contribute total static power dissipation CMOS circuits leakage current input/output current. Leakage current results from reverse bias between well substrate region CMOS circuit. Since there current path from power ground through CMOS logic gate steady state, static current except leakage current flows through internal circuitry CMOS device. amount this leakage current normally order tens nano amperes negligible. Input/output current flows through buffers when circuit interfaced with other devices, especially TTL. current pull-up/pull-down transistor input buffers typically order tens micro amperes (33µA 3.3V, 25µA 2.5V, 18µA 1.8V), which also negligible. Therefore, only current that output buffers source sink needs counted estimate total static power dissipation. power dissipation output bi-directional buffers determined following formula:
PDC_OUTPUT [mW] VOL(k) IOL(k) tL(k) VOH(k) IOH(k) tH(k) PDC_BI [mW] VOL(k) IOL(k) IOH(k) tH(k) Sout
where, Number output bidirectional buffers Total operation time output mode logic high state time logic state time (assuming that output bi-directional buffers tri-state) Sout output mode ratio bi-directional buffers (typically 0.5)
Samsung ASIC
1-33
STDL131
Power Dissipation
Introduction
1.9.3 DYNAMIC (AC) POWER DISSIPATION When CMOS logic gate changes state, draws switching current result charging discharging load capacitance, power associated with switching current node capacitance,
where power supply voltage. addition power dissipated changing load capacitance, CMOS circuits consume power current flowing from power supply ground through p-channel transistors during switching. dynamic power dissipation entire chip difficult estimate since depends switching activity circuit. Samsung found that switching activity about average recommends using this number estimating total dynamic power dissipation. 1.9.4 POWER DISSIPATION STDL131 This section describes equations used estimate power dissipation STDL131. explained previous section, total power dissipation (PTOTAL) consists static power dissipation (PDC) dynamic power dissipation (PAC). Samsung's internal power estimation tool, CubicPower, uses methodology based following equations. PTOTAL negligible case CMOS logic general. dynamic power dissipation caused four components: input buffers (PAC_INPUT), output buffers (PAC_OUTPUT), bi-directional buffers (PAC_BI), internal cells (PAC_INTERNAL). PAC_ INPUT PAC_OUTPUT PAC_BI PAC_INTERNAL
STDL131
1-34
Samsung ASIC
Introduction
Power Dissipation
Each term mentioned above characterized following equations:
N_1.8V_input
PAC_INPUT [mW]
N_3.3V_input
N_2.5V_input Ij_eq_p i_eq_p
N_total_input (0.001 Cl_inload) k_eq_p 3.24
N_1.8V_output
PAC_OUTPUT [mW] 6.25
N_3.3V_output
N_2.5V_output i_eq_p j_eq_p N_1.8V_output 3.24 0.001 Ci_outload k_eq_p N_3.3V_output
N_2.5V_output
0.001 Cj_outload 10.89
0.001 Ck_outload
PAC_BI [mW] PAC_BI_INPUT Sout PAC_BI_OUTPUT Sout
N_1.8V_bi
PAC_BI_INPUT [mW]
N_3.3V_bi
N_2.5V_bi j_eq_p i_eq_p
N_total_bi 3.24 0.001 Cl_inload k_eq_p N_1.8V_bi
PAC_BI_OUTPUT [mW] 6.25
N_3.3V_bi
N_2.5V_bi j_eq_p i_eq_p
N_2.5V_bi
3.24 k_eq_p
N_1.8V_bi
0.001 Ci_outload
N_3.3V_bi
0.001 Cj_outload 10.89
N_macro
0.001 Ck_outload
PAC_INTERNAL [mW] 0.001 0.1338 0.0160
0.001
where, N_1.8V_input number 1.8V interface input buffers used, N_2.5V_input number 2.5V interface input buffers used, N_3.3V_input number 3.3V interface input buffers used, N_total_input N_1.8V_input N_2.5V_input N_3.3V_input, N_1.8V_output number 1.8V interface output buffers used, N_2.5V_output number 2.5V interface output buffers used, N_3.3V_output number 3.3V interface output buffers used, N_1.8V_bi number 1.8V interface bi-directional buffers used, N_2.5V_bi number 2.5V interface bi-directional buffers used, N_3.3V_bi number 3.3V interface bi-directional buffer used, N_total_bi N_1.8V_bi N_2.5V_bi N_3.3V_bi, N_macro number macro cells used, total gate count design, operating frequency MHz, estimated switching activity (typically internal logic I/O), Sout output mode ratio bi-directional buffers (typically 0.5), load capacitance pF,, characterized power i-th hard macro block W/MHz)
Samsung ASIC
1-35
STDL131
Power Dissipation
Introduction
1.9.5 TEMPERATURE POWER DISSIPATION total power dissipation, PTOTAL used find device temperature following equation: PTOTAL where,
package thermal impedance,
junction temperature device, ambient temperature.
Thermal impedances Samsung packages given following table. junction temperature, determines derating factor propagation delays also used reliability calculations. Hence, designers achieve desired derating factor reliability targets choosing appropriate packages system cooling methods. Table 1-11. Number Thermal Impedances Samsung Plastic Packages SOP/TSOP 41-44 46-56 44-71 Number 39-59 34-56 27-33 34-46
JA[°C/W] JA[°C/W] JA[°C/W] JA[°C/W] JA[°C/W]
51-62
43-56
43-74
27-61
33-47
43-51
29-51
22-43
28-47
29-42
TQFP/LQFP Number 68-70 37-70 35-62 PBGA Number 19-22 16-19 SBGA Number 14.1 13.1 11.7 10.2 (TEPBGA) (TEPBGA) 31-34 37-56 30-42
STDL131
1-36
Samsung ASIC
Introduction
1.10
VDD/VSS Rules Guidelines
1.10 VDD/VSS Rules Guidelines
Three kinds power supplies exist STDL131 providing power internal areas: Core logic VDD1IH_LP, VDD1IM_LP, VDD1I_LP, VSS3I_LP, VSS2I_LP, VSS1I_LP Pre-driver (I/O area) VDD3P_LP, VDD2P_LP, VDD1P_LP, VSS3P_LP, VSS2P_LP, VSS1P_LP Output-drive (I/O area) VDD3O_LP, VDD2O_LP, VDD1O_LP, VSS3O_LP, VSS2O_LP, VSS1O_LP
number pads required specific design depends following factors: Number input output buffers Number simultaneous switching outputs Number used gates simultaneous switching gates Operating frequency
1.10.1 BASIC PLACEMENT GUIDELINES purpose these guidelines minimize drop noise reliable device operations. Core logic pre-driver VDD/VSS pads should evenly distributed sides chip. have core block demanding high power (compiled memory, analog), extra power pads should used supply that block. Power pads group should evenly distributed group. place quiet signal (analog, reference), analog power (VDDA/ VSSA), bi-directional buffer next group. Opposite types power pads (VDD/VSS) should placed close together possible. possible, place power pads (VDD/VSS) corner chip.
1.10.2 VDD1I_LP/VSS1I_LP ALLOCATION GUIDELINES purpose these guidelines ensure that minimum number core logic power pairs used while meeting electromigration rules. number VDD1I_LP/VSS1I_LP pads required specific design function operating frequency chip. VDD1I_LP width number pads equal those VSS1I VDD1I_LP/VSS1I_LP buses pads should distributed evenly core each side chip.
Samsung ASIC
1-37
STDL131
1.10
VDD/VSS Rules Guidelines
Introduction
number VDD1I_LP/VSS1I_LP pairs required design calculated from following expression: number VDD1I_LP/VSS1I_LP pairs 0.001 0.0743 0.0089
N_macro
round
where, core (excluding hard macro blocks) size gate counts switching ratio (typically 0.1) Operating frequency (MHz) Characterized current i-th hard macro block (mA/MHz) Operating frequency i-th hard macro block (MHz) Current limit VDD/VSS pairs based electromigration rule (40mA) reliable device operation minimize drop, device should have fewer than VDD1I_LP/VSS1I_LP power pairs. Extra power pairs needed high power consuming macro blocks (SRAM, analog blocks, etc.). 1.10.3 VDD1P_LP/VSS1P_LP (VDD2P_LP, 3P_LP/VSS2P_LP, 3P_LP) ALLOCATION GUIDELINES. These guidelines ensure that adequate input threshold voltage margin maintained during switching. number VDD1P_LP/VSS1P_LP, VDD2P_LP/VSS2P_LP, VDD3P_LP/VSS3P_LP pads required design calculated from following expression: leq_p Number_ of_VDD1P_LP/VSS1P_LP (VDD2P_LP, 3P_LP/VSS2P_LP, 3P_L) pairs round above expression, Ieq_p (Average current input/output buffers bi-direction pre-drivers maximum operational frequency) [mA] (Refer Table 1-12, Table 1-13 Table 1-14)
N_input
Ieq_p
N_output N_bi j_eq_p_out Ik_eq_p_in Sout Ik_eq_p_out Sout eq_p_in
where, N_input number input buffers used, N_output number output buffers used, N_bi number bi-directional buffers used, operating frequency MHz, Sout output mode ratio bi-directional buffers (typically 0.5), Current limit VDD/VSS pairs based electromigration rules. (40mA)
STDL131
1-38
Samsung ASIC
Introduction
1.10
VDD/VSS Rules Guidelines
Table 1-12. 1.8V Interface Input Buffer Type CMOS Ieq_p_in Normal 0.27 (mA) Tolerant 0.28 Output Pre-Driver CMOS Driver Type B1-4 B8-16 B20-24 Ieq_p_out Normal 0.11 0.36 0.53 (mA) Slew-rate 0.11 0.35 0.47 Table 1-13. 2.5V Interface Input Buffer Type CMOS Ieq_p_in Normal 0.27 (mA) Tolerant 0.27 Output Pre-Driver CMOS Driver Type B1-4 B8-16 B20-24 Ieq_p_out Normal 0.27 0.60 0.84 (mA) Slew-rate 0.29 0.55 0.72 Table 1-14. 3.3V Interface Input Buffer Type CMOS Ieq_p_in Normal 0.32 (mA) Tolerant 0.31 Output Pre-Driver CMOS Driver Type B1-4 B8-16 B20-24 Ieq_p_out Normal 0.32 0.57 0.77 (mA) Slew-rate 0.30 0.57 0.75
T1-4 0.15 0.16
Schmitt Trigger 0.28 0.29 Tristate T8-16 T20-24 0.41 0.58 0.41 0.52
Tolerant 0.28 0.29
T1-4 0.28 0.29
Schmitt Trigger 0.30 0.32 Tristate T8-16 T20-24 0.67 0.77 0.61 0.71
Tolerant 0.39 0.42
T1-4 0.34 0.31
Schmitt Trigger 0.38 0.34 Tristate T8-16 T20-24 0.59 0.79 0.58 0.76
Tolerant 0.35 0.43
reliable device operation minimum voltage drop, least pairs VDD1P_LP/VSS1P_LP (VDD2P_LP, 3P_LP/VSS2P_LP, 3P_LP) power pads should used.
Samsung ASIC
1-39
STDL131
1.10
VDD/VSS Rules Guidelines
Introduction
1.10.4 VDD1O_LP/VSS1O_LP (VDD2O_LP, 3O_LP/VSS2O_LP, 3O_LP) ALLOCATION GUIDE (Simultaneous Switching Output) current induced power ground wire inductances cause system failure because voltage spikes during switching. calculate number output drive power pads, noise well current limit based electromigration taken into consideration. defined number outputs switching simultaneously windows, such type buffers.
NOTE: case heavy loads, high frequency, package inductance, number power pads block could determined electromigration rule rather than noise limit. number power pads block should determined worst case power number determined noise electromigration rules.
Number power pads block Number power pads block under limit noise Calculating number power each group from following expressions: number_of_SSO NVDDOeach_SSO -NBvdd DSSO_mode number_of_SSO NVSSOeach_SSO -NBvss DSSO_mode where, NVDDOeach_sso Number VDD1O_LP (VDD2O_LP, 3O_LP) required each group, NVSSOeach_sso Number VSS1O_LP (VSS2O_LP, 3O_LP) required each group, NBvdd Number buffers VDD1O_LP (VDD2O_LP, 3O_LP) power with lead inductance (Refer Table 1-18), NBvss Number buffers VSS1O_LP (VSS2O_LP, 3O_LP) ground with lead inductance, Package lead frame inductance power/ground (Refer package capability pitch lead count), Dsso_mode DL_mode DP_mode DV_mode DT_mode DC_mode (Refer Table 1-15, Table 1-16 Table 1-17) DL_mode Lead inductance derating factor DP_mode Process derating factor DV_mode Voltage derating factor DT_mode Temperature derating factor DC_mode Cload derating factor (mode either VSS.)
STDL131
1-40
Samsung ASIC
Introduction
1.10
VDD/VSS Rules Guidelines
Table 1-15. Item
Package Lead
Derating Equation (External 1.8V Interface) Equation Mode 1-8mA
DL_vdd DL_vss 0.3214 0.3571 0.1964 1.6071 0.0095 1.7143 0.0381 1.4286 1.0000 1.2857 2.8125 1.0000 1.3333 3.0476 2.0833 voltage 4.9464 1.3095 voltage 3.5536 2.8571 voltage 6.3619 1.4603 voltage 3.8476 0.00071 temp 1.0000 0.00032 temp 1.0097 0.0053 temp 1.0000 0.0052 temp 1.0035 0.0379 cload 0.6205 0.0183 cload 1.2098 0.0438 cload 0.5619 0.0109 cload 1.5476
12-24mA
Range
10nH 10nH 15nH 10nH 10nH 15nH best typical worst best typical worst 1.65 voltage voltage 1.95 1.65 voltage voltage 1.95 temp temp temp temp 10pF cload 30pF 30pF cload 50pF 10pF cload 30pF 30pF cload 50pF
Process
DP_vdd
DP_vss
Voltage
DV_vdd DV_vss
Temperature
DT_vdd DT_vss
Cload
DC_vdd DC_vss
0.0435 1.3043 0.0435 1.3043 0.0400 1.2000 0.0400 1.2000 1.0000 1.1667 1.4167 1.0000 1.0400 1.2400 1.1594 voltage 3.2174 0.8696 voltage 2.6957 0.2067 voltage 1.5200 0.2067 voltage 1.5200 0.0035 temp 1.0000 0.0008 temp 1.0672 0.0016 temp 1.0000 0.0022 temp 0.9855 0.0261 cload 0.7391 0.0043 cload 1.3913 0.0100 cload 0.9000 0.0020 cload 1.1400
Table 1-16.
Item Package Lead
Derating Equation (External 2.5V Interface)
Mode DL_vdd DL_vss Equation 1-8mA 12-24mA 0.0123 1.9753 0.1250 0.8333 0.0247 1.8518 0.0833 1.2500 0.0430 1.5054 0.0769 0.7692 0.0323 1.6129 0.0385 1.1538 1.0000 1.0000 1.6419 1.2083 2.0778 1.3750 1.0000 1.0000 1.1613 1.0000 1.7742 1.1154 1.2962 voltage 4.4012 0.2083 voltage 1.6042 0.8025 voltage 3.1667 0.4167 voltage 2.1250 1.1828 voltage 4.1075 0.1923 voltage 1.5577 0.7527 voltage 3.0323 0.3846 voltage 2.0385 0.000988 temp 1.0000 0.001667 temp 1.0000 0.000455 temp 1.0135 0.000758 temp 1.0227 0.00258 temp 1.0000 0.00154 temp 1.0000 0.00254 temp 1.00097 0.00209 temp 0.9860 0.0370 cload 0.6296 0.0125 cload 0.8750 0.0154 cload 1.2778 0.0021 cload 1.1875 0.0328 cload 0.6720 0.0115 cload 0.8846 0.0199 cload 1.0591 0.0019 cload 1.1730 Range 10nH 10nH 15nH 10nH 10nH 15nH best typical worst best typical worst voltage voltage voltage voltage temp temp temp temp 10pF cload 30pF 30pF cload 50pF 10pF cload 30pF 30pF cload 50pF
Process
DP_vdd
DP_vss
Voltage
DV_vdd DV_vss
Temperature
DT_vdd DT_vss
Cload
DC_vdd DC_vss
Samsung ASIC
1-41
STDL131
1.10
VDD/VSS Rules Guidelines
Introduction
Table 1-17.
Item Package Lead
Derating Equation (External 3.3V Interface)
Mode DL_vdd DL_vss Equation 1-8mA 12-24mA 0.0320 1.6800 0.0857 1.1429 0.0320 1.6800 0.1143 0.8571 0.0609 1.4634 0.0909 0.9091 0.0244 1.8293 0.0455 1.3636 1.0000 1.0000 1.4720 1.2000 1.7520 1.3428 1.0000 1.0000 1.1097 1.0000 1.4390 1.1304 0.7200 voltage 3.5120 0.2857 voltage 2.0000 0.4533 voltage 2.6320 0.1905 voltage 1.6857 0.5285 voltage 2.8536 0.1515 voltage 1.5909 0.3658 voltage 2.3170 0.3030 voltage +2.0909 0.00096 temp 1.0000 0.00114 temp 1.0000 0.00058 temp 1.0095 0.00156 temp 0.9896 0.00146 temp 1.0000 0.00364 temp 1.0000 0.00155 temp 0.9978 0.00165 temp 1.0496 0.0236 cload 0.7640 0.0257 cload 0.7429 0.0264 cload 0.6800 0.0043 cload 1.3857 0.0207 cload 0.7927 0.01136 cload 0.8864 0.0177 cload 0.8841 0.00227 cload 1.1591 Range 10nH 10nH 15nH 10nH 10nH 15nH best typical worst best typical worst voltage voltage voltage voltage temp temp temp temp 10pF cload 30pF 30pF cload 50pF 10pF cload 30pF 30pF cload 50pF
Process
DP_vdd
DP_vss
Voltage
DV_vdd DV_vss
Temperature
DT_vdd DT_vss
Cload
DC_vdd DC_vss
STDL131
1-42
Samsung ASIC
Introduction
1.10
VDD/VSS Rules Guidelines
Table 1-18.
NBvdd/NBvss Parameter (Process best, Volt 1.95V/2.7V/3.6V, Temp 0°C, Llead 1nH) Slew-Rate Medium Normal Slew-Rate High (sh) (sm) Buffer Type Voltage Type NBvdd NBvss NBvdd NBvss NBvdd NBvss pob1 (pot1)_lp pob2 (pot2)_lp pob4 (pot4)_lp pob8 (pot8)_lp Interface pob12 (pot12)_lp pob16 (pot16)_lp pob20 (pot20)_lp pob24 (pot24)_lp ptot1_lp 3.3V Tolerant ptot2_lp ptot4_lp 1.8V Interface ptot6_lp pmob1 (pmot1)_lp pmob2 (pmot2)_lp pmob4 (pmot4)_lp pmob8 (pmot8)_lp 2.5V Interface pmob12 (pmot12)_lp pmob16 (pmot16)_lp pmob20 (pmot20)_lp pmob24 (pmot24)_lp pmtot1_lp pmtot2_lp Tolerant 2.5V Interface pmtot4_lp pmtot6_lp phob1 (phot1)_lp phob2 (phot2)_lp phob4 (phot4)_lp 3.3V Interface phob8 (phot8)_lp phob12 (phot12)_lp phob16 (phot16)_lp phob20 (phot20)_lp phob24 (phot24)_lp phtot1_lp phtot2_lp Tolerant 3.3V Interface phtot4_lp phtot6_lp
NOTE: pob1_lp means output driver cell, pob12_lp means 12mA output driver cell.
Calculating number required power total from following expression: NVDDO1sso NVDDOeach_sso NVSSO1sso NVSSOeach_sso
When there blocks which switching simultaneously with others, only maximum value NVDDO_each_sso/NVSSO_each_sso among block should used.
Samsung ASIC
1-43
STDL131
1.10
VDD/VSS Rules Guidelines
Introduction
above formula, NVDDOsso Number VDD1O_LP (VDD2O_LP, 3O_LP) total buffers NVSSOsso Number VSS1O_LP (VSS2O_LP, 3O_LP) total buffers Number power pads block limit electromigration rules: Calculating following expression: NVDDO2SSO NVSSO2SSO -Iem
N_SSO_output
Ieq_o
Ieq_o
N_SSO_bi
0.001 Ci_outload
0.001 j_outload j_out
where, N_SSO_output number simultaneous switching output buffers used, N_SSO_bi number simultaneous switching bi-directional buffers used, Coutload Output load capacitance [pF], Operating voltage [V], Maximum operating frequency [MHz], Switching ratio (typically 0.5), Sout Output mode ratio bi-directional buffers (typically 0.5), Current limit VDD/VSS pairs based electromigration rule. (40mA) Number power pads non-SSO block Calculating following expression: NVDDOnon_SSO NVSSOnon_SSO -Iem
N_non_SSO_output
Ieq_o
N_non_SSO_bi
Ieq_o
0.001 Ci_outload
0.001 j_outload j_out
where, N_non_SSO_output number non-simultaneous switching output buffers used, N_non_SSO_bi number non-simultaneous switching bi-directional buffers used, Coutload Output load capacitance [pF], Operating voltage [V], Maximum operating frequency [MHz], Switching ratio (typically 0.5), Sout Output mode ratio bi-directional buffers (typically 0.5), Current limit VDD/VSS pairs based electromigration rule. (40mA) Total number power pads VDD1O_LP/VSS1O_LP (VDD2O_LP, 3O_LP/VSS2O_LP, 3O_LP) Calculating following expressions:
Number VDD1O_LP (VDD2O_LP, 3O_LP) NVDDO1SSO, NVDDO2SSO NVDDOnon_SSO round-up Number VSS1O_LP (VSS2O_LP, 3O_LP) NVSSO1SSO, NVSSO2SSO NVSSOnon_SSO round-up
When open drain type buffers used, consider using VSS1O_LP (VSS2O_LP, 3O_LP) pads since they have current sink only.
STDL131
1-44
Samsung ASIC
Introduction
1.11
Crystal Oscillator Consideration
1.11 Crystal Oscillator Consideration
1.11.1 OVERVIEW STDL131 library contains cell commonly referred on-chip oscillator. on-chip oscillator itself really oscillator, amplifier suitable being used feedback amplifier oscillator circuit. With proper selection off-chip components (crystal ceramic resonator, resistors capacitors) this oscillator circuit performs better than other types clock oscillators. very important select suitable off-chip components on-chip oscillator circuitry. should noted, however, that Samsung cannot assume responsibility writing specifications off-chip components performance finished oscillator design production since optimization crystal oscillator circuit will specific given application. Samsung does, however, spec guarantee performance on-chip oscillator cell. 1.11.2 OSCILLATOR DESIGN CONSIDERATIONS designers have number options clocking system. primary decision whether on-chip oscillator external oscillator. choice on-chip oscillator, designer must then choose type oscillator off-chip component values. These decisions will based both economic technical requirements.The following section discusses some factors considered. 1.11.2.1 On-Chip Oscillator most cases, on-chip oscillator with appropriate external components provides most economical solution clocking problem. Exceptions arise server environments when frequency tolerances tighter than about 0.01%. external components commonly used oscillator circuit positive reactance (normal crystal oscillator), capacitors, resistors, shown figure below. Figure 1-15. CMOS Oscillator Inside Chip PADA
PADY
Feedback Amplifier
1.11.2.2 Crystal Specifications Specifications appropriate crystal very critical. fundamental mode crystal medium better quality used. Crystal resistance affects start-up time steady state amplitude compensated choice however, lower crystal resistance, better. discussion external components follows below.
Samsung ASIC
1-45
STDL131
1.11
Crystal Oscillator Consideration
Introduction
1.11.2.3 Oscillation Frequency oscillation frequency mainly determined crystal. on-chip oscillator little effect frequency. influence on-chip oscillator frequency results from input output (pin-to-ground) capacitances which parallel PADA-toPADY (pin-to-pin) capacitance which parallels crystal. input pin-topin capacitances about each. 1.11.2.4 Selection Optimal values depend whether quartz crystal ceramic resonator being used, application-specific requirements start-up time frequency tolerance. Start-up time sometimes more critical microcontroller systems than frequency stability because various reset initialization requirements. Accuracy oscillator frequency less commonly critical, when oscillator being used time base. general rule, fast start-up stable frequency tend pull oscillator design opposite directions. Considerations both start-up time frequency stability over temperature suggest that should about equal least 15pF (but they don't have either). Increasing value these capacitors above 40pF 50pF improves frequency stability, also increases start-up time. capacitors large (several hundred pF), oscillator won't start all. 1.11.2.5 Selection large ohm) holds on-chip oscillator CMOS inverter) linear region allowing oscillate. inverter fairly output resistance which de-stabilizes oscillator circuit. several K-ohms added feedback network, shown Figure 1-15 stabilize oscillator circuit. higher oscillator frequencies, 20pF 30pF capacitor sometimes used place compensate internal propagation delay. 1.11.3 CONSIDERATIONS Noise glitches arising PADA PADY pins wrong time cause miscount internal clock-generating circuitry. These kinds glitches produced through capacitive coupling between oscillator components traces carrying digital signals with fast rise fall times. this reason, oscillator components should mounted close chip have short, direct traces PADA, PADY, pins. possible, dedicated pins on-chip oscillator. addition, surrounding oscillator components with "quiet" traces (VDD VSS) will alleviate capacitive coupling signals having fast edges. minimize inductive coupling, layout should minimize lead, wire, trace lengths oscillator components.
STDL131
1-46
Samsung ASIC
Introduction
1.11
Crystal Oscillator Consideration
Paths that need checked are: PADA through resonator PADY; PADA through pin; PADY through pin. unusual find that ground ends connect through long traces board. 1.11.4 TROUBLESHOOTING OSCILLATOR PROBLEMS cause oscillator problem difficult find once detected. Below some suggested first things investigate oscillator problem detected. There significant differences stray capacitances between test fixture actual application, particularly actual application multilayer board. This result oscillator problem occurring test fixture that will occur board, problem occurring board that cannot duplicated test fixture. Noise glitches present test fixture present application board another cause oscillator problem. Capacitive coupling between oscillator circuitry other signal should investigated. Inductive coupling also possible there lead, trace, wire with large current nearby. Finally, should overlooked that software problems mimic symptoms slow-starting oscillator incorrect frequency. Software should also invigilated.
Samsung ASIC
1-47
STDL131
Electrical Characteristics
Contents
Electrical Characteristics
ELECTRICAL CHARACTERISTICS
ELECTRICAL CHARACTERISTICS
ELECTRICAL CHARACTERISTICS
following tables define electrical characteristics standard LVCMOS buffers described Chapter "Input/Output Cells." electrical characteristics oscillator standard interface buffers such follow desciptions those buffer cells Chapter 1.8V± 0.15V, 85°C, VEXT 3.3V 0.3V case 3.3V tolerant)
Symbol Parameter High level input voltage LVCMOS interface level input voltage LVCMOS interface Switching threshold Schmitt trigger, positive-going threshold Schmitt trigger, negative-going threshold High level input current Input buffer Input buffer with pull-down level input current Input buffer Input buffer with pull-up High level output voltage Type Type Type Type Type Type Type Type Type level output voltage Type Type Type Type Type Type Type Type Type Tri-state output leakage current Quiescent supply current Input capacitance Output capacitance Condition 1.27 0.57 0.5VDD CMOS CMOS 0.57 1.27 Type Unit
0.05
-1µA -1mA -2mA -4mA -8mA -12mA -16mA -20mA -24mA 12mA 16mA 20mA 24mA VOUT =VSS input Bi-directional buffers output buffer
0.05
0.45
COUT
Samsung ASIC
STDL131
ELECTRICAL CHARACTERISTICS
ELECTRICAL CHARACTERISTICS
2.5V± 0.2V, 85°C, VEXT 0.25V case tolerant)
Symbol Parameter High level input voltage LVCMOS interface level input voltage LVCMOS interface Switching threshold Schmitt trigger, positive-going threshold Schmitt trigger, negative-going threshold High level input current Input buffer Input buffer with pull-down level input current Input buffer Input buffer with pull-up High level output voltage Type Type Type Type Type Type Type Type Type level output voltage Type Type Type Type Type Type Type Type Type Tri-state output leakage current Quiescent supply current Input capacitance Output capacitance Condition 0.5VDD CMOS CMOS Type Unit
0.05
-1µA -1mA -2mA -4mA -8mA -12mA -16mA -20mA -24mA 12mA 16mA 20mA 24mA VOUT =VSS input Bi-directional buffers output buffer
0.05
COUT
STDL131
Samsung ASIC
ELECTRICAL CHARACTERISTICS
ELECTRICAL CHARACTERISTICS
3.3V± 0.3V, 85°C, VEXT 0.25V case tolerant)
Symbol Parameter High level input voltage LVCMOS interface level input voltage LVCMOS interface Switching threshold Schmitt trigger, positive-going threshold Schmitt trigger, negative-going threshold High level input current Input buffer Input buffer with pull-down level input current Input buffer Input buffer with pull-up High level output voltage Type Type Type Type Type Type Type Type Type level output voltage Type Type Type Type Type Type Type Type Type Tri-state output leakage current Quiescent supply current Input capacitance Output capacitance Condition CMOS CMOS Type Unit
0.05
-1µA -1mA -2mA -4mA -8mA -12mA -16mA -20mA -24mA 12mA 16mA 20mA 24mA VOUT =VSS input Bi-directional buffers output buffer
0.05
COUT
Samsung ASIC
STDL131
ELECTRICAL CHARACTERISTICS
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Symbol Parameter supply voltage 1.8V 2.5V 3.3V 1.8V input buffer 2.5V input buffer input voltage 3.3V input buffer 1.8V interface/3.3V tolerant input buffer 3.3V interface/5V tolerant input buffer 1.8V output buffer 2.5V output buffer VOUT output voltage 3.3V output buffer 1.8V interface/3.3V tolerant output buffer 3.3V interface/5V tolerant output buffer ILatch TSTG Latch current Storage temperature Rating Unit
Recommended Operating Conditions
Symbol Parameter supply voltage internal (=VDDIN) supply voltage block (=VDDIO) Rating 1.8V 1.8V 2.5V 3.3V 1.8V 2.5V 3.3V 1.8V input buffer 2.5V input buffer input voltage 3.3V input buffer 1.8V interface/3.3V tolerant input buffer 3.3V interface/5V tolerant input buffer 1.8V output buffer 2.5V output buffer VOUT output voltage 3.3V output buffer 1.8V interface/3.3V tolerant output buffer 3.3V interface/5V tolerant output buffer Commercial temperature range Industrial temperature range 1.65 1.65 -0.1 -0.2 -0.3 -0.1 -0.3 -0.1 -0.2 -0.3 -0.1 -0.3 1.95 1.95 VDDIO+0.15 VDDIO+0.2 VDDIO+0.3 VDDIO+0.15 VDDIO+0.2 VDDIO+0.3 Unit
supply voltage analog core (=VDDA)
STDL131
Samsung ASIC
Internal Macrocells
Contents
Overview Summary Tables. Logic Cells. Flip-Flops. 3-219 Latches. 3-296 Holder. 3-321 Internal Clock Drivers 3-322 Adders 3-324 Multiplexers 3-329 Integraged Clock-Gating Cells. 3-342
INTERNAL MACROCELLS
OVERVIEW
OVERVIEW
This chapter contains data sheets standard logic macrocells; combinational logic cells, flip-flops, latches, holder, internal clock drivers, decoders, adders, multiplexers integrated clock-gating cells. electrical characteristics each cell follow each cell's description. summary table following pages list entire STDL131 standard logic macrocell library cell type along with cell description page number. Moreover, each section begins with table containing brief functional description each cell that section.
Samsung ASIC
STDL131
SUMMARY TABLES
INTERNAL MACROCELLS
SUMMARY TABLES
Logic Cells
Cell Type Cell Cell Name AD3_LP/AD3D2_LP/AD3D4_LP AD4_LP/AD4D2_LP/AD4D4_LP AD5_LP/AD5D2_LP/AD5D4_LP NAND Cell ND4_LP/ND4D2_LP/ND4D4_LP ND5_LP/ND5D2_LP/ND5D4_LP ND6_LP/ND6D2_LP/ND6D4_LP ND8_LP/ND8D2_LP/ND8D4_LP Cell NR4_LP/NR4D2_LP/NR4D4_LP NR5_LP/NR5D2_LP/NR5D4_LP NR6_LP/NR6D2_LP/NR6D4_LP NR8_LP/NR8D2_LP/NR8D4_LP Cell OR3_LP/OR3D3_LP/OR3D4_LP OR4_LP/OR4D2_LP/OR4D4_LP OR5_LP/OR5D2_LP/OR5D4_LP Exclusive-NOR Cell Exclusive-OR Cell XN2_LP/XN2D2_LP/XN2D4_LP XN3_LP/XN3D2_LP/XN3D4_LP XO2_LP/XO2D2_LP/XO2D4_LP XO3_LP/XO3D2_LP/XO3D4_LP Page 3-14 3-16 3-18 3-20 3-22 3-25 3-27 3-29 3-32 3-35 3-37 3-40 3-44 3-48 3-50 3-52 3-55 3-57 3-61 3-65 3-69 3-71 3-73 3-75 3-77 3-80 3-82 3-84 3-86
STDL131
Samsung ASIC
INTERNAL MACROCELLS
SUMMARY TABLES
Cell Type Combinational Cell
Cell Name AO21_LP/AO21D2_LP/AO21D4_LP AO211_LP/AO211D2_LP/AO211D4_LP AO2111_LP/AO2111D2_LP AO22_LP/AO22D2_LP/AO22D4_LP AO22A_LP AO221_LP/AO221D2_LP/AO221D4_LP AO222_LP/AO222D2_LP/AO222D4_LP AO222A_LP AO31_LP/AO31D2_LP/AO31D4_LP AO311_LP AO3111_LP AO32_LP/AO32D2_LP AO321_LP AO322_LP AO33_LP AO331_LP AO332_LP
Page 3-88 3-90 3-92 3-94 3-96 3-97 3-100 3-104 3-105 3-109 3-111 3-112 3-113 3-115 3-116 3-118 3-120 3-122 3-124 3-126 3-128 3-130 3-132 3-134 3-137 3-141 3-145 3-147 3-148 3-149 3-150 3-151 3-153
Combinational Cell NAND
OA21_LP/OA21D2_LP/OA21D4_LP OA211_LP/OA211D2_LP/OA211D4_LP OA2111_LP/OA2111D2_LP OA22_LP/OA22D2_LP/OA22D4_LP OA22A_LP/OA22D2A_LP/OA22D4A_LP OA221_LP/OA221D2_LP/OA221D4_LP OA222_LP/OA222D2_LP/OA222D4_LP OA31_LP/OA31D2_LP/OA31D4_LP OA311_LP OA3111_LP OA32_LP OA321_LP OA322_LP OA33_LP
Samsung ASIC
STDL131
SUMMARY TABLES
INTERNAL MACROCELLS
Cell Type Complex Cells SCG1_LP/SCG1D2_LP
Cell Name SCG2_LP/SCG2D2_LP/SCG2D4_LP SCG3_LP/SCG3D2_LP/SCG3D4_LP SCG4_LP/SCG4D2_LP/SCG4D4_LP SCG5_LP/SCG5D2_LP/SCG5D4_LP SCG6_LP/SCG6D2_LP SCG7_LP/SCG7D2_LP SCG8_LP/SCG8D2_LP SCG9_LP/SCG9D2_LP SCG10_LP/SCG10D2_LP SCG11_LP/SCG11D2_LP SCG12_LP/SCG12D2_LP/SCG12D4_LP SCG13_LP/SCG13D2_LP SCG14_LP/SCG14D2_LP SCG15_LP/SCG15D2_LP SCG16_LP/SCG16D2_LP SCG17_LP/SCG17D2_LP
Page 3-154 3-157 3-159 3-162 3-166 3-170 3-172 3-174 3-176 3-178 3-180 3-182 3-184 3-186 3-188 3-190 3-192 3-194 3-196 3-198 3-200 3-202 3-204 3-205 3-206 3-207 3-208 3-211 3-213 3-216
Complex Cells
SCG18_LP/SCG18D2_LP SCG19_LP/SCG19D2_LP SCG20_LP/SCG20D2_LP SCG21_LP/SCG21D2_LP SCG22_LP/SCG22D2_LP
Delay Cells
DL1D2_LP DL2D2_LP DL5D2_LP DL10D2_LP
Inverter Inverting Tri-State Buffer Non-Inverting Buffer
IVD16_LP/IVD24_LP NID8_LP/NID16_LP/NID24_LP
STDL131
Samsung ASIC
INTERNAL MACROCELLS
SUMMARY TABLES
Flip-Flops
Cell Type Flip-Flop FD1_LP/FD1D2_LP FD1S_LP/FD1SD2_LP FD1SQ_LP/FD1SQD2_LP FD1Q_LP/FD1QD2_LP Flip-Flop with Reset FD2_LP/FD2D2_LP FD2S_LP/FD2SD2_LP FD2SQ_LP/FD2SQD2_LP FD2Q_LP/FD2QD2_LP Flip-Flop with FD3_LP/FD3D2_LP FD3S_LP/FD3SD2_LP FD3SQ_LP/FD3SQD2_LP FD3Q_LP/FD3QD2_LP Flip-Flop with Reset, FD4_LP/FD4D2_LP FD4S_LP/FD4SD2_LP FD4SQ_LP/FD4SQD2_LP FD4Q_LP/FD4QD2_LP Flip-Flop with Negative Edge Trigger FD5_LP/FD5D2_LP FD5S_LP/FD5SD2_LP FD6_LP/FD6D2_LP FD6S_LP/FD6SD2_LP FD7_LP/FD7D2_LP FD7S_LP/FD7SD2_LP FD8_LP/FD8D2_LP FD8S_LP/FD8SD2_LP Flip-Flop with Synchronous Clear FDS2_LP/FDS2D2_LP FDS2S_LP/FDS2SD2_LP FDS3_LP/FDS3D2_LP FDS3S_LP/FDS3SD2_LP Flip-Flop FJ2_LP/FJ2D2_LP FJ2S_LP/FJ2SD2_LP FJ4_LP/FJ4D2_LP FJ4S_LP/FJ4SD2_LP Toggle Flip-Flop FT2_LP/FT2D2_LP Cell Name Page 3-221 3-223 3-225 3-227 3-229 3-231 3-233 3-235 3-237 3-239 3-241 3-243 3-245 3-248 3-252 3-255 3-257 3-259 3-261 3-263 3-265 3-267 3-269 3-272 3-276 3-278 3-280 3-282 3-284 3-286 3-288 3-291 3-294
Samsung ASIC
STDL131
SUMMARY TABLES
INTERNAL MACROCELLS
Latches
Cell Type Latch with Active High LD1_LP/LD1D2_LP LD1Q_LP/LD1QD2_LP LD2_LP/LD2D2_LP LD2Q_LP/LD2QD2_LP LD3_LP/LD3D2_LP LD4_LP/LD4D2_LP Latch with Active LD5_LP/LD5D2_LP LD5Q_LP/LD5QD2_LP LD6_LP/LD6D2_LP LD6Q_LP/LD6QD2_LP Cell Name Page 3-297 3-299 3-301 3-304 3-306 3-309 3-312 3-314 3-316 3-319
Holder
Cell Type Holder BUSHOLDER_LP Cell Name Page 3-321
Internal Clock Drivers
Cell Type Internal Clock Drivers Cell Name CK2_LP/CK4_LP/CK6_LP/CK8_LP Page 3-322
Adders
Cell Type Full Adder Half Adder FA_LP/FAD2_LP HA_LP/HAD2_LP Cell Name Page 3-325 3-327
Multiplexers
Cell Type Non-Inverting Inverting Non-Inverting Cell Name MX2_LP/MX2D2_LP/MX2D4_LP MX2I_LP/MX2ID2_LP/MX2ID4_LP MX2IA_LP/MX2ID2A_LP/MX2ID4A_LP MX4_LP/MX4D2_LP/MX4D4_LP Page 3-330 3-333 3-335 3-338
Integrated Clock-Gating Cells
Cell Type Integrated Clock-Gating Cells Cell Name CGLN_LP/CGLND2_LP/CGLND4_LP CGLP_LP/CGLPD2_LP/CGLPD4_LP Page 3-343 3-346
STDL131
Samsung ASIC
LOGIC CELLS
Cell Names Function Descriptions
Cell Name AD2_LP AD2D2_LP AD2D4_LP AD2D8_LP AD2B_LP AD2BD2_LP AD2BD4_LP AD2BD8_LP AD3_LP AD3D2_LP AD3D4_LP AD4_LP AD4D2_LP AD4D4_LP AD5_LP AD5D2_LP AD5D4_LP ND2_LP ND2D2_LP ND2D4_LP ND2D8_LP ND2B_LP ND2BD2_LP ND2BD4_LP ND2BD8_LP ND3_LP ND3D2_LP ND3D4_LP ND3D8_LP ND3B_LP ND3BD2_LP ND3BD4_LP ND3BD8_LP ND4_LP ND4D2_LP ND4D4_LP ND5_LP ND5D2_LP Function Description 2-Input with Drive 2-Input with Drive 2-Input with Drive 2-Input with Drive 2-Input with Inverted Input, Drive 2-Input with Inverted Input, Drive 2-Input with Inverted Input, Drive 2-Input with Inverted Input, Drive 3-Input with Drive 3-Input with Drive 3-Input with Drive 4-Input with Drive 4-Input with Drive 4-Input with Drive 5-Input with Drive 5-Input with Drive 5-Input with Drive 2-Input NAND with Drive 2-Input NAND with Drive 2-Input NAND with Drive 2-Input NAND with Drive 2-Input NAND with Inverted Input, Drive 2-Input NAND with Inverted Input, Drive 2-Input NAND with Inverted Input, Drive 2-Input NAND with Inverted Input, Drive 3-Input NAND with Drive 3-Input NAND with Drive 3-Input NAND with Drive 3-Input NAND with Drive 3-Input NAND with Inverted Input, Drive 3-Input NAND with Inverted Input, Drive 3-Input NAND with Inverted Input, Drive 3-Input NAND with Inverted Input, Drive 4-Input NAND with Drive 4-Input NAND with Drive 4-Input NAND with Drive 5-Input NAND with Drive 5-Input NAND with Drive
Samsung ASIC
STDL131
LOGIC CELLS
Cell Names Function Descriptions (Continued)
Cell Name ND5D4_LP ND6_LP ND6D2_LP ND6D4_LP ND8_LP ND8D2_LP ND8D4_LP NR2_LP NR2A_LP NR2D2_LP NR2D4_LP NR2D8_LP NR2B_LP NR2BD2_LP NR2BD4_LP NR2BD8_LP NR3_LP NR3A_LP NR3D2_LP NR3D4_LP NR4_LP NR4D2_LP NR4D4_LP NR5_LP NR5D2_LP NR5D4_LP NR6_LP NR6D2_LP NR6D4_LP NR8_LP NR8D2_LP NR8D4_LP OR2_LP OR2D2_LP OR2D4_LP OR2D8_LP OR2B_LP OR2BD2_LP Function Description 5-Input NAND with Drive 6-Input NAND with Drive 6-Input NAND with Drive 6-Input NAND with Drive 8-Input NAND with Drive 8-Input NAND with Drive 8-Input NAND with Drive 2-Input with Drive with P-Transistor, N-Transistor 2-Input with Drive 2-Input with Drive 2-Input with Drive 2-Input with Inverted Input, Drive 2-Input with Inverted Input, Drive 2-Input with Inverted Input, Drive 2-Input with Inverted Input, Drive 3-Input with Drive 3-Input with P-Transistor, N-Transistor 3-Input with Drive 3-Input with Drive 4-Input with Drive 4-Input with Drive 4-Input with Drive 5-Input with Drive 5-Input with Drive 5-Input with Drive 6-Input with Drive 6-Input with Drive 6-Input with Drive 8-Input with Drive 8-Input with Drive 8-Input with Drive 2-Input with Drive 2-Input with Drive 2-Input with Drive 2-Input with Drive 2-Input with Inverted Input, Drive 2-Input with Inverted Input, Drive
STDL131
Samsung ASIC
LOGIC CELLS
Cell Names Function Descriptions (Continued)
Cell Name OR2BD4_LP OR2BD8_LP OR3_LP OR3D2_LP OR3D4_LP OR4_LP OR4D2_LP OR4D4_LP OR5_LP OR5D2_LP OR5D4_LP XN2_LP XN2D2_LP XN2D4_LP XN3_LP XN3D2_LP XN3D4_LP XO2_LP XO2D2_LP XO2D4_LP XO3_LP XO3D2_LP XO3D4_LP AO21_LP AO21D2_LP AO21D4_LP AO211_LP AO211D2_LP AO211D4_LP AO2111_LP AO2111D2_LP AO22_LP AO22D2_LP AO22D4_LP AO22A_LP AO221_LP AO221D2_LP AO221D4_LP Function Description 2-Input with Inverted Input, Drive 2-Input with Inverted Input, Drive 3-Input with Drive 3-Input with Drive 3-Input with Drive 4-Input with Drive 4-Input with Drive 4-Input with Drive 5-Input with Drive 5-Input with Drive 5-Input with Drive 2-Input Exclusive-NOR with Drive 2-Input Exclusive-NOR with Drive 2-Input Exclusive-NOR with Drive 3-Input Exclusive-NOR with Drive 3-Input Exclusive-NOR with Drive 3-Input Exclusive-NOR with Drive 2-Input Exclusive-OR with Drive 2-Input Exclusive-OR with Drive 2-Input Exclusive-OR with Drive 3-Input Exclusive-OR with Drive 3-Input Exclusive-OR with Drive 3-Input Exclusive-OR with Drive 2-AND into 2-NOR with Drive 2-AND into 2-NOR with Drive 2-AND into 2-NOR with Drive 2-AND into 3-NOR with Drive 2-AND into 3-NOR with Drive 2-AND into 3-NOR with Drive 2-AND into 4-NOR with Drive 2-AND into 4-NOR with Drive 2-ANDs into 2-NOR with Drive 2-ANDs into 2-NOR with Drive 2-ANDs into 2-NOR with Drive 2-AND 2-NOR into 2-NOR with Drive 2-ANDs into 3-NOR with Drive 2-ANDs into 3-NOR with Drive 2-ANDs into 3-NOR with Drive
Samsung ASIC
STDL131
LOGIC CELLS
Cell Names Function Descriptions (Continued)
Cell Name AO222_LP AO222D2_LP AO222D4_LP AO222A_LP AO2222_LP AO2222D2_LP AO2222D4_LP AO31_LP AO31D2_LP AO31D4_LP AO311_LP AO3111_LP AO32_LP AO32D2_LP AO321_LP AO322_LP AO33_LP AO331_LP AO332_LP OA21_LP OA21D2_LP OA21D4_LP OA211_LP OA211D2_LP OA211D4_LP OA2111_LP OA2111D2_LP OA22_LP OA22D2_LP OA22D4_LP OA22A_LP OA22D2A_LP OA22D4A_LP OA221_LP OA221D2_LP OA221D4_LP OA222_LP OA222D2_LP Function Description Three 2-ANDs into 3-NOR with Drive Three 2-ANDs into 3-NOR with Drive Three 2-ANDs into 3-NOR with Drive Inverting 2-of-3 Majority with Drive Four 2-ANDs into 4-NOR with Drive Four 2-ANDs into 4-NOR with Drive Four 2-ANDs into 4-NOR with Drive 3-AND into 2-NOR with Drive 3-AND into 2-NOR with Drive 3-AND into 2-NOR with Drive 3-AND into 3-NOR with Drive 3-AND into 4-NOR with Drive 3-AND 2-AND into 2-NOR with Drive 3-AND 2-AND into 2-NOR with Drive 3-AND 2-AND into 3-NOR with Drive 3-AND 2-ANDs into 3-NOR with Drive 3-ANDs into 2-NOR with Drive 3-ANDs into 3-NOR with Drive 3-ANDs 2-AND into 3-NOR with Drive 2-OR into 2-NAND with Drive 2-OR into 2-NAND with Drive 2-OR into 2-NAND with Drive 2-OR into 3-NAND with Drive 2-OR into 3-NAND with Drive 2-OR into 3-NAND with Drive 2-OR into 4-NAND with Drive 2-OR into 4-NAND with Drive 2-ORs into 2-NAND with Drive 2-ORs into 2-NAND with Drive 2-ORs into 2-NAND with Drive 2-OR 2-NAND into 2-NAND with Drive 2-OR 2-NAND into 2-NAND with Drive 2-OR 2-NAND into 2-NAND with Drive 2-ORs into 3-NAND with Drive 2-ORs into 3-NAND with Drive 2-ORs into 3-NAND with Drive Three 2-ORs into 3-NAND with Drive Three 2-ORs into 3-NAND with Drive
STDL131
3-10
Samsung ASIC
LOGIC CELLS
Cell Names Function Descriptions (Continued)
Cell Name OA222D4_LP OA2222_LP OA2222D2_LP OA2222D4_LP OA31_LP OA31D2_LP OA31D4_LP OA311_LP OA3111_LP OA32_LP OA321_LP OA322_LP OA33_LP SCG1_LP SCG1D2_LP SCG2_LP SCG2D2_LP SCG2D4_LP SCG3_LP SCG3D2_LP SCG3D4_LP SCG4_LP SCG4D2_LP SCG4D4_LP SCG5_LP SCG5D2_LP SCG5D4_LP SCG6_LP SCG6D2_LP SCG7_LP SCG7D2_LP SCG8_LP SCG8D2_LP SCG9_LP SCG9D2_LP SCG10_LP SCG10D2_LP SCG11_LP Function Description Three 2-ORs into 3-NAND with Drive Four 2-ORs into 4-NAND with Drive Four 2-ORs into 4-NAND with Drive Four 2-ORs into 4-NAND with Drive 3-OR into 2-NAND with Drive 3-OR into 2-NAND with Drive 3-OR into 2-NAND with Drive 3-OR into 3-NAND with Drive 3-OR into 4-NAND with Drive 3-OR 2-OR into 2-NAND with Drive 3-OR 2-OR into 3-NAND with Drive 3-OR 2-ORs into 3-NAND with Drive 3-ORs into 2-NAND with Drive 2-NAND (2-AND into 2-NOR)s into 3-NAND with Drive 2-NAND (2-AND into 2-NOR)s into 3-NAND with Drive 2-ANDs into 2-OR with Drive 2-ANDs into 2-OR with Drive 2-ANDs into 2-OR with Drive 2-NANDs into 3-NAND with Drive 2-NANDs into 3-NAND with Drive 2-NANDs into 3-NAND with Drive (two 2-ANDs into 2-NOR)s into 2-NAND with Drive (two 2-ANDs into 2-NOR)s into 2-NAND with Drive (two 2-ANDs into 2-NOR)s into 2-NAND with Drive Three 2-ANDs into 3-OR with Drive Three 2-ANDs into 3-OR with Drive Three 2-ANDs into 3-OR with Drive 2-AND into 2-OR with Drive 2-AND into 2-OR with Drive 2-NAND (2-AND into 2-NOR) into 2-NAND with Drive 2-NAND (2-AND into 2-NOR) into 2-NAND with Drive 2-AND into 3-OR with Drive 2-AND into 3-OR with Drive 2-OR into 2-AND with Drive 2-OR into 2-AND with Drive 2-ORs into 2-AND with Drive 2-ORs into 2-AND with Drive 2-NORs into 3-NOR with Drive
Samsung ASIC
3-11
STDL131
LOGIC CELLS
Cell Names Function Descriptions (Continued)
Cell Name SCG11D2_LP SCG12_LP SCG12D2_LP SCG12D4_LP SCG13_LP SCG13D2_LP SCG14_LP SCG14D2_LP SCG15_LP SCG15D2_LP SCG16_LP SCG16D2_LP SCG17_LP SCG17D2_LP SCG18_LP SCG18D2_LP SCG19_LP SCG19D2_LP SCG20_LP SCG20D2_LP SCG21_LP SCG21D2_LP SCG22_LP SCG22D2_LP DL1D2_LP DL2D2_LP DL5D2_LP DL10D2_LP IV_LP IVD2_LP IVD3_LP IVD4_LP IVD6_LP IVD8_LP IVD16_LP IVD24_LP IVT_LP IVTD2_LP Function Description 2-NORs into 3-NOR with Drive 2-NAND into 2-NOR with Drive 2-NAND into 2-NOR with Drive 2-NAND into 2-NOR with Drive 2-NOR into 2-NAND with Drive 2-NOR into 2-NAND with Drive 2-NAND into 2-NAND with Drive 2-NAND into 2-NAND with Drive 2-NAND into 3-NAND with Drive 2-NAND into 3-NAND with Drive 2-OR with inverted input into 2-NAND with Drive 2-OR with inverted input into 2-NAND with Drive 2-AND into 2-NOR into 2-NAND with Drive 2-AND into 2-NOR into 2-NAND with Drive 2-AND into 2-NOR into 3-NAND with Drive 2-AND into 2-NOR into 3-NAND with Drive 2-AND into 2-AND into 2-NOR with Drive 2-AND into 2-AND into 2-NOR with Drive 2-NOR into 2-NOR with Drive 2-NOR into 2-NOR with Drive 2-NOR into 3-NOR with Drive 2-NOR into 3-NOR with Drive 2-NAND into 2-OR into 2-NAND with Drive 2-NAND into 2-OR into 2-NAND with Drive Delay Cell with Drive Delay Cell with Drive Delay Cell with Drive 10ns Delay Cell with Drive Inverter with Drive Inverter with Drive Inverter with Drive Inverter with Drive Inverter with Drive Inverter with Drive Inverter with Drive Inverter with Drive Inverting Tri-State Buffer with Enable High, Drive Inverting Tri-State Buffer with Enable High, Drive
Samsung ASIC
3-12
STDL131
LOGIC CELLS
Cell Names Function Descriptions (Continued)
Cell Name IVTD4_LP IVTD8_LP IVTD16_LP NID_LP NID2_LP NID3_LP NID4_LP NID6_LP NID8_LP NID16_LP NID24_LP NIT_LP NITD2_LP NITD4_LP NITD8_LP NITD16_LP Function Description Inverting Tri-State Buffer with Enable High, Drive Inverting Tri-State Buffer with Enable High, Drive Inverting Tri-State Buffer with Enable High, Drive Non-Inverting Buffer with Drive Non-Inverting Buffer with Drive Non-Inverting Buffer with Drive Non-Inverting Buffer with Drive Non-Inverting Buffer with Drive Non-Inverting Buffer with Drive Non-Inverting Buffer with Drive Non-Inverting Buffer with Drive Non-Inverting Tri-State Buffer with Enable High, Drive Non-Inverting Tri-State Buffer with Enable High, Drive Non-Inverting Tri-State Buffer with Enable High, Drive Non-Inverting Tri-State Buffer with Enable High, Drive Non-Inverting Tri-State Buffer with Enable High, Drive
Samsung ASIC
3-13
STDL131
2-Input with 1X/2X/4X/8X Drive Logic Symbol
Truth Table
Cell Data
AD2_LP Input Load (SL) AD2D2_LP AD2D4_LP AD2D8_LP AD2_LP 1.33 Gate Count AD2D2_LP AD2D4_LP 1.67 2.33 AD2D8_LP 4.33
Switching Characteristics
AD2_LP
Path
(Typical process, 25°C, 1.8V, tR/tF 0.19ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.046 0.026*SL 0.039 0.017*SL 0.146 0.013*SL 0.154 0.010*SL 0.045 0.026*SL 0.040 0.017*SL 0.143 0.013*SL 0.163 0.010*SL
Parameter
Delay [ns]
Group3*
0.035 0.027*SL 0.028 0.018*SL 0.149 0.012*SL 0.158 0.010*SL 0.035 0.027*SL 0.029 0.018*SL 0.146 0.012*SL 0.168 0.010*SL
0.100 0.051 0.025*SL 0.073 0.040 0.017*SL 0.168 0.140 0.014*SL 0.169 0.146 0.012*SL 0.100 0.050 0.025*SL 0.075 0.043 0.016*SL 0.165 0.136 0.014*SL 0.178 0.154 0.012*SL *Group3 *Group1 *Group2
AD2D2_LP
Path
Parameter
Delay [ns]
Delay Equations [ns] Group1* Group2*
0.048 0.013*SL 0.036 0.008*SL 0.147 0.007*SL 0.148 0.005*SL 0.048 0.013*SL 0.040 0.008*SL 0.144 0.007*SL 0.157 0.005*SL
Group3*
0.039 0.013*SL 0.032 0.009*SL 0.154 0.006*SL 0.156 0.005*SL 0.038 0.013*SL 0.032 0.009*SL 0.150 0.006*SL 0.165 0.005*SL
0.077 0.055 0.011*SL 0.052 0.035 0.009*SL 0.156 0.139 0.009*SL 0.155 0.141 0.007*SL 0.074 0.049 0.012*SL 0.054 0.035 0.010*SL 0.153 0.136 0.008*SL 0.164 0.150 0.007*SL *Group1 *Group2 *Group3
STDL131
3-14
Samsung ASIC
2-Input with 1X/2X/4X/8X Drive Switching Characteristics
AD2D4_LP
Path
(Typical process, 25°C, 1.8V, tR/tF 0.19ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.064 0.006*SL 0.051 0.004*SL 0.184 0.004*SL 0.181 0.003*SL 0.064 0.006*SL 0.050 0.004*SL 0.180 0.004*SL 0.189 0.003*SL
Parameter
Delay [ns]
Group3*
0.055 0.006*SL 0.047 0.004*SL 0.201 0.003*SL 0.199 0.002*SL 0.055 0.006*SL 0.049 0.004*SL 0.198 0.003*SL 0.207 0.002*SL
0.075 0.061 0.007*SL 0.057 0.047 0.005*SL 0.187 0.176 0.006*SL 0.183 0.174 0.005*SL 0.075 0.062 0.007*SL 0.058 0.049 0.004*SL 0.184 0.173 0.006*SL 0.191 0.182 0.005*SL *Group1 *Group2 *Group3
AD2D8_LP
Path
Parameter
Delay [ns]
Delay Equations [ns] Group1* Group2*
0.063 0.003*SL 0.049 0.002*SL 0.178 0.002*SL 0.176 0.002*SL 0.062 0.003*SL 0.050 0.002*SL 0.175 0.002*SL 0.184 0.002*SL
Group3*
0.055 0.003*SL 0.047 0.002*SL 0.199 0.002*SL 0.196 0.001*SL 0.055 0.003*SL 0.048 0.002*SL 0.196 0.002*SL 0.205 0.001*SL
0.066 0.057 0.005*SL 0.051 0.045 0.003*SL 0.180 0.174 0.003*SL 0.177 0.172 0.003*SL 0.067 0.061 0.003*SL 0.053 0.049 0.002*SL 0.177 0.170 0.003*SL 0.185 0.180 0.003*SL *Group3 *Group1 *Group2
Samsung ASIC
3-15
STDL131
2-Input with Inverted Input, 1X/2X/4X/8X Drive Logic Symbol
Truth Table
Cell Data
Input Load (SL) Gate Count AD2B_LP AD2BD2_LP AD2BD4_LP AD2BD8_LP AD2B_LP AD2BD2_LP AD2BD4_LP AD2BD8_LP 2.00 2.00 2.67 4.67
Switching Characteristics
AD2B_LP
Path
(Typical process, 25°C, 1.8V, tR/tF 0.19ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.045 0.026*SL 0.037 0.017*SL 0.215 0.013*SL 0.180 0.010*SL 0.046 0.026*SL 0.039 0.017*SL 0.144 0.013*SL 0.162 0.010*SL
Parameter
Delay [ns]
Group3*
0.036 0.027*SL 0.028 0.018*SL 0.218 0.012*SL 0.184 0.010*SL 0.036 0.027*SL 0.029 0.018*SL 0.146 0.012*SL 0.166 0.010*SL
0.101 0.052 0.024*SL 0.072 0.038 0.017*SL 0.237 0.208 0.014*SL 0.195 0.172 0.012*SL 0.100 0.051 0.025*SL 0.075 0.043 0.016*SL 0.166 0.137 0.014*SL 0.177 0.154 0.012*SL *Group1 *Group2 *Group3
STDL131
3-16
Samsung ASIC
2-Input with Inverted Input, 1X/2X/4X/8X Drive Switching Characteristics
AD2BD2_LP
Path
(Typical process, 25°C, 1.8V, tR/tF 0.19ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.048 0.013*SL 0.038 0.008*SL 0.227 0.007*SL 0.188 0.005*SL 0.049 0.012*SL 0.041 0.008*SL 0.144 0.007*SL 0.157 0.005*SL
Parameter
Delay [ns]
Group3*
0.039 0.013*SL 0.033 0.009*SL 0.234 0.006*SL 0.196 0.005*SL 0.039 0.013*SL 0.033 0.009*SL 0.151 0.006*SL 0.166 0.005*SL
0.074 0.051 0.012*SL 0.054 0.037 0.009*SL 0.236 0.220 0.008*SL 0.195 0.181 0.007*SL 0.078 0.056 0.011*SL 0.054 0.035 0.010*SL 0.154 0.137 0.009*SL 0.164 0.150 0.007*SL *Group1 *Group2 *Group3
AD2BD4_LP
Path
Parameter
Delay [ns]
Delay Equations [ns] Group1* Group2*
0.066 0.006*SL 0.051 0.004*SL 0.264 0.004*SL 0.220 0.003*SL 0.066 0.006*SL 0.050 0.004*SL 0.183 0.004*SL 0.189 0.003*SL
Group3*
0.056 0.006*SL 0.048 0.004*SL 0.282 0.003*SL 0.238 0.002*SL 0.056 0.006*SL 0.050 0.004*SL 0.201 0.003*SL 0.208 0.002*SL
0.075 0.059 0.008*SL 0.057 0.046 0.005*SL 0.267 0.256 0.006*SL 0.222 0.213 0.005*SL 0.075 0.060 0.007*SL 0.058 0.050 0.004*SL 0.187 0.175 0.006*SL 0.192 0.182 0.005*SL *Group3 *Group1 *Group2
AD2BD8_LP
Path
Parameter
Delay [ns]
Delay Equations [ns] Group1* Group2*
0.061 0.003*SL 0.047 0.002*SL 0.272 0.002*SL 0.226 0.002*SL 0.063 0.003*SL 0.050 0.002*SL 0.178 0.002*SL 0.184 0.002*SL
Group3*
0.055 0.003*SL 0.048 0.002*SL 0.293 0.002*SL 0.246 0.001*SL 0.056 0.003*SL 0.048 0.002*SL 0.199 0.002*SL 0.205 0.001*SL
0.068 0.062 0.003*SL 0.051 0.046 0.002*SL 0.274 0.267 0.003*SL 0.227 0.221 0.003*SL 0.068 0.061 0.003*SL 0.054 0.049 0.002*SL 0.179 0.173 0.003*SL 0.185 0.179 0.003*SL *Group3 *Group1 *Group2
Samsung ASIC
3-17
STDL131
AD3_LP/AD3D2_LP/AD3D4_LP
3-Input with 1X/2X/4X Drive Logic Symbol
Truth Table
Cell Data
AD3_LP Input Load (SL) AD3D2_LP AD3D4_LP AD3_LP 1.67 Gate Count AD3D2_LP 2.33 AD3D4_LP 3.00
Switching Characteristics
AD3_LP
Path
(Typical process, 25°C, 1.8V, tR/tF 0.19ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.060 0.026*SL 0.044 0.016*SL 0.181 0.013*SL 0.167 0.010*SL 0.060 0.026*SL 0.045 0.016*SL 0.184 0.013*SL 0.177 0.010*SL 0.060 0.026*SL 0.046 0.016*SL 0.184 0.013*SL 0.185 0.010*SL
Parameter
Delay [ns]
Group3*
0.045 0.026*SL 0.032 0.017*SL 0.188 0.012*SL 0.173 0.009*SL 0.045 0.026*SL 0.033 0.017*SL 0.191 0.012*SL 0.183 0.009*SL 0.045 0.026*SL 0.035 0.017*SL 0.190 0.012*SL 0.193 0.009*SL
0.112 0.063 0.025*SL 0.078 0.046 0.016*SL 0.201 0.169 0.016*SL 0.181 0.157 0.012*SL 0.113 0.064 0.025*SL 0.077 0.044 0.017*SL 0.204 0.173 0.016*SL 0.191 0.166 0.012*SL 0.113 0.064 0.025*SL 0.080 0.048 0.016*SL 0.203 0.172 0.016*SL 0.200 0.175 0.012*SL *Group1 *Group2 *Group3
AD3D2_LP
Path
Parameter
Delay [ns]
Delay Equations [ns] Group1* Group2*
0.066 0.012*SL 0.044 0.008*SL 0.197 0.007*SL 0.168 0.006*SL 0.067 0.012*SL 0.046 0.008*SL 0.201 0.007*SL 0.178 0.006*SL 0.067 0.012*SL 0.048 0.008*SL 0.201 0.007*SL 0.186 0.006*SL
Group3*
0.058 0.013*SL 0.041 0.008*SL 0.213 0.006*SL 0.181 0.005*SL 0.058 0.013*SL 0.041 0.008*SL 0.218 0.006*SL 0.191 0.005*SL 0.058 0.013*SL 0.043 0.008*SL 0.218 0.006*SL 0.200 0.005*SL
0.090 0.063 0.013*SL 0.060 0.043 0.009*SL 0.205 0.185 0.010*SL 0.175 0.160 0.008*SL 0.090 0.063 0.013*SL 0.060 0.042 0.009*SL 0.210 0.189 0.010*SL 0.185 0.169 0.008*SL 0.090 0.064 0.013*SL 0.063 0.045 0.009*SL 0.210 0.190 0.010*SL 0.193 0.177 0.008*SL *Group1 *Group2 *Group3
STDL131
3-18
Samsung ASIC
AD3_LP/AD3D2_LP/AD3D4_LP
3-Input with 1X/2X/4X Drive Switching Characteristics
AD3D4_LP
Path
(Typical process, 25°C, 1.8V, tR/tF 0.19ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.081 0.006*SL 0.058 0.004*SL 0.233 0.004*SL 0.202 0.003*SL 0.081 0.006*SL 0.058 0.004*SL 0.237 0.004*SL 0.211 0.003*SL 0.081 0.006*SL 0.061 0.004*SL 0.238 0.004*SL 0.220 0.003*SL
Parameter
Delay [ns]
Group3*
0.082 0.006*SL 0.059 0.004*SL 0.263 0.003*SL 0.225 0.002*SL 0.082 0.006*SL 0.059 0.004*SL 0.267 0.003*SL 0.234 0.002*SL 0.082 0.006*SL 0.061 0.004*SL 0.268 0.003*SL 0.244 0.003*SL
0.090 0.075 0.008*SL 0.063 0.051 0.006*SL 0.237 0.224 0.007*SL 0.204 0.194 0.005*SL 0.090 0.074 0.008*SL 0.065 0.055 0.005*SL 0.241 0.227 0.007*SL 0.213 0.203 0.005*SL 0.091 0.075 0.008*SL 0.066 0.054 0.006*SL 0.241 0.228 0.007*SL 0.222 0.211 0.005*SL *Group3 *Group1 *Group2
Samsung ASIC
3-19
STDL131
AD4_LP/AD4D2_LP/AD4D4_LP
4-Input with 1X/2X/4X Drive Logic Symbol
Truth Table
Cell Data
AD4_LP AD4_LP 2.00 Input Load (SL) AD4D2_LP Gate Count AD4D2_LP 2.33 AD4D4_LP AD4D4_LP 3.00
Switching Characteristics
AD4_LP
Path
(Typical process, 25°C, 1.8V, tR/tF 0.19ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.068 0.025*SL 0.049 0.017*SL 0.190 0.013*SL 0.180 0.010*SL 0.068 0.025*SL 0.050 0.017*SL 0.201 0.013*SL 0.195 0.010*SL 0.068 0.025*SL 0.051 0.017*SL 0.206 0.013*SL 0.207 0.010*SL 0.068 0.025*SL 0.055 0.017*SL 0.211 0.013*SL 0.215 0.010*SL
Parameter
Delay [ns]
Group3*
0.053 0.026*SL 0.037 0.017*SL 0.201 0.012*SL 0.189 0.010*SL 0.053 0.026*SL 0.038 0.017*SL 0.212 0.012*SL 0.204 0.010*SL 0.053 0.026*SL 0.039 0.017*SL 0.218 0.012*SL 0.217 0.010*SL 0.053 0.026*
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